KR20240049127A - Thin film transistor, transistor array substrate, and method for fabricating the transistor array substrate - Google Patents

Abstract

A thin film transistor, a transistor array substrate including the same, and a method of manufacturing the transistor array substrate are provided. The thin film transistor is disposed on a substrate and includes a channel region, an active layer including a source region connected to one side of the channel region and a drain region connected to the other side of the channel region, and a gate insulator disposed on the channel region of the active layer. layer, and a gate electrode disposed on the gate insulating layer. The inclination of the side of the gate electrode with respect to the interface between the gate insulating layer and the gate electrode is an obtuse angle, and the inclination of the side of the gate insulating layer with respect to the interface between the gate insulating layer and the gate electrode is an obtuse angle.

Description

Thin film transistor, transistor array substrate, and method of manufacturing a transistor array substrate {THIN FILM TRANSISTOR, TRANSISTOR ARRAY SUBSTRATE, AND METHOD FOR FABRICATING THE TRANSISTOR ARRAY SUBSTRATE}

The present invention relates to thin film transistors, transistor array substrates, and methods for manufacturing transistor array substrates.

As the information society develops, the demand for display devices for displaying images is increasing in various forms. For example, display devices are applied to various electronic devices such as smartphones, digital cameras, laptop computers, navigation systems, and smart televisions.

A display device may include a display panel that emits light for displaying an image, and a driver that supplies a signal or power to drive the display panel.

The display panel may include a display area through which light for displaying an image is emitted, and may include a polarizing member or a light-emitting member disposed in the display area.

In the display area, pixels that display each luminance and color may be arranged. Each pixel may include three or more sub-pixels that are adjacent to each other and each emit three or more different colors.

The display panel may include a transistor array substrate including a substrate and a circuit layer disposed on the substrate and including pixel drivers respectively corresponding to sub-pixels. Light-emitting elements corresponding to sub-pixels of the display area may be individually driven by the pixel drivers of the circuit layer.

Each of the pixel drivers of the circuit layer of the transistor array substrate may include at least one thin film transistor.

A thin film transistor includes a gate electrode and an active layer. The active layer includes a channel area, a source area and a drain area connected to both ends of the channel area. Accordingly, in a thin film transistor, when the voltage difference between one of the source and drain regions and the gate electrode according to the driving signal transmitted to the gate electrode becomes more than a threshold, the source and drain regions are electrically connected through the channel region of the active layer. It may be a switching element.

Thin film transistors can be divided into a top gate structure and a bottom gate structure depending on the positional relationship between the active layer and the gate electrode. Alternatively, the thin film transistor may have a double gate structure including two gate electrodes disposed above and below the active layer.

In the case of a thin film transistor having a top gate structure, it may include a gate insulating layer disposed on a channel region of the active layer and a gate electrode disposed on the gate insulating layer. Additionally, the active layer and gate electrode of the thin film transistor may be covered with an interlayer insulating layer.

Meanwhile, in order to increase the resolution of the display device, the gate electrode may be made of a metal material with relatively low specific resistance. Additionally, in order to increase the resolution of the display device, when arranging the gate insulating layer and the gate electrode, the metal material may be etched using isotropic dry etching, which has a relatively smaller process error compared to anisotropic wet etching. However, in the case of a pattern prepared by dry etching, the side surface has a steep slope that is close to vertical, so there is a disadvantage in that cracks or gaps easily occur in the insulating layer covering the pattern.

That is, due to step coverage, the thickness of the interlayer insulating layer covering the side surface of the gate insulating layer may be smaller than the thickness of the interlayer insulating layer covering the top surface of the gate electrode.

In addition, when the side of the gate insulating layer is steeply inclined close to vertical, cracks or gaps are generated in the interlayer insulating layer due to the inclination of the side of the gate insulating layer with respect to the active layer, thereby interfering with the active layer as an interlayer insulating layer. It may not be completely covered. As a result, disconnection of the active layer or deterioration of semiconductor characteristics of the active layer may cause a rapid decrease in the lifespan of the thin film transistor and a decrease in the uniformity of characteristics of the thin film transistor.

Accordingly, the problem to be solved by the present invention is to provide a thin film transistor that is advantageous for high resolution and can prevent disconnection of the active layer and deterioration of semiconductor characteristics, a transistor array substrate including the same, and a method of manufacturing the transistor array substrate. will be.

The problems of the present invention are not limited to the problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the description below.

A thin film transistor according to an embodiment for solving the above problem is disposed on a substrate and includes a channel region, a source region connected to one side of the channel region, and a drain region connected to the other side of the channel region. It includes a gate insulating layer disposed on the channel region, and a gate electrode disposed on the gate insulating layer. The inclination of the side of the gate electrode with respect to the interface between the gate insulating layer and the gate electrode is an obtuse angle, and the inclination of the side of the gate insulating layer with respect to the interface between the gate insulating layer and the gate electrode is an obtuse angle.

The active layer and the gate electrode may be covered with an interlayer insulating layer disposed flat on the substrate. The gate electrode may include an electrode main layer and an electrode barrier layer disposed between the electrode main layer and the gate insulating layer, and between a side of the electrode main layer and the interlayer insulating layer.

The electrode main layer is made of at least one metal material of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). It may include a single layer or multiple layers made of one metal material, or may include an alloy of two or more metal materials. The electrode barrier layer may include a metal oxide material including one or more of indium (In), gallium (Ga), zinc (Zn), tin (Sn), aluminum (Al), and molybdenum (Mo).

The active layer includes an oxide semiconductor material including one or more metal materials selected from the group consisting of indium (In), gallium (Ga), zinc (Zn), tin (Sn), aluminum (Al), and molybdenum (Mo). Among them, the source region and the drain region may be in a conductive state.

The interlayer insulating layer includes a first interlayer insulating layer in contact with the source region and drain region of the active layer, the gate insulating layer and the gate electrode, and a second interlayer insulating layer disposed flat on the first interlayer insulating layer. may include.

The thin film transistor may further include a light blocking layer disposed on a first buffer layer covering the substrate and overlapping at least the channel region of the active layer. The active layer may be disposed on a second buffer layer covering the light blocking layer.

The second buffer layer may be arranged flat.

A side surface of the light blocking layer may be in contact with the first buffer layer.

The light blocking layer is at least one of the following metal materials: molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). It may include a single layer or multiple layers made of a metal material, or an alloy of two or more metal materials.

A transistor array substrate according to an embodiment for solving the above problem includes a substrate including a display area in which sub-pixels are arranged, and a circuit layer disposed on the substrate and including pixel drivers corresponding to each of the sub-pixels. do. Each of the pixel drivers includes at least one thin film transistor. A thin film transistor of one of the circuit layers is disposed on the substrate and includes a channel region, an active layer including a source region connected to one side of the channel region and a drain region connected to the other side of the channel region, and the channel of the active layer. It includes a gate insulating layer disposed on the region, and a gate electrode disposed on the gate insulating layer. The inclination of the side of the gate electrode with respect to the interface between the gate insulating layer and the gate electrode is an obtuse angle, and the inclination of the side of the gate insulating layer with respect to the interface between the gate insulating layer and the gate electrode is an obtuse angle.

The circuit layer may further include an interlayer insulating layer that covers the active layer and the gate electrode and is flatly disposed on the substrate. The gate electrode may include an electrode main layer and an electrode barrier layer disposed between the electrode main layer and the gate insulating layer, and between a side of the electrode main layer and the interlayer insulating layer.

The electrode main layer is made of at least one metal material of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). It may include a single layer or multiple layers made of one metal material, or may include an alloy of two or more metal materials.

The electrode barrier layer may include a metal oxide material including one or more of indium (In), gallium (Ga), zinc (Zn), tin (Sn), aluminum (Al), and molybdenum (Mo).

The interlayer insulating layer includes a first interlayer insulating layer in contact with the source region and drain region of the active layer, the gate insulating layer and the gate electrode, and a second interlayer insulating layer disposed flat on the first interlayer insulating layer. may include.

The thin film transistor of one of the circuit layers may further include a light blocking layer disposed on a first buffer layer covering the substrate and overlapping at least the channel region of the active layer. The active layer may be disposed on a second buffer layer covering the light blocking layer. The second buffer layer may be arranged flat.

A side surface of the light blocking layer may be in contact with the first buffer layer.

It may further include a light emitting device layer disposed on the circuit layer and including light emitting devices each electrically connected to the pixel drivers. One of the pixel drivers may transmit a driving current to one of the light emitting devices. The one pixel driver includes a first thin-film transistor connected in series with the one light-emitting device between a first power line and a second power line that respectively transmit first and second power sources for driving the light-emitting devices. , a second thin film transistor electrically connected between a data line transmitting a data signal and the gate electrode of the first thin film transistor and turned on based on the scan signal of the scan gate line, and the gate electrode of the first thin film transistor and the It may include a pixel capacitor electrically connected to a first node between the second thin film transistors and a second node between the first thin film transistor and the one light emitting device. The first electrode of the first thin film transistor may be electrically connected to the first power wiring. The second electrode of the first thin film transistor may be electrically connected to the anode electrode of the one light emitting device.

The circuit layer may further include a conductive wiring layer disposed on the interlayer insulating layer, and a via layer disposed flat on the interlayer insulating layer and covering the conductive wiring layer. The wiring conductive layer includes the data wiring, the first power wiring, a gate connection electrode electrically connecting the gate electrode of the second thin film transistor and the light blocking layer of the second thin film transistor, and the active conductive layer of the first thin film transistor. It may include an anode connection electrode electrically connected to the source region of the layer and the light blocking layer of the first thin film transistor. The anode electrode may be disposed on the via layer and electrically connected to the anode connection electrode.

The circuit layer includes a first capacitor electrode disposed on the first buffer layer, a second capacitor electrode disposed on the second buffer layer and overlapping the capacitor electrode, and a second capacitor electrode disposed on the interlayer insulating layer. It may further include a third capacitor electrode overlapping. The pixel capacitor may be provided as an overlap area between each of the first and third capacitor electrodes and the second capacitor electrode.

A method of manufacturing a transistor array substrate according to an embodiment for solving the above problem includes pixel drivers each corresponding to the sub-pixels and each including at least one thin film transistor on a substrate including a display area where sub-pixels are arranged. A step of disposing a circuit layer including a circuit layer, and disposing a light emitting device layer including light emitting devices corresponding to each of the sub-pixels and electrically connected to the pixel drivers, respectively, on the circuit layer. The step of disposing the circuit layer includes disposing a thin film transistor on the substrate, and disposing an interlayer insulating layer covering the thin film transistor on the substrate. Disposing the thin film transistor includes disposing a first buffer layer on the substrate, disposing a light-shielding layer on the first buffer layer, and disposing a second buffer layer covering the light-shielding layer on the first buffer layer. steps, disposing a layer of semiconductor material on the second buffer layer, and disposing a gate insulating layer and a gate electrode on a portion of the layer of semiconductor material. The inclination of the side of the gate electrode with respect to the interface between the gate insulating layer and the gate electrode is an obtuse angle, and the inclination of the side of the gate insulating layer with respect to the interface between the gate insulating layer and the gate electrode is an obtuse angle.

In the step of disposing the gate insulating layer and the gate electrode, the gate electrode is disposed between the electrode main layer and the gate insulating layer, and between the side of the electrode main layer and the interlayer insulating layer. It may include an electrode barrier layer.

Disposing the gate insulating layer and the gate electrode may include disposing an insulating material layer of a first thickness covering the semiconductor material layer on the second buffer layer, partially etching the insulating material layer, and changing a portion of the layer of insulating material that overlaps a portion of the layer of material to a second thickness that is less than the first thickness, disposing a layer of metal oxide material on the layer of metal oxide material, Disposing a metal material layer, performing an ashing process on the metal material layer and the metal oxide material layer until the first thickness of the insulating material layer is exposed, thereby remaining on the second thickness of the insulating material layer. providing the gate electrode including an electrode barrier layer made of a metal oxide material layer and an electrode main layer made of a metal material layer remaining on the electrode barrier layer, and performing an etching treatment on the insulating material layer, Removing the insulating material layer of the first thickness and providing the gate insulating layer with the insulating material layer of the second thickness remaining between the gate electrode and the semiconductor material layer. In the step of preparing the gate electrode, the electrode barrier layer may be disposed between the electrode main layer and the gate insulating layer and may surround a side of the electrode main layer. In the step of preparing the gate insulating layer, an active layer including a source region and a drain region each composed of a channel region composed of a portion of the semiconductor material layer overlapping with the gate electrode and other portions disposed at both ends of the channel region. It can be provided.

The metal oxide material layer may include a metal oxide material including one or more of indium (In), gallium (Ga), zinc (Zn), tin (Sn), aluminum (Al), and molybdenum (Mo). . The metal material layer is made of at least one of the following metal materials: molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). It may include a single layer or multiple layers made of one metal material, or may include an alloy of two or more metal materials.

The step of disposing the interlayer insulating layer includes disposing a first interlayer insulating layer in contact with the source region and drain region of the active layer, the gate insulating layer, and the gate electrode, and an insulating material on the first interlayer insulating layer. It may include the step of laminating, and performing an ashing treatment on the insulating material laminated on the first interlayer insulating layer to provide a second interlayer insulating layer that is arranged flatly.

The step of disposing the second buffer layer may include performing an ashing process on the insulating material laminated on the first buffer layer to provide a flatly disposed second buffer layer.

In the step of disposing the first buffer layer, the first buffer layer may have a third thickness. The step of disposing the light blocking layer includes partially etching the first buffer layer to change a portion of the first buffer layer to a fourth thickness smaller than the third thickness, and disposing a light blocking material layer on the first buffer layer. performing an ashing process on the light-shielding material layer until the first buffer layer of the third thickness is exposed, thereby providing the light-shielding layer with the light-shielding material layer remaining on the first buffer layer of the fourth thickness. May include steps. A side surface of the light blocking layer may be in contact with the first buffer layer.

Specific details of other embodiments are included in the detailed description and drawings.

A thin film transistor according to an embodiment includes an active layer disposed on a substrate, a gate insulating layer disposed on a channel region of the active layer, and a gate electrode disposed on the gate insulating layer, between the gate insulating layer and the gate electrode. The slope of the side surface of the gate electrode and the slope of the side surface of the gate insulating layer with respect to the interface are obtuse angles.

As such, since the side of the gate insulating layer has an obtuse angle at the interface between the gate insulating layer and the gate electrode, the side of the gate insulating layer may have an acute angle at the interface between the gate insulating layer and the active layer.

According to one embodiment, among the methods of manufacturing a transistor array substrate including a thin film transistor, disposing a thin film transistor on a substrate includes disposing a first buffer layer on the substrate, disposing a light blocking layer on the first buffer layer. , disposing a second buffer layer covering the light blocking layer, disposing a semiconductor material layer on the second buffer layer, and disposing a gate insulating layer and a gate electrode on a portion of the semiconductor material layer.

The step of disposing the gate insulating layer and the gate electrode includes disposing a layer of insulating material of a first thickness covering the semiconductor material layer on the second buffer layer, and adjusting a portion of the insulating material layer to a second thickness less than the first thickness. altering, disposing a layer of metal oxide material on the layer of insulating material, disposing a layer of metal material on the layer of metal oxide material, the layer of metal material and the metal oxide material until the first thickness of the insulating material layer is exposed. An ashing process is performed on the layer to form a gate electrode including an electrode barrier layer made of a metal oxide material layer remaining on the second thickness insulating material layer and an electrode main layer made of a metal material layer remaining on the electrode barrier layer. providing a step of etching the insulating material layer to remove the insulating material layer of the first thickness, and providing a gate insulating layer with the insulating material layer of the second thickness remaining between the gate electrode and the semiconductor material layer. May include steps. In the step of preparing the gate insulating layer, an active layer including a channel region composed of a portion of the semiconductor material layer that overlaps the gate electrode and a source region and drain region composed of other portions disposed at both ends of the channel region may be prepared. .

As such, according to one embodiment, among the steps of disposing the gate insulating layer and the gate electrode, the step of providing the gate electrode is performed until the metal oxide material layer and the metal material layer disposed on the insulating material layer of the second thickness remain. It includes the process of performing ashing treatment. In other words, preparing the gate electrode does not include performing an etching process on the metal material. Accordingly, due to dry etching of the metal material layer, the side of the gate electrode can be prevented from having a sharp inclination close to being vertical.

Additionally, the slope of the side of the gate electrode corresponds to the slope of the side of the part of the second buffer layer changed to the second thickness. Accordingly, since the slope of the part of the second buffer layer can be adjusted in the step of changing the part of the second buffer layer to the second thickness, the slope of the side of the gate electrode can be adjusted relatively easily.

Therefore, during the etching process for the insulating material layer during the step of preparing the gate insulating layer, the side of the gate insulating layer may have a relatively gentle inclination due to the relatively gentle inclination of the side of the gate electrode. . That is, even if dry etching is performed on the insulating material layer, the side of the gate insulating layer can be prevented from having a sharp inclination close to being vertical.

Therefore, the occurrence of gaps or cracks in the interlayer insulating layer due to the sharp inclination of the gate insulating layer can be prevented. Accordingly, since the active layer can be completely covered with the interlayer insulating layer, disconnection of the active layer and deterioration of semiconductor characteristics can be prevented, thereby preventing deterioration of lifespan and characteristic uniformity of the thin film transistor.

A transistor array substrate including such thin film transistors can be easily applied to a high-resolution display device and can have a beneficial effect on improving the image quality of the display device.

Effects according to the embodiments are not limited to the content exemplified above, and further various effects are included in the present specification.

1 is a perspective view showing a display device according to an embodiment.
FIG. 2 is a plan view showing the display device of FIG. 1 .
FIG. 3 is a cross-sectional view showing an example of a surface cut along line A-A' of FIG. 1.
FIG. 4 is a layout diagram showing an example of the circuit layer of FIG. 3.
FIG. 5 is an equivalent circuit diagram showing an example of one sub-pixel of FIG. 4.
FIG. 6 is a cross-sectional view showing a first embodiment of the first thin film transistor, the second thin film transistor, and the pixel capacitor of the pixel driver of FIG. 5.
FIG. 7 is an enlarged view showing the first thin film transistor of FIG. 6 in detail.
FIG. 8 is a cross-sectional view showing a second embodiment of the first thin film transistor, the second thin film transistor, and the pixel capacitor of the pixel driver of FIG. 5.
FIG. 9 is a cross-sectional view showing a third embodiment of the first thin film transistor, the second thin film transistor, and the pixel capacitor of the pixel driver of FIG. 5.
FIG. 10 is a cross-sectional view showing a fourth embodiment of the first thin film transistor, the second thin film transistor, and the pixel capacitor of the pixel driver of FIG. 5.
Figure 11 is a flowchart showing a method of manufacturing a transistor array substrate according to an embodiment.
FIG. 12 is a flowchart showing detailed steps of arranging the gate insulating layer and gate electrode of FIG. 11 .
Figures 13 to 34 are process diagrams for some steps in Figures 11 and 12.

The advantages and features of the present invention and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and will be implemented in various different forms. The present embodiments only serve to ensure that the disclosure of the present invention is complete and that common knowledge in the technical field to which the present invention pertains is not limited. It is provided to fully inform those who have the scope of the invention, and the present invention is only defined by the scope of the claims.

When an element or layer is referred to as “on” another element or layer, it includes instances where the element or layer is directly on top of or intervening with the other element. Like reference numerals refer to like elements throughout the specification. The shape, size, ratio, angle, number, etc. disclosed in the drawings for explaining the embodiments are illustrative and the present invention is not limited to the details shown.

Although first, second, etc. are used to describe various components, these components are of course not limited by these terms. These terms are merely used to distinguish one component from another. Therefore, it goes without saying that the first component mentioned below may also be a second component within the technical spirit of the present invention.

Each feature of the various embodiments of the present invention can be combined or combined with each other partially or entirely, and various technical interconnections and operations are possible, and each embodiment can be implemented independently of each other or together in a related relationship. It may be possible.

Hereinafter, specific embodiments will be described with reference to the attached drawings.

1 is a perspective view showing a display device according to an embodiment. FIG. 2 is a plan view showing the display device of FIG. 1 . Figure 3 is a cross-sectional view showing an example of a surface cut along line A-A' of Figure 1.

1 and 2, the display device 1 is a device that displays moving images or still images, and is used in mobile phones, smart phones, tablet personal computers, and smart watches. (smart watch), watch phone, mobile communication terminal, electronic notebook, e-book, PMP (portable multimedia player), navigation, UMPC (Ultra Mobile PC), as well as portable electronic devices such as television, laptop, monitor, etc. , can be used as a display screen for various products such as billboards and the Internet of Things (IOT).

The display device 1 includes an organic light emitting display device using an organic light emitting diode, a quantum dot light emitting display device including a quantum dot light emitting layer, an inorganic light emitting display device including an inorganic semiconductor, and an ultra-small light emitting diode (micro or nano light emitting diode (micro LED). It may be a light-emitting display device such as a miniature light-emitting display device using (or nano LED)). Hereinafter, the description will focus on the fact that the display device 1 is an organic light emitting display device. However, the present invention is not limited to this and can be applied to display devices including organic insulating materials, organic light-emitting materials, and metal materials.

The display device 1 may be formed flat, but is not limited thereto. For example, the display device 1 is formed at the left and right ends and may include curved portions having a constant curvature or a changing curvature. In addition, the display device 1 may be flexibly formed to be bent, curved, bent, folded, or rolled.

The display device 1 may include a transistor array substrate 10 .

The display device 1 may further include a protection substrate 20 that faces the transistor array substrate 10 and covers the light emitting device layer 13 .

In addition, the display device 1 includes a display driving circuit 31 for supplying each data signal to the data lines (DL in FIG. 4) of the circuit layer (12 in FIG. 3) of the transistor array substrate 10, and It may further include a circuit board 32 for supplying various signals and power to the transistor array board 10 and the display driving circuit 31.

Referring to FIG. 3 , the transistor array substrate 10 may include a substrate 11 and a circuit layer 12 disposed on the substrate 11 .

The transistor array substrate 10 may further include a light emitting device layer 13 disposed on the circuit layer 12.

That is, the light emitting device layer 13 is disposed between the substrate 11 and the protection substrate 20.

The circuit layer 12 supplies driving signals for each sub-pixel corresponding to the image signal to the light emitting device layer 13. The light emitting device layer 13 may emit light from each sub-pixel according to a driving signal. Light from the light emitting device layer 13 may be emitted to the outside through at least one of the substrate 11 and the protection substrate 20. As a result, the display device 1 can provide the function of displaying images.

Additionally, the display device 1 may further include a touch detection unit (not shown) that detects the coordinates of a point touched by the user among the display surface from which light for displaying an image is emitted.

The touch sensing unit may be attached to one side of the cover substrate 20 or may be embedded between the transistor array substrate 10 and the cover substrate 20.

The touch sensing unit may include a touch electrode (not shown) arranged in a touch sensing area corresponding to the display surface and made of a transparent conductive material.

This touch detection unit can detect whether a touch is input and the coordinates of a point where the touch is input by periodically detecting a change in the capacitance value of the touch electrode while applying a touch driving signal to the touch electrode.

The cover substrate 20 may be bonded opposite to the transistor array substrate 10 .

The cover substrate 20 may be a means of providing rigidity to protect against external physical and electrical shock. The cover substrate 20 may be made of a transparent material that has insulating properties and rigidity.

In addition, the display device 1 may further include a sealing layer 30 disposed at an edge between the transistor array substrate 10 and the cover substrate 20 and bonding the transistor array substrate 10 and the cover substrate 20 to each other. You can.

Additionally, the display device 1 may further include a filling layer (not shown) that fills the space between the transistor array substrate 10 and the cover substrate 20.

As shown in FIGS. 1 and 2, the display surface of the display device 1 has a short side in the first direction (X-axis direction) and a short side in the second direction (Y-axis direction) that intersects the first direction (X-axis direction). It may have a rectangular shape with long sides. However, this is just an example, and the display screen of the display device 1 may be implemented in various forms.

For example, the display surface may be rounded so that a corner where a short side in the first direction (X-axis direction) and a long side in the second direction (Y-axis direction) meet has a predetermined curvature. Alternatively, the display surface may have a polygonal, circular, or oval shape.

Figure 1 shows that the transistor array substrate 10 is in the form of a flat plate, but the present invention is not limited thereto. That is, the transistor array substrate 10 may be bent at both ends in the Y-axis direction. Alternatively, the transistor array substrate 10 may be provided flexibly so that it can be bent, curved, bent, folded, or rolled.

The display driving circuit 31 outputs signals and voltages for driving the transistor array substrate 10.

For example, the display driving circuit 31 supplies a data signal to the data line (DL in FIG. 4) of the transistor array substrate 10, and the first driving power line (VDL in FIG. 4) of the transistor array substrate 10. ) can be supplied with the first driving power. Additionally, the display driving circuit 31 may supply a scan control signal to the scan driver (33 in FIG. 4) built into the transistor array substrate 10.

The display driving circuit 31 may be provided as an integrated circuit (IC).

The integrated circuit chip of the display driving circuit 31 may be directly mounted on the transistor array substrate 10 using a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic bonding method. In this case, as shown in FIG. 2, the integrated circuit chip of the display driving circuit 31 may be disposed in an area of the transistor array substrate 10 that is not covered by the cover substrate 20.

Alternatively, the integrated circuit chip of the display driving circuit 31 may be mounted on the circuit board 32.

Circuit board 32 may include an anisotropic conductive film. The circuit board 32 may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

Circuit board 32 may be attached to electrode pads of transistor array substrate 10 . Because of this, the lead lines of the circuit board 32 may be electrically connected to the electrode pads of the transistor array substrate 10.

FIG. 4 is a layout diagram showing an example of the circuit layer of FIG. 3.

Referring to FIG. 4 , the transistor array substrate 10 may include a display area DA that emits light for image display and a non-display area NDA surrounding the display area DA. The non-display area NDA may be indicated as an area from the edge of the display area DA to the edge of the substrate (11 in FIG. 3).

The transistor array substrate 10 includes sub-pixels (SPX) arranged in a matrix in the vertical and horizontal directions in the display area (DA). Each sub-pixel (SPX) may be a unit that individually displays luminance and color.

Pixels can be provided by these sub-pixels (SPX). Each pixel may include three or more sub-pixels that are adjacent to each other and each emit light of three or more different colors.

The non-display area NDA may include a display pad area DPA disposed adjacent to an edge of the substrate 11 . The transistor array substrate 10 may further include a signal pad (SPD) disposed in the display pad area (DPA) of the non-display area (NDA).

The circuit board 32 may be attached to the display pad area (DPA) of the transistor array substrate 10 and electrically connected to the signal pad (SPD).

The transistor array substrate 10 is disposed in the display area DA and further includes wires that supply signals or power to the plurality of sub-pixels SPX. Wires of the transistor array substrate 10 may include a scan gate wire (SGL), a data wire (DL), and a first power wire (VDL).

The scan gate wire SGL may extend in the first direction DR1 (left and right direction in FIG. 4).

The data line DL may extend in the second direction DR2 (up and down direction in FIG. 4).

The first power line VDL may extend in either the first direction DR1 or the second direction DR2. For example, the first power line VDL may extend in the second direction DR2 like the data line DL.

Alternatively, the circuit layer 12 extends in a direction intersecting the first power line (VDL) and is connected to the first power line (VDL) in order to reduce the RC delay of the first power supply due to the resistance of the first power line (VDL). It may further include a first power auxiliary wiring (not shown) electrically connected to the VDL).

The scan gate line (SGL) transmits a scan signal for controlling whether or not to transmit a data signal to the sub-pixels (SPX).

The scan gate wire (SGL) may be connected to the gate driver 33 disposed in a portion of the non-display area (NDA) of the transistor array substrate 10.

The gate driver 33 may be electrically connected to the display driving circuit 31 or at least one of the signal pads (SPD) through at least one gate control supply line (GCSPL).

The gate driver 33 may apply a scan signal to the scan gate lines SGL based on a gate control signal and gate level power supplied through at least one gate control supply line GCSPL.

According to the illustration of FIG. 4 , the gate driver 33 is disposed in a portion of the non-display area NDA adjacent to one side of the display area DA in the first direction DR1 (i.e., the left side of FIG. 4 ). However, this is only an example, and the gate driver 33 may be disposed in another part of the non-display area NDA adjacent to the right side of the display area DA. Alternatively, the gate driver 33 may be disposed on both left and right sides of the display area DA.

The data line DL is electrically connected between the display driving circuit 31 and the sub-pixels SPX, and transmits the data signal output from the display driving circuit 31 to the sub-pixels SPX.

The display driving circuit 31 may be electrically connected to some of the signal pads SPD through a data connection line DLL. That is, the display driving circuit 31 may be electrically connected to the circuit board 31 through a data connection line (DLL) and some signal pads (SPD).

The circuit board 32 may supply digital video data and timing signals corresponding to the image signal to the display driving circuit 31.

The circuit layer 12 extends from the non-display area (NDA) to the display area (DA) and includes a first power source (ELVDD in FIG. 5) and a second power source (ELVDD in FIG. 5) for driving the light emitting devices (EMD in FIG. 5). It may further include a first power line (VDL) and a second power line (not shown) that respectively transmit ELVSS). Here, the second power source (ELVSS) may have a lower voltage level than the first power source (ELVDD).

Each of the first power line (VDL) and the second power line (not shown) may be electrically connected to the display driving circuit 31 or at least one signal pad (SPD) among the signal pads (SPD).

The circuit layer 12 includes pixel drivers (PXD in FIG. 5) that correspond to the sub-pixels (SPX) and are electrically connected to the scan gate line (SGL), the data line (DL), and the first power line (VDL). Includes.

FIG. 5 is an equivalent circuit diagram showing an example of one sub-pixel of FIG. 4.

Referring to FIG. 5, one of the pixel drivers (PXD) corresponding to the sub-pixels (SPX) is one of the light-emitting devices (EMD) of the light-emitting device layer 13. It is electrically connected to the anode electrode and can supply a driving current (Ids) to one light emitting device (EMD).

One pixel driver PXD may include at least one thin film transistor T1, T2, and T3.

As an example, one pixel driver (PXD) is electrically connected between the first thin film transistor (T1) electrically connected to the light emitting device (EMD) and the gate electrode of the first thin film transistor (T1) and the data line (DL). It may include a second thin film transistor (T2). Additionally, one pixel driver (PXD) may further include a pixel capacitor (PC).

Alternatively, one pixel driver (PXD) may further include a third thin film transistor (T3) electrically connected between the initialization voltage line (VIL) delivering the initialization voltage (VINT) and the anode electrode of the light emitting device (EMD). You can.

One light emitting device (EMD) may be an organic light emitting diode (Organic Light Emitting Diode) including a light emitting layer made of organic material. Alternatively, one light emitting device (EMD) may include a light emitting layer made of an inorganic material. Alternatively, the light emitting device (EMD) may be a quantum dot light emitting device having a quantum dot light emitting layer. Alternatively, the light emitting device (EMD) may be a micro light emitting diode.

The first thin film transistor T1 is connected in series with the light emitting device (EMD) between the first power line (VDL) and the second power line (VSL). That is, the first electrode (e.g., drain electrode) of the first thin film transistor T1 is electrically connected to the first power line (VDL), and the second electrode (e.g., , source electrode) may be electrically connected to the anode electrode (AND) of the light emitting device (EMD).

However, the source electrode and drain electrode of the first thin film transistor T1 may be changed differently from the example in FIG. 5 depending on the structure of the first thin film transistor T1.

The cathode electrode (CTD in FIG. 7) of the light emitting device (EMD) may be electrically connected to the second power line (VSL).

Additionally, the gate electrode of the first thin film transistor T1 may be electrically connected to the second thin film transistor T2.

The pixel capacitor PC may be electrically connected between the first node ND1 and the second node ND2. The first node ND1 is a contact point between the gate electrode of the first thin film transistor T1 and the second thin film transistor T2. The second node ND2 is a contact point between the first thin film transistor T1 and the light emitting device EMD.

The second thin film transistor T2 is electrically connected between the data line DL and the gate electrode of the first thin film transistor T1 and may be turned on based on the scan signal SCS of the scan gate line SGL.

That is, when the scan signal (SCS) is applied through the scan gate line (SGL), the second thin film transistor (T2) is turned on, and the data line (DL) and the gate electrode of the first thin film transistor (T1) are electrically connected. You can. At this time, the data signal VDATA of the data line DL is transmitted to the pixel capacitor PC and the gate electrode of the first thin film transistor T1 through the turned-on second thin film transistor T2 and the first node ND1. can be supplied.

The first thin film transistor T1 may be turned on when the voltage difference between the gate electrode and the drain electrode becomes greater than the threshold voltage. That is, when the voltage difference between the drain electrode and the gate electrode to which the first power source (ELVDD) and the data signal (VDATA) are respectively applied is greater than the threshold voltage of the first thin film transistor (T1), the first thin film transistor (T1) can be turned on. there is. At this time, the current (Ids) between the source and drain electrodes of the first thin film transistor (T1) is supplied as the driving current of the light emitting device (EMD). And, the magnitude of the current (Ids) between the source and drain electrodes of the first thin film transistor (T1) corresponds to the data signal (VDATA). That is, when the driving current Ids corresponding to the data signal VDATA is supplied to the light emitting device EMD, the light emitting device EMD can emit light with a brightness corresponding to the data signal VDATA.

The pixel capacitor PC is electrically connected between the first node ND1 and the second node ND2. Therefore, until the data signal VDATA of the next image frame is applied, the potential of the first node N1 can be maintained at the voltage charged in the pixel capacitor PC.

The third thin film transistor T3 may be electrically connected between the initialization voltage line VIL and the second node ND2. The gate electrode of the third thin film transistor T3 may be electrically connected to the initialization gate line IGL.

That is, when the initialization control signal (ICS) is applied through the initialization gate line (IGL), the third thin film transistor (T3) is turned on, and the initialization voltage line (VIL) and the second node (ND2) can be electrically connected. . At this time, the initialization voltage (VINT) of the initialization voltage line (VIL) may be supplied to the anode electrode (AND) of the light emitting device (EMD) through the turned-on third thin film transistor (T3) and the second node (ND2). . Accordingly, the potential of the anode electrode (AND) can be initialized to the initialization voltage (VINT).

Meanwhile, Figure 5 shows that the pixel driver (PXD) has a 3T1C structure including a first thin film transistor (T1), a second thin film transistor (T2), a third thin film transistor (T3), and one pixel capacitor (PC). However, this is just an example. That is, the pixel driver PXD according to one embodiment is not limited to the 3T1C structure shown in FIG. 5, and may be changed differently from the structure shown in FIG. 5 as needed. For example, the pixel driver PXD may not include the third thin film transistor T3, or may further include a thin film transistor for initializing the potential of the first node N1.

In addition, FIG. 5 shows a case where at least one thin film transistor (T1, T2, T3) provided in the pixel driver (PXD) is made of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), but this is only an example. That is, at least one of the at least one thin film transistor T1, T2, and T3 provided in the pixel driver PXD may be a P-type MOSFET.

FIG. 6 is a cross-sectional view showing a first embodiment of the first thin film transistor, the second thin film transistor, and the pixel capacitor of the pixel driver of FIG. 5. FIG. 7 is an enlarged view showing the first thin film transistor of FIG. 6 in detail.

Referring to FIG. 6, the transistor array substrate 10 according to the first embodiment includes a substrate 11 and a circuit layer 12 disposed on the substrate 11.

The substrate 11 includes a display area DA in which sub-pixels SPX are arranged, and the circuit layer 12 includes pixel drivers PXD corresponding to each of the sub-pixels SPX.

The transistor array substrate 10 may further include a light emitting device layer 13 disposed on the circuit layer 12. The light emitting device layer 13 may include light emitting devices (EMD) that respectively correspond to the sub-pixels (SPX) and are electrically connected to the pixel drivers (PXDs) of the circuit layer 12, respectively.

In addition, the transistor array substrate 10 may further include a sealing layer 14 disposed on the light emitting device layer 13.

Each of the pixel drivers PXD of the circuit layer 12 may include at least one thin film transistor T1 and T2. That is, each of the pixel drivers PXD of the circuit layer 12 may include a first thin film transistor T1 and a second thin film transistor T2.

According to the first embodiment, the circuit layer 12 is disposed flat on the substrate 11 and may further include an interlayer insulating layer 123 covering the first thin film transistor T1 and the second thin film transistor T2. You can.

The substrate 11 may be made of a rigid insulating material such as glass.

Alternatively, the substrate 11 may be made of an insulating material such as polymer resin. For example, the substrate 11 may be made of polyimide.

The substrate 11 may be a flexible substrate capable of bending, folding, rolling, etc.

The first thin film transistor T1 includes an active layer (ACT) disposed on the substrate 11, a gate insulating layer (GI) disposed on the channel area (CHA) of the active layer (ACT), and a gate insulating layer (GI). ) and a gate electrode (GE) disposed on the gate electrode (GE).

The active layer (ACT) includes a channel area (CHA), a source area (SA) connected to one side of the channel area (CHA), and a drain area (DA) connected to the other side of the channel area (CHA).

The active layer (ACT) may be made of one of the following semiconductor materials: poly silicon, amorphous silicon, and oxide semiconductor. The oxide semiconductor may contain one or more metals including indium (In), gallium (Ga), zinc (Zn), tin (Sn), aluminum (Al), and molybdenum (Mo), as well as oxygen (Oxyzene).

When the active layer (ACT) is made of an oxide semiconductor, the source area (SA) and drain area (DA) may be made conductive by containing a lower content of oxygen than the channel area (CHA).

The gate insulating layer (GI) may be made of a multilayer in which one or more inorganic layers of silicon nitride, silicon oxy nitride, silicon oxide, titanium oxide, and aluminum oxide are alternately stacked.

The gate electrode GE may include a main electrode layer (MNL) and an electrode barrier layer (BRL). The electrode barrier layer (BRL) may be disposed between the electrode main layer (MNL) and the gate insulating layer (GI), and between the side of the electrode main layer (MNL) and the interlayer insulating layer 123.

The electrode main layer (MNL) may be made of a metal material with relatively low specific resistance in order to lower the resistance of the gate electrode (GE).

As an example, the electrode main layer (MNL) is made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Among the metal materials, it may include a single layer or multiple layers made of at least one metal material, or may include an alloy of two or more metal materials.

The electrode barrier layer (BRL) can block the metal material of the electrode main layer (MNL) from diffusing, particularly from diffusing into the channel area (CHA) of the active layer (ACT) through the gate insulating layer (GI). This electrode barrier layer (BRL) may include a metal oxide material including one or more of indium (In), gallium (Ga), zinc (Zn), tin (Sn), aluminum (Al), and molybdenum (Mo). You can.

According to the first embodiment, the electrode barrier layer (BRL) is not only disposed between the lower surface of the electrode main layer (MNL) and the gate insulating layer (GI), but also the side surface of the electrode main layer (MNL) and the interlayer insulating layer 123. ) is also placed between. Accordingly, since the side surface of the electrode main layer (MNL) is not exposed to oxygen contained in the interlayer insulating layer 123, corrosion of the edge between the inclined side surface and the top surface of the electrode main layer (MNL) can be prevented. Therefore, the change in switching characteristics of the first thin film transistor T1 may be delayed, and the lifespan of the first thin film transistor T1 may be improved.

The interlayer insulating layer 123 may be disposed on the second buffer layer 122 and flatly cover the gate electrode (GE) and the active layer (ACT). That is, the interlayer insulating layer 123 may be in contact with the source area (SA) and drain area (DA) of the active layer (ACT), the side surface of the gate insulating layer (GI), and the top and side surfaces of the gate electrode (GE). .

The interlayer insulating layer 123 may be made of a multilayer in which one or more inorganic layers of silicon nitride, silicon oxy nitride, silicon oxide, titanium oxide, and aluminum oxide are alternately stacked.

According to the first embodiment, the circuit layer 12 includes a first buffer layer 121 disposed on the substrate 11, a light blocking layer (LSL) on the first buffer layer 121, and a second light blocking layer (LSL) covering the light blocking layer (LSL). It may further include a buffer layer 122.

That is, the first thin film transistor T1 is disposed on the first buffer layer 121 covering the substrate 11 and may further include a light blocking layer (LSL) overlapping at least the channel area (CHA) of the active layer (ACT). You can. Accordingly, the active layer ACT may be disposed on the second buffer layer 122 covering the light blocking layer LSL.

The light blocking layer (LSL) may include a light blocking metal material. As an example, the light blocking layer (LSL) is made of metals such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Among the materials, it may include a single layer or multiple layers made of at least one metal material, or an alloy of two or more metal materials.

Since the second thin film transistor T2 has substantially the same structure as the first thin film transistor T1, redundant description will be omitted below.

In addition, although not shown in FIG. 6 or the like, the third thin film transistor T3 has substantially the same structure as the first thin film transistor T1, and therefore duplicate description will be omitted below.

Referring to FIG. 7, the slope θ1 of the side of the gate electrode GE with respect to the interface between the gate insulating layer GI and the gate electrode GE is an obtuse angle. That is, the cross section of the gate electrode GE may have an inverted trapezoidal shape.

Additionally, due to the influence of the inclination (θ1) of the side of the gate electrode (GE), the inclination (θ2) of the side of the gate insulating layer (GI) with respect to the interface between the gate insulating layer (GI) and the gate electrode (GE) is an obtuse angle. am. That is, the cross-section of the gate insulating layer GI may have a trapezoidal shape. Accordingly, the slope of the side of the gate insulating layer (GI) with respect to the interface between the gate insulating layer (GI) and the active layer (ACT) may be at an acute angle.

In addition, as described later with reference to FIG. 12 and the like, the gate electrode GE is prepared through an ashing process, so that the cross-sectional shape of the gate electrode GE may be inverted trapezoidal.

That is, since the gate electrode GE is not prepared through a dry etching process, the side of the gate electrode GE can be prevented from having a sharp inclination close to vertical due to the dry etching process. As a result, the side surface of the gate insulating layer GI may not have a sharp slope close to being vertical.

Accordingly, a defect in which the active layer ACT is not completely covered by the interlayer insulating layer 123 due to a sharp slope of the side of the gate insulating layer GI can be prevented. Therefore, disconnection of the active layer (ACT) and deterioration of semiconductor characteristics can be prevented, and the lifespan and characteristic uniformity of the first thin film transistor (T1) can be improved.

As shown in FIG. 6, the circuit layer 12 of the transistor array substrate 10 according to the first embodiment includes a wiring conductive layer (LCDL) disposed on the interlayer insulating layer 123, and an interlayer insulating layer 123. It may further include a via layer 124 disposed flat on the surface and covering the wiring conductive layer (LCDL).

The wiring conductive layer (LCDL) includes a data line (DL) that transmits the data signal (VDATA), a first power line (VDL) that transmits the first power source (ELVDD), and a gate electrode (GE) of the second thin film transistor (T1). ) may include a gate connection electrode (GCE) electrically connected to and an anode connection electrode (ANCE) electrically connected to the source area (SA) of the active layer (ACT) of the first thin film transistor (T1).

The anode connection electrode ANCE may be electrically connected to the source area SA of the active layer ACT of the first thin film transistor T1 and the light blocking layer LSL of the first thin film transistor T1.

The anode connection electrode (ANCE) may be electrically connected to the source area (SA) of the active layer (ACT) of the first thin film transistor (T1) through the first anode connection hole (ANCH1) penetrating the interlayer insulating layer 123. there is.

The anode connection electrode (ANCE) is electrically connected to the light blocking layer (LSL) of the first thin film transistor (T1) through the second anode connection hole (ANCH2) penetrating the interlayer insulating layer 123 and the second buffer layer 122. You can.

As a result, the light blocking layer (LSL) of the first thin film transistor (T1) is electrically connected to the source area (SA) of the active layer (ACT) of the first thin film transistor (T1) through the anode connection electrode (ANCE), 1 The resistance between the thin film transistor (T1) and the light emitting device (EMD) can be lowered.

The gate connection electrode (GCE) may be electrically connected to the gate electrode (GE) of the second thin film transistor (T2) through the first gate connection hole (GCH1) penetrating the interlayer insulating layer 123.

The gate connection electrode (GCE) is electrically connected to the light blocking layer (LSL) of the second thin film transistor (T2) through the second gate connection hole (GCH2) penetrating the interlayer insulating layer 123 and the second buffer layer 122. You can.

Accordingly, since the light blocking layer (LSL) of the second thin film transistor (T2) becomes a bottom gate electrode disposed below the active layer (ACT), the second thin film transistor (T2) can be provided with a double gate structure. As a result, the characteristic curve of the second thin film transistor T2 may become gentle. Here, the characteristic curve represents the change in the magnitude of drain-source current according to the change in gate-source voltage.

The data line DL may be electrically connected to the drain area DA of the active layer ACT of the second thin film transistor T2 through the data connection hole DCH penetrating the interlayer insulating layer 123.

The first power line (VDL) may be electrically connected to the drain area (DA) of the active layer (ACT) of the first thin film transistor (T1) through the power connection hole (VDCH) penetrating the interlayer insulating layer 123. .

The wiring conductive layer (LCDL) is made of metal materials such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). It may include a single layer or multiple layers made of at least one metal material, or an alloy of two or more metal materials.

The via layer 124 may be disposed flat on the interlayer insulating layer 122. This via layer 123 may be made of an organic film such as acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. there is.

The circuit layer 12 includes a first capacitor electrode (CAE1) disposed on the first buffer layer 121, and a second capacitor electrode (CAE2) disposed on the second buffer layer 122 and overlapping the first capacitor electrode (CAE1). ), and a third capacitor electrode (CAE3) disposed on the interlayer insulating layer 123 and overlapping the second capacitor electrode (CAE2).

The second capacitor electrode CAE2 may be made of a conductive semiconductor material, like the source area SA and drain area DA of the active layer ACT.

Although not separately shown, the first capacitor electrode CAE1 may be connected to the light blocking layer LSL of the first thin film transistor T1 in a plane view. The second capacitor electrode CAE2 may be electrically connected to the gate electrode GE of the first thin film transistor T1. Additionally, the third capacitor electrode CAE3 may be connected to the anode connection electrode ANCE.

In this case, the light blocking layer (LSL) of the first thin film transistor (T1) is electrically connected to the anode connection electrode (ANCE), so the first capacitor electrode (CAE1) and the third capacitor electrode (CAE3) are connected to the first thin film transistor ( Like the source area (SA) of the active layer (ACT) of T1), it corresponds to the second node (N2). And, the second capacitor electrode CAE2 corresponds to the first node N1, like the gate electrode GE of the first thin film transistor T1.

As a result, the pixel capacitor PC can be provided by the overlapping area between each of the first and third capacitor electrodes CAE1 and CAE3 and the second capacitor electrode CAE2.

The light emitting device layer 13 includes light emitting devices (EMD) corresponding to each sub-pixel (PX). One of the light emitting devices (EMD) is interposed between the anode electrode 131 and the cathode electrode 132, and the anode electrode 131 and the cathode electrode 132, and is made of a photoelectric conversion material. It may include a light-emitting layer 133 formed.

The light emitting device layer 13 may further include a pixel definition layer 132 covering an edge of the anode electrode (AND).

The anode electrode 131 is disposed on the via layer 124, corresponds to each of the sub-pixels (SPX), and is connected to the anode connection electrode (ANCE) through the third anode contact hole (ANCH3) penetrating the via layer 124. ) can be electrically connected to.

Accordingly, the anode electrode 131 can be electrically connected to the source area (SA) of the active layer (ACT) of the first thin film transistor (T1) through the anode connection electrode (ANCE).

The pixel definition layer 132 is disposed on the via layer 124, corresponds to the spaced area between the sub-pixels (SPX), and may cover the edge of the anode electrode 131.

The pixel definition layer 132 may be disposed flat on the interlayer insulating layer 122. This via layer 123 may be made of an organic film such as acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. there is.

The light emitting layer 133 may be disposed on the anode electrode 131.

The cathode electrode 134 generally corresponds to the sub-pixels (SPX) and may be disposed on the light emitting layer 133 and the pixel definition layer 132.

The sealing layer 14 blocks oxygen or moisture from penetrating into the circuit layer 12 and the light-emitting device layer 13, and protects the circuit layer 12 and the light-emitting device layer 13 from physical and electrical shock caused by foreign substances, etc. It is for this purpose.

The sealing layer 14 may have a structure in which at least one inorganic layer and at least one organic layer are alternately stacked. As an example, the sealing layer 14 includes a first inorganic layer 141 disposed on the light emitting device layer 13 and made of an inorganic insulating material, and an organic layer disposed on the first inorganic layer 141 and made of an organic insulating material ( 142), and a second inorganic layer 143 disposed on the first inorganic layer 141, covering the organic layer 142, and made of an inorganic insulating material.

As described above, according to the first embodiment, the slope of the side of the gate electrode (GE) and the slope of the side of the gate insulating layer (GI) are respectively based on the interface between the gate electrode (GE) and the gate insulating layer (GI). It can be provided at an obtuse angle. That is, the gate electrode GE may have a cross-section of an inverted trapezoid, and the gate insulating layer GI may have a cross-section of a trapezoid.

Also, since the slope of the side of the gate electrode GE is not affected by dry etching, it may be relatively gentle. As a result, the slope of the side of the gate insulating layer GI may also be relatively gentle. Therefore, reliability that the active layer ACT is completely covered with the interlayer insulating layer 123 can be improved.

As a result, disconnection of the active layer ACT and deterioration of semiconductor characteristics can be prevented, and therefore, deterioration of lifespan and characteristic uniformity of the thin film transistors T1 and T2 can be prevented.

The transistor array substrate 10 including such thin film transistors T1 and T2 can be easily applied to the high-resolution display device 1 and can lead to improved image quality of the display device 1.

FIG. 8 is a cross-sectional view showing a second embodiment of the first thin film transistor, the second thin film transistor, and the pixel capacitor of the pixel driver of FIG. 5.

The transistor array substrate 10 according to the second embodiment is substantially the same as the first embodiment of FIGS. 6 and 7 except that the second buffer layer 122' is disposed flat, so duplicate descriptions are provided below. omit.

According to the second embodiment, the second buffer layer 122' is disposed flat on the first buffer layer 121 and covers the light blocking layer (LSL) and the first capacitor electrode (CAE1).

For example, the second buffer layer 122' according to the second embodiment may be prepared by flattening the insulating material layer laminated on the first buffer layer 121 through an ashing process or the like.

According to the second embodiment, as the second buffer layer 122' is disposed flat, disconnection or separation defects of the active layer ACT disposed on the second buffer layer 122' can be prevented. As a result, the characteristic uniformity of the thin film transistors T1 and T2 can be improved.

FIG. 9 is a cross-sectional view showing a third embodiment of the first thin film transistor, the second thin film transistor, and the pixel capacitor of the pixel driver of FIG. 5.

Referring to FIG. 9, the transistor array substrate 10 according to the third embodiment is except that the interlayer insulating layer 123' includes a first interlayer insulating layer 1231 and a second interlayer insulating layer 1232. Since it is substantially the same as the first embodiment shown in FIGS. 6 and 7 or the second embodiment shown in FIG. 8, overlapping descriptions will be omitted below.

The first interlayer insulating layer 1231 is disposed on the second buffer layer 122' and includes the source area (SA) and drain area (DA) of the active layer (ACT), the gate insulating layer (GI), and the gate electrode (GE). You can come into contact with. The first interlayer insulating layer 1231 may contact the side of the gate insulating layer (GI) and the top and side surfaces of the gate electrode (GE).

The first interlayer insulating layer 1231 may be disposed to have a thickness greater than or equal to a critical thickness that completely covers the side of the active layer (ACT), the side of the gate insulating layer (GI), and the side of the gate electrode (GE). Accordingly, the reliability of the active layer (ACT), gate insulating layer (GI), and gate electrode (GE) being covered by the first interlayer insulating layer 1231 can be improved.

The second interlayer insulating layer 1232 is disposed flat on the first interlayer insulating layer 1231.

For example, the second interlayer insulating layer 1232 according to the third embodiment may be prepared by flattening the insulating material layer laminated on the first interlayer insulating layer 1231 through an ashing process or the like.

According to the third embodiment, the interlayer insulating layer 123' can be arranged flat, and the reliability of the active layer ACT and the gate electrode GE being completely covered by the interlayer insulating layer 123' is low. It can be improved.

FIG. 10 is a cross-sectional view showing a fourth embodiment of the first thin film transistor, the second thin film transistor, and the pixel capacitor of the pixel driver of FIG. 5.

Referring to FIG. 10, the transistor array substrate 10 according to the fourth embodiment is except that the side surfaces of each of the light blocking layer (LSL') and the first capacitor electrode (CAE1') are in contact with the first buffer layer (121'). In other words, since it is substantially the same as the first embodiment shown in FIGS. 6 and 7, the second embodiment shown in FIG. 8, or the third embodiment shown in FIG. 9, overlapping descriptions will be omitted below.

According to the fourth embodiment, the light blocking layer (LSL') and the first capacitor electrode (CAE1') are respectively disposed in the grooves of the first buffer layer (121'), so that the light blocking layer (LSL') and the first capacitor electrode ( The step difference due to CAE1') can be reduced.

As a result, the second buffer layer 122' can be arranged more flatly, and thus disconnection or separation defects of the active layer ACT disposed on the second buffer layer 122' can be further prevented.

Next, a method for manufacturing a transistor array substrate according to an embodiment will be described.

Figure 11 is a flowchart showing a method of manufacturing a transistor array substrate according to an embodiment. FIG. 12 is a flowchart showing detailed steps of arranging the gate insulating layer and gate electrode of FIG. 11 . Figures 13 to 34 are process diagrams for some steps in Figures 11 and 12.

Referring to FIG. 11, a method of manufacturing a transistor array substrate according to an embodiment includes a substrate 11 including a display area DA in which the sub-pixels SPX are arranged, each corresponding to the sub-pixels SPX. A step S10 of disposing a circuit layer 12 including pixel drivers PXD each including at least one thin film transistor T1, T2, and T3, and forming a sub-pixel SPX on the circuit layer 12. It includes a step (S20) of disposing the light emitting device layer 13 including light emitting devices (EMD) corresponding to the pixel drivers (PXDs) and electrically connected to each of the pixel drivers (PXDs).

Additionally, the method of manufacturing the transistor array substrate may further include disposing the sealing layer 14 on the light emitting device layer 13 (S30).

According to one embodiment, the step of disposing the circuit layer 12 (S10) includes the step of disposing the thin film transistors (T1 and T2) on the substrate 11 (S110) and covering the thin film transistors (T1 and T2). It includes the step of disposing the interlayer insulating layer 123 (S120).

In addition, the step of arranging the circuit layer 12 (S10) includes connection holes (ANCH1, ANCH2, GCH1, GCH2) penetrating at least the interlayer insulating layer 123 among the interlayer insulating layer 123 and the second buffer layer 122. , DCH, VDCH), then disposing a wiring conductive layer (LCDL) on the interlayer insulating layer 123 (S130), and disposing a via layer 124 covering the wiring conductive layer (LCDL). (S140) may be further included.

Accordingly, in the step of disposing the light emitting device layer 13 (S20), the light emitting device layer 13 may be disposed on the via layer 124.

According to one embodiment, the step of disposing the thin film transistors T1 and T2 (S110) includes the step of disposing the first buffer layer 121 on the substrate 11 (S111) and blocking light on the first buffer layer 121. A step of disposing a layer (LSL) (S112), a step of disposing a second buffer layer 122 covering the light blocking layer (LSL) on the first buffer layer 121 (S113), a semiconductor layer on the second buffer layer 122 It includes disposing a material layer (PACT in FIG. 15) (S114), and disposing a gate insulating layer (GI) and a gate electrode (GE) on a portion of the semiconductor material layer (PACT) (S115).

In the step of disposing the gate insulating layer GI and the gate electrode GE (S115), the slope of the side of the gate electrode GE with respect to the interface between the gate insulating layer GI and the gate electrode GE is an obtuse angle. Additionally, the slope of the side of the gate insulating layer (GI) with respect to the interface between the gate insulating layer (GI) and the gate electrode (GE) is an obtuse angle.

As shown in FIG. 12, according to one embodiment, the step of disposing the gate insulating layer GI and the gate electrode GE (S115) is an etching process for the insulating material layer (202 in FIG. 16) and a metal It may be the shape of the gate electrode (GE) and the shape of the gate insulating layer (GI) resulting from the ashing process for the material layer (204 in FIG. 19).

As shown in FIG. 12, according to one embodiment, the step (S115) of disposing the gate insulating layer (GI) and the gate electrode (GE) is performed by covering the semiconductor material layer (PACT) on the second buffer layer 122. Step (S1151) of disposing an insulating material layer (202 in FIG. 16) with a thickness of 1 (TH1 in FIG. 16), partially etching the insulating material layer 202 to create insulation that overlaps a portion of the semiconductor material layer (PACT) Changing a portion of the material layer 202 to a second thickness (TH2 in FIG. 17) smaller than the first thickness TH1 (S1152), forming a metal oxide material layer (203 in FIG. 18) on the insulating material layer 202 ), a step of disposing (S1153), a step of disposing a metal material layer (204 in FIG. 19) on the metal oxide material layer 203 (S1154), and the insulating material layer 202 of the first thickness TH1 is exposed. By performing ashing treatment on the metal material layer 204 and the metal oxide material layer 203 until A step of providing a gate electrode (GE) including an electrode barrier layer (BRL) and an electrode main layer (MNL) made of a metal material layer 204 remaining on the electrode barrier layer (BRL) (S1155), and an insulating material An etching process is performed on the layer 202 to remove the first thickness TH1 of the insulating material layer 202 and the second thickness TH2 remaining between the gate electrode GE and the semiconductor material layer PACT. ) may include providing a gate insulating layer (GI) with the insulating material layer 202 (S1156).

Referring to FIG. 13 , a first buffer layer 121 covering the substrate 11 may be disposed by laminating an inorganic insulating material on the substrate 11 . (S111)

The substrate 11 may be made of an insulating material such as glass.

Thereafter, the light blocking material on the first buffer layer 121 may be partially etched to form a light blocking layer (LSL). (S112)

At this time, the first capacitor electrode CAE1 may be further disposed along with the light blocking layer LSL.

The light blocking material is at least one of the following metal materials: molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). It may include a single layer or multiple layers made of a metal material, or an alloy of two or more metal materials.

In consideration of higher resolution, the etching process for the light-shielding material can be performed by dry etching, which has a relatively lower process error than wet etching.

Next, an inorganic insulating material is laminated on the first buffer layer 121, the light blocking layer (LSL), and the first capacitor electrode (CAE1), thereby forming a second buffer layer covering the light blocking layer (LSL) and the first capacitor electrode (CAE1) 122) can be placed. (S113)

Each of the first buffer layer 121 and the second buffer layer 122 may be made of a multilayer in which one or more inorganic layers selected from the group consisting of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide are alternately stacked.

When preparing the transistor array substrate 10 of the second embodiment, as shown in FIG. 14, the step (S113) of disposing the second buffer layer 122' is an inorganic insulation layer laminated on the first buffer layer 121. It may include performing an ashing process on the material 201 to provide a flatly disposed second buffer layer 122'.

Referring to FIG. 15 , the semiconductor material layer PACT may be disposed by partially etching the semiconductor material stacked on the second buffer layer 122'. (S114)

The semiconductor material layer (PACT) is a preliminary component prepared as the active layer (ACT) of the thin film transistors (T1 and T2) in subsequent steps.

At this time, a free capacitor electrode PCAE2 that overlaps the first capacitor electrode CAE1 may be further disposed along with the semiconductor material layer PACT. The pre-capacitor electrode PCAE2 is a preliminary component prepared as the second capacitor electrode CAE2 in subsequent steps.

The semiconductor material may be made of one of poly silicon, amorphous silicon, and oxide semiconductor. The oxide semiconductor may contain one or more metals including indium (In), gallium (Ga), zinc (Zn), tin (Sn), aluminum (Al), and molybdenum (Mo), as well as oxygen (Oxyzene).

Referring to FIG. 16, an insulating material is stacked on the second buffer layer 122' and the semiconductor material layer (PACT) to cover the semiconductor material layer (PACT) on the second buffer layer 122' and form a first thickness ( An insulating material layer 202 made of TH1) may be disposed. (S1151)

The insulating material layer 202 may be made of a multilayer in which one or more inorganic layers of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide are alternately stacked.

Referring to FIG. 17, the insulating material layer 202 laminated on the second buffer layer 122' is partially etched, and a portion of the insulating material layer 202 overlapping with a portion of the semiconductor material layer (PACT) is etched. It may be changed to a second thickness (TH2) that is smaller than the first thickness (TH1). (S1152)

Here, the insulating material layer 202 of the second thickness TH2 may be provided by a groove (GROOVE) disposed in the insulating material layer 202 of the first thickness TH1.

Since the groove of the insulating material layer 202 corresponding to the insulating material layer 202 of the second thickness TH2 becomes the mold of the gate electrode GE through subsequent steps, the first thickness TH1 and the second thickness TH1 The difference between the thicknesses TH2, that is, the thickness of the groove of the insulating material layer 202, may be greater than or equal to the thickness of the gate electrode GE. In addition, in consideration of stacking defects of the interlayer insulating layer 123 due to the inclination of the side of the gate electrode GE, a groove in the insulating material layer 202 corresponding to the insulating material layer 202 of the second thickness TH2 is formed. may include aspects of gentle slope.

In addition, in consideration of the ease of the etching process for placing the gate insulating layer (GI), the groove of the insulating material layer 202 corresponding to the insulating material layer 202 of the second thickness (TH2) has an inverted trapezoidal shape. It can have a cross section of .

Referring to FIG. 18 , the metal oxide material layer 203 may be disposed by stacking a metal oxide material on the insulating material layer 202 including the groove. (S1153)

The metal oxide material layer 203 includes oxygen (Oxyzene) and one or more metals of indium (In), gallium (Ga), zinc (Zn), tin (Sn), aluminum (Al), and molybdenum (Mo). can do. Additionally, the metal oxide material layer 203 may be conductive.

Referring to FIG. 19, the metal material layer 204 may be disposed by stacking a metal material on the metal oxide material layer 203. (S1154)

The metal material layer 204 is made of metal materials such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). It may include a single layer or multiple layers made of at least one metal material, or an alloy of two or more metal materials.

The total thickness of the metal oxide material layer 203 and the metal material layer 204 may be less than or equal to the thickness of the groove of the insulating material layer 202.

Subsequently, as shown in the horizontal dotted line in FIG. 19, ashing processing is performed on the metal oxide material layer 203 and the metal material layer 204 until the insulating material layer 202 of the first thickness TH1 is exposed. You can.

Therefore, as shown in FIG. 20, a portion of each of the metal oxide material layer 203 and the metal material layer 204 disposed on the insulating material layer 202 of the first thickness TH1 may be removed. That is, the remaining portions of each of the metal oxide material layer 203 and the metal material layer 204 may remain in the groove of the insulating material layer 202 corresponding to the insulating material layer 202 of the second thickness TH2. . In this way, the electrode barrier layer (BRL) and the electrode main layer (MNL) composed of the remaining metal oxide material layer 203 and the metal material layer 204, respectively, are prepared, so that the electrode barrier layer (BRL) and the electrode main layer (MNL) are formed. ) may be provided. (S1155)

The gate electrode GE may be formed in a shape defined by a groove in the insulating material layer 202 corresponding to the insulating material layer 202 of the second thickness TH2.

Referring to FIG. 21, the insulating material layer 202 of the first thickness TH1 may be removed by etching the insulating material layer 202 while using the gate electrode GE as a mask. . As a result, the insulating material layer 202 of the second thickness TH2 disposed between the gate electrode GE and the semiconductor material layer PACT remains, and the gate insulating layer GI can be prepared. (S1156)

In consideration of higher resolution, the etching process for the insulating material layer 202 may be performed by dry etching, which has a relatively lower process error than wet etching.

At this time, since the side of the gate electrode (GE) has a relatively gentle slope, even if dry etching is performed on the insulating material layer 202, due to the gentle slope of the side of the gate electrode (GE), the gate insulating layer ( The slope of the side of GI) can be relatively gentle.

In addition, when the insulating material layer 202 of the first thickness TH1 is removed, the remaining portion of the semiconductor material layer PACT, excluding the portion overlapping with the gate insulating layer GI, is etched. It can be made conductive by exposure to an etching material.

As a result, the channel area (CHA) consists of a part of the semiconductor material layer (PACT) that overlaps the gate electrode (GE), and other parts disposed at both ends of the channel area (CHA) of the semiconductor material layer (PACT) and are conductive. An active layer (ACT) including a source area (SA) and a drain area (DA) may be provided.

Accordingly, thin film transistors T1 and T2 including a light blocking layer (LSL), an active layer (ACT), and a gate electrode (GE) may be disposed on the substrate 110. (S110)

Additionally, when the insulating material layer 202 of the first thickness TH1 is removed, the pre-capacitor electrode PCAE2 is exposed to the etching material and becomes conductive, thereby forming the second capacitor electrode CAE2.

Next, referring to FIGS. 23 and 24 , after placing the insulating material 205 covering the thin film transistors T1 and T2 on the substrate 11, an ashing process is performed on the insulating material 205 to form a flat surface. An interlayer insulating layer 123 may be provided. (S120)

The interlayer insulating layer 123 is formed on the source area (SA) and drain area (DA) of the active layer (ACT) of the thin film transistors (T1 and T2), the side surface of the gate insulating layer (GI), and the top surface of the gate electrode (GE). and can be accessed from the side.

The interlayer insulating layer 123 may be made of a multilayer in which one or more inorganic layers of silicon nitride, silicon oxy nitride, silicon oxide, titanium oxide, and aluminum oxide are alternately stacked.

Alternatively, when preparing the transistor array substrate 10 of the third embodiment, the step of disposing the interlayer insulating layer 123' includes disposing the first interlayer insulating layer 1231, and the step of disposing the first interlayer insulating layer 1231. It may include the step of laminating an insulating material on the first interlayer insulating layer 1231, and performing an ashing treatment on the insulating material on the first interlayer insulating layer 1231 to provide a second interlayer insulating layer 1232 arranged flatly. .

That is, as shown in FIG. 24, an insulating material is stacked on the thin film transistors T1 and T2, so that the source area (SA) and drain area (DA) of the active layer (ACT) of the thin film transistors (T1 and T2) are formed. A gate insulating layer (GI) and a first interlayer insulating layer 1231 in contact with the gate electrode (GE) may be disposed.

As shown in FIG. 25, the insulating material 205 is laminated on the first interlayer insulating layer 1231, and ashing treatment may be performed on the insulating material 205.

As a result, as shown in FIG. 26, the second interlayer insulating layer 1232 is arranged flat on the first interlayer insulating layer 1231, so that the first interlayer insulating layer 1231 and the second interlayer insulating layer ( An interlayer insulating layer 123' including 1232) may be provided.

Next, as shown in FIG. 27, a partial etching process is performed on at least the interlayer insulating layer 123' among the interlayer insulating layer 123' and the second buffer layer 122' to form the connection holes ANCH1 and ANCH2. , GCH1, GCH2, DCH, VDCH) may be provided.

Thereafter, as shown in FIG. 28, the conductive material on the interlayer insulating layer 123' may be partially etched, and a conductive wiring layer (LCDL) may be disposed. (S130)

The wiring conductive layer (LCDL) includes a data line (DL) that transmits the data signal (VDATA), a first power line (VDL) that transmits the first power source (ELVDD), and a gate electrode (GE) of the second thin film transistor (T1). ), an anode connection electrode (ANCE) electrically connected to the source area (SA) of the active layer (ACT) of the first thin film transistor (T1), and a second capacitor electrode ( It may include a third capacitor electrode (CAE3) overlapping with CAE2).

As shown in FIG. 29, an insulating material is stacked on the interlayer insulating layer 123' to provide a via layer 124 that is placed flat on the interlayer insulating layer 123' and covers the wiring conductive layer (LCDL). It can be. (S140)

The via layer 124 may be made of an organic film such as acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. .

As a result, the circuit layer 12 including thin film transistors T1 and T2, an interlayer insulating layer 123', a conductive wiring layer (LCDL), and a via layer 124 can be disposed on the substrate 11. (S10)

Next, referring to FIG. 30, on the via layer 124 of the circuit layer 120, a light emitting device layer including an anode electrode 131, a pixel definition layer 132, a light emitting layer 133, and a cathode electrode 134. (13) can be arranged. (S20)

Next, referring to FIG. 31, a sealing layer 14 including a first inorganic layer 141, an organic layer 142, and a second inorganic layer 143 may be disposed on the light emitting device layer 13. (S30)

Meanwhile, when preparing the transistor array substrate 10 of the fourth embodiment, the light blocking layer (LSL) may be prepared through an ashing process rather than an etching process for a metal material.

That is, referring to FIG. 31, in the step of disposing the first buffer layer 121 (S111), the first buffer layer 121 may have a third thickness TH3.

Referring to FIG. 32, by partially etching the first buffer layer 121, a portion of the first buffer layer 121' may be changed to a fourth thickness TH4 that is smaller than the third thickness TH3.

Here, the first buffer layer 121' of the fourth thickness TH4 may be provided by a groove disposed in the first buffer layer 121' of the third thickness TH3.

The groove of the first buffer layer 121' corresponding to the first buffer layer 121' of the fourth thickness TH4 becomes the mold for the light blocking layer LSL and the first capacitor electrode CAE1 in the subsequent steps. , the difference between the third thickness TH3 and the fourth thickness TH4, that is, the thickness of the groove of the first buffer layer 121', may be greater than or equal to the thickness of the light blocking layer LSL.

Next, referring to FIG. 33, a light blocking material layer 206 may be disposed on the first buffer layer 121'.

Subsequently, as shown in the horizontal dotted line in FIG. 33, ashing processing may be performed on the light blocking material layer 206 until the first buffer layer 121' of the third thickness TH3 is exposed.

Therefore, as shown in FIG. 34, a part of the light blocking material layer 206 disposed on the first buffer layer 121' of the third thickness TH3 is removed, so that the other remaining part of the light blocking material layer 206 is removed. By remaining in the groove of the first buffer layer 121' corresponding to the first buffer layer 121' of the fourth thickness TH4, the light blocking layer LSL' and the first capacitor electrode CAE1' can be provided. there is.

In this way, each side of the light blocking layer (LSL') and the first capacitor electrode (CAE1') prepared through the etching process for the first buffer layer 121 and the ashing process for the light blocking material layer 206 is formed with a first buffer layer ( 121').

As described above, in the method of manufacturing a transistor array substrate according to an embodiment, dry etching of the metal material is not performed when the gate electrode GE is disposed, so the side of the gate electrode GE is sharply close to vertical. Having a tilt can be prevented. Therefore, even if dry etching is used when arranging the gate insulating layer (GI), due to the influence of the inclination of the side of the gate electrode (GE), the side of the gate insulating layer (GI) has a steep inclination to the extent of being close to vertical. It can be prevented from having . Accordingly, defective stacking of the interlayer insulating layer 123 due to the slope of the side of the gate insulating layer GI can be prevented, and thus the lifespan and characteristic uniformity of the thin film transistors T1 and T2 can be prevented from being deteriorated. .

Accordingly, thin film transistors (T1, T2) can be prepared in which the gate electrode (GE) contains a metal material, so that the resistance can be lowered, and the decrease in lifespan and characteristic uniformity due to poor stacking of the interlayer insulating layer 123 is prevented. there is.

Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention can be implemented in other specific forms without changing its technical idea or essential features. You will be able to understand it. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive.

1: Display device 10: Transistor array substrate
20: cover substrate 31: display driving circuit
32: circuit board 11: board
12: circuit layer 13: light emitting element layer
14: Sealing layer SPX: Sub pixel
DA: Display area NDA: Non-display area
SGL: Scan gate wiring DL: Data wiring
VDL: 1st power wiring VSL: 2nd power wiring
VIL: Initialization voltage wiring IGL: Initialization gate wiring
PXD: Pixel driver EMD: Light emitting device
T1, T2, T3: first, second, third thin film transistors
PC: Pixel Capacitor
ACT: Active layer CHA: Channel area
SA: Source area DA: Drain area
GE: Gate electrode GI: Gate insulating layer
121, 121': first buffer layer 122, 122': second buffer layer
123, 123': interlayer insulating layer 124: via layer
1231, 1232: first and second interlayer insulating layers
LSL: light blocking electrode
CAE1, CAE2, CAE3: first, second, third capacitor electrodes

Claims (26)

An active layer disposed on a substrate and including a channel region, a source region connected to one side of the channel region, and a drain region connected to the other side of the channel region;
a gate insulating layer disposed on the channel region of the active layer; and
It includes a gate electrode disposed on the gate insulating layer,
The slope of the side of the gate electrode with respect to the interface between the gate insulating layer and the gate electrode is an obtuse angle,
A thin film transistor wherein the slope of the side of the gate insulating layer with respect to the interface between the gate insulating layer and the gate electrode is an obtuse angle. According to claim 1,
The active layer and the gate electrode are covered with an interlayer insulating layer disposed flat on the substrate,
The gate electrode is
Electrode main layer; and
A thin film transistor comprising an electrode barrier layer disposed between the electrode main layer and the gate insulating layer, and between a side of the electrode main layer and the interlayer insulating layer. According to clause 2,
The electrode main layer is made of at least one metal material of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Contains a single layer or multiple layers of one metallic material, or an alloy of two or more metallic materials,
The electrode barrier layer is a thin film transistor comprising a metal oxide material including one or more of indium (In), gallium (Ga), zinc (Zn), tin (Sn), aluminum (Al), and molybdenum (Mo). According to clause 2,
The active layer includes an oxide semiconductor material including one or more metal materials among indium (In), gallium (Ga), zinc (Zn), tin (Sn), aluminum (Al), and molybdenum (Mo),
A thin film transistor in which the source region and the drain region of the active layer are in a conductive state. According to clause 2,
The interlayer insulating layer is
a first interlayer insulating layer in contact with the source and drain regions of the active layer, the gate insulating layer, and the gate electrode; and
A thin film transistor including a second interlayer insulating layer flatly disposed on the first interlayer insulating layer. According to clause 2,
It further includes a light blocking layer disposed on the first buffer layer covering the substrate and overlapping at least the channel region of the active layer,
The active layer is a thin film transistor disposed on a second buffer layer covering the light blocking layer. According to clause 6,
A thin film transistor wherein the second buffer layer is arranged flat. According to clause 6,
A thin film transistor wherein a side of the light blocking layer is in contact with the first buffer layer. According to clause 6,
The light blocking layer is made of at least one of the following metal materials: molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). A thin film transistor comprising a single layer or multiple layers of a metal material or an alloy of two or more metal materials. A substrate including a display area where sub-pixels are arranged; and
A circuit layer disposed on the substrate and including pixel drivers corresponding to each of the sub-pixels,
Each of the pixel drivers includes at least one thin film transistor,
A thin film transistor in one of the circuit layers is
an active layer disposed on the substrate and including a channel region, a source region connected to one side of the channel region, and a drain region connected to the other side of the channel region;
a gate insulating layer disposed on the channel region of the active layer; and
It includes a gate electrode disposed on the gate insulating layer,
The slope of the side of the gate electrode with respect to the interface between the gate insulating layer and the gate electrode is an obtuse angle,
A transistor array substrate wherein the slope of the side of the gate insulating layer with respect to the interface between the gate insulating layer and the gate electrode is an obtuse angle. According to claim 10,
The circuit layer is
Further comprising an interlayer insulating layer covering the active layer and the gate electrode and disposed flat on the substrate,
The gate electrode is
Electrode main layer; and
A transistor array substrate comprising an electrode barrier layer disposed between the electrode main layer and the gate insulating layer, and between a side of the electrode main layer and the interlayer insulating layer. According to claim 11,
The electrode main layer is made of at least one metal material of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Contains a single layer or multiple layers of one metallic material, or an alloy of two or more metallic materials,
The electrode barrier layer is a transistor array substrate comprising a metal oxide material including one or more metal materials selected from indium (In), gallium (Ga), zinc (Zn), tin (Sn), aluminum (Al), and molybdenum (Mo). . According to claim 11,
The interlayer insulating layer is
a first interlayer insulating layer in contact with the source and drain regions of the active layer, the gate insulating layer, and the gate electrode; and
A transistor array substrate including a second interlayer insulating layer flatly disposed on the first interlayer insulating layer. According to claim 11,
The thin film transistor of one of the circuit layers further includes a light blocking layer disposed on a first buffer layer covering the substrate and overlapping at least the channel region of the active layer,
The active layer is a transistor array substrate disposed on a second buffer layer covering the light blocking layer. According to claim 14,
A transistor array substrate wherein the second buffer layer is arranged flat. According to claim 14,
A transistor array substrate where a side of the light blocking layer is in contact with the first buffer layer. According to claim 14,
Further comprising a light emitting device layer disposed on the circuit layer and including light emitting devices electrically connected to the pixel drivers, respectively,
One of the pixel drivers transmits a driving current to one of the light-emitting devices,
The one pixel driver
a first thin film transistor connected in series with the one light-emitting device between first and second power lines that respectively transmit first and second power supplies for driving the light-emitting devices;
a second thin film transistor electrically connected between a data line transmitting a data signal and a gate electrode of the first thin film transistor and turned on based on a scan signal of the scan gate line; and
A pixel capacitor electrically connected to a first node between the gate electrode of the first thin film transistor and the second thin film transistor, and a second node between the first thin film transistor and the one light emitting device,
The first electrode of the first thin film transistor is electrically connected to the first power wiring,
A transistor array substrate wherein the second electrode of the first thin film transistor is electrically connected to the anode electrode of the one light-emitting device. According to claim 17,
The circuit layer is
a wiring conductive layer disposed on the interlayer insulating layer; and
It further includes a via layer disposed flat on the interlayer insulating layer and covering the wiring conductive layer,
The wiring conductive layer is
the data wiring;
the first power wiring;
a gate connection electrode electrically connecting the gate electrode of the second thin film transistor and the light blocking layer of the second thin film transistor; and
It includes an anode connection electrode electrically connected to the source region of the active layer of the first thin film transistor and the light blocking layer of the first thin film transistor,
The anode electrode is disposed on the via layer and electrically connected to the anode connection electrode. According to clause 18,
The circuit layer is
a first capacitor electrode disposed on the first buffer layer;
a second capacitor electrode disposed on the second buffer layer and overlapping the capacitor electrode; and
It further includes a third capacitor electrode disposed on the interlayer insulating layer and overlapping the second capacitor electrode,
The pixel capacitor is provided in an overlap area between each of the first capacitor electrode and the third capacitor electrode and the second capacitor electrode. Arranging a circuit layer including pixel drivers corresponding to the sub-pixels and each including at least one thin film transistor on a substrate including a display area where sub-pixels are arranged; and
On the circuit layer, disposing a light-emitting device layer including light-emitting devices corresponding to the sub-pixels and electrically connected to the pixel drivers, respectively,
The step of arranging the circuit layer is
Placing a thin film transistor on the substrate; and
It includes disposing an interlayer insulating layer covering the thin film transistor on the substrate,
The step of placing the thin film transistor is
disposing a first buffer layer on the substrate;
disposing a light blocking layer on the first buffer layer;
disposing a second buffer layer covering the light blocking layer on the first buffer layer;
disposing a layer of semiconductor material on the second buffer layer; and
disposing a gate insulating layer and a gate electrode on a portion of the semiconductor material layer;
The slope of the side of the gate electrode with respect to the interface between the gate insulating layer and the gate electrode is an obtuse angle,
A method of manufacturing a transistor array substrate wherein the slope of the side of the gate insulating layer with respect to the interface between the gate insulating layer and the gate electrode is an obtuse angle. According to claim 20,
In the step of disposing the gate insulating layer and the gate electrode, the gate electrode is
Electrode main layer; and
A method of manufacturing a transistor array substrate including an electrode barrier layer disposed between the electrode main layer and the gate insulating layer, and between a side of the electrode main layer and the interlayer insulating layer. According to claim 20,
The step of arranging the gate insulating layer and the gate electrode includes,
disposing a layer of insulating material of a first thickness covering the layer of semiconductor material on the second buffer layer;
partially etching the insulating material layer to change a portion of the insulating material layer that overlaps a portion of the semiconductor material layer to a second thickness that is less than the first thickness;
disposing a layer of metal oxide material on the layer of insulating material;
disposing a layer of metal material on the layer of metal oxide material;
An electrode barrier made of the metal oxide material layer remaining on the insulating material layer of the second thickness by performing an ashing process on the metal material layer and the metal oxide material layer until the insulating material layer of the first thickness is exposed. providing the gate electrode including a main electrode layer consisting of a layer and a metal material layer remaining on the electrode barrier layer; and
By performing an etching process on the insulating material layer, the insulating material layer of the first thickness is removed, and the gate insulating layer is formed with the insulating material layer of the second thickness remaining between the gate electrode and the semiconductor material layer. Including steps to prepare,
In the step of preparing the gate electrode, the electrode barrier layer is disposed between the electrode main layer and the gate insulating layer and surrounds a side of the electrode main layer,
In the step of preparing the gate insulating layer, an active layer including a source region and a drain region each composed of a channel region composed of a portion of the semiconductor material layer overlapping with the gate electrode and other portions disposed at both ends of the channel region. Method for manufacturing a transistor array substrate. According to clause 22,
The metal oxide material layer includes a metal oxide material including one or more of indium (In), gallium (Ga), zinc (Zn), tin (Sn), aluminum (Al), and molybdenum (Mo),
The metal material layer is made of at least one of the following metal materials: molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). A method of manufacturing a transistor array substrate comprising a single layer or multiple layers of one metal material, or an alloy of two or more metal materials. According to clause 22,
The step of disposing the interlayer insulating layer is
disposing a first interlayer insulating layer in contact with the source region and drain region of the active layer, the gate insulating layer, and the gate electrode;
laminating an insulating material on the first interlayer insulating layer; and
A method of manufacturing a transistor array substrate comprising performing an ashing process on an insulating material laminated on the first interlayer insulating layer to provide a second interlayer insulating layer arranged flatly. According to clause 22,
The step of disposing the second buffer layer includes performing an ashing process on the insulating material laminated on the first buffer layer to provide a flatly disposed second buffer layer. According to clause 22,
In the step of disposing the first buffer layer, the first buffer layer has a third thickness,
The step of arranging the light blocking layer is
Partially etching the first buffer layer to change a portion of the first buffer layer to a fourth thickness smaller than the third thickness;
disposing a layer of light blocking material on the first buffer layer; and
Performing an ashing process on the light-shielding material layer until the first buffer layer of the third thickness is exposed, thereby providing the light-shielding layer with the light-shielding material layer remaining on the first buffer layer of the fourth thickness; ,
A method of manufacturing a transistor array substrate where a side of the light blocking layer is in contact with the first buffer layer.

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