KR20240047894A - Semiconductor package - Google Patents

Abstract

The semiconductor package includes: a first semiconductor structure including a first semiconductor substrate and a lower penetrating structure penetrating the first semiconductor substrate; a connection structure on the first semiconductor structure; and a second semiconductor structure disposed on the connecting structure, the second semiconductor structure comprising a second semiconductor substrate and an upper penetrating structure penetrating the second semiconductor substrate, the connecting structure comprising: a lower curved pad on the lower penetrating structure; and an upper flex pad on the lower flex pad, wherein an upper surface of the lower flex pad is a curved surface and a lower surface of the upper flex pad is a curved surface, and the upper flex pad is electrically connected to the upper penetrating structure.

Description

Semiconductor package {SEMICONDUCTOR PACKAGE}

The present invention relates to a semiconductor package, and more particularly to a stacked semiconductor package.

In the semiconductor industry, as demand for high capacity, thinness, and miniaturization of semiconductor packages and electronic products using them increases, various package technologies related to this are emerging one after another. One of them is a packaging technology that can implement high-density chip stacking by vertically stacking various semiconductor chips. This technology can have the advantage of being used when integrating semiconductor chips with various functions in a smaller area than a typical package consisting of a single semiconductor chip.

A semiconductor package is an integrated circuit chip implemented in a form suitable for use in electronic products. With the development of the electronics industry, various research is being conducted to improve the reliability and durability of semiconductor packages.

The problem to be solved by the present invention is to provide a semiconductor package with improved reliability during the bonding process.

The problem to be solved by the present invention is not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

A semiconductor package according to embodiments of the present invention for solving the above-described technical problems includes: a first semiconductor structure including a first semiconductor substrate and a lower penetrating structure penetrating the first semiconductor substrate; a connection structure on the first semiconductor structure; and a second semiconductor structure disposed on the connecting structure, the second semiconductor structure comprising a second semiconductor substrate and an upper penetrating structure penetrating the second semiconductor substrate, the connecting structure comprising: a lower curved pad on the lower penetrating structure; and an upper flex pad on the lower flex pad, wherein an upper surface of the lower flex pad is a curved surface, a lower surface of the upper flex pad is a curved surface, and the upper flex pad can be electrically connected to the upper penetrating structure.

A semiconductor package according to embodiments of the present invention for solving the above-described technical problems includes: a first semiconductor structure including a first semiconductor substrate and a lower penetrating structure penetrating the first semiconductor substrate;

a connection structure on the first semiconductor structure; and a second semiconductor structure disposed on the connection structure, including a second semiconductor substrate and an upper penetrating structure penetrating the second semiconductor substrate, wherein the connection structure includes: a lower insulating film on the first semiconductor substrate; a lower curved pad disposed on the lower insulating film and electrically connected to the lower penetrating structure; and a lower connection pad disposed on the lower insulating film and spaced apart from the lower curved pad, wherein the level of the upper surface of the lower curved pad may be lower than the level of the upper surface of the lower connection pad.

A semiconductor package according to embodiments of the present invention for solving the above-described technical problems includes: a first semiconductor structure including a first semiconductor substrate and a lower penetrating structure penetrating the first semiconductor substrate; a connection structure on the first semiconductor structure; and a second semiconductor structure disposed on the connection structure, including a second semiconductor substrate and an upper penetrating structure penetrating the second semiconductor substrate, wherein the connection structure includes: a lower insulating film on the first semiconductor substrate; an intervening film on the lower insulating film; a lower flex pad on the lower penetrating structure; and an upper flex pad on the lower flex pad, An upper surface of the lower curved pad is a curved surface, a lower surface of the upper curved pad is a curved surface, the upper curved pad is electrically connected to the upper penetrating structure, and the level of the upper surface of the interlayer is lower than the level of the upper surface of the curved pad. It can be low.

In the semiconductor package according to embodiments of the present invention, when the upper structure and the lower structure are in contact, the topology of the semiconductor structure can be relaxed because the curved surfaces of the insulating film and the curved surfaces of the pad are in contact with each other.

1 is a cross-sectional view illustrating a semiconductor package according to embodiments of the present invention.
FIG. 2 is a plan view showing the upper curved pads of the semiconductor package according to FIG. 1.
FIG. 3 is a plan view showing lower curved pads of the semiconductor package according to FIG. 1 .
Figure 4 is an enlarged cross-sectional view of portion Q of Figure 1.
Figure 5 is a cross-sectional view illustrating bonding between semiconductor substrates according to embodiments of the present invention.
Figure 6 is a cross-sectional view for explaining a semiconductor package according to embodiments of the present invention.
Figure 7 is a plan view for explaining a semiconductor package according to embodiments of the present invention.
Figure 8 is a plan view for explaining a semiconductor package according to embodiments of the present invention.
Figure 9 is an enlarged cross-sectional view of portion Qb of Figure 1.
FIG. 10 is a cross-sectional view illustrating bonding between semiconductor substrates according to embodiments of the present invention.
11 to 18 are plan views for explaining a method of manufacturing a semiconductor package according to embodiments of the present invention.
Figure 19 is a cross-sectional view for explaining a semiconductor package according to embodiments of the present invention.
Figure 20 is an enlarged cross-sectional view of portion P of Figure 19.
Figure 21 is a cross-sectional view for explaining a semiconductor package according to embodiments of the present invention.

A semiconductor package according to the concept of the present invention will be described with reference to the drawings.

1 is a cross-sectional view illustrating a semiconductor package according to embodiments of the present invention. In Figure 1, for convenience of explanation, some components are omitted or several components are merged and shown as one configuration.

The semiconductor package according to embodiments of the present invention may be a stacked package using a penetrating structure. For example, semiconductor chips of the same type may be stacked on a base substrate, and the semiconductor chips may be electrically connected to each other through penetrating structures penetrating them. Semiconductor chips can be connected to each other using their pads facing each other.

Referring to FIG. 1 , the semiconductor package 1 according to embodiments of the present invention may have the shape of a plate extending along a plane defined by the first direction D1 and the second direction D2. The first direction D1 and the second direction D2 may intersect each other. For example, the first direction D1 and the second direction D2 may be perpendicular to each other. The semiconductor package 1 according to embodiments of the present invention includes a solder ball 81, a solder layer 90, a base structure 100, a first connection structure 210, a first semiconductor structure 220, and a second connection. It may include a structure 310, a second semiconductor structure 320, a third connection structure 410, a third semiconductor structure 420, and a molding layer 190.

A solder ball 81 may be provided. The solder ball 81 may contain a conductive material. The solder ball 81 may be electrically connected to the base structure 100, the first semiconductor structure 220, the second semiconductor structure 320, and the third semiconductor structure 420. The solder ball 81 may electrically connect the base structure 100, the first semiconductor structure 220, the second semiconductor structure 320, and the third semiconductor structure 420 with an external device (not shown).

A solder layer 90 may be provided on the solder ball 81. The solder layer 90 may include a solder insulating film 91 and a solder pad 92. The solder insulating film 91 may surround the side of the solder pad 92.

The solder insulating film 91 may include an insulating material. The solder insulating film 91 may include, for example, at least one of silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON).

The solder pad 92 may include a conductive material. The solder pad 92 may include, for example, one or more of copper (Cu), aluminum (Al), and/or nickel (Ni). The solder pad 92 may be electrically connected to the solder ball 81.

Base structure 100 may be provided on solder layer 90 . The base structure 100 may include, for example, a base substrate 101 and a base through-via 102.

The base substrate 101 may include circuitry directly therein. For example, the base substrate 101 may be a wafer level die made of a semiconductor such as silicon (Si). In some embodiments, the base substrate 101 may be a substrate that does not include electronic devices such as transistors, and may be, for example, a printed circuit board (PCB).

The first connection structure 210 may be interposed between the base substrate 101 and the first semiconductor substrate 225 . The first connection structure 210 may have a similar structure to the second connection structure 310, which will be described later. The base substrate 101 and the first semiconductor substrate 225 may be bonded to each other through the first connection structure 210 . The base substrate 101 and the first semiconductor structure 220 may be electrically connected through the first connection structure 210.

A first semiconductor structure 220 may be provided on the first connection structure 210. The first semiconductor structure 220 may include a first semiconductor substrate 225 and a plurality of lower penetrating structures 221, 222, and 223. The plurality of lower penetrating structures 221, 222, and 223 may include a first lower penetrating structure 221, a second lower penetrating structure 222, and a third lower penetrating structure 223. The first lower penetrating structure 221, the second lower penetrating structure 222, and the third lower penetrating structure 223 may penetrate the first semiconductor substrate 225.

The first semiconductor substrate 225, the base structure 100, and the solder ball 81 are electrically connected through the first lower penetrating structure 221, the second lower penetrating structure 222, and the third lower penetrating structure 223. can be connected

A second connection structure 310 may be provided on the first semiconductor substrate 225 . The second connection structure 310 may be interposed between the first semiconductor substrate 225 and the second semiconductor substrate.

A second semiconductor structure 320 may be provided on the second connection structure 310. The second semiconductor structure 320 may have a similar structure to the first semiconductor structure 220.

A third connection structure 410 may be provided on the second semiconductor structure 320 . The third connection structure 410 may have a structure similar to the first and second connection structures 210 and 310.

A third semiconductor structure 420 may be provided on the third connection structure 410. The third semiconductor structure 420 may have a structure similar to the first and second semiconductor structures 220.

A fourth connection structure 510 may be provided on the third semiconductor structure 420 . The fourth connection structure 510 may have a structure similar to the first, second, and third connection structures 210, 310, and 410.

A fourth semiconductor structure 520 may be provided on the third connection structure 510. The fourth semiconductor structure 520 includes the first semiconductor structure 220 and It may be similar.

A molding layer 190 may be provided on the base structure 100. The molding layer 190 includes a first connection structure 210, a first semiconductor structure 220, a second connection structure 310, a second semiconductor structure 320, a third connection structure 410, and a third semiconductor. It may be provided to surround the structure 420. The molding layer 190 may include an insulating material. For example, the molding layer 190 may include epoxy molding compound (EMC).

FIG. 2 is a plan view showing the upper curved pads of the semiconductor package according to FIG. 1. FIG. 3 is a plan view showing lower curved pads of the semiconductor package according to FIG. 1 . Figure 4 is an enlarged cross-sectional view of portion Q of Figure 1. Figure 5 is a cross-sectional view illustrating bonding between semiconductor substrates according to embodiments of the present invention.

2, 3, and 4, the second connection structure 310 may be interposed between the first semiconductor substrate 225 and the second semiconductor substrate 325. The second connection structure 310 may be formed by joining the upper structure US and the lower structure LS, which will be described later. The second connection structure 310 includes a lower insulating film 317, an intervening film 318 on the lower insulating film 317, lower connection pads 311, 312, 313, and 314 on the lower insulating film 317, and a lower insulating film 317. ), the lower curved pads 381, 382, 383, the junction insulating film 319 on the intervening film 318, the upper connection pads 321, 322, 323 on the lower connection pads 311, 312, 313, 314. , 324), upper flex pads 391, 392, 393 on lower flex pads 381, 382, 383, upper connecting uppermost pads 331 on upper connecting pads 321, 322, 323, 324. 332, 336, 337), upper curved top pads 333, 334, 335 on top curved pads 391, 392, 393, and upper conductive pads on top curved top pads 333, 334, 335. It may include (351, 352, 353).

Referring to FIG. 2 , from a plan view, the junction insulating layer 319 may have the shape of a plate extending in the first direction D1 and the second direction D2.

The upper connection pads 321, 322, 323, and 324 include a plurality of first upper connection pads 321, a plurality of second upper connection pads 322, a plurality of third upper connection pads 323, and a plurality of fourth upper connection pads 324.

The upper connection top pads 331, 332, 336, and 337 include a first connection top pad 331, a second connection top pad 332, a third connection top pad 336, and a fourth connection top pad 337. ) may include. The first to fourth connected uppermost pads 331, 332, 336, and 337 may be spaced apart in the first direction D1.

The first upper connection pads 321 may be circular. The first upper connection pads 321 may include a conductive material. The plurality of first upper connection pads 321 may be arranged to be spaced apart in the second direction D2. The first connection uppermost pad 331 may have a rectangular shape in which the length of the side in the second direction D2 is longer than the length of the side in the first direction D1. The first connection uppermost pad 331 may overlap a plurality of first upper connection pads 321.

The first connected uppermost pad 331 and the second connected uppermost pad 332 may be adjacent to each other. The third connected uppermost pad 336 and the fourth connected uppermost pad 337 may be adjacent to each other. The first upper connection pad 321 and the second upper connection pad 322 may be adjacent to each other. The third upper connection pad 323 and the fourth upper connection pad 324 may be adjacent to each other.

A plurality of curved uppermost pads 333, 334, and 335 may be disposed between the second connected uppermost pad 332 and the third connected uppermost pad 336. A plurality of upper curved pads 391, 392, and 393 may be disposed between the second upper connection pad 322 and the third upper connection pad 323.

The plurality of curved top pads 333, 334, and 335 include a plurality of first curved top pads 333, a plurality of second curved top pads 334, and a plurality of third curved top pads 335. may include. The plurality of upper flex pads 391, 392, 393 may include a plurality of first upper flex pads 391, second upper flex pads 392, and third upper flex pads 393. there is.

The plurality of first curved uppermost pads 333 may be arranged to be spaced apart in the second direction D2. The plurality of first curved uppermost pads 333 may include a conductive material. The plurality of first curved uppermost pads 333 may be circular.

The plurality of first upper curved pads 391 may be arranged to be spaced apart in the second direction D2. The plurality of first upper curved pads 391 may include a conductive material. The plurality of first curved uppermost pads 333 may be circular.

The first curved uppermost pad 333 and the first upper curved pad 391 may be concentric circles. The diameter of the first curved uppermost pad 333 may be larger than the diameter of the first upper curved pad 391. The first upper curved pad 391 and the first curved uppermost pad 333 may overlap.

The same may apply to the second to fourth upper connection pads 322, 323, and 324 and the second to fourth connection uppermost pads 332, 336, and 337.

Referring to FIG. 3 , from a plan view, the lower insulating layer 317 may have the shape of a plate extending in the first direction D1 and the second direction D2.

The lower connection pads 311, 312, 313, and 314 and the lower curved pads 381, 382, and 383 may be circular. The diameter of the lower curved pads 381, 382, and 383 may be larger than the diameter of the lower connection pads 311, 312, 313, and 314.

The lower connection pads 311, 312, 313, and 314 include a plurality of first lower connection pads 311, a plurality of second lower connection pads 312, a plurality of third lower connection pads 313, and a plurality of fourth lower connection pads 314. The plurality of first lower connection pads 311 may be arranged to be spaced apart in the second direction D2. The first lower connection pads 311 and the plurality of second lower connection pads 312 may be adjacent to each other.

The lower flex pads 381, 382, 383 include a plurality of first lower flex pads 381, a plurality of second lower flex pads 382, and a plurality of third lower flex pads 383. can do. The first lower curved pads 381 may be arranged to be spaced apart in the second direction D2. The first to third lower curved pads 381, 382, and 383 may be spaced apart in the first direction D1.

First lower curved pads 381, second lower curved pads 382, and third lower curved pads 383 between the second lower connection pads 312 and third lower connection pads 313. ) can be placed.

Referring to FIG. 4 , a lower insulating film 317 may be disposed on the first semiconductor substrate 225 . The lower insulating film 317 may include an insulating material. Lower penetrating structures 221, 222, and 223 penetrating the first semiconductor substrate 225 and the lower insulating film 317 may be provided. The lower penetrating structures 221, 222, and 223 may include a first lower penetrating structure 221, a second lower penetrating structure 222, and a third lower penetrating structure 223 that are spaced apart from each other.

A first lower connection pad 311, a second lower connection pad 312, a third lower connection pad 313, and a fourth lower connection pad 314 are formed on the lower insulating layer 317 so as to penetrate the intervening film 318. , a first lower flex pad 381, a second lower flex pad 382, and a third lower flex pad 383 may be disposed.

The level of the upper surfaces of the lower curved pads 381, 382, and 383 may be lower than the level of the upper surfaces of the lower connection pads 311, 312, 313, and 314.

The intervening film 318 may include an insulating material. The intervening film 318 may include a different material from the lower insulating film 317 . The intervening film 318 may include, for example, silicon nitride. The level of the upper surface of the intervening film 318 may be lower than the level of the upper surfaces of the first lower connection pad 311 and the first lower curved pad 381.

The lower surfaces of the first lower connection pad 311, the second lower connection pad 312, the third lower connection pad 313, and the fourth lower connection pad 314 may be coplanar with the upper surface of the lower insulating film 317. there is.

A first upper connection pad 321 may be provided on the first lower connection pad 311. The first upper connection pad 321 and the first lower connection pad 311 may be electrically connected. The first upper connection pad 321 and the first lower connection pad 311 may include a conductive material. The first upper connection pad 321 and the first lower connection pad 311 may include copper, for example. The same may apply to the second to fourth upper connection pads 322, 323, and 324 and the second to fourth lower connection pads 312, 313, and 314.

A first upper flex pad 391 may be provided on the first lower flex pad 381. The first lower curved pad 381 and the first upper curved pad 391 may be electrically connected. The first lower curved pad 381 and the first upper curved pad 391 may include a conductive material. The first lower curved pad 381 and the first upper curved pad 391 may include copper, for example. The upper surface 381_CS of the first lower curved pad 381 may be a curved surface. The lower surface 391_CS of the first upper curved pad 391 may be a curved surface. The curvature of the upper surface 381_CS of the first lower curved pad 381 and the curvature of the lower surface 391_CS of the first upper curved pad 391 may be the same. The upper surface 382_CS of the second lower flex pad 382, the lower surface 392_CS of the second upper flex pad 392, the upper surface 383_CS of the third lower flex pad 383, and the third upper flex pad 393 )'s lower surface (393_CS) may also be the same.

A first connection uppermost pad 331 may be provided on the first upper connection pad 321. The first connection top pad 331 may include a conductive material. The first connection uppermost pad 331 may include aluminum, for example. The first connection uppermost pad 331 may include a different material from the first upper connection pad 321.

A first curved uppermost pad 333 may be provided on the first upper curved pad 391. The first curved uppermost pad 333 may include a conductive material. The first curved uppermost pad 333 may include aluminum, for example. The first curved uppermost pad 333 may include a different material than the first upper curved pad 391 .

The level of the upper surface of the first upper curved pad 391 may be lower than the level of the first upper connection pad 321. The width 221w of the first lower penetrating structure 221 may be smaller than the width 391w of the first lower curved pad 391. The width 221w of the first lower penetrating structure 221 may be, for example, 4 μm or less. The width 391w of the first upper curved pad 391 may be smaller than the width 381w of the first lower curved pad 381. The width 381w of the first lower curved pad 381 may be smaller than the width 333w of the first curved uppermost pad 333. The width 391w of the first lower curved pad 391 may be smaller than the width 311w of the first lower connection pad 311. The width 333w of the first curved uppermost pad 333 may be smaller than the width 331w of the first connected uppermost pad 331. For example, the width 333w of the first curved uppermost pad 333 may be 8 μm or less. The width 311w of the first lower connection pad 311 may be smaller than the width 331w of the first connection uppermost pad 331. The height 333h of the first curved uppermost pad 333 may be smaller than the height 331h of the first connected uppermost pad 331. For example, the height of the first connection top pad 331 may be 2.5 um or less. The level of the upper surfaces of the connected uppermost pads 331, 332, 336, and 337 may be higher than the level of the upper surfaces of the curved uppermost pads 333, 334, and 335.

Upper penetrating structures 341, 342, and 343 may be disposed on the curved uppermost pads 333, 334, and 335. The upper penetrating structures 341, 342, and 343 may include a first upper penetrating structure 341, a second upper penetrating structure 342, and a third upper penetrating structure 343.

The first upper penetrating structure 341 may be disposed on the first curved uppermost pad 333. The first conductive pad 351 may be disposed on the first curved uppermost pad 333 so as to overlap the first upper penetrating structure 341 . The same may apply to the second upper penetrating structure 342, the second conductive pad 352, the third upper penetrating structure 343, and the third conductive pad 353.

The first curved uppermost pad 333 and the first conductive pad 351 may be spaced apart. The first conductive pad 351 may include a plurality of first conductive pads 351 spaced apart in the third direction D3. The level of the top surface of the uppermost pad of the plurality of first conductive pads 351 may be lower than the level of the top surface of the junction insulating layer 319. The width 351w of the first conductive pad 351 may be smaller than the width 333w of the first curved uppermost pad 333. The height 351h of the first conductive pad 351 may be smaller than the height 331h of the first connection top pad 331. The height 351h of the first conductive pad 351 may be smaller than the height 333h of the first curved uppermost pad 333.

The bonding insulating film 319 may cover the side and top surfaces of the connected top pads 331, 332, 336, and 337 and the side surfaces of the curved top pads 333, 334, and 335. The junction insulating film 319 may include an insulating material. A second semiconductor substrate 325 may be disposed on the junction insulating film 319 .

The upper penetrating structures 341, 342, and 343 may penetrate the second semiconductor substrate 325. The distance d1 between the center of the first upper connection pad 321 and the center of the second upper connection pad 322 may be 30 um or less. The distance d2 between the center of the second upper penetrating structure 342 and the center of the third upper penetrating structure 343 may be 30 um or less.

The topology of the semiconductor chip can be offset by the second connection structure 310 having lower curved pads 381, 382, and 383 and upper curved pads 391, 392, and 393. Referring to FIG. 5 , the upper structure US and the lower structure LS are provided just before the second connection structure 310 is formed. An upper structure (US) may be provided on the lower structure (LS). For convenience of explanation, detailed descriptions of technical features that overlap with those described above will be omitted, and differences will be explained in detail.

The lower structure LS includes a first semiconductor substrate 225, a lower insulating film 317 on the first semiconductor substrate 225, an intervening film 318 on the lower insulating film 317, and a first curved insulating film on the intervening film 318. (3192), lower penetrating structures (221, 222, 223) penetrating the first semiconductor substrate (225) and the lower insulating film (317), lower curved pads (381) on the lower penetrating structures (221, 222, 223) , 382, 383), and may include lower connection pads (311, 312, 313, 314).

The first semiconductor substrate 225 may include a semiconductor material. For example, the first semiconductor substrate 110 may be a silicon (Si) single crystal substrate.

The first curved insulating film 3192 may include a lower flat surface 3192_FS and a lower curved surface 3192_CS. The lower flat surface 3192_FS and the lower curved surface 3192_CS may be connected without interruption.

The lower flat surface 3192_FS may be a flat upper surface of the first curved insulating film 3192. The lower flat surface 3192_FS may be coplanar with the upper surfaces of the lower connection pads 311, 312, 313, and 314. The level of the lower flat surface 3192_FS may be higher than the lowest level of the lower curved surface 3192_CS.

The lower curved surface 3192_CS may have a downward concave shape. The lower curved surface 3192_CS may be coplanar with the upper surfaces 381_CS, 382_CS, and 383_CS of the lower curved pads 381, 382, and 383.

All of the lower surfaces of the lower connection pads 311, 312, 313, and 314 may be in contact with the lower insulating film 317.

A first lower curved pad 381 may be provided on the first lower penetrating structure 221. A second lower curved pad 382 may be provided on the second lower penetrating structure 222 . A third lower curved pad 383 may be provided on the third lower penetrating structure 223.

The upper structure (US) includes a second curved insulating film 3191, a second semiconductor substrate 325 on the second curved insulating film 3191, and upper connection pads 321, 322, 323, and 324 in the second curved insulating film 3191. ), connection top pads 331, 332, 336, 337 on the top connection pads, curved top pads 333, 334, 335 on the top curved pads 391, 392, 393, a second curved insulating film ( 3191) and upper penetrating structures 341, 342, 343 penetrating the second semiconductor substrate 325, and conductive pads 351, 352, 353 on the curved uppermost pads 333, 334, 335. can do.

The second curved insulating film 3191 may include an upper flat surface 3191_FS and an upper curved surface 3191_CS. The upper flat surface 3191_FS and the upper curved surface 3191_CS may be connected without interruption. The second curved insulating film 3191 may include silicon oxide.

The upper flat surface 3191_FS may be a flat surface of the lower surface of the second curved insulating film 3191. The upper flat surface 3191_FS may be coplanar with the lower surfaces of the upper connection pads 321, 322, 323, and 324. The level of the upper flat surface 3191_FS may be higher than the lowest level of the upper curved surface 3191_CS.

The upper curved surface 3191_CS may have a downward concave shape. The upper curved surface 3191_CS may be coplanar with the lower surfaces 391_CS, 392_CS, and 393_CS of the upper curved pads 391, 392, and 393. The curvature of the lower curved surface 3192_CS and the curvature of the upper curved surface 3191_CS may be the same.

The lower surface 391_CS of the first upper curved pad 391 and the upper surface 381_CS of the first lower curved pad 381 may be in contact with each other. The lower surface 392_CS of the second upper curved pad 392 and the upper surface 382_CS of the second lower curved pad 382 may be in contact with each other. The lower surface 392_CS of the second upper curved pad 392 and the upper surface 382_CS of the second lower curved pad 382 may be in contact with each other. The lower surface 393_CS of the third upper curved pad 393 and the upper surface 383_CS of the third lower curved pad 383 may be in contact with each other. The lower curved surface 3192_CS and the upper curved surface 3191_CS may be in contact with each other. In this case, the second curved insulating film 3192 and the second curved insulating film 3191 may be bonded to each other and then integrated. The first curved insulating film 3192 and the second curved insulating film 3191 may be integrated to form a bonded insulating film 319.

As described above, the upper structure US and the lower structure LS may be bonded to form a connection structure 310 connecting the first semiconductor substrate 225 and the second semiconductor substrate 325.

Since the width 333w of the first curved top pad 333 may be smaller than the width 331w of the first connection top pad 331, the metal density of the portion where the first curved top pad 333 is located is that of the first connection. It may be smaller than the metal density of the area where the top pad 331 is located. The first lower curved pad 381 is disposed to overlap the first curved uppermost pad 333 having a low metal density, thereby reducing the topology when bonding the first semiconductor structure 220 and the second semiconductor structure 320.

Figure 6 is a cross-sectional view for explaining a semiconductor package according to embodiments of the present invention.

Referring to FIG. 6, a semiconductor package 1b is provided. In FIG. 6 , for convenience of explanation, some components are omitted or several components are merged and shown as one configuration. For convenience of explanation, detailed descriptions of technical features that overlap with those described above will be omitted, and differences will be explained in detail.

The semiconductor package 1b according to embodiments of the present invention includes a solder ball 81b, a solder layer 90b, a base structure 100b, a first connection structure 210b, a first semiconductor structure 220b, and a second connection. It may include a structure 310b, a second semiconductor structure 320b, a third connection structure 410b, a third semiconductor structure 420b, and a molding layer 190b.

A solder layer 90b may be provided on the solder ball 81b. The solder layer 90b may include a solder insulating film 91b and a solder pad 92b.

A base structure 100b may be provided on the solder layer 90b. The base structure 100b may include, for example, a base substrate 101b and a base through-via 102b.

The first connection structure 210b may be interposed between the base substrate 101b and the first semiconductor structure 220b. A first semiconductor structure 220b may be provided on the first connection structure 210b. The first semiconductor structure 220b may include a first semiconductor substrate 225b and a plurality of lower penetrating structures 221b, 222b, 223b, and 224b. A plurality of lower penetrating structures (221b, 222b, 223b, 224b) include a first lower penetrating structure (221b), a second lower penetrating structure (222b), a third lower penetrating structure (223b), and a fourth lower penetrating structure ( 224b) may be included. The first lower penetrating structure 221b, the second lower penetrating structure 222b, the third lower penetrating structure 223b, and the fourth lower penetrating structure 224b may penetrate the first semiconductor substrate 225b.

The first semiconductor substrate 225b and the base structure 100b are formed through the first lower penetrating structure 221b, the second lower penetrating structure 222b, the third lower penetrating structure 223b, and the fourth lower penetrating structure 224b. ), and the solder ball 81b may be electrically connected.

The distance between the second lower penetrating structure 222b and the third lower penetrating structure 223b may be greater than the distance between the first lower penetrating structure 221b and the second lower penetrating structure 222b.

A second connection structure 310b may be provided on the first semiconductor substrate 225b. A second semiconductor structure 320b may be provided on the second connection structure 310b. A third connection structure 410b may be provided on the second semiconductor structure 320b. A third semiconductor structure 420b may be provided on the third connection structure 410b. A fourth connection structure 510b may be provided on the third semiconductor structure 420b. A fourth semiconductor structure 520b may be provided on the fourth connection structure 510b. A molding layer 190b may be provided on the base structure 100b.

Figure 7 is a plan view for explaining a semiconductor package according to embodiments of the present invention. Figure 8 is a plan view for explaining a semiconductor package according to embodiments of the present invention. Figure 9 is an enlarged cross-sectional view of portion Qb of Figure 1. FIG. 10 is a cross-sectional view illustrating bonding between semiconductor substrates according to embodiments of the present invention.

Referring to FIGS. 7, 8, and 9, the second connection structure 310b may be interposed between the first semiconductor substrate 225b and the second semiconductor substrate 325b. The second connection structure 310b may be formed by joining an upper structure (USb) and a lower structure (LSb), which will be described later.

The second connection structure 310b includes a lower insulating film 317b, an intervening film 318b on the lower insulating film 317b, lower connection pads 311b, 312b, 313b, and 314b on the lower insulating film 317b, and a lower insulating film 317b. ), the lower curved pads 381b, 382b, 383b, the junction insulating film 319b on the intervening film 318b, the upper connection pads 321b, 322b, 323b on the lower connection pads 311b, 312b, 313b, 314b. , 324b), upper curved pads 391, 392, 393 on lower curved pads 381b, 382b, 383b, upper connecting uppermost pads 331b on upper connecting pads 321b, 322b, 323b, 324b. 332b, 336b, and 337b), and upper conductive pads 351b, 352b, 353b, and 354b on the upper connection top pads 331b, 332b, 336b, and 337b.

Referring to FIG. 7 , from a plan view, the junction insulating layer 319b may have the shape of a plate extending in the first direction D1 and the second direction D2.

The upper connection pads 321b, 322b, 323b, and 324b include a plurality of first upper connection pads 321b, a plurality of second upper connection pads 322b, a plurality of third upper connection pads 323b, and a plurality of fourth upper connection pads 324b.

The upper connection top pads 331b, 332b, 336b, and 337b include a first connection top pad 331b, a second connection top pad 332b, a third connection top pad 336b, and a fourth connection top pad 337b. ) may include. The first to fourth connected uppermost pads 331b, 332b, 336b, and 337b may be spaced apart in the first direction D1.

The first upper connection pads 321b may be circular. The first upper connection pads 321b may include a conductive material. The plurality of first upper connection pads 321b may be arranged to be spaced apart in the second direction D2. The first connected uppermost pad 331b may have a rectangular shape in which the length of the side in the second direction D2 is longer than the length of the side in the first direction D1. The first connection uppermost pad 331b may overlap a plurality of first upper connection pads 321b. The same may apply to the second to fourth upper connection pads 322b, 323b, and 324b and the second to fourth connection uppermost pads 332b, 336b, and 337b.

The first connected uppermost pad 331b and the second connected uppermost pad 332b may be adjacent to each other. The third connected uppermost pad 336b and the fourth connected uppermost pad 337b may be adjacent to each other. The first upper connection pad 321b and the second upper connection pad 322b may be adjacent to each other. The third upper connection pad 323b and the fourth upper connection pad 324b may be adjacent to each other.

The distance between the second connected uppermost pad 332b and the third connected uppermost pad 333b may be greater than the distance between the first connected uppermost pad 331b and the second connected uppermost pad 332b.

Referring to FIG. 3 , from a plan view, the lower insulating layer 317b may have the shape of a plate extending in the first direction D1 and the second direction D2.

The lower connection pads 311b, 312b, 313b, and 314b and the lower curved pads 381b, 382b, and 383b may be circular. The diameter of the lower curved pads 381b, 382b, and 383b may be smaller than the diameter of the lower connection pads 311b, 312b, 313b, and 314b.

Referring to FIG. 9, the first semiconductor substrate 225b, the lower insulating film 317b on the first semiconductor substrate 225b, and the lower penetrating structures 221b penetrating the first semiconductor substrate 225b and the lower insulating film 317b. , 222b, 223b, 224b) may be provided. The lower penetrating structures 221b, 222b, 223b, and 224b are a first lower penetrating structure 221b, a second lower penetrating structure 222b, a third lower penetrating structure 223b, and a fourth lower penetrating structure spaced apart from each other. (224b).

A first lower connection pad 311b, a second lower connection pad 312b, a third lower connection pad 313b, and a fourth lower connection pad 314b are formed on the lower insulating layer 317b so as to penetrate the intervening film 318b. , the first lower curved pad 381b, the second lower curved pad 382b, and the third lower curved pad 383b may be disposed.

The plurality of lower curved pads 381b, 382b, and 383b may be disposed between the plurality of lower connection pads 311b, 312b, 313b, and 314b.

A first lower connection pad 311b may be disposed on the first lower penetrating structure 221b. The first lower penetrating structure 221b and the first lower connection pad 311b may overlap. A first lower connection pad 312b may be disposed on the second lower penetrating structure 222b. The second lower penetrating structure 222b and the first lower connection pad 312b may overlap. A third lower connection pad 313b may be disposed on the third lower penetrating structure 223b. The third lower penetrating structure 223b and the third lower connection pad 313b may overlap. A fourth lower connection pad 314b may be disposed on the fourth lower penetrating structure 224b. The fourth lower penetrating structure 224b and the fourth lower connection pad 314b may overlap.

A first upper connection pad 321b may be provided on the first lower connection pad 311b. The same may apply to the second to fourth upper connection pads 322b, 323b, and 324b and the second to fourth lower connection pads 312b, 313b, and 314b.

The lower surface of the first lower curved pad 381b may be in contact with the upper surface of the lower insulating film 317b. The lower surface of the second lower curved pad 382b may be in contact with the upper surface of the lower insulating film 317b. The lower surface of the third lower curved pad 383b may be in contact with the upper surface of the lower insulating film 317b.

The upper surface 381b_CS of the first lower curved pad 381b may be a curved surface. The upper surface 382b_CS of the second lower curved pad 382b may be a curved surface. The upper surface 383b_CS of the third lower curved pad 383b may be a curved surface.

A first connection uppermost pad 331b may be provided on the first upper connection pad 321b. A second connection uppermost pad 332b may be provided on the second upper connection pad 322b. A third connection uppermost pad 333b may be provided on the third upper connection pad 323b. A fourth connection top pad 334b may be provided on the fourth top connection pad 324b. The upper penetrating structures 341b, 342b, 343b, and 344b may penetrate the second semiconductor substrate 325b.

The first lower penetrating structure 221b, the first lower connection pad 381b, and the uppermost connection pad 331b may overlap vertically. The second lower penetrating structure 222b, the first lower connection pad 382b, and the uppermost connection pad 332b may overlap vertically. The third lower penetrating structure 223b, the first lower connection pad 383b, and the uppermost connection pad 333b may overlap vertically.

Upper penetrating structures (341b, 342b, 343b, 344b) may be disposed on the uppermost connected pads (331b, 332b, 333b, and 334b). The first upper penetrating structure 341b may be disposed on the first connection uppermost pad 331b. The first conductive pad 351b may be disposed on the first connection top pad 333b so as to overlap the first upper penetrating structure 341b. The same may apply to the second upper penetrating structure 342b, the second conductive pad 352b, the third upper penetrating structure 343b, and the third conductive pad 353b. The first connection top pad 333b and the first conductive pad 351b may be spaced apart.

The width 221bw of the first lower penetrating structure 221b may be smaller than the width 311bw of the first lower connection pad 311b. The width 381w of the first lower curved pad 381b may be smaller than the width 311bw of the first lower connection pad 311b. For example, the width 221bw of the first lower penetrating structure 221b may be 4 μm or less. For example, the width 311bw of the first lower connection pad 311b may be 8 μm or less. The distance d3 between the third lower penetrating structure 223b and the fourth lower penetrating structure 224b may be, for example, 30 um or less. The width of the first connection uppermost pad 331b may be larger than the width of the first upper connection pad 321b.

Referring to FIG. 10, the upper structure USb and the lower structure LSb are provided just before the second connection structure 310b is formed. An upper structure (USb) may be provided on the lower structure (LSb). For convenience of explanation, detailed descriptions of technical features that overlap with those described above will be omitted, and differences will be explained in detail.

The lower structure LSb includes a first semiconductor substrate 225b, a lower insulating film 317b on the first semiconductor substrate 225b, an intervening film 318b on the lower insulating film 317b, and a first curved insulating film on the intervening film 318b. (3192b), lower penetrating structures 221b, 222b, 223b, 224b penetrating the first semiconductor substrate 225b and the lower insulating film 317b, lower connections on the lower penetrating structures 221b, 222b, 223b, 224b It may include pads 311b, 312b, 313b, 314b, and lower curved pads 381b, 382b, 383b.

The first curved insulating film 3192b may include a lower flat surface 3192b_FS and a lower curved surface 3192b_CS.

The lower flat surface 3192b_FS may be a flat upper surface of the first curved insulating film 3192b.

The lower curved surface 3192b_CS may have a downward concave shape. The lower curved surface 3192b_CS may be coplanar with the upper surfaces 381b_CS, 382b_CS, and 383b_CS of the lower curved pads 381b, 382b, and 383b.

The lower connection pads 311b, 312b, 313b, and 314b may contact the lower penetrating structures 221b, 222b, 223b, and 224b.

The upper structure (USb) includes a second curved insulating film 3191b, a second semiconductor substrate 325b on the second curved insulating film 3191b, and upper connection pads 321b, 322b, 323b, and 324b in the second curved insulating film 3191b. ), upper penetration through the connection uppermost pads (331b, 332b, 334b, 335b) on the upper connection pads (321b, 322b, 323b, 324b), the second curved insulating film (3191b), and the second semiconductor substrate (325b) It may include conductive pads 351b, 352b, 353b, and 354b on the structures 341b, 342b, 343b, and 344b and the uppermost connected pads 331b, 332b, 333b, and 334b.

The second curved insulating film 3191b may include an upper flat surface 3191b_FS and an upper curved surface 3191b_CS.

The upper flat surface 3191b_FS may be a flat surface of the lower surface of the second curved insulating film 3191b. The upper curved surface 3191b_CS may have a downward concave shape. The curvature of the lower curved surface 3192b_CS and the curvature of the upper curved surface 3191b_CS may be the same. The curvature of the first lower curved pad 381b and the curvature of the upper curved surface 3191b_CS may be the same.

The upper surface 381b_CS of the first lower curved pad 381b, the upper surface 382b_CS of the second lower curved pad 382b, and the upper surface and upper curved surface 3191b_CS of the third lower curved pad 383b_CS may be in contact with each other. . In this case, the first curved insulating film 3192b and the second curved insulating film 3191b can be bonded to each other and then integrated. The first curved insulating film 3192b and the second curved insulating film 3191b may be integrated to form a bonded insulating film 319b.

As described above, the upper structure (USb) and the lower structure (LSb) are bonded to form a connection structure (310b) connecting the first semiconductor substrate (225b) and the second semiconductor substrate (325b).

11 to 18 are cross-sectional views for explaining a method of manufacturing a semiconductor package according to embodiments of the present invention.

Referring to FIGS. 11 to 18 , a method of manufacturing a semiconductor package having a structure similar to the lower structure LS of FIG. 4 is provided.

Referring to FIG. 11, a carrier substrate 700, a tape (TP) on the carrier substrate 700, a base insulating film 219 on the tape (TP), a first semiconductor substrate 225 on the base insulating film 219, and a base Spare upper curved pads (p291, p292, p293) in the insulating film 219, curved uppermost pads (233, 234, 235) on the spare upper curved pads (p291, p292, p293), curved uppermost pads (233, Conductive pads 251, 252, 253 above (234, 235) and upper penetrating structures (221, 222, 223) are provided.

The tape TP may be formed between the carrier substrate 700 and the base insulating layer 219. The base insulating film 219 and the preliminary upper curved pads p291, p292, and p293 may be fixed on the carrier substrate 700 by the tape TP.

The first semiconductor substrate 225 may be formed to cover the upper surfaces of the upper penetrating structures 221, 222, and 223.

Referring to FIG. 12 , the first semiconductor substrate 225 may be selectively etched to expose portions of the side surfaces and upper surfaces of the upper penetrating structures 221, 222, and 223.

Referring to FIG. 13 , a lower insulating film 317 may be formed on the first semiconductor substrate 225 . The lower insulating film 317 may be formed to cover the upper surfaces of the upper penetrating structures 221, 222, and 223. A preliminary intervening layer 3181 may be formed on the lower insulating layer 317. An intermediate insulating layer 3183 may be formed on the preliminary intervening layer 3181.

The portion of the lower insulating film 317 that overlaps the upper penetrating structures 221, 222, and 223 may be formed in a raised shape. The portion of the lower insulating film 317 that overlaps the upper penetrating structures 221, 222, and 223 may be formed in a concave-convex shape. The preliminary intervening film 3181 may be deposited conformally along the lower insulating film 317. The intermediate insulating film 3183 may be deposited conformally along the preliminary intervening film 3181.

Referring to FIG. 14, the middle insulating film 3183, the lower insulating film 317, and the preliminary intervening film are formed so that only the lower insulating film 317 and the preliminary intervening film 3181 remain at the same level as the upper penetrating structures 211, 222, and 223. Membrane 3181 may be removed. In this case, the upper surfaces of the upper penetrating structures 221, 222, and 223 may be exposed.

Referring to FIG. 15 , a preliminary curved insulating layer 3193 may be formed on the exposed upper surfaces of the upper penetrating structures 211, 222, and 223, the lower insulating layer 317, and the preliminary intervening layer 3181. The preliminary curved insulating film 3193 and the exposed upper surfaces of the upper penetrating structures 211, 222, and 223 may be in contact with each other. The preliminary curved insulating layer 3193 may include a different material from the preliminary intervening layer 3181. For example, the preliminary curved insulating layer 3193 may include SiO, and the preliminary intervening layer 3181 may include SiN.

Referring to FIG. 16, a portion of the lower insulating layer 317, the preliminary intervening layer 3181, and the preliminary curved insulating layer 3193 are removed to form the first trench (TR1), the second trench (TR2), and the third trench (TR3). can be formed. The first trench TR1 may be formed on the upper surface of the first upper penetrating structure 221. The second trench TR2 may be formed on the upper surface of the second upper penetrating structure 222. The third trench TR3 may be formed on the upper surface of the third upper penetrating structure 223. The first trench TR1 may be formed so that the preliminary interposition layer 3181 and the preliminary curved insulating layer 3193 are exposed on the sidewalls of the first trench TR1. The same may apply to the second trench (TR2) and the third trench (TR3).

The first trench TR1 may be formed such that the width of the first trench TR1 is greater than the width of the first upper penetrating structure 221 . The second trench TR2 may be formed such that the width of the second trench TR2 is greater than the width of the second upper penetrating structure 222 . The third trench TR3 may be formed such that the width of the third trench TR3 is greater than the width of the third upper penetrating structure 223 .

Referring to FIG. 16, a preliminary pad layer 3194 may be formed. The preliminary pad layer 3194 may include a conductive material. The preliminary pad layer 3194 may be formed to fill the first trench TR1, the second trench TR2, and the third trench TR3. The preliminary pad layer 3194 may be formed on the preliminary curved insulating film 3193. The preliminary pad layer 3194 may have preliminary pad curved surfaces 3194_CS at portions that overlap the trenches TR1, TR2, and TR3. The spare pad curved surfaces 3194_CS may have an upwardly convex shape.

Referring to FIG. 17, the preliminary pad layer 3194 may be etched. A portion of the preliminary curved insulating film 3193 may be etched. A first curved insulating film 3192 and a lower curved surface 3192_CS may be formed by removing a portion of the preliminary pad layer 3194 and the preliminary curved insulating film 3193. The preliminary pad layer 3194 located at a level higher than the level of the upper surface of the preliminary pad layer 3194 is removed, and the preliminary pad layer 3194 and the preliminary curved insulating film located at a level higher than the level of the lower curved surface 3192_CS are removed. 3193 may be removed to form a curved insulating film 3193 including a lower curved surface 3192_CS.

The preliminary pad layer 3194 that is not removed may form lower curved pads 381, 382, and 383. The first lower trench TR1 may be filled to form the first lower curved pad 381. The second trench TR2 below the lower curved surface 3192_CS may be filled to form the second lower curved pad 382. The third trench TR3 below the lower curved surface 3192_CS may be filled to form a third lower curved pad 383. The lower curved surface 3192_CS is the upper surface 381_CS of the first lower curved pad 381 of the first lower curved pad 381, and the upper surface of the second lower curved pad 382 of the second lower curved pad 382 ( 382_CS), and an upper surface 383_CS of the third lower curved pad 383. Thereafter, the carrier substrate 700 and the tape TP may be removed.

Figure 19 is a cross-sectional view for explaining a semiconductor package according to embodiments of the present invention. Figure 20 is an enlarged cross-sectional view of portion P of Figure 19. For convenience of explanation, detailed descriptions of technical features that overlap with those described above will be omitted, and differences will be explained in detail. The same reference number may be provided for the same configuration as the semiconductor package according to the embodiments of the present invention described above.

Referring to FIG. 19, a semiconductor package 5 is provided. The semiconductor package 5 includes a solder ball 81, a solder layer 90 on the solder ball 81, a redistribution structure 500 on the solder layer 90, a bump (BP) on the redistribution structure 500, and a bump (BP). ), the first semiconductor structure 220c on the first semiconductor structure 220c, the second semiconductor structure 320c on the first connection structure 310c, and the first connection structure 310c on the redistribution structure 500. 1 May include a molding film 505. The width of the first semiconductor structure 220c may be smaller than the width of the second semiconductor structure 320c.

The redistribution structure 500 may include a first redistribution layer 511, a second redistribution layer 512 on the first redistribution layer 511, and a third redistribution layer 513 on the second redistribution layer 512. You can. The first redistribution layer 511 may include a first redistribution pattern 501 and a first redistribution insulating layer 502. The first redistribution pattern 501 may include a conductive material. The second redistribution layer 512 and the third redistribution layer 513 may be the same as the first redistribution layer 511.

The first redistribution pattern 501, the solder layer 90, and the solder ball 81 may be electrically connected. The solder layer 90, the first redistribution layer 511, the second redistribution layer 512, and the third redistribution layer 513 may be electrically connected.

The redistribution structure 500 and the first semiconductor structure 220c may be electrically connected through a bump BP. The bump BP may include a conductive material. The bump BP may be interposed between the redistribution structure 500 and the first semiconductor structure 220c.

The first molding film 505 is formed on the top surface of the redistribution structure 500, the side surface of the first semiconductor structure 220c, the side surface of the second semiconductor structure 320c, the top surface of the second semiconductor structure 320c, and the second semiconductor structure. It may be provided to cover the lower surface of the structure 320c that is not in contact with the first semiconductor structure 220c. The first molding film 505 may include an insulating material.

Referring to FIG. 20, a semiconductor substrate 225c, lower penetrating structures 221c, 222c, and 223c, a first connection structure 310c on the semiconductor substrate 225c, and a second semiconductor substrate on the first connection structure 310c. (325c) may be provided.

The first connection structure 310c may be interposed between the first semiconductor substrate 225c and the second semiconductor substrate 325c. The first connection structure 310c includes a lower insulating film 317c, an intervening film 318c on the lower insulating film 317c, lower connection pads 311c, 312c, 313c, and 314c on the lower insulating film 317c, and a lower insulating film 317c. ), the lower curved pads 381c, 382c, 383c, the junction insulating film 319c on the intervening film 318c, the upper connection pads 321c, 322c, 323c on the lower connection pads 311c, 312c, 313c, 314c. , 324c), upper curved pads 391c, 392c, 393c on lower curved pads 381c, 382c, 383c, upper connecting uppermost pads 331c on upper connecting pads 321c, 322c, 323c, 324c. 332c, 336c, 337c), upper curved top pads 333c, 334c, 335c on top curved pads 391c, 392c, 393c, and upper conductive pads on top curved top pads 333c, 334c, 335c. It may include (351c, 352c, 353).

The upper surfaces 381c_CS, 382c_CS, 383c_CS of the lower curved pads 381c, 382c, 383c and the lower surfaces 391c_CS, 391c_CS, 393c_CS of the upper curved pads 391c, 392c, 393c may be in contact.

Upper penetrating structures 341c, 342c, and 343c may be provided on the upper curved uppermost pads 333c, 334c, and 335c. The upper penetrating structures 341c, 342c, and 343c may include a first upper penetrating structure 341c, a second upper penetrating structure 342c, and a third upper penetrating structure 343c.

The first upper penetrating structure 341c may be disposed on the first curved uppermost pad 333c. The first conductive pad 351c may be disposed on the first curved uppermost pad 333c so as to overlap the first upper penetrating structure 341c. The same may apply to the second upper penetrating structure 342c, the second conductive pad 352c, the third upper penetrating structure 343c, and the third conductive pad 353c.

The top surface of the first upper penetrating structure 341c may be coplanar with the top surface of the bonding insulating film 319c. The same may apply to the second upper penetrating structure 342c and the third upper penetrating structure 343c.

Figure 21 is a cross-sectional view for explaining a semiconductor package according to embodiments of the present invention.

Referring to FIG. 21 , the semiconductor package may include a package substrate 810. First terminals 820 electrically connected to the package substrate 810 may be provided. A semiconductor package may be mounted on an external device (eg, a main board) through the first terminals 820.

An interposer 830 may be provided on the package substrate 810. Second terminals 840 may be provided to electrically connect the package substrate 810 and the interposer 830. Second terminals 840 may be provided between the package substrate 810 and the interposer 830.

A processor chip 860 may be provided on the interposer 830. For example, processor chip 860 may be a graphics processing unit (GPU) or a central processing unit (CPU). Third terminals 850 may be provided to electrically connect the processor chip 860 and the interposer 830. Third terminals 850 may be provided between the processor chip 860 and the interposer 830.

The semiconductor package structure 1 of FIG. 1 may be provided on the interposer 830. The semiconductor package structure 1 may be spaced apart from the processor chip 860 in the first direction D1. Solder balls that electrically connect the semiconductor package structure 1 and the interposer 830 may be provided.

A molding film (MD) surrounding the interposer 830, the processor chip 860, and the semiconductor package structure 1 may be provided on the package substrate 810.

Above, embodiments of the present invention have been described with reference to the attached drawings, but those skilled in the art will understand that the present invention can be implemented in other specific forms without changing the technical idea or essential features. You will understand that it exists. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive.

Claims (10)

a first semiconductor structure including a first semiconductor substrate and a lower penetrating structure penetrating the first semiconductor substrate;
a connection structure on the first semiconductor structure; and
A second semiconductor structure disposed on the connection structure and including a second semiconductor substrate and an upper penetrating structure penetrating the second semiconductor substrate,
The connection structure is:
a lower flex pad on the lower penetrating structure; and
comprising an upper flex pad on the lower flex pad,
The upper surface of the lower curved pad is a curved surface,
The lower surface of the upper curved pad is a curved surface,
The semiconductor device of claim 1, wherein the upper flex pad is electrically connected to the upper penetrating structure.
According to claim 1,
The connection structure is:
A plurality of upper conductive pads in contact with the upper penetrating structure: and
further comprising a curved uppermost pad on the upper curved pad,
A semiconductor device wherein the width of the upper conductive pads is smaller than the width of the uppermost pad.
According to claim 1,
The connection structure is
an upper connection pad spaced apart from the upper bending pad;
a curved uppermost pad on the upper curved pad; and
Further comprising a connection top pad on the upper connection pad,
A semiconductor device wherein the width of the upper connected uppermost pad is greater than the width of the curved uppermost pad.
According to claim 1,
The connection structure is
a lower insulating film on the first semiconductor substrate; and
It includes a lower connection pad spaced apart from the lower curved pad,
The entire lower surface of the lower connection pad is in contact with the lower insulating film, and the lower surface of the lower curved pad is in contact with the lower penetrating structure.
According to clause 4,
The level of the upper surface of the lower curved pad is lower than the level of the upper surface of the lower connection pad.
According to claim 1,
The connection structure is
a lower insulating layer on the first semiconductor substrate; and
Includes an intervening film on the lower insulating film,
The level of the top surface of the intervening film is lower than the level of the top surface of the lower curved pad.
According to claim 1,
The connection structure is
further comprising a curved uppermost pad on the upper curved pad,
The semiconductor device of claim 1, wherein the curved top pad comprises a different material than the top curved pad.
According to clause 7,
A semiconductor device, wherein the curvature of the upper surface of the lower curved pad and the lower surface of the upper curved pad are the same.
According to claim 1,
The connection structure is
an upper connection pad spaced apart from the upper bending pad;
a curved uppermost pad on the upper curved pad; and
Further comprising a connection top pad on the upper connection pad,
The level of the top surface of the connected uppermost pad is higher than the level of the upper surface of the curved uppermost pad.
a first semiconductor structure including a first semiconductor substrate and a lower penetrating structure penetrating the first semiconductor substrate;
a connection structure on the first semiconductor structure; and
A second semiconductor structure disposed on the connection structure and including a second semiconductor substrate and an upper penetrating structure penetrating the second semiconductor substrate,
The connection structure is:
a lower insulating film on the first semiconductor substrate;
a lower curved pad disposed on the lower insulating film and electrically connected to the lower penetrating structure; and
It is disposed on the lower insulating film and includes a lower connection pad spaced apart from the lower curved pad,
A semiconductor device wherein the level of the upper surface of the lower curved pad is lower than the level of the upper surface of the lower connection pad.