KR20240037132A - Semiconductor system - Google Patents

Abstract

A semiconductor system according to an embodiment includes a transmitter that outputs a plurality of data as a plurality of data input and output signals through a plurality of channels based on a matrix E, and a plurality of data input and output signals received through a plurality of channels based on a matrix D. A receiver that generates multiple data by differentially amplifying signals - All elements of matrix E and matrix D are integers, the product matrix of matrix D and matrix E is a diagonal matrix, and the sum of the components of each row of matrix D is 0. , the sum of the absolute values of the components of each column of the matrix D is less than or equal to a threshold value.

Description

Semiconductor system{SEMICONDUCTOR SYSTEM}

The disclosure relates to semiconductor systems.

To provide a high-speed input/output (I/O) interface, a transmitter/receiver transmits and receives signals using single-ended signaling or differential signaling. can do. Because the number of signal pins and signal lines required to implement single-ended signaling is less than the number of signal pins and signal lines needed to implement differential signaling, the single-ended signaling method occupies a small area in the semiconductor device. In the single-ended signaling method, when multiple single-ended ports of the transmitter switch in the same direction at the same time, noise (SSN: simultaneous switching output induced noise) is induced by the current flowing in the parasitic inductor, which can increase the jitter of the output driver. . Additionally, the single-ended signaling method is affected by the transition of adjacent signal lines, and crosstalk may occur due to an instantaneous change in the transition position.

One embodiment seeks to provide a semiconductor system that prevents signal degradation due to SSN.

One embodiment seeks to provide a semiconductor system that reduces crosstalk occurring between adjacent signal lines.

A semiconductor system according to an embodiment to solve this technical problem includes a transmitter that outputs a plurality of data as a plurality of data input/output signals through a plurality of channels based on a matrix E, and a plurality of channels based on the matrix D. A receiver that generates multiple data by differentially amplifying multiple data input/output signals received through - All elements of matrix E and matrix D are integers, the product matrix of matrix D and matrix E is a diagonal matrix, and each row of matrix D The sum of the components of is 0, and the sum of the absolute values of the components of each column of the matrix D is less than or equal to the threshold value.

The components of matrix D and matrix E are calculated according to the formula below, Here, D is matrix D, E is matrix E, A is a column vector containing multiple data, S+XT is the main diagonal component is the signal strength of each of the multiple channels, and the remaining components are the cross signal by adjacent channels. It can be a torque intensity matrix.

The transmitter includes a plurality of driver groups that output a plurality of data input/output signals, and the first driver group that outputs a first data input/output signal among the plurality of data input/output signals through a first channel among the plurality of channels includes a first driver group that outputs a first data input/output signal among the plurality of data input/output signals. Among the components of the matrix E corresponding to the data input/output signal, the first number of first drivers based on the absolute value of the component corresponding to the first data among the plurality of data and the components of the matrix E corresponding to the first data input/output signal , and may include a second number of second drivers based on the absolute value of a component corresponding to the second data among the plurality of data.

Each of the first drivers in the first number connects a first output node connected to the first channel and a first power supply voltage based on one of the first pull-up control signal and the first pull-down control signal generated based on the first data. It may include a first pull-up transistor and a first pull-down transistor connecting the first output node and the second power voltage based on the other of the first pull-up control signal and the first pull-down control signal.

Among the components of the matrix E corresponding to the first data input/output signal, according to the sign of the component corresponding to the first data among the plurality of data, the first pull-up control signal is applied to the gate of the first pull-up transistor, and the first pull-up control signal is applied to the gate of the first pull-up transistor. The control signal may be applied to the gate of the first pull-down transistor, or the first pull-up control signal may be applied to the gate of the first pull-down transistor, and the first pull-down control signal may be applied to the gate of the first pull-up transistor.

The transmitter may further include a pre-driver that generates a first pull-up control signal and a first pull-down signal based on the first data.

Each of the second number of second drivers includes a second pull-up transistor that connects the first output node and the first power voltage based on one of the second pull-up control signal and the second pull-down control signal generated based on the second data. and a second pull-down transistor connecting the first output node and the second power voltage based on the other of the second pull-up control signal and the second pull-down control signal.

The first number and the second number may be different from each other.

The first number and the second number may be the same.

The total sum of changes in a plurality of data input/output signals in a plurality of channels may be substantially 0.

The receiver includes at least one first transistor electrically connecting a power supply voltage and a first node and at least one second transistor electrically connecting a power supply voltage and a second node, and the voltage of the first node and the second It may further include a differential amplifier that outputs the voltage of the node.

Among the components of the matrix D corresponding to the first data among the plurality of data, if the sign of the component corresponding to the first data input/output signal is positive, the first data input/output signal is applied to the gate of at least one first transistor, Among the components of the matrix D corresponding to the first data among the plurality of data, if the sign of the component corresponding to the first data input/output signal is negative, the second data input/output signal may be applied to the gate of at least one second transistor. there is.

The number of at least one first transistor is based on the absolute value of the component corresponding to the first data input/output signal among the components of the matrix D corresponding to the first data among the plurality of data, and the number of at least one second transistor is based on the absolute value of the component corresponding to the first data input/output signal. Among the components of the matrix D corresponding to the first data among the plurality of data, it may be based on the absolute value of the component corresponding to the second data input/output signal.

A memory device according to an embodiment receives a memory cell array and n pieces of data (n is a natural number) from the memory cell array, emphasizes the n pieces of data with intensity according to the components of the matrix E, and n+1 pieces of data. It includes a transmitter that generates input and output signals - the sum of the elements of matrix E is 0.

The transmitter is configured to connect a first output node connected to a first channel among a plurality of channels and a first power voltage based on one of a first pull-up control signal based on first data among n pieces of data and a first pull-down control signal. At least one first driver each including a 1 pull-up transistor and a first pull-down transistor connecting the first output node and the second power supply voltage based on the other of the first pull-up control signal and the first pull-down control signal, and n A second pull-up transistor connecting the first output node and the first power supply voltage based on one of a second pull-up control signal and a second pull-down control signal based on the second data among the data, a second pull-up control signal, and a second pull-down control signal. It may include at least one second driver each including a second pull-down transistor connecting the first output node and the second power voltage based on another one of the control signals.

The first pull-up control signal may be applied to the gate of the first pull-up transistor, and the first pull-down control signal may be applied to the gate of the first pull-down transistor.

The second pull-down control signal may be applied to the gate of the second pull-up transistor, and the second pull-up control signal may be applied to the gate of the second pull-down transistor.

The number of at least one first driver and the number of at least one second driver may be different from each other.

The number of at least one first driver and the number of at least one second driver may be the same.

A memory system according to an embodiment includes a memory device including a memory cell array and a transmitter that encodes n pieces of data into n+1 data input/output signals and outputs them, and receives n+1 data input/output signals, and n+ It includes a memory controller including a receiver that decodes n pieces of data by differentially amplifying one data input/output signal according to the components of the matrix D, where the sum of the components of the matrix D is 0.

1 is an example block diagram of a memory system according to one embodiment.
Figure 2 is a block diagram showing a memory device according to one embodiment.
Figure 3 is a block diagram showing part of a transmitter according to one embodiment.
Figure 4 is a block diagram showing a receiver according to one embodiment.
Figure 5 is a diagram showing the arrangement of channels according to one embodiment.
Figure 6 is a graph showing the gain of signals measured through a channel.
Figure 7 is a block diagram showing a portion of an output driver according to one embodiment.
Figure 8 is a graph showing the signal output by the output driver according to one embodiment and the effects of SSN and crosstalk.
Figure 9 is a circuit diagram showing a differential amplifier of a receiver according to an embodiment.
Figure 10 is an eye diagram of a non-return to zero (NRZ) signal after passing through a channel.
Figure 11 is an eye diagram of a signal output from a differential amplifier of a receiver according to an embodiment.
Figure 12 is an eye diagram of the NRZ signal with SSN added.
Figure 13 is an eye diagram of a signal output from a differential amplifier of a receiver according to an embodiment to which an SSN is added.
Figure 14 is an eye diagram of a signal output from a differential amplifier of a receiver according to an embodiment.
Figure 15 is a diagram showing the arrangement of channels according to one embodiment.
Figure 16 is a block diagram showing a part of an output driver according to one embodiment.
Figure 17 is a circuit diagram showing a differential amplifier of a receiver according to one embodiment.
Figure 18 is an example block diagram showing a computer system according to one embodiment.

Below, with reference to the attached drawings, embodiments of the present invention will be described in detail so that those skilled in the art can easily implement the present invention. However, the present invention may be implemented in many different forms and is not limited to the embodiments described herein.

In order to clearly explain the present invention in the drawings, parts that are not related to the description are omitted, and similar parts are given similar reference numerals throughout the specification. In the flowchart described with reference to the drawings, the order of operations may be changed, several operations may be merged, certain operations may be divided, and certain operations may not be performed.

Additionally, expressions written in the singular may be interpreted as singular or plural, unless explicit expressions such as “one” or “single” are used. Terms containing ordinal numbers, such as first, second, etc., may be used to describe various components, but the components are not limited by these terms. These terms may be used for the purpose of distinguishing one component from another.

1 is an example block diagram of a memory system according to one embodiment.

Referring to FIG. 1 , the memory system 100 includes a memory device 110 and a memory controller 120. In some embodiments, the memory device 110 and the memory controller 120 are connected through a memory interface and may exchange signals through the memory interface.

The memory device 110 includes a memory cell array (MEMORY CELL ARRAY) 111 and a data input/output circuit (DATA I/O CIRCUIT) 112. The memory cell array 111 includes a plurality of memory cells connected to a plurality of rows and a plurality of columns. The data I/O circuit 112 stores data transmitted from outside the memory device 110 (i.e., the memory controller 120, etc.) in the memory cell array 111 or stores data stored in the memory cell array 111. It can be output to the outside of the memory device 110. The data I/O circuit 112 may include a transmitter (TRANSMITTER) 113 and a receiver (RECEIVER) 114. The transmitter 113 may receive data DATA from the memory cell array 111 and output a data input/output signal DQ based on the data DATA. Transmitter 113 may output DQ in parallel through channels 130. When DQ is output to the channels 130 in parallel, a transition due to a signal may occur in the channels 130. For example, if a transition occurs in a channel adjacent to the target channel, signal transmission in the target channel may be interrupted. This phenomenon may be referred to as crosstalk. In some embodiments, the transmitter 113 may transmit signals using single-ended signaling. The receiver 123 may receive a signal transmitted through channels 130 from the transmitter 113 and determine the bits of the transmission signal by comparing the transmission signal and the reference signal. In the single-ended signaling method, when the DQ output through the channels 130 of the transmitter 113 switches in the same direction at the same time, noise (SSN: simultaneous switching output induced noise) is caused by the current flowing in the parasitic inductor. You can.

The transmitter 113 may output DQ in which data (DATA) is encoded. In some embodiments, the transmitter 113 may output DQ having different levels of voltage to each of the channels 130 for 1 unit interval (UI). The transmitter 113 may output DQ such that the sum of voltage changes in the channels 130 is substantially 0 between two consecutive UIs. As a result, the SSN of channels 130 can be removed.

The transmitter 113 may output DQ encoding data (DATA) to each of the channels 130 based on a gain value determined according to the arrangement of the channels 130. The gain value may include a crosstalk component to remove the influence of the signal component of the channel and the signal component of the adjacent channel. As a result, crosstalk occurring between adjacent channels can be reduced.

The transmitter 113 may output DQ through more channels 130 than the number of bits of data (DATA). In some embodiments, the number of channels 130 may be greater than the number of bits of data (DATA) by 1.

Channels 130 may be paths that physically or electrically connect the memory device 110 and the memory controller 120. For example, the channel 130 may be implemented using a through silicon via (TSV), a trace, or a coaxial cable.

The receiver 114 may receive DQ provided from the memory controller 120, decode the received DQ, and generate data (DATA). The receiver 114 may output the generated data (DATA) to the memory cell array 111. Since the receiver 114 of the memory device 110 is substantially the same as the receiver 123 of the memory controller 120, refer to the following description of the receiver 123 of the memory controller 120.

The memory controller 120 provides signals to the memory device 110 to control memory operations of the memory device 110. The signal may include a command (CMD) and an address (ADDR). In some embodiments, the memory controller 120 may provide a command (CMD) and an address (ADDR) to the memory device 110 to access the memory cell array 111 and control memory operations such as read or write. . According to a read operation, data may be transferred from the memory cell array 111 to the memory controller 120 as DQ, and according to a write operation, data may be transferred from the memory controller 120 to the memory cell array 111 as DQ.

The memory device 110 and the memory controller 120 can transmit and receive DQ to each other using a serial interfacing method. The memory controller 120 may access the memory device 110 according to a request from a host external to the memory system 100. The memory controller 120 may communicate with the host using various protocols. For example, the memory controller 120 may communicate with an external host through parallel interfacing. In some embodiments, the memory controller 200 may communicate with the host through serial interfacing.

Commands (CMD) may include an activate command, a read/write command, and a refresh command. The activation command may be a command that switches the target row of the memory cell array 111 to the active state in order to write data to or read data from the memory cell array 111. Memory cells in the target row may be activated (eg, driven) in response to the activation command. The read/write command may be a command to perform a read or write operation on the target memory cell of the row that has been switched to the active state. The refresh command may be a command to perform a refresh operation in the memory cell array 111.

The data I/O circuit 121 of the memory controller 120 may output data as DQ to the memory device 110 or receive DQ output from the memory device 110. Data I/O circuitry 121 may include a transmitter 122 and a receiver 123. The transmitter 122 may transmit data provided from an external host to the memory device 110. Since the transmitter 122 of the memory controller 120 is substantially the same as the transmitter 113 of the memory device 110, refer to the above description of the transmitter 113 of the memory device 110. The receiver 123 may receive DQ and decode the received DQ. In one embodiment, the receiver 123 may generate one data bit based on a plurality of DQs transmitted from a plurality of channels 130. For example, the receiver 123 may restore one bit of data DATA based on two DQs transmitted from two of the channels 130.

The memory device 110 may be a storage device based on a semiconductor device. In some embodiments, memory device 110 may include a dynamic random access memory (DRAM) device. In some embodiments, memory device 110 may include another volatile or non-volatile memory device for which transmitter 113 or receiver 114 is used.

Hereinafter, the data I/O circuit 112 of the memory device 110 will be described with reference to FIGS. 2 to 4 . However, the description below of the data I/O circuit 112 of the memory device 110 may be equally applied to the data I/O circuit 121 of the memory controller 120.

Figure 2 is a block diagram showing a memory device according to one embodiment.

Referring to FIG. 2, the memory device 200 includes a memory cell array 210, a sense amplifier 211, a control logic circuit 220, an address buffer 230, a row decoder 250, a column decoder 260, It includes an I/O gating circuit 270, and a data I/O circuit 280.

The memory cell array 210 includes a plurality of memory cells (MC). In some embodiments, the memory cell array 210 may include a plurality of memory banks 210a to 210h. Although eight memory banks (BANK0 to BANKh) (210a to 210h) are shown in FIG. 2, the number of memory banks is not limited thereto. Each memory bank 210a to 210h may include a plurality of rows, a plurality of columns, and a plurality of memory cells MC arranged at the intersection of the rows and columns. In some embodiments, a plurality of rows may be defined by a plurality of word lines (WL), and a plurality of columns may be defined by a plurality of bit lines (BL).

The control logic circuit 220 controls the operation of the memory device 200. For example, the control logic circuit 220 may generate a control signal so that the memory device 200 performs a read operation, a write operation, an offset calibration operation, etc. In some embodiments, control logic circuit 220 may include command decoder 221. The command decoder 221 may generate a control signal by decoding a command (CMD) received from a memory controller (eg, 120 in FIG. 1). In some embodiments, the control logic circuit 220 may further include a mode register 222 for setting the operating mode of the memory device 200.

The address buffer 230 receives an address (ADDR) provided from the memory controller 120. The address ADDR includes a row address RA indicating a row of the memory cell array 210 and a column address CA indicating a column. The row address (RA) is provided to the row decoder 250, and the column address (CA) is provided to the column decoder 260. In some embodiments, the memory device 200 may further include a row address multiplexer 251. The row address (RA) may be provided to the row decoder 250 through the row address multiplexer 251. In some embodiments, the address ADDR may further include a bank address BA indicating a memory bank. The bank address (BA) may be provided to the bank control logic 240.

In some embodiments, the memory device 200 may further include bank control logic 240 that generates a bank control signal in response to the bank address (BA). In response to the bank control signal, the bank control logic 240 activates the row decoder 250 corresponding to the bank address (BA) among the plurality of row decoders 250, and activates the bank address (BA) among the plurality of column decoders 260. The column decoder 260 corresponding to BA) can be activated.

The row decoder 250 selects a row to be activated from among a plurality of rows of the memory cell array 210 based on the row address. To this end, the row decoder 250 may apply a driving voltage to the word line corresponding to the row to be activated. In some embodiments, a plurality of row decoders 250a to 250h may be provided corresponding to a plurality of memory banks 210a to 210h.

The column decoder 260 selects a column to be activated among a plurality of columns of the memory cell array 210 based on the column address. To this end, the column decoder 260 may activate the sense amplifier 211 corresponding to the column address (CA) through the I/O gating circuit 270. In some embodiments, a plurality of column decoders 260a to 260h may be provided, respectively corresponding to a plurality of memory banks 210a to 210h. In some embodiments, the I/O gating circuit 270 gates input/output data and includes a data latch for storing data read from the memory cell array 210 and a write driver for writing data to the memory cell array 210. It can be included. Data read from the memory cell array 210 may be sensed by the sense amplifier 211 and stored in the I/O gating circuit 270 (eg, data latch). In some embodiments, a plurality of sense amplifiers 211a to 211h may be provided, respectively corresponding to a plurality of memory banks 210a to 210h.

In some embodiments, data read from the memory cell array 210 (eg, data stored in a data latch) may be provided to the memory controller 120 through the data I/O circuit 280. Data to be written to the memory cell array 210 is provided from the memory controller 120 to the data I/O circuit 280, and data provided to the data I/O circuit 280 is sent to the I/O gating circuit 270. can be provided.

The data I/O circuit 280 may output DQ or receive DQ. Data I/O circuitry 280 may include a transmitter 281 and a receiver 282. The transmitter 281 may encode the data (TXD) transmitted from the I/O gating circuit 270 and output it as DQ. The receiver 282 may decode the received DQ and transmit data (RXD) based on the decoded signal to the I/O gating circuit 270.

In one embodiment, the transmitter 281 may include a serializer (SER) 283, a pre-driver 284, and an output driver 285. The serializer 283 can convert parallel data (TXD) transmitted from the I/O gating circuit 270 into serial data. For example, serializer 283 may be an i:j serializer that converts i-bits of parallel data (TXD) to j-bits of serial data (where i and j are positive numbers, and i>j). . The pre-driver 284 may generate a pull-up control signal (PU) and a pull-down control signal (PD) based on serial data. In some embodiments, if the logical value of the serial data is a logic “low” level, the pre-driver 284 pulls the control signal (PU) up to a logic “low” level and pulls down to a logic “high” level. A control signal (PD) can be generated, and if the logic value of the serial data is a logic “high” level, the pull-up control signal (PU) at the logic “high” level and the pull-down control signal (PD) at the logic “low” level are generated. can be created. The output driver 285 can receive a pull-up control signal (PU) and a pull-down control signal (PD) and output them as an analog signal, DQ. In one embodiment, the output driver 285 may generate one DQ based on a plurality of pull-up control signals (PU) and a plurality of pull-down control signals (PD) generated in response to a plurality of bit data of serial data. there is. For example, a pull-up control signal (PU) and a plurality of pull-down control signals (PD) generated based on the first bit data of serial data and a pull-up control signal (PU) generated based on the second bit data and a plurality of One DQ output to one channel can be generated using a pull-down control signal (PD). In some embodiments, DQ may have voltage levels equal to the number of channels. For example, if the number of channels is 8, the voltage levels of DQ may be 8. In some embodiments, the transmitter 281 may further include an equalizer (not shown) that performs equalization to compensate for DQ distortion.

In one embodiment, receiver 282 may include an amplifier 286 and a deserializer (DES) 287. Amplifier 286 may amplify and sample the DQ to generate a decode signal (DCS). In some embodiments, amplifier 286 may have an input impedance for impedance matching with the transmitter (122 in FIG. 1). In some embodiments, the receiver 282 may further include an equalizer (not shown) that performs equalization to compensate for DQ distortion. The deserializer 287 may receive the decoded signal (DCS) and convert it into received data (RXD).

Next, with reference to FIG. 3, the output driver 285 of the transmitter 281 according to one embodiment will be described in detail.

Figure 3 is a block diagram showing part of a transmitter according to one embodiment.

Referring to FIG. 3, the pre-driver 300 receives data (D0, D1, ..., Dk) and generates a plurality of pull-up control signals (PU0, PU1, ..., PUk) and multiple pull-down control signals (PD0, PD1, ..., PDk) can be generated. The pre-driver 300 may include a plurality of drivers 302_0, 302_1, and 302_k. Each of the plurality of drivers (302_0, 302_1, 302_k) receives data (D0, D1, ..., Dk), pull-up control signals (PU0, PU1, ..., PUk) and pull-down control signals (PD0, PD1, ..., PDk) ) can be output.

The output driver 310 may receive a plurality of pull-up control signals (PU0, PU1, ..., PUk) and a plurality of pull-down control signals (PD0, PD1, ..., PDk). The output driver 310 generates data input/output signals (DQ0, DQ1, ..., DQh) based on a plurality of pull-up control signals (PU0, PU1, ..., PUk) and a plurality of pull-down control signals (PD0, PD1, ..., PDk). ) can be output.

In one embodiment, the output driver 310 may include a plurality of output modules 312_0, 312_1, and 312_h. Each of the plurality of output modules (312_0, 312_1, 312_h) receives two or more pull-up control signals among the plurality of pull-up control signals (PU0, PU1, ..., PUk), and receives a plurality of pull-down control signals (PD0, PD1, ..., PDk). ), two or more pull-down control signals can be input. Each of the plurality of output modules 312_0, 312_1, 312_h may output a corresponding one of the data input/output signals DQ0, DQ1, ..., DQh.

In one embodiment, the plurality of output modules 312_0, 312_1, 312_h may include a plurality of driver groups 314_0, 314_1, ..., 314_h. For example, the output module 312_0 may include a plurality of drivers 314_0a, 314_0b, ..., 314_0e. Each of the plurality of drivers 314_0a, 314_0b, ..., 314_0e may receive a corresponding one of two or more pull-up control signals and a corresponding one of two or more pull-down control signals. DQ0 may be output to the output terminal of the plurality of drivers 314_0a, 314_0b, ..., 314_0e by the pull-up control signal and the pull-down control signal. In some embodiments, two or more drivers among the plurality of drivers 314_0a, 314_0b, ..., 314_0e may receive the same pull-up control signal and the same pull-down control signal.

According to one embodiment, without a separate encoding process, the plurality of output modules 312_0, 312_1, 312_h output pull-up control signals (PU0, PU1, ..., PUk) and pull-down control signals (PD0, PUk) based on different bits of data. By performing pull-up/pull-down operations by PD1, ..., PDk), the corresponding DQ can be output.

Next, with reference to FIG. 4, the amplifier 286 of the receiver 282 according to one embodiment will be described in detail.

Figure 4 is a block diagram showing a receiver according to one embodiment.

Referring to FIG. 4, the receiver 400 may receive a plurality of data input/output signals (DQ0, DQ1, ..., DQh) and output decoding signals (D0, D1, ..., Dk). The receiver 400 may include a plurality of differential amplifiers (410_0, 410_1, ..., 410_k), a plurality of sampler circuits (420_0, 420_1, ..., 420_k), and a plurality of SR latches (430_0, 430_1, ..., 430_k). You can.

The plurality of differential amplifiers 410_0, 410_1, ..., 410_k may receive two or more data input/output signals among the plurality of data input/output signals DQ0, DQ1, ..., DQh. Each of the plurality of differential amplifiers 410_0, 410_1, ..., 410_k is configured to differentially amplify signals input to the first and second input terminals. In some embodiments, two or more differential amplifiers among the plurality of differential amplifiers 410_0, 410_1, ..., 410_k may receive the same data input/output signal. The plurality of differential amplifiers 410_0, 410_1, ..., 410_k may include analog signal processing circuits such as a continuous time linear equalizer (CTLE) and a pre-amplifier. For example, if the plurality of differential amplifiers (410_0, 410_1, …, 410_k) are CTLE, the plurality of differential amplifiers (410_0, 410_1, …, 410_k) remove/reduce channel distortion such as inter-symbol interference (ISI). Or, this can be compensated for, and the noise can be filtered to output the first and second differential output signals (C0a and C0b, C1a and C1b, Cka and Ckb).

A plurality of sampler circuits (420_0, 420_1, ..., 420_k) receive the first and second differential output signals (C0a and C0b, C1a and C1b, Cka and Ckb) and generate the first and second differential output signals in synchronization with the input clock signal (CK). The first and second differential output signals (C0a and C0b, C1a and C1b, Cka and Ckb) can be sampled.

A plurality of SR latches (430_0, 430_1, ..., 430_k) may latch the sampled signals (S0a and S0b, S1a and S1b, Ska and Skb) and output them as sampling data (SD0, SD1, ..., SDk).

According to one embodiment, without a separate decoding process, the receiver 400 differentially amplifies two or more data input and output signals among the plurality of data input and output signals (DQ0, DQ1, ..., DQh), thereby performing sampling data (SD0, SD1, ..., DQh). , SDk) can be output.

The number of drivers in each of the plurality of driver groups 314_0, 314_1, ..., 314_h in FIG. 3, the pull-up control signal and pull-down control signal applied to the plurality of drivers 314_0, 314_1, ..., 314_h, and the Data input/output signals applied to the plurality of differential amplifiers 410_0, 410_1, ..., 410_k may be determined according to the arrangement of channels (130 in FIG. 1) and the number of bits of data to be transmitted during 1 UI period.

In FIG. 3, between the data (D0, D1, ..., Dk) input to the pre-driver 300 and the signals (DQ0, DQ1, ..., DQh) output through the output driver 310, the following Equation 1 A relationship is established.

Here, matrix E defines a rule by which the output driver 310 encodes data (D0, D1, ..., Dk) into signals (DQ0, DQ1, ..., DQh), and can be expressed as Equation 2 below.

A plurality of drivers (314_0, 314_1, ..., 314_h) that output each of the signals (DQ0, DQ1, ..., DQh) include coefficients of a matrix E representing each of the signals (DQ0, DQ1, ..., DQh) and data (D0, Based on D1, ..., Dk), a pull-up control signal and a pull-down control signal can be input. For example, a plurality of drivers (314_0a, 314_0b, ..., 314_0e) that output DQ0 are based on the coefficients (E00, ..., E0k) and data (D0, D1, ..., Dk) of matrix E representing DQ0, The corresponding pull-up control signal and pull-down control signal can be input.

In FIG. 4, the relationship between the signals (DQ0, DQ1, ..., DQh) input to the receiver 400 and the data (SD0, SD1, ..., SDk) output through the receiver 400 is expressed in Equation 3 below: It is established.

Here, matrix D defines the rule by which the receiver 400 restores signals (DQ0, DQ1, ..., DQh) to data (SD0, SD1, ..., SDk), and can be expressed as Equation 4 below.

The differential amplifiers 410_0, 410_1, ..., 410_k for outputting each of the data (SD0, SD1, ..., SDk) use the coefficients of the matrix D representing each of the data (SD0, SD1, ..., SDk) and the signal (DQ0, Based on DQ1, ..., DQh), signals (DQ0, DQ1, ..., DQh) can be received at the first input terminal and the second input terminal. For example, the differential amplifier 410_0, which outputs differential output signals (C0a, C0b) used to output SD0, has the coefficients (D00, ..., D0h) of the matrix D representing SD0 and the signals (DQ0, DQ1, ...). , DQh), the corresponding signals (DQ0, DQ1, ..., DQh) can be received.

Matrix E and matrix D can be generated based on Equation 5 below to satisfy the following conditions.

Condition 1: The components of matrix E and matrix D must be integers.

Condition 2: will be a diagonal matrix

Condition 3: The sum of the components of each row of D is 0.

Condition 4: The sum of the absolute values of the components of each column of D must be less than or equal to the critical value (e.g., 10).

Here, z is a real number, S is the gain value matrix of each channel (hXh, h is a positive number), XT is the coupling coefficient matrix of each channel (hXh), A is a column vector representing data (kX1, k is a positive number) ) can be.

In Equation 5, D×S×E×A may be the restored data as a real multiple of A, and D×XT×E×A may be It may be an ingredient.

The components of matrix D and matrix E can be calculated to minimize the components interfering with the data in D×XT×E×A. That is, as shown in Equation 6, a matrix D such that the ratio with the maximum value among the ratios of the sum of the absolute values of the components of each row excluding the main diagonal component of D × (S + XT) × E × A and the ratio of the main diagonal components is the minimum. The components of and the components of matrix E can be calculated.

Here, c is a component of matrix C, and the matrix C=D×(S+XT)×E×A.

Below, with reference to FIGS. 5 to 14, a description will be given of the transmitter and receiver when transmitting and receiving 7-bit data through 8 channels.

Figure 5 is a diagram showing the arrangement of channels according to one embodiment.

Referring to FIG. 5, two adjacent channels among the plurality of channels 510, ..., 517 may be spaced apart from each other by the same distance (R). A data input/output signal (DQ) may be transmitted through a plurality of channels 510, ..., 517. A crosstalk effect may occur in each of the plurality of channels 510, ..., 517 due to signal transitions of adjacent channels. For example, a crosstalk effect may occur in the channel (CH2) 512 due to the four adjacent channels 510, 511, 513, and 514. A crosstalk effect may occur in the channel (CH1) 511 due to the three adjacent channels 510, 512, and 513. A crosstalk effect may occur in the channel (CH0) 510 due to two adjacent channels 511 and 512.

Figure 6 is a graph showing the gain of signals measured through a channel.

Graph 600 shows the strength of signals transmitted through a channel when the transmission rate is 10 Gbps. The gain value of the target channel (eg, CH2) measured at the Nyquist frequency (5 GHz) is approximately 330 m, and the gain value according to the coupling strength of channels adjacent to the target channel is measured to be approximately 75 m. The gain value according to the coupling strength of the remaining channels that are not adjacent to the target channel is assumed to be 0. Since the channels 510, ..., 517 are arranged symmetrically, the gain values of the remaining channels can be measured using the gain values measured in the channel CH2, that is, 330m and 75m. Based on this, the matrix is expressed as Equation 7 below.

The matrix of Equation 7 models the characteristics of the channels, that is, the coupling relationship between channels and the strength of mutual influence, and can be divided into a crosstalk component and a signal component as shown in Equation 8 and Equation 9 below.

Then, according to Equation 6 and Condition 1, Condition 2, and Condition 3 above, matrix E and matrix D can be calculated as in Equation 10 and Equation 11 below.

The total sum of the elements of matrix E and matrix D may each be 0. Therefore, the DQ output by the output driver 310 satisfies Equation 12 below.

Additionally, the sampling data (SD0, ..., SD6) output by the receiver 400 satisfies Equation 13 below.

Figure 7 is a block diagram showing a portion of an output driver according to one embodiment.

Referring to FIG. 7, the output driver 700 can output DQ0. DQ0 can be generated based on D0, D2, and D6, as in Equation 12. The relationship between DQ0, D0, D2, and D6 can be expressed as Equation 14.

The output driver 700 may output the data input/output signal DQ0 by emphasizing the data D0, D2, and D6 with intensity according to the components of the matrix E according to Equation 14. That is, the data D0, D2, and D6 can be encoded according to Equation 14 and output as DQ0 through the output node N0.

In one embodiment, the output driver 700 may include driver groups 710, 712, and 714 that receive pull-up control signals and pull-down control signals corresponding to data. For example, the driver group 710 may receive a pull-up control signal (PU0) and a pull-down control signal (PD0) corresponding to one bit of data (D0) of data to be transmitted.

In some embodiments, each driver group 710, 712, and 714 may include a number of drivers corresponding to the absolute value of the coefficient multiplied by the data. For example, the driver group 710 may include four first drivers 710a, 710b, 710c, and 710d, corresponding to the coefficient 4 multiplied by D0 in Equation 14. The drivers 710a, 710b, 710c, and 710d have a transistor (DT1) with one end connected to the first power voltage (VDDQ), the other end connected to the output node (N0), one end connected to the output node (N0), and the other end connected to the output node (N0). It may include a transistor (DT2) connected to the second power voltage (VSSQ). The first input terminal of the driver group 710 is connected to the gate of the transistor DT1 of the drivers 710a, 710b, 710c, and 710d, and the second input terminal is connected to the transistor DT2 of the drivers 710a, 710b, 710c, and 710d. can be connected to the gate of The driver group 712 may include three second drivers 712a, 712b, and 712c, corresponding to the coefficient 3 multiplied by D2 in Equation 14. The driver group 714 may include two third drivers 714a and 714b, corresponding to the coefficient 2 multiplied by D6 in Equation 14.

In some embodiments, each driver group 710, 712, and 714 receives a pull-up control signal and a pull-down control signal through a first input terminal and a second input terminal, or receives a pull-up control signal and a pull-down control signal according to the sign of the coefficient multiplied by the data. Control signals can be received through the second input terminal and the first input terminal. For example, since the sign of the coefficient multiplied by D0 is positive, the pull-up control signal PU0 is input to the first input terminal of the driver group 710, and the sign of the coefficient multiplied by D2 is negative. Therefore, the pull-up control signal PU2 may be input to the second input terminal of the driver group 712.

Figure 8 is a graph showing the signal output by the output driver according to one embodiment and the effects of SSN and crosstalk.

Referring to FIG. 8, the signal strength when outputting 7-bit data 11111111, 1101101, and 1000100 to DQ0 to DQ7 in each 1 UI period is shown. When 7-bit data 11111111 is output, and 7-bit data 1101101 is output, the sum of the changes in DQ0 to DQ7 is 0, so the sum of the currents flowing through the channels (510, ..., 517 in FIG. 5) is 0. SSN can be improved.

In addition, since some components (DQ3, DQ4) of the components (AGGRESSORS) that interfere with DQ2 transmitted through the channel 512 cancel each other (CANCELLATION), the crosstalk effect may be reduced.

Figure 9 is a circuit diagram showing a differential amplifier of a receiver according to an embodiment.

Referring to FIG. 9, the differential amplifier 900 may be a CTLE. The differential amplifier 900 may output first and second differential output signals C6a and C6b corresponding to the sampling data SD6. Sampling data (SD6) is DQ0, . . . as in Equation 13. , can be generated based on DQ7. SD6 and DQ0, … , The relationship between DQ7 can be expressed as Equation 15.

That is, the data input/output signals DQ0, ..., DQ7 can be decoded according to Equation 15 and output as first and second differential output signals C6a and C6b.

In one embodiment, the differential amplifier 900 includes transistors (PM1, PM2, PM3), first input transistors (PT0, ..., PT3), second input transistors (PT4, ..., PT7), and resistors ( R1, R2, R3), a capacitor (C1), and a current source (CS1). Sources of the power transistors PM1, PM2, and PM3 may be connected to the power supply voltage VDDA, and gates of the transistors PM1, PM2, and PM3 and drains of the transistor PM1 may be connected to the current source CS1. The drain of the transistor PM2 may be connected to one end of the resistor R1 and one end of the capacitor C1. The drain of the transistor PM3 may be connected to the other end of the resistor R1 and the other end of the capacitor C1.

Gates of the first input transistors PT0, ..., PT3 may receive corresponding data input/output signals DQ4, ..., DQ7. The source of the first input transistors PT0,..., PT3 may be connected to the drain of the transistor PM2, one end of the resistor R1, and one end of the capacitor C1, and the first input transistors PT0,... , PT3) may be connected to the resistor R2 and the first output node N1. Gates of the second input transistors PT4, ..., PT7 may receive corresponding data input/output signals DQ0, ..., DQ3. The source of the second input transistors PT4,..., PT7 may be connected to the drain of the transistor PM3, the other end of the resistor R1, and the other end of the capacitor C1, and the second input transistors PT4,... , PT7) may be connected to the resistor R3 and the second output node N2. A first differential output signal C6a may be output from the first output node N1, and a second differential output signal C6b may be output from the second output node N2. The output signal C6 of the differential amplifier 900 may be the difference between the first differential output signal C6a and the second differential output signal C6b.

In one embodiment, the differential amplifier 900 may include first input transistors (PT0, ..., PT3) and second input transistors (PT4, ..., PT7) in numbers based on coefficients multiplied by data input and output signals. You can. In some embodiments, depending on the sign of the coefficient, the data input/output signal may be received through the first input transistors (PT0, ..., PT3) or the second input transistors (PT4, ..., PT7). For example, since the sign of the coefficient multiplied by DQ0 is negative, DQ0 may be input to the gate of the second input transistor PT4. Likewise, since the sign of the coefficient multiplied by DQ4 is positive, DQ4 can be input to the gate of the first input transistor PT0. In some embodiments, the numbers of first and second input transistors (PT0, ..., PT7) corresponding to each of the data input/output signals (DQ0, ..., DQ7) are multiplied by the data input/output signals (DQ0, ..., DQ7). It may be a number corresponding to the quotients of dividing the coefficients by the greatest common divisor of the coefficients. For example, in order to decode the sampling data (SD6), the coefficients multiplied by the data input/output signals (DQ0, ..., DQ7) are all equal to 2, and the quotient obtained by dividing 2 by the greatest common divisor 2 is 1, so the data input/output signal The number of first and second input transistors corresponding to each of DQ0, ..., DQ7 may be one.

FIG. 10 is an eye diagram of a non-return to zero (NRZ) signal after passing through a channel, and FIG. 11 is an eye diagram of an output signal of a differential amplifier of a receiver according to an embodiment. The x-axis represents time, and the y-axis represents the level of the received signal.

Figure 10 shows the DQ signal received by the receiver when data is transmitted as an 8.75 Gbps NRZ signal in a channel unaffected by SSN, and Figure 11 shows a DQ signal received by the receiver when data is transmitted at 10 GBaud according to an embodiment in a channel unaffected by SSN. When represents the output signal of the receiver's differential amplifier. According to one embodiment, 7 data are transmitted through 8 channels, whereas according to the NRZ method, 7 data are transmitted through 7 channels. Therefore, to compare data transmission rates under the same conditions, when data is transmitted at 8.75Gbps, The NRZ signal was compared with the signal when transmitting data at 10GBaud according to one embodiment. According to one embodiment, the crosstalk effect was reduced compared to the conventional NRZ method, so the eye width (EYE WIDTH) increased by more than 70% and the eye height (EYE HEIGHT) increased by more than 270%.

FIG. 12 is an eye diagram of an NRZ signal with SSN added, and FIG. 13 is an eye diagram of an output signal of a differential amplifier of a receiver according to an embodiment with SSN added.

Figure 12 shows the DQ signal received by the receiver when data is transmitted with an 8.75 Gbps NRZ signal in a channel affected by SSN, and Figure 13 shows a DQ signal received by the receiver when data is transmitted at 10 GBaud according to an embodiment in a channel affected by SSN. When represents the output signal of the receiver's differential amplifier.

In Figure 12, the NRZ method completely closes the eye, while the eye width and eye height measured in Figure 13 do not change significantly compared to the eye width and eye height measured in Figure 11, showing robust results for SSN.

Figure 14 is an eye diagram of a signal output from a differential amplifier of a receiver according to an embodiment.

Referring to FIG. 14, the eye width and eye height of all seven output signals (C0, ..., C6) were measured to be large enough to sample the signals. Accordingly, the signal integrity characteristics of the seven output signals C0, ..., C6 can be improved.

Below, with reference to FIGS. 15 to 17, a description will be given of the transmitter and receiver when transmitting and receiving 5-bit data through 6 channels.

Figure 15 is a diagram showing the arrangement of channels according to one embodiment.

Referring to FIG. 15, two adjacent channels among the plurality of channels 1510, ..., 1515 may be positioned spaced apart by the same distance (R). A data input/output signal (DQ) may be transmitted through a plurality of channels 1510, ..., 1515. A crosstalk effect may occur in each of the plurality of channels 1510, ..., 1515 due to signal transitions of adjacent channels. For example, a crosstalk effect may occur in the channel (CH2) 1512 due to three adjacent channels 1510, 1511, and 1513. A crosstalk effect may occur in the channel (CH1) 1511 due to one adjacent channel 1512.

Matrix E and matrix D can be calculated as shown in Equation 16 and Equation 17 below, based on the gains of signals measured through channels.

The total sum of the elements of matrix E and matrix D may each be 0. Therefore, the DQ output by the output driver 310 satisfies Equation 18 below.

Additionally, the sampling data (SD0, ..., SD4) output by the receiver 400 satisfies Equation 19 below.

Figure 16 is a block diagram showing a portion of an output driver according to one embodiment.

Referring to FIG. 16, the output driver 1600 can output DQ0. DQ0 can be generated based on D0, D1, and D2, as in Equation 18. The relationship between DQ0, D0, D1, and D2 can be expressed as Equation 20.

That is, the data (D0, D1, and D2) can be encoded according to Equation 20 and output as DQ0 through the output node (N0).

In one embodiment, the output driver 1600 may include driver groups 1610, 1612, and 1614 that receive pull-up control signals and pull-down control signals corresponding to data. For example, the driver group 1610 may receive a pull-up control signal (PU0) and a pull-down control signal (PD0) corresponding to one bit of data (D0) of data to be transmitted.

In some embodiments, each driver group 1610, 1612, and 1614 may include a number of drivers corresponding to the absolute value of the coefficient multiplied by the data. For example, the driver group 1610 may include two drivers 1610a and 1610b, corresponding to the coefficient 2 multiplied by D0 in Equation 20. Drivers 1610a and 1610b have a transistor (DT1) with one end connected to the first power voltage (VDDQ), the other end connected to the output node (N0), one end connected to the output node (N0), and the other end connected to the second power supply. It may include a transistor (DT2) connected to a voltage (VSSQ). The first input terminal of the driver group 1610 may be connected to the gate of the transistor DT1 of the drivers 1610a and 1610b, and the second input terminal may be connected to the gate of the transistor DT2 of the drivers 1610a and 1610b.

In some embodiments, each driver group (1610, 1612, 1614) receives a pull-up control signal and a pull-down control signal through a first input terminal and a second input terminal, or receives a pull-up control signal and a pull-down control signal according to the sign of the coefficient multiplied by the data. Control signals can be received through the second input terminal and the first input terminal. For example, since the sign of the coefficient multiplied by D0 is positive, the pull-up control signal PU0 is input to the first input terminal of the driver group 1610, and since the sign of the coefficient multiplied by D2 is negative, the pull-up control signal (PU0) is input to the first input terminal of the driver group 1610. PU2) may be input to the second input terminal of the driver group 1612.

Figure 17 is a circuit diagram showing a differential amplifier of a receiver according to one embodiment.

Referring to FIG. 17, the differential amplifier 1700 may be a CTLE. The differential amplifier 1700 may output first and second differential output signals C0a and C0b corresponding to the sampling data SD0. Sampling data (SD0) is DQ0, . . . as in Equation 19. , can be generated based on DQ5. SD0 and DQ0, … , the relationship between DQ5 can be expressed as Equation 21.

That is, the data input/output signals DQ0, ..., DQ5 can be decoded according to Equation 21 and output as first and second differential output signals C0a and C0b.

In one embodiment, the differential amplifier 1700 includes transistors (PM1, PM2, PM3), first input transistors (PT0, PT1, PT2), second input transistors (PT3, PT4, PT5), and resistors ( R1, R2, R3), a capacitor (C1), and a current source (CS1). Sources of the power transistors PM1, PM2, and PM3 may be connected to the power supply voltage VDDA, and gates of the transistors PM1, PM2, and PM3 and drains of the transistor PM1 may be connected to the current source CS1. The current source CS1 may generate a bias current flowing through the transistor PM2 and a bias current flowing through the power transistor PM2. The drain of the transistor PM2 may be connected to one end of the resistor R1 and one end of the capacitor C1. The drain of the transistor PM3 may be connected to the other end of the resistor R1 and the other end of the capacitor C1.

Gates of the first input transistors PT0, PT1, and PT2 may receive corresponding data input/output signals DQ3, DQ4, and DQ5. The source of the first input transistors PT0, PT1, and PT2 may be connected to the drain of the transistor PM2, one end of the resistor R1, and one end of the capacitor C1, and the first input transistors PT0, PT1 , PT2) may be connected to the resistor R2 and the first output node N1. Gates of the second input transistors PT3, PT4, and PT5 may receive corresponding data input/output signals DQ0, DQ1, and DQ2. The source of the second input transistors PT3, PT4, and PT5 may be connected to the drain of the transistor PM3, the other end of the resistor R1, and the other end of the capacitor C1, and the second input transistors PT3, PT4 , PT5) may be connected to the resistor R3 and the second output node N2. A first differential output signal C0a may be output from the first output node N1, and a second differential output signal C0b may be output from the second output node N2. The output signal C0 of the differential amplifier 1700 may be the difference between the first differential output signal C0a and the second differential output signal C0b.

In one embodiment, the differential amplifier 1700 may include first input transistors (PT0, PT1, PT2) and second input transistors (PT3, PT4, PT5) in a number based on a coefficient multiplied by the data input/output signal. You can. In some embodiments, depending on the sign of the coefficient, the data input/output signal may be received through the first input transistors (PT0, PT1, and PT2) or the second input transistors (PT3, PT4, and PT5). For example, since the sign of the coefficient multiplied by DQ0 is negative, DQ0 may be input to the gate of the second input transistor PT3. Likewise, since the sign of the coefficient multiplied by DQ3 is positive, DQ3 can be input to the gate of the first input transistor PT0. In some embodiments, the numbers of first and second input transistors (PT0, ..., PT5) corresponding to each of the data input/output signals (DQ0, ..., DQ5) are multiplied by the data input/output signals (DQ0, ..., DQ5). It may be a number corresponding to the quotients of dividing the coefficients by the greatest common divisor of the coefficients. For example, in order to decode sampling data (SD0), the coefficients multiplied by the data input/output signals (DQ0, ..., DQ5) are all equal to 2, and the quotient obtained by dividing 2 by the greatest common divisor 2 is 1, so the data input/output signal The number of first and second input transistors corresponding to each of DQ0, ..., DQ5 may be one.

Figure 18 is an example block diagram showing a computer system according to one embodiment.

Referring to FIG. 18, the computing system 1800 includes a processor 1810, a memory 1820, a memory controller 1830, a storage device 1840, a communication interface 1850, and a bus 1860. Computing system 1800 may further include other general purpose components.

The processor 1810 controls the overall operation of each component of the computing system 1800. The processor 1810 may be implemented as at least one of various processing units, such as a central processing unit (CPU), an application processor (AP), or a graphic processing unit (GPU).

The memory 1820 stores various data and commands. The memory 1820 may be implemented as a memory device described with reference to FIGS. 1 to 17 . Memory controller 1830 controls the transfer of data or commands to and from memory 1820. The memory controller 1830 may be implemented as the memory controller described with reference to FIGS. 1 to 17 . In some embodiments, the memory controller 1830 may be provided as a separate chip from the processor 1810. In some embodiments, the memory controller 1830 may be provided as an internal component of the processor 1810. The memory 1820 and the memory controller 1830 can each encode data input/output signals transmitted to a target channel based on a plurality of data, and decode data based on a plurality of data input/output signals received through a plurality of channels. there is. Each of the memory 1820 and the memory controller 1830 may amplify a plurality of data based on the coefficients of the matrix E derived to satisfy Equation 5 and Conditions 1 to 4 and output them as data input/output signals. Each of the memory 1820 and the memory controller 1830 may differentially amplify a plurality of data input/output signals based on the coefficients of the matrix D derived to satisfy Equation 5 and Conditions 1 to 4 and output them as data.

The storage device 1840 non-temporarily stores programs and data. In some embodiments, storage device 1840 may be implemented as non-volatile memory. The communication interface 1850 supports wired and wireless Internet communication of the computing system 1800. Additionally, the communication interface 1850 may support various communication methods other than Internet communication. Bus 1860 provides communication functionality between components of computing system 1800. Bus 1360 may include at least one type of bus depending on the communication protocol between components.

In some embodiments, each component or combination of two or more components described with reference to FIGS. 1-18 may be a digital circuit, a programmable or non-programmable logic device or array, or an application specific integrated circuit. , ASIC), etc.

Although the embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements made by those skilled in the art using the basic concept of the present invention defined in the following claims are also possible. It falls within the scope of rights.

Claims (10)

A transmitter that outputs a plurality of data as a plurality of data input/output signals through a plurality of channels based on the matrix E, and
A receiver that generates the plurality of data by differentially amplifying the plurality of data input and output signals received through the plurality of channels based on the matrix D - all elements of the matrix E and the matrix D are integers, and the matrix D and The product matrix of the matrix E is a diagonal matrix, the sum of the components of each row of the matrix D is 0, and the sum of the absolute values of the components of each column of the matrix D is less than or equal to a threshold value -
A semiconductor system including. According to paragraph 1,
The components of the matrix D and the components of the matrix E are calculated according to the formula below,

Here, D is the matrix D, E is the matrix E, A is a column vector containing the plurality of data, S+XT is the main diagonal component is the signal strength of each of the plurality of channels, and the remaining components are adjacent channels. The crosstalk intensity matrix by
Semiconductor system. According to paragraph 1,
The transmitter includes a plurality of driver groups that output the plurality of data input/output signals,
A first driver group that outputs a first data input/output signal among the plurality of data input/output signals through a first channel among the plurality of channels, among the components of the matrix E corresponding to the first data input/output signal, A first number of first drivers based on the absolute value of the component corresponding to the first data among the plurality of data and the components of the matrix E corresponding to the first data input/output signal, corresponding to the second data among the plurality of data a second number of second drivers based on absolute values of the components,
Semiconductor system. According to paragraph 3,
Each of the first drivers in the first number is:
a first pull-up transistor connecting a first output node connected to the first channel and a first power voltage based on one of a first pull-up control signal and a first pull-down control signal generated based on the first data; Comprising a first pull-down transistor connecting the first output node and a second power supply voltage based on the other of the 1 pull-up control signal and the first pull-down control signal,
Semiconductor system. According to paragraph 4,
Among the components of the matrix E corresponding to the first data input/output signal, the first pull-up control signal is applied to the gate of the first pull-up transistor according to the sign of the component corresponding to the first data among the plurality of data. The first pull-down control signal is applied to the gate of the first pull-down transistor, or the first pull-up control signal is applied to the gate of the first pull-down transistor, and the first pull-down control signal is applied to the gate of the first pull-down transistor. applied to the gate of the transistor,
Semiconductor system. According to paragraph 4,
Each of the second drivers in the second number is:
A second pull-up transistor connecting the first output node and the first power voltage based on one of a second pull-up control signal and a second pull-down control signal generated based on the second data, and the second pull-up control signal And a second pull-down transistor connecting the first output node and the second power voltage based on another one of the second pull-down control signals,
Semiconductor system. According to paragraph 1,
wherein the sum of changes in the plurality of data input/output signals in the plurality of channels is substantially 0,
Semiconductor system. According to paragraph 1,
The receiver includes at least one first transistor electrically connecting a power supply voltage and a first node and at least one second transistor electrically connecting the power supply voltage and a second node, and the voltage of the first node And further comprising a differential amplifier outputting the voltage of the second node,
Semiconductor system. According to clause 8,
Among the components of the matrix D corresponding to the first data among the plurality of data, if the sign of the component corresponding to the first data input/output signal is positive, the first data input/output signal is transmitted from the at least one first transistor. approved at the gate,
Among the components of the matrix D corresponding to the first data among the plurality of data, if the sign of the component corresponding to the first data input/output signal is negative, the second data input/output signal is transmitted from the at least one second transistor. approved at the gate,
Semiconductor system. According to clause 8,
The number of the at least one first transistor is based on the absolute value of the component corresponding to the first data input/output signal among the components of the matrix D corresponding to the first data among the plurality of data,
The number of the at least one second transistor is based on the absolute value of the component corresponding to the second data input/output signal among the components of the matrix D corresponding to the first data among the plurality of data,
Semiconductor system.

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