CN117711453A - Semiconductor system - Google Patents

Abstract

A semiconductor system, comprising: a transmitter configured to output a plurality of data as a plurality of data input/output signals through a plurality of channels based on the matrix E; and a receiver configured to generate a plurality of data by differentially amplifying a plurality of data input/output signals received through a plurality of channels based on a matrix D, wherein all components of the matrix E and the matrix D are integers, a product matrix of the matrix D and the matrix E is a diagonal matrix, a sum of components of each row of the matrix D is 0, and a sum of absolute values of components of each column of the matrix D is less than or equal to a threshold.

Description

Semiconductor system

Cross Reference to Related Applications

The present application claims priority and benefit of korean patent application No. 10-2022-0112093 filed on 9 and 14 of 2022 and korean patent application No. 10-2022-0187703 filed on 12 and 28 of 2022, which are incorporated herein by reference in their entireties.

Technical Field

The present disclosure relates to a semiconductor system.

Background

To provide a high-speed input/output (I/O) interface, the transmitter/receiver may transmit and receive signals using a single-ended signaling method or a differential signaling method. The single-ended signaling method occupies a small area in the semiconductor device because the number of signal pins and signal lines required to implement single-ended signaling is smaller than the number of signal pins and signal lines required to implement differential signaling. However, when multiple single-ended ports on a transmitter are simultaneously switched in the same direction, the single-ended signaling approach may cause noise (e.g., SSN simultaneously switches output induced noise) through current flowing in the parasitic inductor, thereby increasing jitter of the output driver. Furthermore, the single-ended signaling method may be affected by transitions of adjacent signal lines, and thus, crosstalk may occur due to instantaneous changes in transition positions.

Disclosure of Invention

Aspects of the present disclosure provide a semiconductor system having advantages of preventing signal degradation due to SSN.

Aspects of the present disclosure provide a semiconductor system having the advantage of reducing crosstalk between adjacent signal lines.

According to one aspect of an example embodiment, a semiconductor system includes: a transmitter configured to output a plurality of data as a plurality of data input/output signals through a plurality of channels based on the matrix E; and a receiver configured to generate a plurality of data by differentially amplifying a plurality of data input/output signals received through a plurality of channels based on a matrix D, wherein all components of the matrix E and the matrix D are integers, a product matrix of the matrix D and the matrix E is a diagonal matrix, a sum of components of each row of the matrix D is 0, and a sum of absolute values of components of each column of the matrix D is less than or equal to a threshold.

According to one aspect of an example embodiment, a memory device includes a memory cell array and a transmitter configured to receive n (n is a natural number) data from the memory cell array and emphasize the n data in intensity according to components of a matrix E to generate n+1 data input/output signals, wherein a sum of the components of the matrix E is 0.

According to an aspect of an example embodiment, a memory system includes: a memory device configured to include a memory cell array and a transmitter encoding n data into n+1 data input/output signals and outputting the n+1 data input/output signals; and a memory controller configured to include a receiver that receives the n+1 data input/output signals and decodes the n data by differentially amplifying the n+1 data input/output signals according to components of the matrix D, wherein a sum of the components of the matrix D is 0.

Drawings

FIG. 1 is a block diagram of a memory system according to an example embodiment.

FIG. 2 is a block diagram of a memory device according to an example embodiment.

Fig. 3 is a block diagram illustrating a portion of a transmitter according to an example embodiment.

Fig. 4 is a block diagram of a receiver according to an example embodiment.

Fig. 5 is a diagram illustrating a channel arrangement according to an example embodiment.

Fig. 6 is a graph showing signal gains measured through a channel.

Fig. 7 is a block diagram illustrating a portion of an output driver according to an example embodiment.

Fig. 8 is a graph illustrating the effects of signals, SSNs, and crosstalk output from an output driver according to an example embodiment.

Fig. 9 is a circuit diagram illustrating a differential amplifier of a receiver according to an example embodiment.

Fig. 10 is an eye diagram of a non-return to zero (NRZ) signal after passing through a channel.

Fig. 11 is an eye diagram of a signal output from a differential amplifier of a receiver according to an example embodiment.

Fig. 12 is an eye diagram of an SSN-added NRZ signal.

Fig. 13 is an eye diagram of a signal output from a differential amplifier of a receiver according to an example embodiment.

Fig. 14 is an eye diagram of a signal output from a differential amplifier of a receiver according to an example embodiment.

Fig. 15 is a diagram illustrating an arrangement of channels according to an example embodiment.

Fig. 16 is a block diagram illustrating a portion of an output driver according to an example embodiment.

Fig. 17 is a circuit diagram illustrating a differential amplifier of a receiver according to an example embodiment.

FIG. 18 is a block diagram of a computer system according to an example embodiment.

Detailed Description

In the following detailed description, certain exemplary embodiments of the present invention have been shown and described, simply by way of illustration. As will be recognized by those skilled in the art, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the invention.

Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive. Like numbers refer to like elements throughout. In the flowcharts described with reference to the drawings, the order of operations may be changed, several operations may be combined, some operations may be divided, and a specific operation may not be performed.

Furthermore, unless explicitly stated otherwise, such as "a" or "an" is used, expressions written in the singular may be construed as singular or plural. Terms including ordinal numbers, such as first, second, etc., may be used to describe various components, but the components are not limited to these terms. These terms may be used for purposes of distinguishing one component from another.

FIG. 1 is a block diagram of a memory system according to an example embodiment.

Referring to fig. 1, a memory system 100 includes a memory device 110 and a memory controller 120. In some example embodiments, the memory device 110 and the memory controller 120 may be connected through a memory interface to exchange signals through the memory interface.

The memory device 110 includes a memory cell array 111 and a data input/output circuit (data I/O circuit) 112. The memory cell array 111 includes a plurality of memory cells connected to a plurality of rows and a plurality of columns. The data I/O circuit 112 may store data transferred from outside the memory device 110 (i.e., the memory controller 120, etc.) into the memory cell array 111, or output data stored in the memory cell array 111 to outside the memory device 110. The data I/O circuit 112 may include a transmitter 113 and a receiver 114. The transmitter 113 may receive the DATA from the memory cell array 111 and output a DATA input/output signal DQ based on the DATA. Transmitter 113 may output DQs in parallel over channel 130. When DQs are output in parallel to channel 130, signals in channel 130 may transition. For example, when the transition occurs in a channel adjacent to the target channel, the signal transmission of the target channel may be interrupted. This phenomenon may be referred to as crosstalk. In some example embodiments, the transmitter 113 may transmit signals in a single-ended signaling method. The receiver 123 may receive the signal transmitted through the channel 130 from the transmitter 113 and determine bits of the transmitted signal by comparing the transmitted signal with a reference signal. According to the single-ended signaling method, when DQs output from the transmitter 113 through the channel 130 are simultaneously switched in the same direction, current flowing in the parasitic inductor may induce noise (e.g., simultaneous switching output induced noise (SSN)).

The transmitter 113 may output the DQ of the encoded DATA. In some example embodiments, transmitter 113 may output DQs having different voltage levels to each channel 130 within one Unit Interval (UI). Transmitter 113 may output DQ such that the sum of the voltage changes in channel 130 is substantially 0 between two consecutive UIs. As a result, the SSN of channel 130 may be removed or reduced.

The transmitter 113 may output DQs encoded with DATA to each channel 130 based on gain values determined according to the arrangement of channels 130. The gain value may include a crosstalk component for removing the effects of the signal component of the channel and the signal component of the adjacent channel. Therefore, crosstalk occurring between adjacent channels can be reduced.

Transmitter 113 may output DQ through a greater number of channels 130 than the number of bits in DATA. In some example embodiments, the number of channels 130 may be 1 greater than the number of bits of the DATA.

The channel 130 may be a path that physically or electrically connects the memory device 110 and the memory controller 120. For example, the channel 130 may be implemented using a Through Silicon Via (TSV), trace, or coaxial cable.

The receiver 114 may receive DQs provided from the memory controller 120 and decode the received DQs to generate DATA. The receiver 114 may output the generated DATA to the memory cell array 111. Since the receiver 114 of the memory device 110 is substantially identical to the receiver 123 of the memory controller 120, reference will be made to the following description of the receiver 123 of the memory controller 120.

The memory controller 120 provides signals to the memory device 110 to control memory operations of the memory device 110. The signals may include a command CMD and an address ADDR. In some example embodiments, the memory controller 120 may provide commands CMD and addresses ADDR to the memory device 110 to access the memory cell array 111 and control memory operations such as reading or writing. Data is transferred from the memory cell array 111 to the memory controller 120 as DQs according to a read operation, and data can be transferred from the memory controller 120 to the memory cell array 111 as DQs according to a write operation.

Memory device 110 and memory controller 120 may send and receive DQs to each other via a serial interface method. Memory controller 120 may access memory device 110 upon request from an external host of memory system 100. The memory controller 120 may communicate with the host using various protocols. For example, the memory controller 120 may communicate with an external host through a parallel interface method. In some example embodiments, the memory controller 200 may communicate with a host through a serial interface method.

The commands CMD may include an activate command, a read/write command, and a refresh command. The activate command may be a command to convert a target row of the memory cell array 111 into an activated state in order to write data to the memory cell array 111 or read data from the memory cell array 111. In response to the activate command, the memory cells of the target row may be activated (e.g., driven). The read/write command may be a command for performing a read or write operation on a target memory cell of a row that transitions to an active state. The refresh command may be a command for performing a refresh operation in the memory cell array 111.

The data I/O circuits 121 of the memory controller 120 may output data to the memory device 110 as DQs or receive DQ outputs from the memory device 110. The data I/O circuit 121 may include a transmitter 122 and a receiver 123. The transmitter 122 may transmit data provided from an external host to the memory device 110. Since the transmitter 122 of the memory controller 120 is substantially identical to the transmitter 113 of the memory device 110, reference will be made to the above description of the transmitter 113 of the memory device 110. Receiver 123 may receive DQs and decode the received DQs. In an example embodiment, receiver 123 may generate one data bit based on a plurality of DQs transmitted from a plurality of channels 130. For example, receiver 123 may recover 1-bit DATA of DATA based on two DQs sent from two channels 130.

The memory device 110 may be a semiconductor device based storage device. In some example embodiments, the memory device 110 may include a Dynamic Random Access Memory (DRAM) device. In some example embodiments, the memory device 110 may include another volatile or nonvolatile memory device that uses the transmitter 113 or the receiver 114.

Hereinafter, the data I/O circuit 112 of the memory device 110 will be described with reference to fig. 2 to 4. However, hereinafter, the description of the data I/O circuitry 112 of the memory device 110 may apply equally to the data I/O circuitry 121 of the memory controller 120.

FIG. 2 is a block diagram of a memory device according to an example embodiment.

Referring to fig. 2, the memory device 200 includes a memory cell array 210, a sense amplifier 211, a control logic circuit 220, an address buffer 230, a row decoder 250, a column decoder 260, an I/O gating circuit 270, and a data I/O circuit 280.

The memory cell array 210 includes a plurality of memory cells MC. In some example embodiments, the memory cell array 210 may include a plurality of memory banks 210a to 210h. Although eight memory BANKs BANK0 to BANKh 210a to 210h are shown in fig. 2, the number of memory BANKs is not limited thereto. Each of the memory banks 210a to 210h may include a plurality of rows, a plurality of columns, and a plurality of memory cells MC arranged at intersections of the plurality of rows and the plurality of columns. In some example embodiments, the plurality of rows may be defined by a plurality of word lines WL and the plurality of columns may be defined by a plurality of bit lines BL.

The control logic 220 controls the operation of the memory device 200. For example, the control logic 220 may generate control signals to allow the memory device 200 to perform read operations, write operations, offset calibration operations, and the like. In some example embodiments, the control logic 220 may include a command decoder 221. The command decoder 221 may generate the control signal by decoding a command CMD received from a memory controller (e.g., 120 of fig. 1). In some example embodiments, the control logic 220 may also include a mode register 222 for setting the mode of operation of the memory device 200.

Address buffer 230 receives address ADDR provided from memory controller 120. The address ADDR includes a row address RA indicating a row of the memory cell array 210 and a column address CA indicating a column of the memory cell array 210. The row address RA is provided to the row decoder 250 and the column address CA is provided to the column decoder 260. In some example embodiments, the memory device 200 may further include a row address multiplexer 251. The row address RA may be supplied to the row decoder 250 through the row address multiplexer 251. In some example embodiments, the address ADDR may further include a bank address BA indicating a memory bank. The bank address BA may be provided to the bank control logic 240.

In some example embodiments, the memory device 200 may further include bank control logic 240, the bank control logic 240 generating the bank control signal in response to the bank address BA. The bank control logic 240 may activate a row decoder 250 corresponding to a bank address BA among the plurality of row decoders 250 and activate a column decoder 260 corresponding to a Bank Address (BA) among the plurality of column decoders 260 in response to the bank control signal.

The row decoder 250 selects a row to be activated from among a plurality of rows of the memory cell array 210 based on a row address. To this end, the row decoder 250 may apply a driving voltage to a word line corresponding to a row to be activated. In some example embodiments, a plurality of row decoders 250 a-250 h corresponding to the plurality of memory banks 210 a-210 h may be provided.

The column decoder 260 selects a column to be activated from a plurality of columns of the memory cell array 210 based on a column address. To this end, the column decoder 260 may activate the sense amplifier 211 corresponding to the column address CA through the I/O gating circuit 270. In some example embodiments, a plurality of column decoders 260a to 260h corresponding to the plurality of memory banks 210a to 210h, respectively, may be provided. In some example embodiments, the I/O gating circuit 270 may gate input and output data and include a data latch for storing data read from the memory cell array 210 and a write driver for writing data to the memory cell array 210. Data read from the memory cell array 210 may be detected by the sense amplifier 211 and stored in the I/O gating circuit 270 (e.g., a data latch). In some example embodiments, a plurality of sense amplifiers 211a to 260h corresponding to the plurality of memory banks 210a to 210h, respectively, may be provided.

In some example embodiments, data read from the memory cell array 210 (e.g., data stored in data latches) may be provided to the memory controller 120 through the data I/O circuit 280. Data to be written to the memory cell array 210 may be provided from the memory controller 120 to the data I/O circuit 280 and data provided to the data I/O circuit 280 may be provided to the I/O strobe circuit 270.

The data I/O circuit 280 may output DQ or receive DQ. The data I/O circuit 280 may include a transmitter 281 and a receiver 282. The transmitter 281 may encode the data TXD transmitted from the I/O gating circuit 270 and output the encoded data TXD as DQ. The receiver 282 may decode the received DQs and send data RXD to the I/O gating circuit 270 based on the decoded signals.

In an example embodiment, the transmitter 281 may include a Serializer (SER) 283, a pre-driver 284, and an output driver 285. Serializer 283 may convert parallel data TXD transmitted from I/O gating circuit 270 into serial data. For example, serializer 283 may be i: a j serializer that converts i-bit parallel data (TXD) into j-bit serial data (where i and j are positive numbers and i > j). The pre-driver 284 may generate a pull-up control signal PU and a pull-down control signal PD based on serial data. In some example embodiments, the pre-driver 284 may generate the logic "low" level pull-up control signal PU and the logic "high" level pull-down control signal PD when the logic value of the serial data is a logic "low" level, and generate the logic "high" level pull-up control signal PU and the logic "low" level pull-down control signal PD when the logic value of the serial data is a logic "high" level. The output driver 285 may receive the pull-up control signal PU and the pull-down control signal PD, and output the received pull-up control signal PU and pull-down control signal PD as DQ as analog signals. In some example embodiments, the output driver 285 may generate one DQ based on a plurality of pull-up control signals PU and a plurality of pull-down control signals PD generated in response to a plurality of bit data of the serial data. For example, the output driver 285 may generate one DQ output to one channel by using a plurality of pull-up control signals PU and a plurality of pull-down control signals PD generated based on first bit data of the serial data and a plurality of pull-up control signals PU and a plurality of pull-down control signals PD generated based on second bit data. In some example embodiments, DQs may have voltage levels for the number of channels. For example, when the number of channels is 8, the voltage level of DQ may be 8. In some example embodiments, transmitter 281 may also include an equalizer (not shown) that performs equalization to compensate for DQ distortion.

In an example embodiment, the receiver 282 may include an amplifier 286 and a Deserializer (DES) 287. Amplifier 286 may amplify and sample DQ to generate decoded signal DCS. In some example embodiments, the amplifier 286 may have an input impedance for impedance matching with the transmitter (122 in fig. 1). In some example embodiments, receiver 282 may further include an equalizer (not shown) that performs equalization to compensate for DQ distortion. The deserializer 287 may receive the decoded signal DCS and convert the received decoded signal DCS into the received data RXD.

Next, referring to fig. 3, the output driver 285 of the transmitter 281 according to an example embodiment will be described in detail.

Fig. 3 is a block diagram illustrating a portion of a transmitter according to an example embodiment.

Referring to fig. 3, the pre-driver 300 may correspond to the pre-driver 284 in fig. 2. The pre-driver 300 may receive the data D0, D1, …, dk and generate a plurality of pull-up control signals PU0, PU1, and PUk and a plurality of pull-down control signals PD0, PD1, and PDk based on the logical values of the data D0, D1, and. The pre-driver 300 may include a plurality of drivers 302_0, 302_1, and 302_k. Each of the plurality of drivers 302_0, 302_1, and 302—k may receive the data D0, D1, and the driving voltages Dk and output the pull-up control signals PU0, PU1, and PUk, and the pull-down control signals PD0, PD1, and the driving voltages PDk.

The output driver 310 may receive a plurality of pull-up control signals PU0, PU1, PUk and a plurality of pull-down control signals PD0, PD1, PDk. The output driver 310 may output data input and output signals DQ0, DQ1, …, DQh based on a plurality of pull-up control signals PU0, PU1, and PUk and a plurality of pull-down control signals PD0, PD1, and PDk.

In an example embodiment, the output driver 310 may include a plurality of output modules 312_0, 312_1, and 312_h. Each of the plurality of output modules 312_0, 312_1, and 312_h may receive two or more pull-up control signals among the plurality of pull-up control signals PU0, PU1, and PUk, and two or more pull-down control signals among the plurality of pull-down control signals PD0, PD1, and PDk. Each of the plurality of output modules 312_0, 312_1, and 312_h may output a corresponding one of the data input/output signals DQ0, DQ 1.

In an example embodiment, the plurality of output modules 312_0, 312_1, and 312_h may include a plurality of driver groups 314_0, 314_1,. For example, the output module 312_0 may include a plurality of drivers 314_0a, 314_0b. Each of the plurality of drivers 314_0a, 314_0b, 314_0e may receive a corresponding one of the two or more pull-up control signals and a corresponding one of the two or more pull-down control signals. DQ0 may be output to the output terminals of the plurality of drivers 314_0a, 314_0b, and..314_0e by a pull-up control signal and a pull-down control signal. In some example embodiments, two or more drivers among the plurality of drivers 314_0a, 314_0b, 314_0e may receive the same pull-up control signal and pull-down control signal.

According to example embodiments, the plurality of output modules 312_0, 312_1, and 312_h operate a pull-up/pull-down operation through pull-up control signals PU0, PU1, and PUk and pull-down control signals PD0, PD1, and PDk based on data of different bits without a separate encoding process, thereby outputting corresponding DQs.

Next, referring to fig. 4, an amplifier 286 of the receiver 282 according to an example embodiment will be described in detail.

Fig. 4 is a block diagram of a receiver according to an example embodiment.

Referring to fig. 4, a receiver 400 may correspond to the receiver 282 of fig. 2. The receiver 400 may receive a plurality of data input/output signals DQ0, DQ1, and DQh, and output decoded signals D0, D1, and Dk. The receiver 400 may include a plurality of differential amplifiers 410_0, 410_1..410_k, a plurality of sampler circuits 420_0, 420_1..420_k, and a plurality of SR latches 430_0, 430_1..430_k.

The plurality of differential amplifiers 410_0, 410_1, 410—k may receive two or more data input/output signals among the plurality of data input/output signals DQ0, DQ1, DQh. Each of the plurality of differential amplifiers 410_0, 410_1, 410—k is configured to differentially amplify signals input to the first input terminal and the second input terminal. In some example embodiments, two or more differential amplifiers among the plurality of differential amplifiers 410_0, 410_1, 410—k may receive the same data input/output signal. The plurality of differential amplifiers 410_0, 410_1, 410—k may include analog signal processing circuitry, such as a continuous time linear equalizer (continuous time linear equalizer, CTLE) and a pre-amplifier. For example, when the plurality of differential amplifiers 410_0, 410_1, 410_k are CTLE, the plurality of differential amplifiers 410_0, 410_1, 410_k may cancel/reduce channel distortion such as inter-symbol interference (inter-symbol interference, ISI) and compensate for the channel distortion, and filter noise to output the first and second differential output signals C0a and C0b, C1a and C1b, and Cka and cbb.

The plurality of sampler circuits 420_0, 420_1, 420_k may receive the first and second differential output signals C0a and C0b, C1a and C1b, and Cka and Ckb, and sample the first and second differential output signals C0a and C0b, C1a and C1b, and Cka and Ckb in synchronization with the input clock signal CK.

The plurality of SR latches 430_0, 430_1, 430_k may latch sampling signals S0a and S0b, S1a and S1b, …, ska and Skb, and output the latched sampling signals S0a and S0b, S1a and S1b, …, ska and Skb as sampling data SD0, SD1, SDk.

According to an example embodiment, the receiver 400 differentially amplifies two or more data input/output signals among the plurality of data input/output signals DQ0, DQ1, DQh without a separate decoding process, thereby outputting the sampled data SD0, SD1, SDk.

The number of drivers of each of the plurality of driver groups 314_0, 314_1,..314_h in fig. 3, the pull-up control signal and the pull-down control signal applied to the plurality of drivers 314_0, 314_1,..314_h, and the data input/output signal applied to the plurality of differential amplifiers 410_0, 410_1,..410_k in fig. 4 may be determined according to the arrangement of channels (130 in fig. 1) and the number of bits of data to be transmitted during one UI period.

In fig. 3, as shown in the following equation 1, a relationship is established between data D0, D1, D, dk input to the pre-driver 300 and signals DQ0, DQ1, D, DQh output through the output driver 310.

(equation 1)

Here, the matrix E defines rules for the output driver 310 to encode the data D0, D1, dk into the signals DQ0, DQ1, DQh, and may be expressed as the following equation 2.

(equation 2)

The plurality of drivers 314_0, 314_1, and..314_h, which respectively output the signals DQ0, DQ1, and.. DQh, may receive the pull-up control signal and the pull-down control signal based on the coefficients of the matrix E and the data D0, D1, and Dk, which respectively represent the signals DQ0, DQ1, and.. DQh. For example, the plurality of drivers 314_0a, 314_0b, and..fwdarw.314_0e that output DQ0 may receive corresponding pull-up and pull-down control signals based on coefficients E00, …, E0k and data D0, D1, and Dk representing a matrix E of DQ 0.

In fig. 4, as shown in the following equation 3, a relationship is established between signals DQ0, DQ1,.. DQh input to the receiver 400 and data SD0, SD1,..sdk output through the receiver 400.

(equation 3)

Here, the matrix D defines a rule that the receiver 400 restores the signals DQ0, DQ1,.. DQh to the data SD0, SD1,..and SDk, and may be expressed as the following equation 4.

(equation 4)

The differential amplifier 410_0, 410_1 for outputting each data SD0, SD1, SDk may receive the signals DQ0, DQ1, and DQh input to the first and second input terminals based on the coefficients of the matrix D representing each data SD0, SD1, SD, and the signals DQ0, DQ1, DQh. For example, based on the coefficients D00, # D0h and the signals DQ0, DQ1, # DQh of the matrix D representing SD0, the differential amplifier 410_0 outputting the differential output signals C0a and C0b for outputting SD0 may receive the corresponding signals of the signals DQ0, DQ1, DQh.

The matrix E and the matrix D may be generated based on equation 5 to satisfy the following condition.

Condition 1: the components (i.e., elements) of matrix E and matrix D should be integers

Condition 2: dxE should be a diagonal matrix

Condition 3: the sum of the components of each row of D should be 0

Condition 4: the sum of the absolute values of the components of each column of D should be less than or equal to a threshold (e.g., 10)

(equation 5)

zA＝D×(S+XT)×E×A

Here, z may be a real number, S may be a gain value matrix of each channel (hXh, h is a positive number), XT may be a coupling coefficient matrix of each channel (hXh), and a may be a column vector (kX 1, k is a positive number) representing data. Thus, s+xt is a matrix where the main diagonal component is the signal strength of each of the plurality of channels and the remaining component is the crosstalk strength of the adjacent channels.

In equation 5, dxSxExA may be data reconstructed as a real multiple of a, and DxXTxExA may be a component that interferes with recovered data due to the crosstalk effect of channel 130.

The components of matrices D and E may be calculated so as to minimize the components of the interference data in d×xt×e×a. That is, as shown in equation 6, the components of the matrix D and the components of the matrix E may be calculated so as to minimize the ratio having the maximum value among the ratios of the main diagonal components of d× (s+xt) xexa, and the sum of the absolute values of the components of each row other than the main diagonal components of d× (s+xt) xexa.

(equation 6)

Here, C is a component of matrix C, where matrix c=d× (s+xt) ×e×a.

Hereinafter, referring to fig. 5 to 14, a transmitter and a receiver when 7-bit data is transmitted and received through 8 channels will be described.

Fig. 5 is a diagram illustrating a channel arrangement according to an example embodiment.

Referring to fig. 5, two adjacent channels among the plurality of channels 510-517 may be spaced apart from each other by the same distance R. The data input/output signal DQ may be transmitted over multiple channels 510-517. In each of the plurality of channels 510-517, crosstalk effects according to signal transitions of adjacent channels may occur. For example, a crosstalk effect may be generated in channel CH2 512 by four adjacent channels 510, 511, 513, and 514. The crosstalk effect of the three adjacent channels 510, 512 and 513 may occur in the channel CH1 511. Crosstalk caused by two adjacent channels 511 and 512 may occur in channel CH0 510.

Fig. 6 is a graph showing signal gains measured through a channel.

Graph 600 shows the strength of a signal transmitted over a channel at a transmission rate of 10 Gbps. The gain value of the target channel (e.g., CH 2) measured at the nyquist frequency (5 GHz) is about 330m, and the gain value measured according to the coupling strength of the channel adjacent to the target channel is about 75m. The gain value according to the coupling strength of the remaining channels not adjacent to the target channel is assumed to be 0. Since channels 510-517 are symmetrically arranged, the gain values measured in channel CH2, i.e., 330m and 75m, may also be measured for other channels. Based on this, the matrix is expressed as the following equation 7.

(equation 7)

The matrix of equation 7 models the channel characteristics, i.e., the coupling relationship between channels and the strength of the interaction, and can be divided into a crosstalk component and a signal component, as shown in equations 8 and 9 below.

(equation 8)

(equation 9)

Then, according to equation 6 and conditions 1, 2, and 3, the matrix E and the matrix D can be calculated as in equations 10 and 11 below.

(equation 10)

(equation 11)

The sum of the components of matrix E and matrix D may each be 0. Accordingly, the DQ output from the output driver 310 satisfies the following equation 12.

(equation 12)

In addition, the sampling data SD0 to SD6 outputted from the receiver 400 satisfy the following equation 13.

(equation 13)

Fig. 7 is a block diagram illustrating a portion of an output driver according to an example embodiment.

Referring to fig. 7, the output driver 700 may correspond to the output driver 285 of fig. 2. Output driver 700 may output DQ0.DQ0 may be generated based on D0, D2, and D6 as shown in equation 12. The relationship between DQ0 and D0, D2 and D6 can be expressed as equation 14.

(equation 14)

DQ0＝4D0-3D2-2D6

According to equation 14, the output driver 700 may output the data input/output signal DQ0 by emphasizing the data D0, D2, and D6 with intensities according to the components of the matrix E. That is, data D0, D2, and D6 may be encoded according to equation 14 and output as DQ0 through output node N0.

In an example embodiment, the output driver 700 may include driver groups 710, 712, and 714 that receive pull-up control signals and pull-down control signals corresponding to data. For example, the driver group 710 may receive a pull-up control signal PU0 and a pull-down control signal PD0 corresponding to 1-bit data D0 of data to be transmitted.

In some example embodiments, each of the driver groups 710, 712, and 714 may include a number of drivers corresponding to an absolute value of a coefficient multiplied by the data. For example, the driver group 710 may include four first drivers 710a, 710b, 710c, and 710D corresponding to a coefficient 4 multiplied by D0 in equation 14. The drivers 710a, 710b, 710c, and 710d may include a transistor DT1 and a transistor DT2, one end of the transistor DT1 being connected to the first power voltage VDDQ, the other end being connected to the output node N0, one end of the transistor DT2 being connected to the output node N0, the other end being connected to the second power voltage VSSQ. A first input terminal of the driver group 710 may be connected to gates of the transistors DT1 of the drivers 710a, 710b, 710c, and 710d, and a second input terminal may be connected to gates of the transistors DT2 of the drivers 710a, 710b, 710c, and 710d. The driver set 712 may include three second drivers 712a, 712b, and 712c corresponding to a coefficient 3 multiplied by D2 in equation 14. The driver set 714 may include two third drivers 714a and 714b corresponding to a coefficient 2 multiplied by D6 in equation 14.

In some example embodiments, each of the driver groups 710, 712, and 714 may receive a pull-up control signal and a pull-down control signal input to the first input terminal and the second input terminal, or a pull-up control signal and a pull-down control signal input to the second input terminal and the first input terminal, depending on a sign of a coefficient multiplied by data. For example, since the sign of the coefficient multiplied by D0 is positive, the pull-up control signal PU0 is input to the first input terminal of the driver group 710, and since the sign of the coefficient multiplied by D2 is negative, the pull-up control signal PU2 may be input to the second input terminal of the driver group 712.

Fig. 8 is a graph illustrating the effects of signals, SSNs, and crosstalk output from an output driver according to an example embodiment.

Referring to fig. 8, signal strengths when 7-bit data 1111111, 1101101, and 1000100 are output to DQ0 through DQ7 in each 1UI period are shown. When 7-bit data 1111111 is output and 7-bit data 1101101 is output, the sum of the changes of DQ0 through DQ7 is 0, and thus the sum of currents flowing through channels (510 to 517 in fig. 5) becomes 0, thereby improving SSN.

In addition, since some DQ3 and DQ4 in the component (aggrestors) of DQ2 transmitted through the channel 512 are interfered with each other (cancel), the crosstalk effect can be reduced.

Fig. 9 is a circuit diagram illustrating a differential amplifier of a receiver according to an example embodiment.

Referring to fig. 9, the differential amplifier 900 may be a CTLE. The differential amplifier 900 may output first and second differential output signals C6a and C6b corresponding to the sampling data SD 6. As in equation 13, sample data SD6 may be generated based on DQ0-DQ 7. The relationship between SD6 and DQ0-DQ7 can be expressed as equation 15.

(equation 15)

SD6＝-2DQ0-2DQ1-2DQ2-2DQ3+2DQ4+2DQ5+2DQ6+2DQ7

That is, the data input/output signals DQ0 through DQ7 can be decoded according to equation 15 and output as the first and second differential output signals C6a and C6b.

In an example embodiment, the differential amplifier 900 may include transistors PM1, PM2, and PM3, first input transistors PT0-PT3, second input transistors PT4-PT7, resistors R1, R2, and R3, a capacitor C1, and a current source CS1. The sources of the power transistors PM1, PM2, and PM3 may be connected to the power supply voltage VDDA, the gates of the transistors PM1, PM2, and PM3, and the drain of the transistor PM1 may be connected to the current source CS1. The drain of the transistor PM2 may be connected to one end of the resistor R1 and one end of the capacitor C1. The drain of the transistor PM3 may be connected to the other end of the resistor R1 and the other end of the capacitor C1.

The gates of the first input transistors PT0-PT3 may receive corresponding data input/output signals DQ4-DQ7. The sources of the first input transistors PT0-PT3 may be connected to the drain of the transistor PM2, one end of the resistor R1, and one end of the capacitor C1, and the drains of the first input transistors PT0-PT3 may be connected to the resistor R2 and the first output node N1. The gates of the second input transistors PT4-PT7 may receive corresponding data input/output signals DQ0-DQ3. The sources of the second input transistors PT4-PT7 may be connected to the drain of the transistor PM3, the other end of the resistor R1, and the other end of the capacitor C1, and the drains of the second input transistors PT4-PT7 may be connected to the resistor R3 and the second output node N2. The first differential output signal C6a may be output from the first output node N1, and the second differential output signal C6b may be output from the second output node N2. The output signal C6 of the differential amplifier 900 may be a difference between the first differential output signal C6a and the second differential output signal C6 b.

In an example embodiment, the differential amplifier 900 may include first input transistors PT0-PT3 and second input transistors PT4-PT7, the number of which is based on a coefficient multiplied by a data input/output signal. In some example embodiments, the data input/output signals may be received by the first input transistors PT0-PT3 or the second input transistors PT4-PT7 depending on the sign of the coefficient. For example, since the sign of the coefficient multiplied by DQ0 is negative, DQ0 may be input to the gate of the second input transistor PT 4. Similarly, because the sign of the coefficient multiplied by DQ4 is positive, DQ4 can be input to the gate of the first input transistor PT 0. In some example embodiments, the number of the first and second input transistors PT0-PT7 corresponding to each of the data input/output signals DQ0-DQ7 may be a number corresponding to a quotient obtained by dividing a coefficient by a greatest common divisor of the coefficients multiplied by the data input/output signals DQ0-DQ 7. For example, since all coefficients multiplied by the data input/output signals DQ0 through DQ7 to decode the sampled data SD6 are equal to 2, and a quotient obtained by dividing 2 by the greatest common divisor 2 is 1, all the numbers of the first and second input transistors corresponding to each of the data input and output signals DQ0 through DQ7 may be 1.

Fig. 10 is an eye diagram of a non-return to zero (NRZ) signal after passing through a channel, and fig. 11 is an eye diagram of an output signal of a differential amplifier of a receiver according to an example embodiment. The x-axis represents time and the y-axis represents the level of the received signal.

Fig. 10 illustrates DQ signals received by a receiver when data is transmitted as an NRZ signal of 8.75Gbps in a channel unaffected by the SSN, and fig. 11 illustrates output signals of a differential amplifier of the receiver when data is transmitted at 10GBaud in a channel unaffected by the SSN according to an example embodiment. According to an example embodiment, 7 data is transmitted to 7 channels according to the NRZ method, as compared to 7 data transmitted to eight channels. Thus, for a data rate comparison under the same conditions, according to an example embodiment, the NRZ signal when data is transmitted at 8.75Gbps is compared to the signal when data is transmitted at 10 GBaud. According to an exemplary embodiment, the crosstalk effect is reduced compared to the conventional NRZ method, and thus the eye width is increased by more than 70% and the eye height is increased by more than 270%.

Fig. 12 is an eye diagram of an SSN-added NRZ signal, and fig. 13 is an eye diagram of an output signal of a differential amplifier of a receiver according to an example embodiment to which SSN is added.

Fig. 12 shows DQ signals received by a receiver when data is transmitted as an NRZ signal of 8.75Gbps in a channel affected by SSN, and fig. 13 shows output signals of a differential amplifier of the receiver when data is transmitted at 10GBaud in a channel affected by SSN according to an example embodiment.

According to the NRZ method in fig. 12, the eyes are completely closed, but since the eye width and eye height measured in fig. 13 are not significantly changed from those measured in fig. 11, a result robust to SSN can be seen.

Fig. 14 is an eye diagram of a signal output from a differential amplifier of a receiver according to an example embodiment.

Referring to fig. 14, the eye width and eye height of all seven output signals C0-C6 are measured to be large enough to sample the signals. Thus, the signal integrity characteristics of the seven output signals C0-C6 may be improved.

Hereinafter, referring to fig. 15 to 17, a transmitter and a receiver when transmitting and receiving 5-bit data through 6 channels will be described.

Fig. 15 is a diagram illustrating a channel arrangement according to an example embodiment.

Referring to fig. 15, two adjacent channels among the plurality of channels 1510-1515 may be spaced apart from each other by the same distance R. The data input/output signal DQ may be transmitted over multiple channels 1510-1515. In each of the plurality of channels 1510-1515, crosstalk effects according to signal transitions of adjacent channels may occur. For example, crosstalk effects due to the three adjacent channels 1510, 1511, and 1513 may occur in channel CH2 1512. Crosstalk effects due to one adjacent channel 1512 may occur in channel CH1 1511.

Based on the signal gains measured through the channels, the matrices E and D can be calculated as shown in equations 16 and 17 below.

(equation 16)

(equation 17)

The sum of the components of matrix E and matrix D may each be zero. Accordingly, the DQ output from the output driver 310 satisfies the following equation 18.

(equation 18)

Further, the sampling data SD0 to SD4 outputted from the receiver 400 satisfy the following equation 19.

(equation 19)

Fig. 16 is a block diagram illustrating a portion of an output driver according to an example embodiment.

Referring to fig. 16, an output driver 1600 may output DQ0.DQ0 may be generated based on D0, D1, and D2, as shown in equation 18. The relationship between DQ0 and D0, D1 and D2 can be expressed as equation 20.

(equation 20)

DQ0＝2D0-2D1-3D2

That is, the data D0, D1, and D2 may be encoded according to equation 20 and output as DQ0 through the output node N0.

In an example embodiment, the output driver 1600 may include driver groups 1610, 1612, and 1614 receiving a pull-up control signal and a pull-down control signal corresponding to data. For example, the driver group 1610 may receive a pull-up control signal PU0 and a pull-down control signal PD0 corresponding to 1-bit data D0 of data to be transmitted.

In some example embodiments, each of the driver groups 1610, 1612, and 1614 may include a number of drivers corresponding to an absolute value of a coefficient multiplied by data. For example, the driver group 1610 may include two drivers 1610a and 1610b corresponding to a coefficient 2 multiplied by D0 in equation 20. The drivers 1610a and 1610b may include a transistor DT1 having one end connected to the first power voltage VDDQ and the other end connected to the output node N0, and a transistor DT2 having one end connected to the output node N0 and the other end connected to the second power voltage VSSQ. A first input terminal of the driver set 1610 may be connected to the gates of the transistors DT1 of the drivers 1610a and 1610b, and a second input terminal may be connected to the gates of the transistors DT2 of the drivers 1610a and 1610b.

In some example embodiments, each of the driver groups 1610, 1612, and 1614 may receive a pull-up control signal and a pull-down control signal input to the first input terminal and the second input terminal, or a pull-up control signal and a pull-down control signal input to the second input terminal and the first input terminal, depending on a sign of a coefficient multiplied by data. For example, since the sign of the coefficient multiplied by D0 is positive, the pull-up control signal PU0 is input to the first input terminal of the driver group 1610, and since the sign of the coefficient multiplied by D2 is negative, the pull-up control signal PU2 may be input to the second input terminal of the driver group 1612.

Fig. 17 is a circuit diagram illustrating a differential amplifier of a receiver according to an example embodiment.

Referring to fig. 17, the differential amplifier 1700 may be a CTLE. The differential amplifier 1700 may output first and second differential output signals C0a and C0b corresponding to the sampling data SD0. As in equation 19, sample data SD0 may be generated based on DQ0-DQ 5. The relationship between SD0 and DQ0-DQ5 can be expressed as equation 21.

(equation 21)

SD0＝2DQ0+2DQ1+2DQ2-2DQ3-2DQ4-2DQ5

That is, the data input/output signals DQ0 through DQ5 can be decoded according to equation 21 and output as the first and second differential output signals C0a and C0b.

In an example embodiment, the differential amplifier 1700 may include transistors PM1, PM2, and PM3, first input transistors PT0, PT1, and PT2, second input transistors PT3, PT4, and PT5, resistors R1, R2, and R3, a capacitor C1, and a current source CS1. The sources of the power transistors PM1, PM2, and PM3 may be connected to the power supply voltage VDDA, the gates of the transistors PM1, PM2, and PM3, and the drain of the transistor PM1 may be connected to the current source CS1. The current source CS1 may generate a bias current flowing through the transistor PM2 and a bias current flowing through the power transistor PM 3. The drain of the transistor PM2 may be connected to one end of the resistor R1 and one end of the capacitor C1. The drain of the transistor PM3 may be connected to the other end of the resistor R1 and the other end of the capacitor C1.

The gates of the first input transistors PT0, PT1, and PT2 may receive corresponding data input/output signals DQ3, DQ4, and DQ5. Sources of the first input transistors PT0, PT1, and PT2 may be connected to a drain of the transistor PM2, one end of the resistor R1, and one end of the capacitor C1, and drains of the first input transistors PT0, PT1, and PT2 may be connected to the resistor R2 and the first output node N1. The gates of the second input transistors PT3, PT4, and PT5 may receive the corresponding data input/output signals DQ0, DQ1, and DQ2. Sources of the second input transistors PT3, PT4, and PT5 may be connected to the drain of the transistor PM3, the other end of the resistor R1, and the other end of the capacitor C1, and drains of the second input transistors PT3, PT4, and PT5 may be connected to the resistor R3 and the second output node N2. The first differential output signal C0a may be output from the first output node N1, and the second differential output signal C0b may be output from the second output node N2. The output signal C0 of the differential amplifier 1700 may be a difference between the first differential output signal C0a and the second differential output signal C0 b.

In an example embodiment, the differential amplifier 1700 may include first input transistors PT0, PT1, and PT2 and second input transistors PT3, PT4, and PT5, the number of which is based on a coefficient multiplied by the data input/output signal. In some example embodiments, the data input/output signal may be received by the first input transistors PT0, PT1, and PT2 or the second input transistors PT3, PT4, and PT5 depending on the sign of the coefficient. For example, since the sign of the coefficient multiplied by DQ0 is positive, DQ0 may be input to the gate of the first input transistor PT 0. Similarly, because the sign of the coefficient multiplied by DQ3 is negative, DQ3 can be input to the gate of the second input transistor PT 3. In some example embodiments, the number of the first and second input transistors PT0-PT5 corresponding to each of the data input/output signals DQ0-DQ5 may be a number corresponding to a quotient obtained by dividing a coefficient by a greatest common divisor of the coefficients multiplied by the data input/output signals DQ0-DQ 5. For example, since all coefficients multiplied by the data input/output signals DQ0 through DQ5 to decode the sampled data SD0 are equal to 2, and a quotient obtained by dividing 2 by the greatest common divisor 2 is 1, all the numbers of the first and second input transistors corresponding to each of the data input and output signals DQ0 through DQ5 may be 1.

FIG. 18 is an example block diagram of a computer system according to an example embodiment.

With reference to fig. 18, a computing system 1800 includes a processor 1810, a memory 1820, a memory controller 1830, a storage device 1840, a communication interface 1850, and a bus 1860. The computing system 1800 may also include other general-purpose components.

The processor 1810 controls the overall operation of each component of the computing system 1800. The processor 1810 may be implemented as at least one of various processing units such as a Central Processing Unit (CPU), an Application Processor (AP), and a Graphics Processing Unit (GPU).

The memory 1820 stores various data and commands. The memory 1820 may be implemented as the memory device described with reference to fig. 1 through 17. The memory controller 1830 controls the transfer of data or commands to and from the memory 1820. The memory controller 1830 may be implemented as the memory controller described with reference to fig. 1 through 17. In some example embodiments, the memory controller 1830 may be provided as a separate chip from the processor 1810. In some example embodiments, a memory controller 1830 may be provided as an internal component of the processor 1810. Each of the memory 1820 and the memory controller 1830 may encode a data input/output signal transmitted to a target channel based on a plurality of data and decode data based on a plurality of data input/output signals received through a plurality of channels. Each of the memory 1820 and the memory controller 1830 may amplify a plurality of data based on coefficients of the matrix E derived to satisfy equation 5 and conditions 1 to 4, and output the amplified data as a data input/output signal. Each of the memory 1820 and the memory controller 1830 may differentially amplify a plurality of data input and output signals based on coefficients of the matrix D derived to satisfy equation 5 and conditions 1 to 4, and output the amplified signals as data input/output signals.

Storage 1840 non-transitory stores programs and data. In some example embodiments, the storage device 1840 may be implemented as non-volatile memory. Communication interface 1850 supports wired and wireless internet communication for the computing system 1800. Further, the communication interface 1850 can support various communication methods other than internet communication. Bus 1860 provides a communication function between the components of computing system 1800. The bus 1360 may include at least one type of bus depending on the communication protocol between the components.

In some example embodiments, each component or a combination of two or more components described with reference to fig. 1-18 may be implemented as a digital circuit, a programmable or non-programmable logic device or array, an Application Specific Integrated Circuit (ASIC), or the like.

Although the exemplary embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto. That is, several modifications and variations made by those skilled in the art using the basic concept of the invention as defined in the claims fall within the scope of the invention.

Claims (20)

1. A semiconductor system, comprising:

a transmitter configured to output a plurality of data as a plurality of data input/output signals through a plurality of channels based on the matrix E; and

A receiver configured to generate a plurality of data by differentially amplifying a plurality of data input/output signals received through a plurality of channels based on a matrix D, all components of the matrix E and the matrix D being integers, a product matrix of the matrix D and the matrix E being a diagonal matrix, a sum of components of each row of the matrix D being 0, and a sum of absolute values of components of each column of the matrix D being less than or equal to a threshold value.

2. The semiconductor system of claim 1, wherein:

the components of the matrix D and the components of the matrix E are calculated according to the following formula,

where c=d× (s+xt) xexa,

where D is the matrix D, E is the matrix E, a is a column vector including the plurality of data, and s+xt is a matrix in which the main diagonal component is the signal strength of each of the plurality of channels, and the remaining components are the crosstalk strengths of neighboring channels.

3. The semiconductor system of claim 1, wherein:

the transmitter includes a plurality of driver groups outputting a plurality of data input/output signals, an

The first driver group outputting a first data input/output signal among the plurality of data input/output signals through a first channel among the plurality of channels includes a first driver based on a first number of absolute values of components corresponding to first data among the components of the matrix E corresponding to the first data input/output signal, and a second driver based on a second number of absolute values of components corresponding to second data among the plurality of data among the components of the matrix E corresponding to the first data input/output signal.

4. A semiconductor system according to claim 3, wherein:

each first driver of the first number comprises

A first pull-up transistor configured to connect a first output node connected to a first channel and a first power supply voltage based on one of a first pull-up control signal and a first pull-down control signal generated according to first data; and a first pull-down transistor configured to connect the first output node and the second power supply voltage based on the other of the first pull-up control signal and the first pull-down control signal.

5. The semiconductor system of claim 4, wherein:

among the components of the matrix E corresponding to the first data input/output signal, the first pull-up control signal is applied to the gate of the first pull-up transistor and the first pull-down control signal is applied to the gate of the first pull-down transistor, or the first pull-up control signal is applied to the gate of the first pull-down transistor and the first pull-down control signal is applied to the gate of the first pull-up transistor, depending on the sign of the component corresponding to the first data among the plurality of data.

6. The semiconductor system of claim 5, wherein the transmitter further comprises a pre-driver configured to generate the first pull-up control signal and the first pull-down control signal based on the first data.

7. The semiconductor system of claim 4, wherein:

a second number of each second driver includes

The second pull-up transistor is configured to connect the first output node and the first power supply voltage based on one of a second pull-up control signal and a second pull-down control signal generated according to the second data, and the second pull-down transistor is configured to connect the first output node and the second power supply voltage based on the other of the second pull-up control signal and the second pull-down control signal.

8. A semiconductor system according to claim 3, wherein the first number and the second number are different from each other.

9. A semiconductor system according to claim 3, wherein the first number and the second number are identical to each other.

10. The semiconductor system of claim 1, wherein:

the sum of the changes of the plurality of data input/output signals in the plurality of channels is 0.

11. A semiconductor system according to claim 3, wherein:

the receiver includes: at least one first transistor configured to electrically connect a power supply voltage and a first node; at least one second transistor configured to electrically connect a power supply voltage and a second node; and a differential amplifier configured to output a voltage of the first node and a voltage of the second node.

12. The semiconductor system of claim 11, wherein:

when the sign of the component corresponding to the first data input/output signal among the components of the matrix D corresponding to the first data among the plurality of data is positive, the first data input/output signal is applied to the gate of at least one first transistor, and

when the sign of a component corresponding to the first data input/output signal among components of the matrix D corresponding to the first data among the plurality of data is negative, the first data input/output signal is applied to the gate of the at least one second transistor.

13. The semiconductor system of claim 11, wherein:

the number of at least one first transistor is based on an absolute value of a component corresponding to the first data input/output signal among components of the matrix D corresponding to the first data among the plurality of data, and

the number of the at least one second transistor is based on an absolute value of a component corresponding to the second data input/output signal among components of the matrix D corresponding to the first data among the plurality of data.

14. A memory device, comprising:

a memory cell array; and

a transmitter configured to receive n data from the memory cell array, the n being a natural number, and emphasize the n data by intensity according to components of a matrix E to generate n+1 data input/output signals, wherein a sum of the components of the matrix E is 0.

15. The memory device of claim 14, wherein the transmitter comprises:

at least one first driver, each first driver including a first pull-up transistor connecting a first output node connected to a first channel among the plurality of channels to a first power supply voltage based on one of a first pull-up control signal and a first pull-down control signal according to first data among the n data, and a first pull-down transistor connecting the first output node and a second power supply voltage based on the other of the first pull-up control signal and the first pull-down control signal; and

at least one second driver, each second driver including a second pull-up transistor and a second pull-down transistor, the second pull-up transistor connecting the first output node and the first power supply voltage based on one of a second pull-up control signal and a second pull-down control signal according to second data among the n data, the second pull-down transistor connecting the first output node and the second power supply voltage based on the other of the second pull-up control signal and the second pull-down control signal.

16. The memory device of claim 15, wherein a first pull-up control signal is applied to a gate of the first pull-up transistor and a first pull-down control signal is applied to a gate of the first pull-down transistor.

17. The memory device of claim 15, wherein a second pull-down control signal is applied to a gate of the second pull-up transistor and the second pull-up control signal is applied to the gate of the second pull-down transistor.

18. The memory device of claim 15, wherein the number of at least one first driver and the number of at least one second driver are different from each other.

19. The memory device of claim 15, wherein the number of at least one first driver and the number of at least one second driver are the same as each other.

20. A memory system, comprising:

a memory device configured to include a memory cell array and a transmitter encoding n data into n+1 data input/output signals and outputting the n+1 data input/output signals; and

and a memory controller configured to include a receiver that receives the n+1 data input/output signals and decodes the n data by differentially amplifying the n+1 data input/output signals according to components of a matrix D, wherein a sum of the components of the matrix D is 0.