KR20240025999A - Semiconductor device - Google Patents

Abstract

The technical idea of the present invention is to include a semiconductor substrate; A gate stack including a plurality of gate layers and a plurality of insulating layers alternately stacked on the semiconductor substrate; a plurality of first channel structures extending vertically through the gate stack; a first insulating layer disposed on the gate stack; a string selection line stack disposed on the first insulating layer; a word line cut extending vertically through the gate stack, the first insulating layer, and the string select line stack; wherein the word line cut includes a first portion penetrating a portion of the gate stack, the first insulating layer, and the string select line stack, and a second portion penetrating a remaining portion of the string select line stack. and the horizontal width of the first portion is smaller than the horizontal width of the second portion.

Description

Semiconductor device

The technical idea of the present invention relates to semiconductor devices. More specifically, it relates to a semiconductor device having a non-volatile vertical memory element.

Semiconductor devices capable of storing high-capacity data are required in electronic systems that require data storage, and accordingly, ways to increase the data storage capacity of semiconductor devices are being studied. For example, as one of the methods for increasing the data storage capacity of a semiconductor device, a semiconductor device including a vertical memory element with three-dimensionally arranged memory cells instead of two-dimensionally arranged memory cells has been proposed. It is becoming.

The problem to be solved by the technical idea of the present invention is to provide a semiconductor device with improved reliability.

In order to solve the above-described problems, the technical idea of the present invention is to provide a semiconductor substrate;

A gate stack including a plurality of gate layers and a plurality of insulating layers alternately stacked on the semiconductor substrate; a plurality of first channel structures extending vertically through the gate stack; a first insulating layer disposed on the gate stack; a string selection line stack disposed on the first insulating layer; a word line cut extending vertically through the gate stack, the first insulating layer, and the string select line stack; wherein the word line cut includes a first portion penetrating a portion of the gate stack, the first insulating layer, and the string select line stack, and a second portion penetrating a remaining portion of the string select line stack. and the horizontal width of the first portion is smaller than the horizontal width of the second portion.

According to exemplary embodiments of the present invention, a word line cut is formed after a string selection line stack is formed in a semiconductor device, thereby preventing foreign substances such as CMP slurry from being trapped in a seam disposed within the word line cut. there is. Accordingly, the structural reliability of the semiconductor device can be improved.

1 is a block diagram showing a semiconductor device according to an exemplary embodiment of the present invention.
Figure 2 is an equivalent circuit diagram of a memory cell array of a semiconductor device according to an exemplary embodiment of the present invention.
3 is a schematic perspective view of a semiconductor device according to an exemplary embodiment of the present invention.
4 is a cross-sectional view showing a semiconductor device according to an exemplary embodiment of the present invention.
Figure 5 is an enlarged cross-sectional view of the EX portion of Figure 4.
6A to 6J are cross-sectional views showing each step of the semiconductor device manufacturing method according to an exemplary embodiment of the present invention.
7 is a diagram illustrating an electronic system including a semiconductor device according to an exemplary embodiment of the present invention.
8 is a perspective view showing an electronic system including a semiconductor device according to an exemplary embodiment of the present invention.
9 is a cross-sectional view showing a semiconductor package including a semiconductor device according to an exemplary embodiment of the present invention.

Hereinafter, embodiments of the technical idea of the present invention will be described in detail with reference to the attached drawings. The same reference numerals are used for the same components in the drawings, and duplicate descriptions thereof are omitted.

1 is a block diagram showing a semiconductor device according to an exemplary embodiment of the present invention.

Referring to FIG. 1 , the semiconductor device 10 may include a memory cell array 20 and a peripheral circuit 30.

The memory cell array 20 includes a plurality of memory cell blocks BLK1, BLK2,..., BLKn. Each of the plurality of memory cell blocks (BLK1, BLK2, ..., BLKn) may include a plurality of memory cells. The plurality of memory cell blocks (BLK1, BLK2, ..., BLKn) are connected to the peripheral circuit 30 through the bit line (BL), word line (WL), string select line (SSL), and ground select line (GSL). can be connected

The memory cell array 20 may be connected to the page buffer 34 through a bit line (BL), and a row decoder ( 32). In the memory cell array 20, each of the memory cells included in the memory cell blocks BLK1, BLK2,..., BLKn may be a flash memory cell. The memory cell array 20 may include a three-dimensional memory cell array. The three-dimensional memory cell array may include a plurality of NAND strings, and the plurality of NAND strings may each include a plurality of memory cells connected to a plurality of vertically stacked word lines (WL).

The peripheral circuit 30 may include a row decoder 32, a page buffer 34, a data input/output circuit 36, and control logic 38. Although not shown, the peripheral circuit 30 includes a voltage generation circuit for generating various voltages required for the operation of the semiconductor device 10, an error correction circuit for correcting errors in data read from the memory cell array 20, It may further include various circuits such as input/output interfaces.

The peripheral circuit 30 can receive an address (ADDR), a command (CMD), and a control signal (CTRL) from the outside of the semiconductor device 10, and can receive devices and data outside of the semiconductor device 10 ( DATA) can be sent and received. A detailed look at the configuration of the peripheral circuit 30 is as follows.

The row decoder 32 may select at least one of a plurality of memory cell blocks (BLK1, BLK2, ..., BLKn) in response to an external address (ADDR), and the word line (WL) and string of the selected memory cell block A select line (SSL) and a ground select line (GSL) can be selected. The row decoder 32 may transmit a voltage for performing a memory operation to the word line (WL) of the selected memory cell block.

The page buffer 34 may be connected to the memory cell array 20 through a bit line BL. The page buffer 34 operates as a write driver during a program operation to apply a voltage to the bit line BL according to the data (DATA) to be stored in the memory cell array 20, and detects it during a read operation. By operating as an amplifier, data (DATA) stored in the memory cell array 20 can be detected. The page buffer 34 may operate according to a control signal (PCTL) provided from the control logic 38.

The data input/output circuit 36 may be connected to the page buffer 34 through data lines DLs. The data input/output circuit 36 receives data (DATA) from a memory controller (not shown) during a program operation, and stores the program data (DATA) in a page buffer based on the column address (C_ADDR) provided from the control logic 38. It can be provided in (34). The data input/output circuit 36 may provide read data DATA stored in the page buffer 34 to the memory controller based on the column address C_ADDR provided from the control logic 38 during a read operation. The data input/output circuit 36 may transmit an input address or command to the control logic 38 or the row decoder 32.

The control logic 38 may receive a command (CMD) and a control signal (CTRL) from the memory controller. The control logic 38 may provide a row address (R_ADDR) to the row decoder 32 and a column address (C_ADDR) to the data input/output circuit 36. The control logic 38 may generate various internal control signals used within the semiconductor device 10 in response to the control signal CTRL. For example, the control logic 38 may adjust the voltage level provided to the word line (WL) and the bit line (BL) when performing a memory operation such as a program operation or an erase operation.

Figure 2 is an equivalent circuit diagram of a memory cell array of a semiconductor device according to an exemplary embodiment of the present invention.

Referring to FIG. 2, an equivalent circuit diagram of a vertical NAND flash memory device having a vertical channel structure is illustrated.

The memory cell array (MCA) may include a plurality of memory cell strings (MS). The memory cell array (MCA) includes a plurality of bit lines (BL), a plurality of word lines (WL), at least one string select line (SSL), at least one ground select line (GSL), and a common source line (CSL). ) may include.

A plurality of memory cell strings (MS) may be formed between the plurality of bit lines (BL) and the common source line (CSL). Although the drawing illustrates a case where a plurality of memory cell strings (MS) each include two string selection lines (SSL), the technical idea of the present invention is not limited thereto. For example, each of the plurality of memory cell strings MS may include one string select line SSL.

Each of the plurality of memory cell strings (MS) may include a string select transistor (SST), a ground select transistor (GST), and a plurality of memory cell transistors (MC1, MC2, ..., MCn-1, MCn). The drain region of the string select transistor (SST) may be connected to the bit line (BL), and the source region of the ground select transistor (GST) may be connected to the common source line (CSL). The common source line (CSL) may be an area where the source regions of a plurality of ground selection transistors (GST) are commonly connected.

The string select transistor (SST) may be connected to the string select line (SSL), and the ground select transistor (GST) may be connected to the ground select line (GSL). A plurality of memory cell transistors (MC1, MC2, ..., MCn-1, MCn) may each be connected to a plurality of word lines (WL).

3 is a schematic perspective view of a semiconductor device according to an exemplary embodiment of the present invention.

Referring to FIG. 3 , the semiconductor device 10 may include a memory cell array structure (CS) and a peripheral circuit structure (PS) that overlap each other in the vertical direction.

The memory cell array structure CS may include the memory cell array 20 described with reference to FIG. 1 . The peripheral circuit structure PS may include the peripheral circuit 30 described with reference to FIG. 1 .

The memory cell array structure CS may include a plurality of tiles. The plurality of tiles may each include a plurality of memory cell blocks (BLK1, BLK2,..., BLKn). Each of the plurality of memory cell blocks (BLK1, BLK2, ..., BLKn) may include memory cells arranged three-dimensionally.

In some embodiments, two tiles may constitute one mat, but the present invention is not limited thereto. For example, the memory cell array 20 described with reference to FIG. 1 may include a plurality of mats.

4 is a cross-sectional view showing a semiconductor device according to an exemplary embodiment of the present invention. Figure 5 is an enlarged cross-sectional view of the EX portion of Figure 4.

Referring to FIGS. 4 and 5 , the semiconductor device 100 may include a peripheral circuit structure (PS) and a cell array structure (CS) disposed on the peripheral circuit structure (PS).

The peripheral circuit structure PS may include a lower substrate 101, a plurality of transistors TR disposed on the lower substrate 101, and a wiring structure 60.

The lower substrate 101 may be made of a semiconductor substrate. The lower substrate 101 may include, for example, Si, Ge, or SiGe. An active area AC may be defined on the lower substrate 101 by a device isolation layer 102 .

A plurality of transistors TR may be formed on the active area AC. The plurality of transistors TR may each include a gate PG and a plurality of ion implantation regions PSD formed in the active region AC on both sides of the gate PG. The plurality of ion implantation regions (PSD) may each form a source region or a drain region of the transistor (TR).

The wiring structure 60 may include a plurality of contacts 62 and a plurality of wiring layers 64. The plurality of wiring layers 64 may have a multi-layer structure including a plurality of layers arranged at different vertical levels. At least some of the plurality of wiring layers 64 may be configured to be electrically connected to the transistor TR. The plurality of contacts 62 may be configured to interconnect portions selected from the plurality of transistors TR and the plurality of wiring layers 64.

An interlayer insulating film 70 surrounding a plurality of transistors TR and the wiring structure 60 may be disposed on the lower substrate 101 . The interlayer insulating film 70 may include a silicon oxide film, a silicon nitride film, a SiON film, a SiOCN film, or a combination thereof.

The cell array structure (CS) may be disposed on the peripheral circuit structure (PS). The cell array structure (CS) may include a cell array region (MCR) and a connection region (CON).

The upper substrate 110 may be made of a semiconductor substrate. The upper substrate 110 may include, for example, a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI oxide semiconductor.

The gate stack GS may be disposed on the upper substrate 110 . The gate stack GS may extend parallel to the top surface of the upper substrate 110 . The gate stack GS may include a plurality of gate layers 120 and a plurality of insulating layers 130. A plurality of gate layers 120 and a plurality of insulating layers 130 may be alternately stacked in the vertical direction on the upper substrate 110.

The gate layer 120 may include a conductive layer (not shown) and an insulating liner (not shown) surrounding the conductive layer. For example, the conductive layer may include a metal such as tungsten, a metal silicide such as tungsten silicide, doped polysilicon, or a combination thereof. The insulating liner may include a high dielectric material such as aluminum oxide, for example.

The gate layer 120 may correspond to the ground select line (GSL) and word line (WL) that constitute the memory cell string (MS) described with reference to FIG. 2 . For example, the lowest gate layer 120 may function as a ground selection line (GSL), and the remaining gate layers 120 may function as word lines (WL).

The plurality of first channel structures 140 may extend in the vertical direction from the top surface of the upper substrate 110 in the cell array region MCR through the gate stack GS. The plurality of first channel structures 140 may be arranged to be spaced apart at predetermined intervals along the first horizontal direction and the second horizontal direction. The plurality of first channel structures 140 may be arranged in a zigzag shape or a staggered shape.

A plurality of first channel structures 140 may be formed inside the first channel hole 140H. Each of the plurality of first channel structures 140 may include a conductive plug 142, a buried insulating layer 144, a channel layer 146, and a gate insulating layer 148. A gate insulating layer 148 and a channel layer 146 may be sequentially disposed on the sidewall of the first channel hole 140H. A buried insulating layer 144 may be disposed on the channel layer 146 to fill the remaining space of the first channel hole 140H. A conductive plug 142 may be disposed on the upper side of the first channel hole 140H, which contacts the channel layer 146 and blocks the uppermost end of the first channel hole 140H.

The gate insulating layer 148 may include a tunneling dielectric layer (not shown), a charge storage layer (not shown), and a blocking dielectric layer (not shown) sequentially disposed on the outer wall of the channel layer 146. The tunneling dielectric layer may include silicon oxide, hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, etc. The charge storage layer is a region in which electrons passing through the tunneling dielectric layer from the channel layer 146 can be stored, and may include silicon nitride, boron nitride, silicon boron nitride, or polysilicon doped with impurities. The blocking dielectric layer may be made of silicon oxide, silicon nitride, or a metal oxide with a higher dielectric constant than silicon oxide.

A first insulating layer 170 may be disposed on the gate stack GS. The first insulating layer 170 may be, for example, silicon nitride.

The string selection line stack SS may be disposed on the first insulating layer 170 . The string select line stack SS may include a first string select line insulating layer 210, a string select line gate layer 220, and a second string select line insulating layer 230. The first string selection line insulating layer 210, the string selection line gate layer 220, and the second string selection line insulating layer 230 may be sequentially stacked in a vertical direction from the top surface of the first insulating layer 170. there is.

The first string selection line insulating layer 210 and the second string selection line insulating layer 230 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

The string select line gate layer 220 may include a string select line buried conductive layer (not shown) and a string select line insulating liner (not shown) surrounding the string select line buried conductive layer. The string selection line gate layer 220 may have a single-layer structure of polysilicon, a stacked structure of oxide/polysilicon, or a stacked structure of oxide/metal, but is not limited thereto.

The word line cut (WLC) may extend vertically from the upper substrate 110 through the gate stack (GS), the first insulating layer 170, and the string select line stack (SS). In an exemplary embodiment, the word line cut (WLC) includes a first portion (WLCa) penetrating a portion of the gate stack (GS), the first insulating layer 170, and the string select line stack (SS) and a string select line. It may include a second part (WLCb) penetrating the remaining part of the stack (SS). In an exemplary embodiment, the first portion WLCa and the second portion WLCb may have a tapered shape whose horizontal width increases as the distance from the top surface of the upper substrate 110 increases. In an exemplary embodiment, the horizontal width of the first portion (WLCa) may be smaller than the horizontal width of the second portion (WLCb).

The first part (WLCa) includes a first insulating separation layer 180 and a first seam (180S) that is an empty space inside the first insulating separation layer 180, and the second part (WLCb) It may include a second insulating separation layer 280 and a second shim 280S that is an empty space inside the second insulating separation layer 280. The first insulating separation layer 180 and the second insulating separation layer 280 may be, for example, silicon oxide, but are not limited thereto. In an exemplary embodiment, the first insulating separation layer 180 and the second insulating separation layer 280 may include seam-free oxide (SFO). In an example embodiment, the first shim 180S may extend in the vertical direction to a vertical level higher than the top surface of the gate stack GS.

A word line spacer (WLS) may surround a portion of a word line cut (WLC). The word line spacer (WLS) is located on the first part (WLSa) and a first spacer part (WLSa) surrounding the first part (WLCa) of the word line cut (WLC). It may include a second spacer portion (WLSb) surrounding the second portion (WLCb). The word line spacer (WLS) may include the same material as the word line cut (WLC), but is not limited thereto.

In an exemplary embodiment, the top surface of the first spacer portion (WLSa) is located at a lower vertical level than the top surface of the string selection line stack (SS) and is located at a higher vertical level than the bottom surface of the string selection line stack (SS). You can.

In an exemplary embodiment, the lower surface of the word line spacer (WLS) may be positioned at the same vertical level as the lower surface of the first insulating layer 170. Specifically, the lower surface of the first spacer portion (WLSa) of the word line spacer (WLS) may be positioned at the same vertical level as the lower surface of the first insulating layer 170 . Unlike shown in FIGS. 4 and 5 , in another embodiment, the lower surface of the word line spacer (WLS) may be located at a lower vertical level than the lower surface of the first insulating layer 170 . Specifically, the lower surface of the first spacer portion (WLSa) of the word line spacer (WLS) may be located at a lower vertical level than the lower surface of the first insulating layer 170 .

In an exemplary embodiment, the thickness d1 of the first spacer portion WLSa may be greater than the thickness d2 of the second spacer portion WLSb.

The plurality of second channel structures 240 are disposed on the first insulating layer 170 and may extend vertically through the string selection line stack SS. The plurality of second channel structures 240 may be arranged to be spaced apart at predetermined intervals along the first horizontal direction and the second horizontal direction. The plurality of second channel structures 240 may be arranged in a zigzag shape or a staggered shape.

A plurality of second channel structures 240 may be formed inside the second channel hole 240H. Each of the plurality of second channel structures 240 may include a conductive plug 242, a buried insulating layer 244, a channel layer 246, and a gate insulating layer 248. Each configuration of the second channel structure 240 may be similar to each corresponding configuration of the first channel structure 140.

In an exemplary embodiment, the central axes of the first plurality of channel structures 140 and the central axes of the plurality of second channel structures 240 may be arranged to be offset from each other.

The connection via 240V penetrates the first insulating layer 170 and may be interposed between the gate stack GS and the string select line stack SS. The upper surface of the connection via 240V may be in contact with the second channel structure 240, and the lower surface of the connection via 240V may be in contact with the first channel structure 140. Accordingly, even when the central axis of the first channel structure 140 and the central axis of the corresponding second channel structures 240 are arranged to be offset from each other, the plurality of first channel structures 140 are connected through the connection via 240V. ) and the plurality of second channel structures 240 may be electrically connected.

The string selection line cut (SLC) may extend vertically through the string selection line stack (SS) in the cell array region (MCR). The string selection line cut (SLC) may include an insulating material. In an exemplary embodiment, the string selection line cut (SLC) may have a tapered shape whose horizontal width increases as the distance from the top surface of the upper substrate 110 increases.

The second insulating layer 250 may be disposed on the string select line stack SS. The second insulating layer 250 may be, for example, silicon oxide, but is not limited thereto. In an exemplary embodiment, the second portion (WLCb) of the word line cut (WLC) may extend through the second insulating layer 250 in the vertical direction. In this case, the top surface of the second portion (WLCb) may be located at the same vertical level as the top surface of the second insulating layer 250. The third insulating layer 270 may be disposed on the second insulating layer 250 .

The plurality of first bit line contact plugs BLCa are connected to the second channel structure 240 and may penetrate the second insulating layer 250 and the third insulating layer 270 in the vertical direction. The second channel structure 240 may be connected to a bit line (not shown) disposed on the third insulating layer 270 through a plurality of first bit line contact plugs (BLCa). The first bit line contact plug (BLCa) may be made of tungsten, titanium, tantalum, copper, aluminum, titanium nitride, tantalum nitride, tungsten nitride, or a combination thereof.

In the connection area CON, the gate layer 120 may be extended to form a pad portion (not shown) at an end of the gate layer 120, and a cover insulating layer 150 may be disposed to cover the pad portion. In the connection area CON, the plurality of gate layers 120 may extend to have a shorter length in the first horizontal direction as they move away from the top surface of the upper substrate 110 in the vertical direction. That is, the plurality of gate layers 120 in the connection area CON may have a staircase structure.

In the connection area CON, the first insulating layer 170 may extend in the first horizontal direction. In the connection area CON, a second cover insulating layer SLP may be disposed on the first insulating layer 170. The second cover insulating layer (SLP) may include the same material as the string selection line cut (SLC). In addition, the upper surface of the second cover insulating layer (SLP) is located at the same vertical level as the upper surface of the Strang selection line cut (SLC), and the lower surface of the second cover insulating layer (SLP) is located at the lower surface of the Strang selection line cut (SLC). It can be located at the same vertical level as. In the connection area CON, the second insulating layer 250 extends in the first horizontal direction and may be disposed on the second cover insulating layer SLP.

In the connection area CON, the gate layer 120 penetrates the cover insulating layer 150, the first insulating layer 170, the second cover insulating layer (SLP), and the second insulating layer 250 in the vertical direction. ) A contact plug (CNT) connected to the pad portion may be disposed. The contact plug (CNT) includes a first plug portion (160ㅔ) penetrating the cover insulating layer 150, a first insulating layer 170, a second cover insulating layer (SLP), and a second insulating layer 250. It may include a penetrating second plug portion 260. The first plug portion 160 and the second plug portion 260 may have a tapered shape whose horizontal width increases as the distance from the upper surface of the upper substrate 110 increases.

In the connection area CON, the third insulating layer 270 extends in the first horizontal direction and may be disposed on the second insulating layer 250. The second bit line contact plug (BLCb) penetrates the third insulating layer 270 in the vertical direction and may be connected to the contact plug (CNT). The contact plug (CNT) may be connected to a bit line (not shown) through the second bit line contact plug (BLCb).

The contact plug (CNT) and the second bit line contact plug (BLCb) may be made of tungsten, titanium, tantalum, copper, aluminum, titanium nitride, tantalum nitride, tungsten nitride, or a combination thereof.

Since the semiconductor device 100 according to an exemplary embodiment of the present invention forms the word line cut (WLC) after forming the string select line stack (SS), CMP slurry is applied to the shim disposed in the word line cut (WLC). This can prevent foreign substances such as getting stuck. Accordingly, the structural reliability of the semiconductor device 100 may be improved. In addition, the semiconductor device 100 includes a word line spacer (WLS) surrounding the word line cut (WLC) and is disposed on the lower surface of the string select line stack (SS) when performing the replacement process of the gate layer 120. The first insulating layer 170 can be prevented from being replaced with a conductive material. Accordingly, the bridging phenomenon that occurs when the first insulating layer 170 is replaced with a conductive material can be prevented.

6A to 6J are cross-sectional views showing each step of the semiconductor device manufacturing method according to an exemplary embodiment of the present invention. Specifically, FIGS. 6A to 6J are cross-sectional views showing each step of a method for manufacturing a cell array structure (CS) of a semiconductor device according to an exemplary embodiment of the present invention.

Referring to FIG. 6A , first, a first channel structure 140 penetrating a plurality of alternatingly stacked sacrificial layers 120M and a plurality of insulating layers 130 may be formed. Specifically, a plurality of sacrificial layers 120M and a plurality of insulating layers 130 may be alternately stacked on the upper substrate 110 (see FIG. 4). Next, a photolithography process is performed in the connection region CON to remove a portion of each of the plurality of sacrificial layers 120M and the plurality of insulating layers 130, thereby vertically moving away from the top surface of the upper substrate 110. Accordingly, a structure in which the first horizontal length of the plurality of sacrificial layers 120M and the first horizontal length of the plurality of insulating layers 130 are shorter, that is, a step structure can be formed. Next, in the connection area CON, a cover insulating layer 150 may be formed to cover the plurality of sacrificial layers 120M and the plurality of insulating layers 130. Next, a first channel hole 140H and a first contact plug hole 160H that penetrate the plurality of sacrificial layers 120M and the plurality of insulating layers 130 may be formed. Thereafter, a first channel structure 140 including a gate insulating layer 148, a channel layer 146, a buried insulating layer 144, and a conductive plug 142 is formed in the first channel hole 140H. , a first contact plug layer 160M may be formed in the first contact plug hole 160H. In an example embodiment, the first contact plug layer 160M may include polysilicon.

Referring to FIG. 6B, in the result of FIG. 6A, the first insulating layer 170 can be formed on the uppermost insulating layer 130, the first channel structure 140, and the first contact plug layer 160M. there is. The first insulating layer 170 may be formed, for example, through a deposition process. Next, a string selection line stack (SS) may be formed on the first insulating layer 170. At this time, the first string selection line insulating layer 210, the first string selection line gate layer 220, and the second string selection line insulating layer 230 may be sequentially formed through a deposition process.

Referring to FIG. 6C, in the result of FIG. 6B, a word line open trench (WLOT), a string select line cut trench (SLT), and a second cover insulating layer trench (SLPT) can be formed. Specifically, a word line open trench (WLOT) penetrating the string selection line stack (SS) and the first insulating layer 170 by performing a photolithography process, and a string selection line cut trench penetrating the string selection line stack (SS). (SLT) and the second cover insulating layer trench (SLPT) can be formed simultaneously.

Referring to FIG. 6D, in the result of FIG. 6C, each of the word line open trench (WLOT), string select line cut trench (SLT), and second cover insulating layer trench (SLPT) may be filled with insulating materials. Accordingly, the first insulating material layer (Ox1) is in the word line open trench (WLOT), the second insulating material layer (Ox2) in the second cover insulating layer trench (SLPT), and the string selection line cut trench (SLT). A string selection line cut (SLC) may be formed simultaneously. Accordingly, the first insulating material layer Ox1, the second insulating material layer Ox2, and the string selection line cut SLC may include the same insulating material. The insulating material may be, for example, silicon oxide.

Referring to FIG. 6E, in the result of FIG. 6D, a connection via 240V and a second channel structure 240 connected to the connection via 240V may be formed. Specifically, after performing a photolithography process to form a connection via (240V) penetrating the first insulating layer 170, a second channel hole (240H) can be formed through the string selection line stack (SS). . Next, a channel structure 240 including a gate insulating layer 248, a channel layer 246, a buried insulating layer 244, and a conductive plug 242 may be formed in the second channel hole 240H. .

Referring to FIG. 6F, in the result of FIG. 6E, a plurality of sacrificial layers 120M, a plurality of insulating layers 130, a first insulating layer 170, and a first insulating material formed in the word line open trench (WLOT) A first word line cut trench (WLTa) penetrating the layer (Ox1) may be formed. At this time, the remaining first insulating material layer (Ox1) may function as a word line spacer (WLS).

Referring to FIG. 6G, in the result of FIG. 6F, a plurality of gate layers 120 are formed by replacing a plurality of sacrificial layers (120M, see FIG. 6F), and the first contact plug layer (160M) is replaced to form a first contact plug layer (160M). A plug portion 160 may be formed. That is, a replacement process can be performed to form the plurality of gate layers 120 and the first plug portion 160 by replacing the plurality of sacrificial layers 120M and the first contact plug layer 160M with a conductive material. there is. Through the substitution process, a gate stack GS including a plurality of gate layers 120 and a plurality of insulating layers 130 may be formed.

Referring to FIG. 6H, in the result of FIG. 6G, the first word line cut trench (WLTa) may be filled with an insulating material to form the first portion (WLCa) of the word line cut (WLC, see FIG. 4). The first part (WLCa) may be made of a first insulating separation layer 180. In an exemplary embodiment, the first insulating isolation layer 180 may be made of silicon oxide, silicon nitride, silicon oxynitride, or a low dielectric material. At this time, the insulating separation layer 180 may include a seam 180S, which is an empty space.

Referring to FIG. 6i, in the result of FIG. 6h, the second word line cut trench (WLTb) and the first insulating layer 170 penetrating a portion of the Strang select line stack (SS) and the second insulating layer 250. , the string selection line stack SS, and the second contact plug hole 260H penetrating the second insulating layer 250 may be formed. The second word line cut trench (WLTb) and the second contact plug hole (260H) may be formed through a photolithography process. As the second word line cut trench WLTb is formed, the upper portion of the first portion WLCa and a portion of the upper portion of the word line spacer WLS may be removed. As a result, the portion of the word line spacer (WLS) partially removed by the second word line cut trench (WLTb) becomes the second spacer portion (WLSb), and the remaining portion of the word line spacer (WLS) becomes the first spacer (WLSb). It may be a spacer portion (WLSa).

Referring to FIG. 6J, in the result of FIG. 6I, the second portion (WLCb) of the word line cut (WLC) is formed in the second word line cut trench (WLTb), and the second portion (WLCb) is formed in the second contact plug hole (260H). A plug portion 260 may be formed. The second part (WLCb) may be made of a second insulating separation layer 280. In an exemplary embodiment, the second insulating isolation layer 280 may be made of silicon oxide, silicon nitride, silicon oxynitride, or a low dielectric material. At this time, the second insulating separation layer 280 may include a seam 280S, which is an empty space. The second plug portion 260 is connected to the first plug portion 160 and may form a contact plug (CNT). Next, a third insulating layer 270 is formed on the second insulating layer 250, the second plug portion 260, and the second portion (WLCb), and a portion of the conductive plug 242 and the second insulating layer are formed on the second insulating layer 250, the second plug portion 260, and the second portion WLCb. A first bit line contact trench (BCTa) penetrating the layer 250 and the third insulating layer 270 and a second bit line contact trench (BCTb) penetrating the third insulating layer 270 may be formed. . The first bit line contact trench (BCTa) is formed to vertically overlap the second channel structure 240, and the second bit line contact trench (BCTb) is formed to vertically overlap the contact plug (CNT). It can be.

Next, in the result of FIG. 6J, the first bit line contact trench (BCTa) and the second bit line contact trench (BCTb) are filled with a conductive material to form the first bit line contact plug (BLCa) and the second bit line contact plug ( By forming BLCb), the cell array structure (CS) of the semiconductor device 100 shown in FIG. 4 can be completed.

7 is a diagram illustrating an electronic system including a semiconductor device according to an exemplary embodiment of the present invention.

Referring to FIG. 7 , the electronic system 1000 according to the present invention may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100.

The electronic system 1000 may be a storage device including one or more semiconductor devices 1100 or an electronic device including a storage device. For example, the electronic system 1000 may be a solid state drive device (SSD) device, a universal serial bus (USB) device, a computing system, a medical device, or a communication device including at least one semiconductor device 1100 .

The semiconductor device 1100 may be a non-volatile vertical memory device. For example, the semiconductor device 1100 may be a NAND flash memory device including the semiconductor device 10 described with reference to FIGS. 4 and 5 . The semiconductor device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F. In some embodiments, the first structure 1100F may be placed next to the second structure 1100S.

The first structure 1100F may be a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second structure 1100S includes a bit line (BL), a common source line (CSL), a plurality of word lines (WL), first and second gate upper lines (UL1, UL2), and first and second gate lower lines. It may be a memory cell structure including (LL1, LL2), and a plurality of memory cell strings (CSTR) between the bit line (BL) and the common source line (CSL).

In the second structure 1100S, the plurality of memory cell strings (CSTR) include lower transistors (LT1, LT2) adjacent to the common source line (CSL), upper transistors (UT1, UT2) adjacent to the bit line (BL), and and a plurality of memory cell transistors (MCT) disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of lower transistors LT1 and LT2 and the number of upper transistors UT1 and UT2 may vary depending on embodiments.

In some embodiments, the top transistors UT1 and UT2 may include string select transistors, and the bottom transistors LT1 and LT2 may include ground select transistors. The plurality of gate lower lines LL1 and LL2 may be gate layers of the lower transistors LT1 and LT2, respectively. The word line WL may be a gate layer of the memory cell transistor MCT, and the upper gate lines UL1 and UL2 may be the gate layers of the upper transistors UT1 and UT2.

The common source line (CSL), the plurality of gate lower lines (LL1, LL2), the plurality of word lines (WL), and the plurality of gate upper lines (UL1, UL2) are formed within the first structure (1100F) and the second structure ( It can be electrically connected to the decoder circuit 1110 through a plurality of first connection wires 1115 extending up to 1100S. The plurality of bit lines BL may be electrically connected to the page buffer 1120 through a plurality of second connection wires 1125 extending from the first structure 1100F to the second structure 1100S.

In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 may perform a control operation on at least one of a plurality of memory cell transistors (MCT). The decoder circuit 1110 and page buffer 1120 may be controlled by the logic circuit 1130.

The semiconductor device 1100 may communicate with the controller 1200 through an input/output pad 1101 that is electrically connected to the logic circuit 1130. The input/output pad 1101 may be electrically connected to the logic circuit 1130 through an input/output connection wire 1135 extending from the first structure 1100F to the second structure 1100S.

The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface 1230. In some embodiments, the electronic system 1000 may include a plurality of semiconductor devices 1100, and in this case, the controller 1200 may control the plurality of semiconductor devices 1100.

The processor 1210 may control the overall operation of the electronic system 1000, including the controller 1200. The processor 1210 may operate according to predetermined firmware and may control the NAND controller 1220 to access the semiconductor device 1100. The NAND controller 1220 may include a NAND interface 1221 that processes communication with the semiconductor device 1100. Through the NAND interface 1221, control commands for controlling the semiconductor device 1100, data to be written to a plurality of memory cell transistors (MCTs) of the semiconductor device 1100, and a plurality of memory cells of the semiconductor device 1100. Data to be read from the transistor (MCT) may be transmitted. The host interface 1230 may provide a communication function between the electronic system 1000 and an external host. When receiving a control command from an external host through the host interface 1230, the processor 1210 may control the semiconductor device 1100 in response to the control command.

8 is a perspective view showing an electronic system including a semiconductor device according to an exemplary embodiment of the present invention.

Referring to FIG. 8, the electronic system 2000 according to an embodiment of the present invention includes a main board 2001, a controller 2002 mounted on the main board 2001, one or more semiconductor packages 2003, and DRAM 2004. ) may include.

The main board 2001 may include a connector 2006 including a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary depending on the communication interface between the electronic system 2000 and the external host. In some embodiments, the electronic system 2000 is connected to any one of the following interfaces: USB, Peripheral Component Interconnect Express (PCI-Express), Serial Advanced Technology Attachment (SATA), and M-Phy for Universal Flash Storage (UFS). Accordingly, it is possible to communicate with an external host. In some embodiments, the electronic system 2000 may operate with power supplied from an external host through the connector 2006. The electronic system 2000 may further include a Power Management Integrated Circuit (PMIC) that distributes power supplied from the external host to the controller 2002 and the semiconductor package 2003. The semiconductor package 2003 and the DRAM 2004 may be connected to the controller 2002 through a plurality of wiring patterns 2005 formed on the main board 2001.

The controller 2002 can write data to the semiconductor package 2003 or read data from the semiconductor package 2003, and can improve the operating speed of the electronic system 2000.

DRAM (2004) may be a buffer memory to alleviate the speed difference between the semiconductor package (2003), which is a data storage space, and an external host. The DRAM 2004 included in the electronic system 2000 may operate as a type of cache memory and may provide a space for temporarily storing data during control operations for the semiconductor package 2003. When the electronic system 2000 includes the DRAM 2004, the controller 2002 may further include a DRAM controller for controlling the DRAM 2004 in addition to a NAND controller for controlling the semiconductor package 2003.

The semiconductor package 2003 may include first and second semiconductor packages 2003a and 2003b that are spaced apart from each other. Each of the first and second semiconductor packages 2003a and 2003b may be a semiconductor package including a plurality of semiconductor chips 2200. Each of the first and second semiconductor packages 2003a and 2003b includes a package substrate 2100, a plurality of semiconductor chips 2200 on the package substrate 2100, and an adhesive layer disposed on the lower surface of each of the plurality of semiconductor chips 2200. 2300), a connection structure 2400 that electrically connects the plurality of semiconductor chips 2200 and the package substrate 2100, and a molding that covers the plurality of semiconductor chips 2200 and the connection structure 2400 on the package substrate 2100. It may include a layer 2500.

The package substrate 2100 may be a printed circuit board including a plurality of package upper pads 2130. Each of the plurality of semiconductor chips 2200 may include an input/output pad 2201. The input/output pad 2201 may correspond to the input/output pad 1101 of FIG. 7 . Each of the plurality of semiconductor chips 2200 may include a plurality of gate stacks 3210 and a plurality of channel structures 3220. The plurality of semiconductor chips 2200 may include the semiconductor device 10 described with reference to FIGS. 4 and 5 .

In some embodiments, the connection structure 2400 may be a bonding wire that electrically connects the input/output pad 2201 and the top pad of the package 2130. Accordingly, in the first and second semiconductor packages 2003a and 2003b, the plurality of semiconductor chips 2200 may be electrically connected to each other using a bonding wire method and may be electrically connected to the package upper pad 2130 of the package substrate 2100. can be connected In some embodiments, in the first and second semiconductor packages 2003a and 2003b, the plurality of semiconductor chips 2200 use a through electrode (Through Silicon Via, TSV) instead of the bonding wire-type connection structure 2400. They may be electrically connected to each other by a connection structure that includes a connection structure.

In some embodiments, the controller 2002 and the plurality of semiconductor chips 2200 may be included in one package. In some embodiments, the controller 2002 and a plurality of semiconductor chips 2200 are mounted on a separate interposer board different from the main board 2001, and the controller 2002 and the controller 2002 are connected by wiring formed on the interposer board. A plurality of semiconductor chips 2200 may be connected to each other.

9 is a cross-sectional view showing a semiconductor package including a semiconductor device according to an exemplary embodiment of the present invention. Specifically, FIG. 9 shows the configuration of a cross-sectional view taken along line A-A' of FIG. 8 in detail.

Referring to FIG. 9, in the semiconductor package 3003, the package substrate 2100 may be a printed circuit board.

The package substrate 2100 includes a body portion 2120, a plurality of package upper pads 2130 (see FIG. 8) disposed on the upper surface of the body portion 2120, and disposed on the lower surface of the body portion 2120 or exposed through the lower surface. It may include a plurality of lower pads 2125 and a plurality of internal wirings 2135 that electrically connect the plurality of upper pads 2130 and the plurality of lower pads 2125 within the body portion 2120. The plurality of upper pads 2130 may be electrically connected to the plurality of connection structures 2400 (see FIG. 8). The plurality of lower pads 2125 may be connected to the plurality of wiring patterns 2005 on the main board 2001 of the electronic system 2000 illustrated in FIG. 8 through the plurality of conductive connectors 2800.

Each of the plurality of semiconductor chips 2200 may include a semiconductor substrate 3010 and a first structure 3100 and a second structure 3200 sequentially stacked on the semiconductor substrate 3010. The first structure 3100 may include a peripheral circuit area including a plurality of peripheral wires 3110. The second structure 3200 is electrically connected to the common source line 3205, the gate stack 3210 on the common source line 3205, the channel structure 3220 penetrating the gate stack 3210, and the channel structure 3220. It may include a connected bit line 3240.

Each of the plurality of semiconductor chips 2200 is electrically connected to the plurality of peripheral wirings 3110 of the first structure 3100 and may include a through wiring 3245 extending into the second structure 3200. The through wiring 3245 may be disposed outside the gate stack 3210. In other embodiments, the semiconductor package 3003 may further include a through wiring that penetrates the gate stack 3210. Each of the plurality of semiconductor chips 2200 may further include an input/output pad 2201 (see FIG. 8 ) that is electrically connected to the plurality of peripheral wirings 3110 of the first structure 3100.

As above, exemplary embodiments have been disclosed in the drawings and specification. In this specification, embodiments have been described using specific terms, but this is only used for the purpose of explaining the technical idea of the present disclosure and is not used to limit the meaning or scope of the present disclosure described in the claims. Therefore, those skilled in the art will understand that various modifications and other equivalent embodiments are possible therefrom. Therefore, the true technical protection scope of the present disclosure should be determined by the technical spirit of the attached claims.

10: semiconductor device, 20: memory cell array, 30: peripheral circuit, 60: wiring structure, 70: interlayer insulating film, 100: semiconductor device, 110: upper substrate, 120: gate layer, 130: insulating layer, 140: first Channel structure, 150: cover insulating layer, 160: first plug portion, 170: first insulating layer, 180: first insulating separation layer, 210: first string selection line insulating layer, 220: string selection line gate layer, 230 : second string selection line insulating layer, 240: second channel structure, 250: second insulating layer, 260: second plug portion, 270: third insulating layer, GS: gate stack, SS: string selection line stack, WLC : word line cut, WLS: word line spacer, CNT: contact plug, SLC: string selection line cut, BLCa, BLCb: bit line contact plug.

Claims (10)

semiconductor substrate;
A gate stack including a plurality of gate layers and a plurality of insulating layers alternately stacked on the semiconductor substrate;
a plurality of first channel structures extending vertically through the gate stack;
a first insulating layer disposed on the gate stack;
a string selection line stack disposed on the first insulating layer;
a word line cut extending vertically through the gate stack, the first insulating layer, and the string select line stack;
Including,
The word line cut includes a first portion penetrating a portion of the gate stack, the first insulating layer, and the string select line stack, and a second portion penetrating a remaining portion of the string select line stack. A semiconductor device wherein the horizontal width of the first portion is smaller than the horizontal width of the second portion. According to claim 1,
A semiconductor device wherein a seam, which is an empty space, is disposed inside the first portion, and the seam extends vertically to a vertical level higher than the top surface of the gate stack. According to claim 1,
A semiconductor device further comprising a word line spacer surrounding the word line cut. According to clause 3,
The word line spacer includes a first spacer portion surrounding the first portion of the word line cut and a second spacer portion surrounding the second portion of the word line cut, the thickness of the first spacer portion being: A semiconductor device having a thickness greater than the thickness of the second spacer portion. According to clause 3,
A semiconductor device wherein the lower surface of the word line spacer is located at the same or lower vertical level than the lower surface of the first insulating layer. According to claim 1,
A semiconductor device further comprising a second insulating layer disposed on the string select line stack. According to clause 6,
The second portion extends vertically through the second insulating layer. According to clause 7,
A semiconductor device wherein the top surface of the second portion is located at the same vertical level as the top surface of the second insulating layer. According to claim 1,
a plurality of second channel structures extending through the string selection line stack; and a connection via configured to electrically connect the plurality of first channel structures and the plurality of second channel structures,
A semiconductor device in which the central axis of the first channel structure and the central axis of the second channel structure are arranged to be offset from each other. According to claim 1,
The word line cut is a semiconductor device including SFO (Seam-Free Oxide).

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