KR20240121592A - Semiconductor device and electronic system - Google Patents

Abstract

The technical idea of the present invention provides a semiconductor device including: a peripheral circuit structure; and a cell array structure vertically overlapping the peripheral circuit structure and including first to third memory cell blocks; wherein the peripheral circuit structure includes: a central active region extending in a first horizontal direction; and first to third extended active regions extending from the central active region in a second horizontal direction perpendicular to the first horizontal direction; a substrate having an active region and a device isolation film defining the active region; and first to third gate structures disposed on the active region and spaced apart from each other; wherein the central active region, the first to third extended active regions, and the first to third gate structures constitute first to third pass transistors, respectively, and the first to third pass transistors share one drain region in the central active region, and the active region has an h-shape that is inverted upside down.

Description

Semiconductor device and electronic system including the same {Semiconductor device and electronic system}

The technical idea of the present invention relates to a semiconductor device and an electronic system including the same. Specifically, it relates to a semiconductor device having a nonvolatile vertical memory element and an electronic system including the same.

In electronic systems requiring data storage, semiconductor devices capable of storing large amounts of data are in demand, and accordingly, methods for increasing the data storage capacity of semiconductor devices are being studied. For example, as one method for increasing the data storage capacity of semiconductor devices, a semiconductor device including a vertical memory element having memory cells arranged three-dimensionally instead of two-dimensionally is being proposed.

The technical idea of the present invention is to provide a semiconductor device and an electronic system including the same with improved performance and reliability while reducing the size.

In addition, the problems to be solved by the technical idea of the present invention are not limited to the problems mentioned above, and other problems can be clearly understood by those skilled in the art from the description below.

In order to solve the above problem, the technical idea of the present invention provides a semiconductor device including: a peripheral circuit structure; and a cell array structure vertically overlapping the peripheral circuit structure and including first to third memory cell blocks; wherein the peripheral circuit structure includes: a central active region extending in a first horizontal direction; and first to third extended active regions extending from the central active region in a second horizontal direction perpendicular to the first horizontal direction; a substrate having an active region and a device isolation film defining the active region; and first to third gate structures disposed on the active region and spaced apart from each other; wherein the central active region, the first to third extended active regions, and the first to third gate structures constitute first to third pass transistors, respectively, and the first to third pass transistors share one drain region in the central active region, and the active region has an h-shape that is inverted upside down.

According to the technical idea of the present invention, a semiconductor device is composed of an active region having an upside-down h shape and first to third gate structures arranged on the active region, and by forming first to third pass transistors sharing one drain region, the area occupied by each of the first to third pass transistors is reduced, so that the size of the semiconductor device including the same can be reduced. In addition, the spacing between adjacent drain regions increases, so that the adjacent drain regions can be electrically isolated. Accordingly, the performance and reliability of the semiconductor device can be improved.

The effects obtainable from the exemplary embodiments of the present disclosure are not limited to the effects mentioned above, and other effects not mentioned can be clearly derived and understood by those skilled in the art to which the exemplary embodiments of the present disclosure belong from the following description. That is, unintended effects resulting from practicing the exemplary embodiments of the present disclosure can also be derived by those skilled in the art from the exemplary embodiments of the present disclosure.

FIG. 1 is a block diagram of a semiconductor device according to an exemplary embodiment of the present invention.
FIG. 2 is an equivalent circuit diagram of a memory cell array of a semiconductor device according to an exemplary embodiment of the present invention.
FIG. 3 is a schematic perspective view of a semiconductor device according to an exemplary embodiment of the present invention.
FIG. 4 is a layout diagram showing a semiconductor device according to an exemplary embodiment of the present invention.
Figure 5a is a cross-sectional view along line A-A' of Figure 4.
Figure 5b is a cross-sectional view along line B-B' of Figure 4.
FIG. 6 is a layout diagram showing a semiconductor device according to an exemplary embodiment of the present invention.
FIGS. 7A to 7D are layout diagrams showing semiconductor devices according to exemplary embodiments of the present invention.
FIGS. 8A and 8B are cross-sectional views showing a semiconductor device according to an exemplary embodiment of the present invention.
FIG. 9 is a schematic diagram illustrating an electronic system including a semiconductor device according to an exemplary embodiment of the present invention.
FIG. 10 is a perspective view schematically illustrating an electronic system including a semiconductor device according to an exemplary embodiment of the present invention.
FIG. 11 is a cross-sectional view schematically illustrating semiconductor packages according to an exemplary embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. The same reference numerals are used for the same components in the drawings, and redundant descriptions thereof are omitted.

FIG. 1 is a block diagram of a semiconductor device (10) according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a semiconductor device (10) may include a memory cell array (20) and a peripheral circuit (30). The memory cell array (20) includes a plurality of memory cell blocks (BLK1, BLK2, ..., BLKp). Each of the plurality of memory cell blocks (BLK1, BLK2, ..., BLKp) may include a plurality of memory cells. The memory cell blocks (BLK1, BLK2, ..., BLKp) may be connected to a peripheral circuit (30) through a bit line (BL), a word line (WL), a string select line (SSL), and a ground select line (GSL).

The peripheral circuit (30) may include a row decoder (32), a page buffer (34), a data input/output circuit (36), a control logic (38), and a common source line driver (39). The peripheral circuit (30) may further include various circuits such as a voltage generation circuit that generates various voltages necessary for the operation of the semiconductor device (10), an error correction circuit for correcting errors in data read from the memory cell array (20), and an input/output interface.

A memory cell array (20) may be connected to a row decoder (32) via a word line (WL), a string select line (SSL), and a ground select line (GSL), and may be connected to a page buffer (34) via a bit line (BL). In the memory cell array (20), a plurality of memory cells included in a plurality of memory cell blocks (BLK1, BLK2, ..., BLKp) may each be a flash memory cell. The memory cell array (20) may include a three-dimensional memory cell array. The three-dimensional memory cell array may include a plurality of NAND strings, and the plurality of NAND strings may include a plurality of memory cells connected to a plurality of word lines (WL) that are each vertically stacked.

The peripheral circuit (30) can receive an address (ADDR), a command (CMD), and a control signal (CTRL) from outside the semiconductor device (10), and can transmit and receive data (DATA) with a device outside the semiconductor device (10).

The row decoder (32) can select at least one of a plurality of memory cell blocks (BLK1, BLK2, ..., BLKp) in response to an address (ADDR) from the outside, and can select a word line (WL), a string select line (SSL), and a ground select line (GSL) of the selected memory cell block. The row decoder (32) can transmit a voltage for performing a memory operation to the word line (WL) of the selected memory cell block.

The page buffer (34) can be connected to the memory cell array (20) via a bit line (BL). The page buffer (34) can operate as a write driver during a program operation to apply a voltage according to data (DATA) to be stored in the memory cell array (20) to the bit line (BL), and can operate as a sense amplifier during a read operation to detect data (DATA) stored in the memory cell array (20). The page buffer (34) can operate according to a control signal (PCTL) provided from a control logic (38).

The data input/output circuit (36) can be connected to the page buffer (34) via a plurality of data lines (DLs). The data input/output circuit (36) can receive data (DATA) from a memory controller (not shown) during a program operation, and provide program data (DATA) to the page buffer (34) based on a column address (C_ADDR) provided from a control logic (38). The data input/output circuit (36) can provide read data (DATA) stored in the page buffer (34) to the memory controller based on a column address (C_ADDR) provided from a control logic (38) during a read operation.

The data input/output circuit (36) can transmit an input address or command to the control logic (38) or the row decoder (32). The peripheral circuit (30) can further include an ESD (Electro Static Discharge) circuit and a pull-up/pull-down driver.

The control logic (38) can receive a command (CMD) and a control signal (CTRL) from the memory controller. The control logic (38) can provide a row address (R_ADDR) to the row decoder (32) and a column address (C_ADDR) to the data input/output circuit (36). The control logic (38) can generate various internal control signals used in the semiconductor device (10) in response to the control signal (CTRL). For example, the control logic (38) can adjust a voltage level provided to a word line (WL) and a bit line (BL) when performing a memory operation such as a program operation or an erase operation.

A common source line driver (39) can be connected to a memory cell array (20) via a common source line (CSL). The common source line driver (39) can apply a common source voltage (e.g., a power supply voltage) or a ground voltage to the common source line (CSL) based on a control signal (CTRL_BIAS) of the control logic (38).

FIG. 2 is an equivalent circuit diagram of a memory cell array (MCA) of a semiconductor device (10) according to exemplary embodiments.

Referring to FIG. 2, a memory cell array (MCA) may include a plurality of memory cell strings (MS). The memory cell array (MCA) may include a plurality of bit lines (BL: BL1, BL2, ??, BLm), a plurality of word lines (WL: WL1, WL2, ??, WLn-1, WLn), at least one string select line (SSL), at least one ground select line (GSL), and a common source line (CSL). A plurality of memory cell strings (MS) may be formed between the plurality of bit lines (BL: BL1, BL2, ??, BLm) and the common source line (CSL). FIG. 2 illustrates a case where each of the plurality of memory cell strings (MS) includes two string select lines (SSL), but the technical idea of the present invention is not limited thereto. For example, each of the plurality of memory cell strings (MS) may include one string select line (SSL).

Each of the plurality of memory cell strings (MS) may include a string select transistor (SST), a ground select transistor (GST), and a plurality of memory cell transistors (MC1, MC2, ??, MCn-1, MCn). A drain region of the string select transistor (SST) may be connected to a bit line (BL: BL1, BL2, ??, BLm), and a source region of the ground select transistor (GST) may be connected to a common source line (CSL). The common source line (CSL) may be a region to which source regions of the plurality of ground select transistors (GST) are commonly connected.

A string select transistor (SST) can be connected to a string select line (SSL), and a ground select transistor (GST) can be connected to a ground select line (GSL). A plurality of memory cell transistors (MC1, MC2, ??, MCn-1, MCn) can be connected to a plurality of word lines (WL: WL1, WL2, ??, WLn-1, WLn), respectively.

FIG. 3 is a schematic perspective view of a semiconductor device (100) according to exemplary embodiments.

Referring to FIG. 3, a semiconductor device (10) may include a memory cell array structure (CS) and a peripheral circuit structure (PS) that overlap each other in a vertical direction.

The memory cell array structure (CS) may include a memory cell array (20) described with reference to FIG. 1. The peripheral circuit structure (PS) may include a peripheral circuit (30) described with reference to FIG. 1.

A memory cell array structure (CS) may include a plurality of tiles. Each of the plurality of tiles may include a plurality of memory cell blocks (BLK1, BLK2, ..., BLKn). Each of the plurality of memory cell blocks (BLK1, BLK2, ..., BLKn) may include memory cells arranged three-dimensionally.

In some embodiments, two tiles may constitute one mat, but this is not limited to the above. For example, the memory cell array (20) described with reference to FIG. 1 may include multiple mats.

Fig. 4 is a layout diagram showing a semiconductor device (100) according to an exemplary embodiment of the present invention. Fig. 5a is a cross-sectional view taken along line A-A' of Fig. 4. Fig. 5b is a cross-sectional view taken along line B-B' of Fig. 4.

Referring to FIGS. 4, 5a, and 5b together, the semiconductor device (100) may include a substrate (101) and first to third gate structures (120a, 120b, 120c). The semiconductor device (100) may be placed in the peripheral circuit structure (PS) described with reference to FIG. 3.

The substrate (101) may be formed of a semiconductor substrate. For example, the substrate (101) may include Si, Ge, or SiGe. An active region (110) may be defined by a device isolation film (150) on the substrate (101). First, second, and third pass transistors (PTR1, PTR2, PTR3, PTR3) may be configured on the active region (110).

The active region (110) may include a central active region (110_1) and first, second, and third extended active regions (110_2a, 110_2b, 110_2c). In an exemplary embodiment, the central active region (110_1) and the first, second, and third extended active regions (110_2a, 110_2b, 110_2c) (i.e., the active region (110)) may together have an h-shape that is inverted upside down on the X-Y plane.

The central active region (110_1) may extend in the first horizontal direction (X direction). The central active region (110_1) may have a rectangular shape on the X-Y plane.

A drain region (D) may be located above the central active region (110_1). The drain region (D) may be a region doped with a first impurity. The first impurity may be, for example, an n-type impurity such as phosphorus (P). The drain region (D) may be connected to a drain contact (140). The drain contact (140) may receive an operating voltage from a voltage generation circuit included in a peripheral circuit (30, see FIG. 1) and may transmit the operating voltage to a word line (WL, see FIG. 1), a string select line (SSL, see FIG. 1), and a ground select line (GSL) of a selected memory cell block. The operating voltage may be, for example, a program voltage (Vpgm). In an exemplary embodiment, the drain contact (140) may be arranged diagonally with respect to the first to third gate structures (120a, 120b, 120c) on the X-Y plane. By arranging the drain contact (140) diagonally with respect to the first to third gate structures (120a, 120b, 120c), the area occupied by the first to third pass transistors (PTR1, PTR2, PTR3) may be reduced while maintaining the separation distance between the drain contact (140) and the first to third gate structures (120a, 120b, 120c). That is, while the breakdown of the gate dielectric films (120al, 120bl, 120cl) due to an electric field that may occur when the separation distance between the drain contact (140) and the first to third gate structures (120a, 120b, 120c) is reduced, the area occupied by the first to third pass transistors (PTR1, PTR2, PTR3) can be reduced.

The first, second, and third extended active regions (110_2a, 110_2b, 110_2c) may extend from the central active region (110_1) in a second horizontal direction (Y direction) perpendicular to the first horizontal direction. Specifically, the first extended active region (110_2a) may extend from one edge of the central active region (110_1) along the second horizontal direction upward to the ground surface of FIG. 4, the second extended active region (110_2b) may extend from the other edge of the central active region (110_1) along the second horizontal direction upward to the ground surface of FIG. 4, and the third extended active region (110_2c) may extend from one edge of the central active region (110_1) along the second horizontal direction downward to the ground surface of FIG. 4. The first, second, and third extended active regions (110_2a, 110_2b, 110_2c) may have a rectangular shape on the X-Y plane.

In an exemplary embodiment, the first extended active region (110_2a) and the second extended active region (110_2b) may be symmetrical with respect to an imaginary line (S-S') passing through the center of the central active region (110_1). The third extended active region (110_2c) and the first extended active region (110_2a) may be symmetrical with respect to the central active region (110_1).

First, second, and third source regions (Sa, Sb, Sc) may be positioned on the upper portions of each of the first, second, and third extended active regions (110_2a, 110_2b, and 110_2c, respectively). Specifically, the first source region (Sa) may be positioned on the upper portion of the first extended active region (110_2a), the second source region (Sb) may be positioned on the upper portion of the second extended active region (110_2b), and the third source region (Sc) may be positioned on the upper portion of the third extended active region (110_2c). The first, second, and third extended active regions (110_2a, 110_2b, and 110_2c) may be regions doped with a second impurity. The second impurity may be, for example, an n-type impurity such as phosphorus (P).

Each of the first, second, and third source regions (Sa, Sb, Sc) may be connected to a first, second, and third contact (130a, 130b, 130c). The first, second, and third contacts (130a, 130b, 130c) may receive the operating voltage from the drain contact (140) and transmit the operating voltage to a word line (WL, see FIG. 1), a string select line (SSL, see FIG. 1), and a ground select line (GSL) of a selected memory cell block. For example, when a memory cell block (hereinafter, referred to as a first memory cell block) connected to the first contact (130a) is selected, the first contact (130a) may receive the operating voltage from the drain contact (140) and transmit the operating voltage to the word line of the first memory cell block.

The first, second, and third gate structures (120a, 120b, 120c) may be arranged to be spaced apart from each other on the substrate (101). Specifically, the first gate structure (120a) may be arranged to be spaced apart from each other on the first extended active region (110_2a) of the substrate (101), the second gate structure (120b) may be arranged to be spaced apart from each other on the second extended active region (110_2b) of the substrate (101), and the third gate structure (120c) may be arranged to be spaced apart from each other on the third extended active region (110_2c) of the substrate (101).

First, second, and third channel regions (CHa, CHb, CHc) may be positioned on the upper portions of each of the first, second, and third gate structures (120a, 120b, and 120c) and each of the first, second, and third extended active regions (110_2a, 110_2b, and 110_2c) that overlap in a third direction (Z direction) perpendicular to the first horizontal direction and the second horizontal direction. For example, the first channel region (CHa) may be positioned on the upper portion of the first extended active region (110_2a) that overlaps the first gate structure (120a) in the third direction.

The first gate structure (120a) can form a first pass transistor (PTR1) together with the first source region (Sa) and the drain region (D). The second gate structure (120b) can form a second pass transistor (PTR2) together with the second source region (Sb) and the drain region (D). The third gate structure (120c) can form a third pass transistor (PTR3) together with the third source region (Sc) and the drain region (D). That is, as described above, the first, second, and third pass transistors (PTR1, PTR2, and PTR3) can share one drain region (D).

Each of the first, second, and third pass transistors (PTR1, PTR2, and PTR3) can be configured to deliver an operating voltage to a different memory cell block. For example, any one of the first, second, and third pass transistors (PTR1, PTR2, and PTR3) can be configured to deliver an operating voltage to any one of the different memory cell blocks based on a memory cell block selection signal.

In an exemplary embodiment, the first, second, and third pass transistors (PTR1, PTR2, PTR3) may be high-voltage pass transistors capable of delivering a high voltage to the memory cell blocks. The high voltage may be, for example, about 10 V to about 30 V.

Each of the first, second, and third gate structures (120a, 120b, and 120c) may include a first, second, and third gate dielectric film (120al, 120bl, and 120cl) and a first, second, and third gate electrode (120ag, 120bg, and 120cg) disposed on the first, second, and third gate dielectric films (120al, 120bl, and 120cl). Each of the first, second, and third gate dielectric films (120al, 120bl, and 120cl) may include, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a combination thereof. Each of the first, second, and third gate electrodes (120ag, 120bg, 120cg) may include, for example, aluminum, silver, copper, molybdenum, chromium, tantalum, titanium, or a combination thereof.

A semiconductor device (100) according to an exemplary embodiment of the present invention includes an active region (110) having an h shape, and first to third gate structures (120a, 120b, 120c) disposed on the active region (110), wherein the active region (110) and the first to third gate structures (120a, 120b, 120c) constitute first to third pass transistors (PTR1, PTR2, PTR3), respectively, and share one drain region of the active region (110). Accordingly, compared to a conventional semiconductor device including an active region and two gate structures disposed on an upper portion of the active region and two pass transistors sharing one drain region of the active region, the area occupied by each of the pass transistors can be reduced. In addition, compared to conventional semiconductor devices, in the exemplary semiconductor device (100) of the present invention, the separation distance between neighboring drain contacts (140) is relatively increased, so that electrical isolation between the neighboring drain contacts (140) can be well achieved. Accordingly, the performance and reliability of the semiconductor device (100) according to the exemplary embodiment of the present invention can be improved.

Fig. 6 is a layout diagram showing a semiconductor device according to an exemplary embodiment of the present invention. Contents already described in the description of Figs. 4, 5a, and 5b are briefly described or omitted. In addition, since each configuration of the semiconductor device (100a) of Fig. 6 is similar to each configuration of the semiconductor device (100) described with reference to Figs. 4, 5a, and 5b, the following description will focus on the differences.

Referring to FIG. 6, the semiconductor device (100a) may include a substrate (101) and first to third gate structures (120a, 120b, 120c). The semiconductor device (100a) may be placed in the peripheral circuit structure (PS) described with reference to FIG. 3.

An active region (110) may be defined on a substrate (101) by a device isolation film (150). The active region (110) may include a central active region (110_1a) and first, second, and third extended active regions (110_2a, 110_2b, 110_2c).

In an exemplary embodiment, each of the first to third gate structures (120a1, 120b1, 120c1) may have any one shape selected from a rectangular shape and an L shape. For example, as illustrated, the first gate structure (120a1) and the third gate structure (120c1) may have an L shape or a rotated L shape, and the second gate structure (120b1) may have a rectangular shape.

Depending on the shape of each of the first to third gate structures (120a1, 120b1, 120c1), the gate length of each of the first to third gate structures (120a1, 120b1, 120c1) may vary. That is, by changing the shape of the first to third gate structures (120a1, 120b1, 120c1), the gate length of each of the first to third gate structures (120a1, 120b1, 120c1) may be adjusted, thereby preventing leakage current and improving the performance of the semiconductor device. In addition, the present invention is not limited thereto, and any one of the first to third gate structures (120a1, 120b1, 120c1) may have a Z shape or a rotated Z shape.

FIGS. 7A to 7D are layout diagrams showing semiconductor devices according to exemplary embodiments of the present invention. Contents already described in the description of FIGS. 4, 5A, and 5B are briefly described or omitted. In addition, since each configuration of the semiconductor device (100a) of FIG. 6 is similar to each configuration of the semiconductor device (100) described with reference to FIGS. 4, 5A, and 5B, the following description will focus on the differences.

Referring to FIG. 7a, a semiconductor device (100b) may include a substrate (101) and first to third gate structures (120a, 120b, 120c). The semiconductor device (100a) may be placed in a peripheral circuit structure (PS) described with reference to FIG. 3. An active region (110a, 110b, 110c, 110d) may be defined by a device isolation film (150) on the substrate (101). First, second, and third pass transistors (PTR1, PTR2, PTR3, PTR3) may be configured on the active region (110a, 110b, 110c, 110d).

The above active regions (110a, 110b, 110c, 110d) may include a first active region (110a), a second active region (110b), a third active region (110c), and a fourth active region (110d). The first active region (110a), the second active region (110b), the third active region (110c), and the fourth active region (110d) may be arranged to be spaced apart from each other. Each of the second active region (110b), the third active region (110c), and the fourth active region (110d) may include a plurality of gate structures, a plurality of pass transistors, and a plurality of contacts, similar to the first active region (110a).

The second active region (110b) may be adjacent to the first active region (110a) in the first horizontal direction and adjacent to the second active region (110b) in the second horizontal direction. The third active region (110c) may be adjacent to the first active region (110a) in the second horizontal direction and adjacent to the fourth active region (110d) in the second horizontal direction.

Additionally, in exemplary embodiments, a portion of the first active region (110a) may horizontally overlap a portion of the third active region (110c) in the first horizontal direction. In exemplary embodiments, a portion of the second active region (110b) may horizontally overlap a portion of the fourth active region (110d) in the first horizontal direction.

In exemplary embodiments, the first active region (110a) and the third active region (110c) may have different shapes. The first active region (110a) may have an upside-down h shape, and the third active region (110c) may have a left-right inverted h shape. The first active region (110a) may have a shape that is the third active region (110a) rotated 180 degrees clockwise. The first active region (110a) and the third active region (110c) may have shapes that are left-right inverted with respect to the second active region (110b) and the fourth active region (110d) with respect to the central axis (CAX). Here, the left-right direction may mean the left-right direction of the first horizontal direction (X direction).

In this way, the semiconductor device (100b) of the present invention is composed of an active region and two gate structures arranged on the upper portion of the active region, and compared to a conventional semiconductor device including two pass transistors sharing one drain region of the active region, the area occupied by each of the pass transistors can be reduced. In addition, the semiconductor device of the present invention can relatively increase a separation distance (D1) between neighboring drain contacts in the first horizontal direction and a separation distance (D2) between neighboring drain contacts in the second horizontal direction, thereby achieving electrical isolation between neighboring drain contacts. In addition, the semiconductor device (100b) of the present invention can relatively increase a separation distance (D3, D4) between neighboring contacts, thereby achieving electrical isolation between neighboring contacts. Through this, the performance and reliability of the semiconductor device can be improved.

Referring to FIG. 7b, the first active region (110a) of the semiconductor device (100c) may have an upside-down inverted h shape, and the third active region (110c) may have an upside-down inverted h shape. Here, the second active region (110b) and the fourth active region (110d) may have the same shape as the first active region (110a) and the third active region (110c). That is, the first active region (110a) and the second active region (110b) may have the same shape and may have an upside-down inverted h shape. In addition, the third active region (110c) and the fourth active region (110d) may have the same shape and may have an upside-down inverted h shape.

Referring to FIG. 7c, the first active region (110a) of the semiconductor device (100d) may have an h-shape that is flipped left-right and up-down. That is, the first active region (110a) may have an h-shape that is rotated 180 degrees clockwise or counterclockwise. The third active region (110c) may have an h-shape. The first active region (110a) and the third active region (110c) may have the same shape as the second active region (110b) and the fourth active region (110d). That is, the first active region (110a) and the second active region (110b) may have the same shape, and may have an h-shape that is flipped left-right and up-down. In addition, the third active region (110c) and the fourth active region (110d) may have the same shape, and may have an h-shape.

Referring to FIG. 7d, the first active region (110a) of the semiconductor device (100d) may have a left-right inverted and up-down inverted h shape. The third active region (110c) may have an h shape. The first active region (110a) and the third active region (110c) may have left-right inverted shapes with respect to the central axis (CAX) compared to the second active region (110b) and the fourth active region (110d). Specifically, the second active region (110b) may have a up-down inverted h shape, and the fourth active region (110d) may have a left-right inverted h shape.

FIG. 8a is a cross-sectional view showing a semiconductor device (300) according to an exemplary embodiment of the present invention.

Referring to FIG. 8a, a semiconductor device (300) may include a cell array structure (CS) and a peripheral circuit structure (PS) that are overlapped in a vertical direction (Z direction). The cell array structure (CS) may include a memory cell region (MEC) and a connection region (CON) arranged on one side of the first horizontal direction (X direction) of the memory cell region (MEC).

In an exemplary embodiment, the semiconductor device (100) may have a C2C (chip to chip) structure. The C2C structure may be obtained by forming a cell array structure (CS) on a first wafer, forming a peripheral circuit structure (PS) on a second wafer different from the first wafer, and then connecting the cell array structure (CS) and the peripheral circuit structure (PS) to each other by a bonding method. For example, the bonding method may mean a method of bonding a first bonding pad (BP1) of the cell array structure (CS) and a second bonding pad (BP2) of the peripheral circuit structure (PS) so as to be electrically connected to each other. In exemplary embodiments, when the first bonding pad (BP1) and the second bonding pad (BP2) are made of copper (Cu), the bonding method may be a Cu-Cu bonding method. In other exemplary embodiments, each of the first bonding pad (BP1) and the second bonding pad (BP2) may be made of aluminum (Al) or tungsten (W).

The peripheral circuit structure (PS) may include a substrate (50), a peripheral circuit transistor (60TR) disposed on the substrate (50), and a peripheral circuit wiring structure (70).

The substrate (50) may be formed of a semiconductor substrate. For example, the substrate (50) may include Si, Ge, or SiGe. An active region (AC) may be defined by a device isolation film (54) in the substrate (52), and a plurality of peripheral circuit transistors (60TR) may be formed on the active region (AC). The plurality of peripheral circuit transistors (60TR) may include a peripheral circuit gate (60G) and source/drain regions (62) disposed in a portion of the substrate (50) on both sides of the peripheral circuit gate (60G). In an exemplary embodiment, the plurality of peripheral circuit transistors (60TR) may include at least one of the structures described above with respect to the pass transistors (PTR1, PTR2, PTR3, PTR3) included in the semiconductor devices (100, 100a, 100b, 200a, 200b, 200c) with reference to FIGS. 4 to 7c.

The plurality of peripheral circuit wiring structures (70) may include a plurality of peripheral circuit contacts (72) and a plurality of peripheral circuit wiring layers (74). At least some of the plurality of peripheral circuit wiring layers (74) may be configured to be electrically connectable to the peripheral circuit transistors (60TR). The plurality of peripheral circuit contacts (72) may be configured to interconnect some selected from the plurality of peripheral circuit transistors (60TR) and the plurality of peripheral circuit wiring layers (74). The plurality of peripheral circuit transistors (60TR) and the plurality of peripheral circuit wiring structures (70) included in the peripheral circuit structure (PS) may be covered with an interlayer insulating film (80). The interlayer insulating film (80) may include a silicon oxide film, a silicon nitride film, a SiON film, a SiOCN film, or a combination thereof.

A plurality of second bonding pads (BP2) may be arranged on the interlayer insulating film (80). The plurality of second bonding pads (BP2) may be connected to a plurality of peripheral circuit wiring structures (70) through second bonding vias (90). In an exemplary embodiment, a top surface of the second bonding pads (BP2) may be coplanar with a top surface of the interlayer insulating film (80). The second bonding pads (BP2) may be made of a conductive material including copper (Cu), gold (Au), silver (Ag), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), or a combination thereof.

The cell array structure (CS) may include a cell stack structure (GS). The cell stack structure (GS) may include a plurality of gate electrodes (321) and a plurality of insulating films (323) that are alternately arranged along the vertical direction. The plurality of gate electrodes (321) may be made of, for example, tungsten, nickel, cobalt, tantalum, tungsten nitride, titanium nitride, tantalum nitride, or a combination thereof. The plurality of insulating films (323) may be made of silicon oxide, silicon nitride, or silicon oxynitride. The plurality of gate electrodes (321) may correspond to a ground select line (GSL), a word line (WL), and at least one string select line (SSL) that constitute a memory cell string (MS, see FIG. 2). For example, in the drawing, the uppermost gate electrode (321) may function as a ground select line (GSL), the lowermost two gate electrodes (321) in the drawing may function as string select lines (SSL), and the remaining gate electrodes (321) may function as word lines (WL). Accordingly, a memory cell string (MS) in which a ground select transistor (GST) and a string select transistor (SST) and memory cell transistors (MC1, MC2, ..., MCn-1, MCn) therebetween are connected in series may be provided.

The cell stack structure (GS) may extend to have a shorter length in the first horizontal direction (X direction) as it moves away from the substrate (310) on the connection region (CON). That is, the cell stack structure (GS) may have a step shape.

The cell stack structure (GS) may be covered by a cover insulating film (330). The cover insulating film (330) may be formed of a silicon oxide film, a silicon nitride film, or a combination thereof.

A plurality of channel structures (CHS) may extend vertically through the cell stack structure (GS) on the memory cell region (MEC). Each of the plurality of channel structures (CHS) may be arranged to be spaced apart from each other by a predetermined interval. The plurality of channel structures (CHS) may be arranged in a zigzag shape or a staggered shape. In an exemplary embodiment, the plurality of channel structures (CHS) may be arranged to extend into the interior of the substrate (310). In another embodiment, the plurality of channel structures (CHS) may be arranged to contact the lower surface of the substrate (310).

A plurality of channel structures (CHS) may each be arranged within a channel hole (not shown). Each of the plurality of channel structures (CHS) may include a gate insulating film (not shown), a channel layer (not shown), a buried insulating film (not shown), and a conductive plug (not shown).

On the sidewall of the channel hole, the gate insulating film and the channel layer may be sequentially arranged. On the channel layer, the buried insulating film may be arranged to fill the residual space of the channel hole. The conductive plug may be arranged in contact with the channel layer to block the entrance of the channel hole.

The plurality of channel structures (CHS) can be in contact with a plurality of bit line contacts (BLC) on a lower surface. The plurality of bit line contacts (BLC) can extend in a vertical direction through a first insulating film (340) and can be mutually insulated by the first insulating film (340). The plurality of bit line contacts (BLC) can be in contact with a plurality of bit lines (BL) on a lower surface. The plurality of bit lines (BL) can extend in a vertical direction through a second insulating film (350) and can be mutually insulated by the second insulating film (350). Each of the plurality of channel structures (CHS) can be connected to a corresponding one of the plurality of bit lines (BL) through the bit line contact (BLC).

A plurality of contact structures (CNT) may extend vertically through the cover insulating film (330) and the first insulating film (340) on the connection region (CON). The plurality of contact structures (CNT) may contact a plurality of wiring layers (ML) on a lower surface. The plurality of wiring layers (ML) may extend vertically through the second insulating film (350) and may be mutually insulated by the second insulating film (350). The plurality of wiring layers (ML) may contact a plurality of first bonding vias (362) on a lower surface. The plurality of first bonding vias (362) may extend vertically through the interlayer insulating film (360) and may be mutually insulated by the interlayer insulating film (360). The first bonding vias (362) may contact a first bonding pad (BP1) on a lower surface.

Fig. 8b is a cross-sectional view showing a semiconductor device (400) according to an exemplary embodiment of the present invention. Since each configuration of the semiconductor device (400) of Fig. 8b is similar to each configuration of the semiconductor device (300) described with reference to Fig. 8a, the following description will focus on the differences.

Referring to FIG. 8b, the semiconductor device (400) may include a cell array structure (CS) and a peripheral circuit structure (PS).

The peripheral circuit structure (PS) of the semiconductor device (400) may be substantially identical to or similar to the peripheral circuit structure (PS) of the semiconductor device (300) described with reference to FIG. 8a.

A cell array structure (CS) may include a cell stack structure (GS) and a cell substrate (410) interposed between the cell stack structure (GS) and a peripheral circuit structure (PS). In an exemplary embodiment, the cell substrate (410) may be made of a semiconductor material such as polysilicon.

The cell stack structure (GS) may be arranged on a cell substrate (410). The cell stack structure (GS) may include a plurality of gate electrodes (421) and a plurality of insulating films (423) that are alternately arranged along the vertical direction. The cell stack structure (GS) may extend to have a shorter length in the first horizontal direction (X direction) as it moves away from the substrate (410) on the connection region (CON). That is, the cell stack structure (GS) may have a step shape. The cell stack structure (GS) may be covered by a cover insulating film (430).

A plurality of channel structures (CHS) may extend vertically through the cell stack structure (GS) on the memory cell region (MEC). The configuration of the plurality of channel structures (CHS) may be substantially the same as or similar to the configuration of the plurality of channel structures (CHS) described with reference to FIG. 8a.

In an exemplary embodiment, the plurality of channel structures (CHS) may be arranged to extend into the interior of the cell substrate (410). In another embodiment, the plurality of channel structures (CHS) may be arranged to contact the lower surface of the cell substrate (410).

The plurality of channel structures (CHS) can be in contact with a plurality of bit line contacts (BLC) at the upper surface. The plurality of bit line contacts (BLC) can extend in the vertical direction through the first insulating film (440) and can be mutually insulated by the first insulating film (440). The plurality of bit line contacts (BLC) can be in contact with a plurality of bit lines (BL) at the upper surface. The plurality of bit lines (BL) can extend in the vertical direction through the second insulating film (450) and can be mutually insulated by the second insulating film (450). Each of the plurality of channel structures (CHS) can be connected to a corresponding one of the plurality of bit lines (BL) through the bit line contact (BLC).

A plurality of contact structures (CNT) may extend vertically through the cover insulating film (430) and the first insulating film (440) on the connection region (CON). The plurality of contact structures (CNT) may contact a plurality of wiring layers (ML) on the upper surface. The plurality of wiring layers (ML) may extend vertically through the second insulating film (450) and may be mutually insulated by the second insulating film (450).

FIG. 9 is a schematic diagram illustrating an electronic system (1000) including a semiconductor device according to an exemplary embodiment of the present invention.

Referring to FIG. 9, an electronic system (1000) according to an exemplary embodiment of the present invention may include a semiconductor device (1100) and a controller (1200) electrically connected to the semiconductor device (1100). The electronic system (1000) may be a storage device including one or more semiconductor devices (1100) or an electronic device including a storage device. For example, the electronic system (1000) may be a solid state drive device (SSD), a Universal Serial Bus (USB), a computing system, a medical device, or a communication device including at least one semiconductor device (1100).

The semiconductor device (1100) may be a nonvolatile memory device. For example, the semiconductor device (1100) may be a NAND flash memory device including at least one of the structures described above with respect to the semiconductor devices (100, 100a, 100b, 200, 200a, 200b, 300, 400) with reference to FIGS. 4 to 8B. The semiconductor device (1100) may include a first structure (1100F) and a second structure (1100S) on the first structure (1100F). In exemplary embodiments, the first structure (1100F) may be disposed next to the second structure (1100S). The first structure (1100F) may be a peripheral circuit structure including a decoder circuit (1110), a page buffer (1120), and a logic circuit (1130). The second structure (1100S) may be a memory cell structure including a bit line (BL), a common source line (CSL), a plurality of word lines (WL), first and second gate upper lines (UL1, UL2), first and second gate lower lines (LL1, LL2), and a plurality of memory cell strings (CSTR) between the bit line (BL) and the common source line (CSL).

In the second structure (1100S), each of the plurality of memory cell strings (CSTR) may include a lower transistor (LT1, LT2) adjacent to a common source line (CSL), an upper transistor (UT1, UT2) adjacent to a bit line (BL), and a plurality of memory cell transistors (MCT) disposed between the lower transistors (LT1, LT2) and the upper transistors (UT1, UT2). The number of the lower transistors (LT1, LT2) and the number of the upper transistors (UT1, UT2) may vary depending on the embodiments.

In exemplary embodiments, the upper transistors (UT1, UT2) may include string select transistors, and the lower transistors (LT1, LT2) may include ground select transistors. The plurality of gate lower lines (LL1, LL2) may be gate electrodes of the lower transistors (LT1, LT2), respectively. The word line (WL) may be a gate electrode of a memory cell transistor (MCT), and the gate upper lines (UL1, UL2) may be gate electrodes of the upper transistors (UT1, UT2).

A common source line (CSL), a plurality of gate lower lines (LL1, LL2), a plurality of word lines (WL), and a plurality of gate upper lines (UL1, UL2) may be electrically connected to a decoder circuit (1110) through a plurality of first connection wires (1115) extending from a first structure (1100F) to a second structure (1100S). A plurality of bit lines (BL) may be electrically connected to a page buffer (1120) through a plurality of second connection wires (1125) extending from a first structure (1100F) to a second structure (1100S).

In the first structure (1100F), the decoder circuit (1110) and the page buffer (1120) can perform a control operation for at least one of a plurality of memory cell transistors (MCTs). The decoder circuit (1110) and the page buffer (1120) can be controlled by the logic circuit (1130).

The semiconductor device (1100) can communicate with the controller (1200) through an input/output pad (1101) that is electrically connected to a logic circuit (1130). The input/output pad (1101) can be electrically connected to the logic circuit (1130) through an input/output connection wiring (1135) that extends from the first structure (1100F) to the second structure (1100S).

The controller (1200) may include a processor (1210), a NAND controller (1220), and a host interface (1230). According to embodiments, the electronic system (1000) may include a plurality of semiconductor devices (1100), in which case the controller (1200) may control the plurality of semiconductor devices (1100).

The processor (1210) can control the overall operation of the electronic system (1000) including the controller (1200). The processor (1210) can operate according to a predetermined firmware and can control the NAND controller (1220) to access the semiconductor device (1100). The NAND controller (1220) can include a NAND interface (1221) that processes communication with the semiconductor device (1100). Through the NAND interface (1221), a control command for controlling the semiconductor device (1100), data to be written to a plurality of memory cell transistors (MCTs) of the semiconductor device (1100), data to be read from a plurality of memory cell transistors (MCTs) of the semiconductor device (1100), etc. can be transmitted. The host interface (1230) can provide a communication function between the electronic system (1000) and an external host. When receiving a control command from an external host through the host interface (1230), the processor (1210) can control the semiconductor device (1100) in response to the control command.

FIG. 10 is a perspective view schematically illustrating an electronic system (2000) including a semiconductor device according to an exemplary embodiment of the present invention.

Referring to FIG. 10, an electronic system (2000) according to an exemplary embodiment of the present invention may include a main substrate (2001), a controller (2002) mounted on the main substrate (2001), one or more semiconductor packages (2003), and a DRAM (2004). The semiconductor packages (2003) and the DRAM (2004) may be interconnected with the controller (2002) by a plurality of wiring patterns (2005) formed on the main substrate (2001).

The main board (2001) may include a connector (2006) including a plurality of pins coupled with an external host. The number and arrangement of the plurality of pins in the connector (2006) may vary depending on a communication interface between the electronic system (2000) and the external host. In exemplary embodiments, the electronic system (2000) may communicate with the external host according to any one of interfaces such as Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI-Express), Serial Advanced Technology Attachment (SATA), and M-Phy for Universal Flash Storage (UFS). In exemplary embodiments, the electronic system (2000) may operate by power supplied from the external host through the connector (2006). The electronic system (2000) may further include a Power Management Integrated Circuit (PMIC) that distributes power supplied from the external host to the controller (2002) and the semiconductor package (2003).

The controller (2002) can write data to the semiconductor package (2003) or read data from the semiconductor package (2003), and can improve the operating speed of the electronic system (2000).

DRAM (2004) may be a buffer memory for mitigating the speed difference between the semiconductor package (2003), which is a data storage space, and an external host. DRAM (2004) included in the electronic system (2000) may also function as a type of cache memory, and may provide a space for temporarily storing data in a control operation for the semiconductor package (2003). When DRAM (2004) is included in the electronic system (2000), the controller (2002) may further include a DRAM controller for controlling DRAM (2004) in addition to a NAND controller for controlling the semiconductor package (2003).

A semiconductor package (2003) may include first and second semiconductor packages (2003a, 2003b) that are spaced apart from each other. The first and second semiconductor packages (2003a, 2003b) may each be a semiconductor package including a plurality of semiconductor chips (2200). Each of the first and second semiconductor packages (2003a, 2003b) may include a package substrate (2100), a plurality of semiconductor chips (2200) on the package substrate (2100), an adhesive layer (2300) disposed on a lower surface of each of the plurality of semiconductor chips (2200), a connection structure (2400) that electrically connects the plurality of semiconductor chips (2200) and the package substrate (2100), and a molding layer (2500) that covers the plurality of semiconductor chips (2200) and the connection structure (2400) on the package substrate (2100).

The package substrate (2100) may be a printed circuit board including a plurality of package upper pads (2130). The plurality of semiconductor chips (2200) may each include an input/output pad (2210). The input/output pad (2210) may correspond to the input/output pad (1101) of FIG. 9. Each of the plurality of semiconductor chips (2200) may include a plurality of gate stacks (3210) and a plurality of channel structures (3220). Each of the plurality of semiconductor chips (2200) may include at least one structure among the structures described above with respect to the semiconductor devices (100, 100a, 100b, 200, 200a, 200b, 300, 400) with reference to FIGS. 4 to 8B.

In exemplary embodiments, the connection structure (2400) may be a bonding wire that electrically connects the input/output pad (2210) and the package upper pad (2130). Accordingly, in the first and second semiconductor packages (2003a, 2003b), the plurality of semiconductor chips (2200) may be electrically connected to each other in a bonding wire manner, and may be electrically connected to the package upper pad (2130) of the package substrate (2100). In exemplary embodiments, in the first and second semiconductor packages (2003a, 2003b), the plurality of semiconductor chips (2200) may be electrically connected to each other by a connection structure including a through silicon via (TSV), instead of the bonding wire-type connection structure (2400).

In exemplary embodiments, the controller (2002) and the plurality of semiconductor chips (2200) may be included in one package. In exemplary embodiments, the controller (2002) and the plurality of semiconductor chips (2200) may be mounted on a separate interposer substrate different from the main substrate (2001), and the controller (2002) and the plurality of semiconductor chips (2200) may be connected to each other by wiring formed on the interposer substrate.

Fig. 11 is a cross-sectional view schematically illustrating semiconductor packages according to an exemplary embodiment of the present invention. Fig. 11 illustrates a configuration along the line II-II' of Fig. 10 in more detail.

Referring to FIG. 11, in a semiconductor package (2003), each of the semiconductor chips (2200b) may include a semiconductor substrate (4010), a first structure (4100) on the semiconductor substrate (4010), and a second structure (4200) bonded to the first structure (4100) in a wafer bonding manner on the first structure (4100).

The first structure (4100) may include a peripheral circuit region including peripheral wiring (4110) and first junction structures (4150). The second structure (4200) may include a common source line (4205), a gate stacked structure (4210) between the common source line (4205) and the first structure (4100), memory channel structures (4220) penetrating the gate stacked structure (4210), and second junction structures (4250) electrically connected to word lines (WL of FIG. 9) of the memory channel structures (4220) and the gate stacked structure (4210), respectively. For example, the second bonding structures (4250) may be electrically connected to the memory channel structures (4220) and the word lines (WL of FIG. 9), respectively, through bit lines (4240) that are electrically connected to the memory channel structures (4220) and gate connection wires that are electrically connected to the word lines (WL of FIG. 9). The first bonding structures (4150) of the first structure (4100) and the second bonding structures (4250) of the second structure (4200) may be bonded while making contact with each other. The bonded portions of the first bonding structures (4150) and the second bonding structures (4250) may be formed of, for example, copper (Cu).

Each of the semiconductor chips (2200b) may further include an input/output pad (2210 of FIG. 10) electrically connected to the peripheral wirings (4110) of the first structure (4100).

The semiconductor chips (2200) of FIG. 10 and the semiconductor chips (2200b) of FIG. 11 may be electrically connected to each other by connection structures (2400) in the form of bonding wires. However, in exemplary embodiments, semiconductor chips within one semiconductor package, such as the semiconductor chips (2200) of FIG. 10 and the semiconductor chips (2200b) of FIG. 11, may also be electrically connected to each other by connection structures including through-silicon vias (TSVs).

As described above, exemplary embodiments have been disclosed in the drawings and the specification. Although specific terms have been used in the specification to describe the embodiments, these have been used only for the purpose of explaining the technical idea of the present disclosure and have not been used to limit the meaning or the scope of the present disclosure set forth in the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Accordingly, the true technical protection scope of the present disclosure should be determined by the technical idea of the appended claims.

Claims (10)

peripheral circuit structures; and
A cell array structure vertically overlapping the peripheral circuit structure and including first to third memory cell blocks;
The above peripheral circuit structure is,
A substrate having an active region including a central active region extending in a first horizontal direction; and first to third extended active regions extending from the central active region in a second horizontal direction perpendicular to the first horizontal direction; and a device isolation film defining the active region; and
and comprising first to third gate structures spaced apart from each other, positioned above the active region;
The above central active region, the first to third extended active regions, and the first to third gate structures constitute first to third pass transistors, respectively.
The first to third pass transistors share one drain region in the central active region,
A semiconductor device characterized in that the active region has an upside-down h-shape. In the first paragraph,
Further comprising a drain contact on the drain region,
A semiconductor device wherein the drain contact is arranged in a diagonal direction with respect to the first to third gate structures on a plane parallel to the first horizontal direction and the second horizontal direction. In the first paragraph,
A semiconductor device, characterized in that the first to third gate structures have a rectangular or L shape. In the first paragraph,
A semiconductor device, wherein any one of the first to third pass transistors is configured to transmit an operating voltage to any one of the first to third memory cell blocks corresponding to any one of the first to third pass transistors based on a block select signal. In the first paragraph,
The active region includes a first active region, a second active region neighboring the first active region in the first horizontal direction, a third active region neighboring the first active region in the second horizontal direction, and a fourth active region neighboring the third active region in the first horizontal direction,
A semiconductor device characterized in that the first active region and the third active region have different shapes. In paragraph 5,
The first active region and the second active region have the same shape,
A semiconductor device characterized in that the third active region and the fourth active region have the same shape. In paragraph 5,
A semiconductor device characterized in that the first active region and the third active region are symmetrical with respect to the second active region and the fourth active region with respect to the central axis. In paragraph 5,
A portion of the first active area horizontally overlaps a portion of the third active area in the first horizontal direction,
A semiconductor device characterized in that a portion of the second active region horizontally overlaps a portion of the fourth active region in the first horizontal direction. In the first paragraph,
The above cell array structure further comprises a plurality of first bonding pads,
The above peripheral circuit structure further includes a plurality of second bonding pads,
A semiconductor device wherein the first bonding pad and the second bonding pad are bonded to each other. In the first paragraph,
The above cell array structure includes a cell stack structure and a cell substrate,
The above cell substrate is a semiconductor device interposed between the above cell stack structure and the above peripheral circuit structure.