KR20240022968A - Integrated circuit performing dynamic voltage and frequency scaling operation based on workload and operating method thereof - Google Patents

Abstract

An integrated circuit and a method of operating the integrated circuit are disclosed that classify the workload of a core based on monitored data and perform a DVFS operation based on the divided workload. As an aspect of the technical idea of the present disclosure, at least one core configured to process instructions according to voltage-frequency levels, receiving a request from the at least one core, accessing an external memory according to the request, and receiving a response from the external memory Receiving a shared buffer, a monitor that monitors the shared buffer to obtain the buffer capacity of the shared buffer and the response waiting time for the response received from the external memory, and receiving the buffer capacity and response waiting time from the monitor, buffer A Dynamic Voltage and Frequency Scaling (DVFS) controller that classifies the workload of at least one core based on capacity and response latency and determines a scaling factor for voltage-frequency levels based on the divided workload. Includes.

Description

Integrated circuit performing DVFS operation based on workload and operating method thereof {INTEGRATED CIRCUIT PERFORMING DYNAMIC VOLTAGE AND FREQUENCY SCALING OPERATION BASED ON WORKLOAD AND OPERATING METHOD THEREOF}

The technical idea of the present disclosure relates to an integrated circuit, and more specifically, to an integrated circuit that classifies the workload of a core based on monitored data and performs a DVFS operation based on the divided workload, and a method of operating the integrated circuit. will be.

As computing systems such as mobile devices become miniaturized, power management has emerged as an important issue. In particular, in portable devices such as mobile devices that use energy-limited batteries, power is lowered to reduce power consumption, but voltage must be increased to increase performance, so workload characteristics such as memory characteristics of the bus or dynamic random access memory (DRAM) must be adjusted. Accordingly, the need for efficient power management is increasing.

As an example, the application processor of a mobile device can manage power by adjusting the voltage through DVFS (Dynamic Voltage and Frequency Scaling) operation, which adjusts the frequency and voltage of the processing device according to the workload of the processing device built into the application processor. there is.

The problem that the technical idea of the present disclosure seeks to solve is to classify the workload by considering not only the status of the CPU (central processing unit), but also the characteristics of the bus or DRAM memory, and based on the divided workload, a scaling factor ( Provides an integrated circuit, an operation method of the integrated circuit, and a computing system that can effectively perform DVFS operations by determining different scaling factors.

To achieve the above object, an integrated circuit according to an exemplary embodiment of the present disclosure receives a request from at least one core, at least one core configured to process an instruction according to a voltage-frequency level, and responds to the request. A shared buffer that accesses external memory and receives a response from the external memory, and a monitor that monitors the shared buffer to obtain the buffer capacity of the shared buffer and the response waiting time for the response received from the external memory. Receive buffer capacity and response latency from the server, distinguish the workload of at least one core based on the buffer capacity and response latency, and set a scaling factor for the voltage-frequency level based on the divided workload. It includes a DVFS (Dynamic Voltage and Frequency Scaling) controller that determines.

A method of operating an integrated circuit according to an exemplary embodiment of the present disclosure includes monitoring a shared buffer, obtaining a buffer capacity of the shared buffer and a response waiting time for a response that the shared buffer receives from an external memory, buffer capacity, and It includes dividing the workload of the core based on the response latency and determining a scaling factor for the voltage-frequency level of the core based on the workload of the divided core.

A computing system according to an exemplary embodiment of the present disclosure includes a processor, at least one memory, a bus connecting the processor and the at least one memory, a buffer capacity of a shared buffer, and a response latency for a response received from the bus. A DVFS controller that separates the workload of at least one core, determines a scaling factor based on the divided workload, and generates a voltage control signal and a frequency control signal based on the determined scaling factor, in response to the voltage control signal. A power management unit that adjusts the size of a power supply voltage provided to at least one core, and a clock management unit that adjusts the frequency of a clock signal provided to the at least one core in response to a frequency control signal, wherein the processor, At least one core configured to process instructions according to the size and frequency of the clock signal, receiving a request from the at least one core, accessing a bus according to the request, and receiving a response from the bus, a shared buffer, and monitoring the shared buffer. Includes monitors to obtain buffer capacity and response latency.

According to an exemplary embodiment of the present disclosure, the workload is divided considering characteristics of the bus or DRAM memory as well as the state of the CPU, and different scaling factors are determined based on the divided workload to efficiently perform DVFS. Operation can be performed and power consumption can be reduced.

Additionally, since the time waiting for data in the shared buffer can be monitored and workloads can be divided based on this, overhead can be reduced compared to classifying workloads through software.

The effects that can be obtained from the technical idea of the present disclosure are not limited to the effects mentioned above, and other effects not mentioned are clear to those skilled in the art from the following description. It can be derived and understood. In other words, unintended effects resulting from implementing the technical idea of the present disclosure may also be derived from the technical idea of the present disclosure by a person skilled in the art.

1 is a block diagram illustrating an integrated circuit according to an exemplary embodiment of the present disclosure.
Figure 2 is a block diagram illustrating data monitored by a shared buffer and a monitor according to an exemplary embodiment of the present disclosure.
3A and 3B are graphs for explaining buffer capacity and response waiting time according to an exemplary embodiment of the present disclosure.
Figure 4 is a block diagram showing an implementation of an integrated circuit according to an exemplary embodiment of the present disclosure.
Figure 5 is a block diagram illustrating an example implementation of an integrated circuit according to an exemplary embodiment of the present disclosure.
6A and 6B are graphs and tables for explaining how a DVFS controller determines a scaling factor according to an exemplary embodiment of the present disclosure.
Figure 7 is a block diagram showing an implementation of an integrated circuit according to an exemplary embodiment of the present disclosure.
Figure 8 is a flowchart showing a method of operating an integrated circuit according to an exemplary embodiment of the present disclosure.
Figure 9 is a flowchart illustrating an example implementation of a method of operating an integrated circuit according to an exemplary embodiment of the present disclosure.
Figure 10 is a flowchart illustrating an example implementation of a method of operating an integrated circuit according to an exemplary embodiment of the present disclosure.
Figure 11 is a block diagram showing a system according to an exemplary embodiment of the present disclosure.
Figure 12 is a block diagram showing a communication device including an application processor according to an example embodiment of the present disclosure.

1 is a block diagram illustrating an integrated circuit according to an exemplary embodiment of the present disclosure.

Referring to FIG. 1, the integrated circuit 10 includes a processor 100, a DVFS controller 200, a clock management unit (CMU) 300, a power management unit (PMU) 400, and a bus. It may include 500 and memory 600. In some embodiments, processor 100, DVFS controller 200, clock manager 300, power manager 400, bus 500, and memory 600 are integrated into one chip, i.e., system-on-chip ( It may be included in a system-on-chip (SoC), and the integrated circuit 10 may be referred to as an application processor (AP).

The integrated circuit 10 may be included in a stationary computing system such as a desktop PC, server, etc., and may also be included in a laptop computer, mobile phone, smartphone, tablet PC, personal digital assistant (PDA), enterprise digital assistant (EDA), or digital still camera ( digital still camera, digital video camera, portable multimedia player (PMP), personal navigation device or portable navigation device (PND), handheld game console, mobile internet device (MID) ), wearable computers, internet of things (IoT) devices, internet of everything (IoE) devices, or e-books.

The processor 100 may include at least one core 110, a shared buffer 120, and a monitor 130. In some embodiments, processor 100 may execute a program comprised of instructions. A program may include a plurality of subprograms, and a subprogram may be referred to as a subroutine, routine, procedure, function, etc.

Core 110 can independently process instructions. Hereinafter, core 110 will be described primarily with reference to a CPU core, but it is noted that exemplary embodiments of the present disclosure are not limited thereto. For example, the core 110 may be a CPU core, a graphics processing unit (GPU) core, a neural processing unit (NPU) core, or an image signal processor (ISP) core. Since the processor 100 may include a plurality of cores 110, the processor 100 may be referred to as a multi-core processor. In some embodiments, the core 110 may process instructions depending on the clock signal (clk) and the power supply voltage (vdd), and the performance of the core 110 may depend on the clock signal (clk) and the power supply voltage (vdd). You can depend on it. Some embodiments of this will be described later with reference to FIGS. 6A and 6B.

The shared buffer 120 may be a buffer shared by a plurality of cores 110 in a multi-core processor. For example, the processor 100 may be a CPU, the plurality of cores 110 may include an L2 cache, and the shared buffer 120 may be an L3 cache. The shared buffer 120 can store data not included in the core 110, and can transmit and receive data to and from the core 110. In some embodiments, data for the core 110 to process a command may not be inside the core 110, and data may be requested from the shared buffer 120. The shared buffer 120 receives a request (Req) from the core 110, and when data corresponding to the request (Req) exists inside the shared buffer 120, the data can be transmitted to the core 110. . If the data corresponding to the request (Req) does not exist inside the shared buffer 120 (for example, a cache miss occurs), external memory can be accessed (Acc), and a response from the external memory ( Res) can be received to obtain data corresponding to the request (Req). For example, the shared buffer 120 can access (Acc) the memory 600 through the bus 500 and receive a response (Res) from the memory 600 through the bus 500. The shared buffer 120 may include a plurality of blocks 121, and some embodiments thereof will be described later with reference to FIG. 2.

The monitor 130 can monitor the shared buffer 120 and obtain the buffer capacity of the shared buffer 120 and the response waiting time for a response received from an external memory. In some embodiments, the buffer capacity of the shared buffer 120 may indicate that the capacity of the plurality of blocks 121 is full, and the response waiting time for a response received from an external memory may indicate that the shared buffer 120 is busy on the bus. This may be the time taken to receive a response (Res) from the memory 600 after accessing (Acc) the memory 600 through (500). Some embodiments of this will be described later with reference to FIGS. 3A and 3B.

In some embodiments, the monitor 130 may monitor the core 110 and obtain the time taken for the core 110 to receive data corresponding to the request (Req) from the shared buffer 120. You can. For example, core 110 may be a CPU core and may include an L2 cache. Shared buffer 120 may be an L3 cache. The data for the CPU core to process instructions may not be in the L2 cache, and it can be requested (Req) from the L3 cache. The L3 cache receives a request (Req) from the L2 cache, and if data corresponding to the request (Req) exists inside the L3 cache, the data can be transmitted to the L2 cache. If the data corresponding to the request (Req) does not exist inside the L3 cache, the L3 cache can access external memory (Acc), receive a response (Re) from the external memory, and retrieve the data corresponding to the request (Req). can be obtained. The L3 cache can transmit data obtained from external memory to the L2 cache. The monitor 130 can monitor the L2 cache, request data from the L3 cache (Req), and obtain the time taken to receive data corresponding to the request (Req) from the L3 cache.

The DVFS controller 200 may receive the buffer capacity of the shared buffer 120 and the response waiting time for the response received from the external memory from the monitor 130, and the core 110 based on the buffer capacity and response waiting time. The workload can be distinguished. In some embodiments, the DVFS controller 200 may divide the workload of the core 110 into a first workload or a second workload, with the first workload requesting access to external memory more than the second workload. It can include more. For example, the first workload may be a memory intensive workload, and the memory intensive workload may be transferred to the bus 500 or the memory 600 when a cache miss occurs during operation of the processor 100. It may mean a situation in which a collision occurs. The second workload may be a computing workload, and the computing workload is related to instruction processing of the core 110, and may mean a situation in which a cache miss does not occur during the operation of the processor 100. .

In some embodiments, if the buffer capacity and response latency are greater than or equal to a threshold, the DVFS controller 200 may classify the workload of the core 110 as a first workload. If the buffer capacity or response latency is less than the threshold, the DVFS controller 200 may classify the workload of the core 110 as a second workload. Some embodiments of this will be described later with reference to FIGS. 2 to 4.

In some embodiments, the DVFS controller 200 may receive from the monitor 130 the time taken for the core 110 to receive data corresponding to the request (Req) from the shared buffer 120, and receive Based on one hour, the workload of the core 110 can be divided into a first workload or a second workload. The first workload may include more requests to access external memory than the second workload. For example, core 110 may be a CPU core and may include an L2 cache. Shared buffer 120 may be an L3 cache. If there is free space in the L3 cache capacity, the L3 cache can receive a request (Req) from the L2 cache, access the external memory (Acc), and respond to the request (Req) by receiving a response (Re) from the external memory. One data can be obtained. At this time, the time taken for the L2 cache to receive data corresponding to the request (Req) from the L3 cache may be shorter than the threshold time, and the DVFS controller 200 transfers the workload of the core 110 to the second workload. can be distinguished. If there is no free space in the L3 cache capacity (for example, if the capacity of the L3 cache is filled with data other than the data corresponding to the request (Req)), the L3 cache cannot receive the request (Req) from the L2 cache. There is none, and a request (Req) can be received after performing an operation on the filled data. Afterwards, data corresponding to the request (Req) can be obtained by accessing the external memory (Acc) and receiving a response (Res) from the external memory. At this time, the time taken for the L2 cache to receive data corresponding to the request (Req) from the L3 cache may be longer than the threshold time, and the DVFS controller 200 divides the workload of the core 110 into the first workload. can be distinguished.

The DVFS controller 200 may determine a scaling factor for the voltage-frequency level based on the workload of the divided cores 110. In some embodiments, a scaling factor may be determined such that the voltage-frequency level is reduced depending on the workload of the divided cores 110. For example, the DVFS controller 200 may divide the workload of the core 110 into a first workload or a second workload, and the first workload may make more requests to access external memory than the second workload. It can include a lot. The core 110 with the first workload may have lower required performance than the core 110 with the second workload. The performance of the core 110 may be dependent on the voltage-frequency level, and the DVFS controller 200 determines a scaling factor so that the voltage-frequency level is reduced when the workload of the core 110 is divided into the first workload. You can. Some embodiments of this will be described later with reference to FIGS. 6A and 6B.

The DVFS controller 200 may generate a control signal based on the determined scaling factor. In some embodiments, the DVFS controller 200 may generate a clock control signal (C_clk) to adjust the frequency of the core 110 and transmit the clock control signal (C_clk) to the clock manager 300. there is. In some embodiments, the DVFS controller 200 may generate a voltage control signal (C_vdd) to adjust the power supply voltage (vdd) of the core 110, and may send the voltage control signal (C_vdd) to the power management unit 400. It can be sent to .

Since the DVFS controller 200 classifies the workload of the core 110 based on the buffer capacity and response latency obtained by the monitor 130 by monitoring the shared buffer 120, the bus 500 or memory 600 Depending on the characteristics of , the scaling factor for the voltage-frequency level can be determined differently. Accordingly, power consumption can be reduced more efficiently than in the case of not dividing workloads, and overhead can be reduced because additional calculations are not required compared to the case of dividing workloads using software. The DVFS controller 200 is described as being located outside the processor 100, but may be located inside the processor 100.

The clock manager 300 may generate a clock signal clk and adjust the frequency of the clock signal clk based on the clock control signal C_clk. For example, the clock manager 300 may include an oscillator that generates a clock signal (clk) based on the clock control signal (C_clk). The clock management unit 300 may also be referred to as a clock generator or clock generation circuit.

The power management unit 400 may generate the power supply voltage (vdd) and adjust the size of the power supply voltage (vdd) based on the voltage control signal (C_vdd). For example, the power management unit 400 may include a switching regulator that generates the power supply voltage (vdd) from a voltage provided from an external power source based on the voltage control signal (C_vdd). The power management unit 400 may also be referred to as a power management integrated circuit (PMIC).

The bus 500 may be a system bus to which a protocol having a predetermined standard bus standard is applied, and may include various IPs (Intellectual Properties) connected to the system bus. As a standard standard for the system bus, the Advanced Microcontroller Bus Architecture (AMBA) protocol of ARM (Advanced RISC Machine) can be applied. Bus types of the AMBA protocol may include Advanced High-Performance Bus (AHB), Advanced Peripheral Bus (APB), Advanced eXtensible Interface (AXI), AXI4, and AXI Coherency Extensions (ACE). In addition, other types of protocols, such as Sonics Inc.'s uNetwork, IBM's CoreConnect, or OCP-IP's Open Core Protocol, may be applied. The bus 500 is described as being included in the integrated circuit 10, but may be located outside the integrated circuit 10.

The memory 600 may correspond to various types of semiconductor memory devices, and according to one embodiment, DDR SDRAM (Double Data Rate Synchronous Dynamic Ramdom Access Memory), LPDDR (Low Power Double Data Rate) SDRAM, GDDR (Graphics Double Data) Rate) It may be dynamic random access memory (Dynamic Ramdom Access Memory, DRAM) such as SDRAM, RDRAM (Rambus Dynamic Ramdom Access Memory), etc. Additionally, the memory 600 may further be any one of flash memory, phase-change RAM (PRAM), magnetoresistive RAM (MRAM), resistive RAM (ReRAM), and ferroelectric RAM (FeRAM). The memory 600 is described as being included in the integrated circuit 10, but may be located outside the integrated circuit 10 and may be referred to as external memory.

Integrated circuit 10 may include components other than those shown in FIG. 1 . For example, the integrated circuit 10 includes various types of functional blocks such as an IO interface block (input/output interface block), a USB host block (universal serial bus host block), and a USB slave block (universal serial bus slave block). It can be included.

Figure 2 is a block diagram illustrating data monitored by a shared buffer and a monitor according to an exemplary embodiment of the present disclosure.

Referring to FIGS. 1 and 2 , the shared buffer 120 of FIG. 2 may be the same as the shared buffer 120 of FIG. 1 and may include a plurality of blocks 121 . Descriptions that overlap with the content of FIG. 1 will be omitted. In some embodiments, at least one block 121 constitutes one set, and the shared buffer 120 may include a plurality of sets. The total capacity of the shared buffer 120 may be determined based on the plurality of sets. For example, the size of the block 121 may be B (B is an integer greater than 0) bytes, and one set may include more than N (N is an integer greater than 1) blocks 121, and the shared buffer (120) may include M (M is an integer of 1 or more) sets. At this time, the total capacity of the shared buffer 120 may be determined as B*N*M bytes.

In some embodiments, when the full capacity of the shared buffer 120 is greater than or equal to a threshold, the DVFS controller 200 may classify the workload of the core 110 as the first workload. For example, if more than 70% of the total capacity of B*N*M bytes of the shared buffer 120 is filled, the DVFS controller 200 may classify the workload of the core 110 as the first workload.

In some embodiments, each core 110 may transmit a request (Req) only to a specific block among the plurality of blocks 121. For example, the request (Req) may include data specifying the location of a specific block among the plurality of blocks 121.

In some embodiments, the memory 600 may be divided into a plurality of regions (not shown), and each block 121 may access (Acc) only a specific region among the plurality of regions of the memory 600. You can. For example, the request (Req) received by the shared buffer 120 from the core 110 may include an address, and the address is data specifying the location of a specific area of the memory 600. may include.

3A and 3B are graphs for explaining buffer capacity and response waiting time according to an exemplary embodiment of the present disclosure.

Referring to FIGS. 1 and 3A , the graph in FIG. 3A may represent the capacity of the block 121 over time. In some embodiments, when the degree to which the capacity of the block 121 is filled is greater than or equal to the critical capacity, the buffer capacity of the shared buffer 120 may be referred to as being full. . For example, if the number of blocks 121 whose capacity is filled to 70% (Th1) or more among the plurality of blocks 121 is more than 50% (threshold number) of the total number of blocks 121, the shared buffer 120 )'s buffer capacity may be full. The sections with full buffer capacity may be section C1 and section C2.

Referring further to FIG. 3B, the graph of FIG. 3B may represent the response waiting time of the shared buffer 120 for a response received from an external memory. In some embodiments, the response waiting time for a response received from an external memory is a response (Re) from memory 600 after the shared buffer 120 accesses (Acc) the memory 600 through the bus 500. It may be the time taken to receive (hereinafter referred to as response waiting time). When the shared buffer 120 accesses (Acc) the memory 600 through the bus 500, a signal may transition from a first level (e.g., logic low) to a second level (e.g., logic high). there is. When the shared buffer 120 receives a response Res from the memory 600 through the bus 500, the signal may transition from the second level to the first level. After the signal transitions from the first level to the second level, the time taken from the second level to the first level (for example, time a1, time a2, time a3, or time b1) is the waiting time for a response. It could be time.

In some embodiments, the DVFS controller 200 indicates that the buffer capacity of the shared buffer 120 is full, and when the response waiting time is longer than the threshold time (Th2), the DVFS controller 200 transfers the workload of the core 110 to the first workload. It can be divided into a first workload or a second workload. The first workload may include more requests to access external memory than the second workload. For example, the state in which the buffer capacity of the shared buffer 120 is full may be section C1 and section C2. If the response waiting time is longer than the threshold time (Th2), it may be time a1, time a2, and time a3. At time T1, the buffer capacity of the shared buffer 120 may be in a full state, and the response waiting time may be longer than the threshold time (Th2). At time T2, the response waiting time is longer than the threshold time (Th2), but the buffer capacity of the shared buffer 120 may not be full. Therefore, there may be a situation in which a collision occurs in the bus 500 or the memory 600 in the section from time T1 to time T2, and the DVFS controller 200 may divide the workload of the core 110 into the first workload. You can.

In some embodiments, monitor 130 may monitor the shared buffer 120 and obtain an identifier (source ID). The identifier (source ID) may refer to the address of the core 110 sending a request (Req) to the shared buffer 120, and the DVFS controller 200 may receive the identifier (source ID) from the monitor 130. You can. In the section from time T1 to time T2, the DVFS controller 200 may identify a specific core among the plurality of cores 110 according to an identifier (source ID) and distinguish the workload of the identified core as the first workload. there is.

Figure 4 is a block diagram showing an implementation of an integrated circuit according to an exemplary embodiment of the present disclosure.

Referring to FIGS. 1 and 4 , the integrated circuit 10a may include a processor 100, a DVFS controller 200, and a temperature sensor 800. In some embodiments, the processor 100 and DVFS controller 200 of FIG. 4 may be the same as the processor 100 and DVFS controller 200 of FIG. 1 . Descriptions that overlap with those of FIG. 1 will be omitted.

The temperature sensor 800 may detect the temperature of the processor 100 and provide temperature information according to the detection result to the DVFS controller 200. The temperature sensor 800 may include a thermistor and a memory (not shown) capable of storing temperature information. In some embodiments, temperature sensor 800 may sense the temperature of cores 110. Temperature information according to the detection result can be provided to the DVFS controller 200 and stored in memory.

Referring further to FIGS. 3A and 3B, in some embodiments, the DVFS controller 200 controls the temperature when the buffer capacity of the shared buffer 120 is not full or the response waiting time is less than or equal to the threshold time (Th2). Based on the information, the workload of the core 110 may be divided into a first workload or a second workload. The first workload may include more requests to access external memory than the second workload. For example, sections other than section C1 and section C2 may not have full buffer capacity. In section C1, the buffer capacity is full, but the response waiting time (eg, time b1) may not exceed the threshold time (Th2). In section C3, the buffer capacity is full, but the response waiting time may not exceed the threshold time (Th2). Therefore, in the section before time T1 or after time T2, the buffer capacity of the shared buffer 120 may not be full or the response waiting time may be less than the threshold time (Th2). In the section before time T1 or after time T2, if the temperature information detected by the temperature sensor 800 is above the critical temperature, the core 110 may operate excessively for command processing, and the processor 100 may operate excessively. There may be a situation where a cache miss does not occur during operation. Accordingly, the DVFS controller 200 may divide the workload of the core 110 into a second workload.

In some embodiments, monitor 130 may monitor the shared buffer 120 and obtain an identifier (source ID). The identifier (source ID) may refer to the address of the core 110 sending a request (Req) to the shared buffer 120, and the DVFS controller 200 may receive the identifier (source ID) from the monitor 130. You can. In the section before time T1 or after time T2, the DVFS controller 200 identifies a specific core among the plurality of cores 110 according to an identifier (source ID) and divides the workload of the identified core into a second workload. You can.

Figure 5 is a block diagram illustrating an example implementation of an integrated circuit according to an exemplary embodiment of the present disclosure.

Referring to FIGS. 1 and 5 , the integrated circuit 10b may include a DVFS controller 200a, a clock management unit 300, a power management unit 400, and a memory 700. In some embodiments, the clock management unit 300 and power management unit 400 of FIG. 5 may be the same as the clock management unit 300 and power management unit 400 of FIG. 1 . Descriptions that overlap with the content of FIG. 1 will be omitted.

The DVFS controller 200a may include workload classification logic 210, a DVFS governor module 220, a clock management driver 230, and a power management driver 240. The workload classification logic 210 includes the address (hereinafter referred to as an identifier) of the core 110 that transmits a request (Req) from the monitor 130 to the shared buffer 120, the buffer capacity of the shared buffer 120, and The response waiting time for a response received from an external memory can be received. The workload classification logic 210 may identify a specific core among the plurality of cores 110 according to an identifier and classify the workload of the specific core based on buffer capacity and response latency. Separated workload data of a specific core can be transmitted to the DVFS manager module 220. For example, the workload classification logic 210 may classify the workload of the core 110 into a first workload or a second workload based on buffer capacity and response latency, and the first workload is the second workload. It may contain more requests accessing external memory than the workload. The workload classification logic 210 may classify the workload of a specific core as the first workload when the buffer capacity is full and the response waiting time is longer than the threshold time, and the specific core is classified as the first workload. Data may be transmitted to the DVFS manager module 220.

The DVFS manager module 220 may determine a scaling factor for the voltage-frequency level based on the separated workload data of a specific core. In some embodiments, when the DVFS manager module 220 receives data indicating that a specific core is classified as the first workload, the power supply voltage (vdd) and clock signal corresponding to the first workload from the memory 700 ( A DVFS table 710 containing frequencies of clk) can be obtained. The DVFS manager module 220 may determine a scaling factor for the voltage-frequency level based on the power supply voltage (vdd) and clock signal (clk) corresponding to the first workload. Hereinafter, module may refer to hardware that can perform functions and operations according to each name, or computer program code that can perform specific functions and operations. However, it is not limited to this and may refer to an electronic recording medium loaded with computer program code that can perform specific functions and operations, such as a processor. In other words, a module may mean a functional and/or structural combination of software to carry out the technical idea of the present invention.

The clock manager driver 230 may generate a clock control signal (C_clk) based on the scaling factor determined by the DVFS manager module 220 and provide the clock control signal (C_clk) to the clock manager 300.

The power management unit driver 240 may generate a power supply voltage control signal (C_vdd) based on the scaling factor determined by the DVFS manager module 220 and provide the power supply voltage control signal (C_vdd) to the power management unit 400.

Memory 700 may include a DVFS table 710. In some embodiments, the DVFS table 710 may include the power supply voltage (vdd) and the frequency of the clock signal (clk) corresponding to each workload. The DVFS table 710 may include values hard coded in the memory 700, and may include soft coded values that can be modified. Modification of the DVFS table 710 may be performed by the DVFS manager module 220. Although one DVFS table 710 is shown in FIG. 5, there may be multiple DVFS tables 710. For example, a plurality of DVFS tables 710 may be created depending on buffer capacity, response waiting time, and workload.

6A and 6B are graphs and tables for explaining how a DVFS controller determines a scaling factor according to an exemplary embodiment of the present disclosure.

Referring to FIGS. 1 and 6A , the graph in FIG. 6A may show the relationship between performance and power consumption of the core 110. Power consumption (P) can satisfy the following [Equation 1].

V may mean the power supply voltage, and f may mean the frequency of the core 110. Power consumption (P) is proportional to the square of the power supply voltage (V) and may be proportional to the frequency (f) of the core 110, so the higher the power supply voltage (V) or the frequency (f) of the core 110, the higher the power consumption. Power (P) can be increased. Performance of core 110 may be dependent on voltage-frequency level. For example, as the size of the power supply voltage (V) increases and the frequency (f) of the core 110 increases, the core 110 can operate faster and the performance of the core 110 can improve. Accordingly, the power consumption (P) and the performance of the core 110 may have a proportional relationship.

Referring further to FIGS. 5 and 6B, the workload classification logic 210 may classify the workload of the core 110 into a first workload or a second workload, and the DVFS manager module 220 may classify the workload of the core 110 into a first workload or a second workload. Based on the workload of (110), the scaling factor for the voltage-frequency level can be determined. The table in FIG. 6B may be the DVFS table 710 in FIG. 5. In some embodiments, when the DVFS manager module 220 receives data W1 indicating that the workload of the core 110 is classified as the first workload, the DVFS manager module 220 generates a power supply voltage v1 and a clock signal from the memory 700. The DVFS table 710 including the frequency (f1) of can be obtained. The DVFS manager module 220 may determine a scaling factor for the voltage-frequency level based on the power supply voltage (v1) and the frequency (f1) of the clock signal. For example, the first workload may be a memory-intensive workload, and the memory-intensive workload is a situation in which a conflict occurs in the bus 500 or the memory 600 when a cache miss occurs during operation of the processor 100. It can mean. If a conflict occurs in the bus 500 or memory 600, the conflict can be resolved by adjusting the number of requests (Req) by lowering the performance of the core 110, and the performance of the core 110 is proportional to the power consumed. Since there is one relationship, power consumption can be reduced. Accordingly, the DVFS manager module 220 may determine a scaling factor to reduce the voltage-frequency level based on the power supply voltage (v1) and the frequency (f1) of the clock signal.

In some embodiments, further referring to FIG. 4, when the temperature information detected by the temperature sensor 800 is above the threshold temperature, the DVFS manager module 220 divides the workload of the core 110 into a second workload. Data (W2) indicating that the data has been received can be received, and the DVFS table 710 including the power supply voltage (v2) and the frequency (f2) of the clock signal can be obtained from the memory 700. For example, the second workload may be a computing workload, and the computing workload may be related to instruction processing of the core 110, and may mean a situation in which a cache miss does not occur during operation of the processor 100. . In a situation where a cache miss does not occur, the number of requests (Req) may not be adjusted by lowering the performance of the core 110, unlike in the case where the workload is classified as the first workload. However, if the temperature of the core 110 is above the critical temperature, increasing the performance of the core 110 may cause malfunction due to heat generation of the core 110, so lower the performance of the core 110 to lower the temperature of the core 110. It can be lowered. Accordingly, the DVFS manager module 220 may determine a scaling factor to reduce the voltage-frequency level based on the power supply voltage (v2) and the frequency (f2) of the clock signal.

The DVFS table 710 may include power voltage and clock signal frequency according to data other than the illustrated data (W1 or W2). For example, if the temperature information detected by the temperature sensor 800 is below the critical temperature, the DVFS manager module 220 may receive data (not shown) indicating that the workload of the core 110 has been classified as a second workload. The DVFS table 710 including the power supply voltage (not shown) and the frequency of the clock signal (not shown) can be obtained from the memory 700. The second workload may be a computing workload, and the core 110 may require high performance for instruction processing. Since the temperature of the core 110 is below the critical temperature, malfunction due to heat generation may not be caused even if the performance of the core 110 is increased. Accordingly, the DVFS manager module 220 may determine a scaling factor to increase the voltage-frequency level based on the power supply voltage (not shown) and the frequency of the clock signal (not shown).

Since the power consumption (P) and the performance of the core 110 may have a proportional relationship, the DVFS manager module 220 can determine the scaling factor differently depending on the workload of the core 110 and efficiently consume power. Management and performance management of the core 110 can be performed.

Figure 7 is a block diagram showing an implementation example of an integrated circuit according to an exemplary embodiment of the present disclosure.

Referring to FIGS. 1 and 7 , the integrated circuit 10c may include at least one processor 100 and a DVFS controller 200b. In some embodiments, processor 100 of FIG. 7 may be the same as processor 100 of FIG. 1 . Descriptions that overlap with the content of FIG. 1 will be omitted.

The DVFS controller 200b may include at least one processor 280, memory 250, artificial intelligence (AI) accelerator 260, and hardware accelerator 270. At least one processor 280 may execute instructions. For example, at least one processor 280 may execute an operating system or applications running on the operating system by executing instructions stored in the memory 250. In some embodiments, at least one processor 280 may direct tasks to AI accelerator 260 and/or hardware accelerator 270 by executing instructions, and AI accelerator 260 and/or hardware accelerator 270 may execute instructions. The task performance result can also be obtained from (270). In some embodiments, at least one processor 280 may be an Application Specific Instruction Set Processor (ASIP) customized for a specific purpose and may support a dedicated instruction set.

Memory 250 may have any structure for storing data. For example, the memory 250 may include volatile memory devices such as Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), and non-volatile memory devices such as flash memory and Resistive Random Access Memory (RRAM). It may also include a memory device.

AI accelerator 260 may refer to hardware designed for AI applications. In some embodiments, the AI accelerator 260 may include a neural processing unit (NPU) for implementing a neuromorphic structure, and may include at least one processor 280 and/or a hardware accelerator 270. Output data may be generated by processing input data provided from and the output data may be provided to at least one processor 280 and/or hardware accelerator 270. In some embodiments, AI accelerator 260 may be programmable and may be programmed by at least one processor 280 and/or hardware accelerator 270.

Hardware accelerator 270 may refer to hardware designed to perform a specific task at high speed. For example, the hardware accelerator 270 may be designed to perform data conversion such as demodulation, modulation, encoding, decoding, etc. at high speed. Hardware accelerator 270 may be programmable and may be programmed by at least one processor 280 and/or hardware accelerator 270.

In some embodiments, AI accelerator 260 may execute an artificial neural network model. For example, with further reference to Figure 1, memory 250 may store training data. The learning data may include buffer capacity and response latency obtained by the monitor 130 by monitoring the shared buffer 120, and includes a scaling factor determined by the DVFS controller 200 based on the buffer capacity and response latency. can do. The AI accelerator 260 can execute an artificial neural network model, and the processor 280 can train the artificial neural network model using training data. After the artificial neural network model is trained, the processor 280 may receive the buffer capacity and response waiting time from the monitor 130. If the received buffer capacity and response latency correspond to the buffer capacity and response latency stored in the memory 250, a scaling factor corresponding to the buffer capacity and response latency can be determined using the learned artificial neural network model. After the artificial neural network model is learned, the DVFS controller 200 can determine the scaling factor without distinguishing the workload of the core 110, thereby quickly generating a clock control signal and a voltage control signal.

In some embodiments, the training data may include an address, and the processor 280 may train an artificial neural network model using the training data including the address. For example, the request (Req) received by the shared buffer 120 from the core 110 may include an address, and the address is data specifying the location of a specific area of the memory 600. may include. After the artificial neural network model is completed training, the processor 280 may receive an address from the monitor 130 and determine a scaling factor corresponding to the address. Learning data may further include data other than the above-described data.

Figure 8 is a flowchart showing a method of operating an integrated circuit according to an exemplary embodiment of the present disclosure. As shown in FIG. 8, the method 900 of operating an integrated circuit may include a plurality of steps S110 to S150.

Referring to Figures 1 and 8, in step S110, the shared buffer 120 is monitored and the buffer capacity of the shared buffer 120 and the response waiting time for the response that the shared buffer 120 receives from the external memory are obtained. You can. In an exemplary embodiment, the buffer capacity of the shared buffer 120 may indicate that the capacity of the plurality of blocks 121 is full, and the response waiting time for a response received from an external memory may indicate that the shared buffer 120 is on the bus. This may be the time taken to receive a response (Res) from the memory 600 after accessing (Acc) the memory 600 through (500).

In step S130, the workload of the core 110 can be distinguished based on buffer capacity and response waiting time. In an exemplary embodiment, if the buffer capacity and response latency are greater than or equal to a threshold, the DVFS controller 200 may classify the workload of the core 110 as a first workload. If the buffer capacity or response latency is below the threshold, the DVFS controller 200 may classify the workload of the core 110 as a second workload.

A scaling factor for the voltage-frequency level of the core 110 may be determined based on the workload of the core 110 classified in step S150. In an exemplary embodiment, when the workload of the core 110 is divided into the first workload, a scaling factor may be determined so that the voltage-frequency level is reduced. When the workload of the core 110 is divided into a second workload, a scaling factor may be determined to increase the voltage-frequency level.

Figure 9 is a flowchart illustrating an example implementation of a method of operating an integrated circuit according to an exemplary embodiment of the present disclosure. Step S130 of FIG. 8 may include an implementation example of the method of operating the integrated circuit of FIG. 9. An implementation example (S130) of a method of operating an integrated circuit may include a plurality of steps (S131 to S135).

Referring to FIGS. 1 and 9 , an implementation example (S130) of a method of operating an integrated circuit may indicate that the DVFS controller 200 operates in three modes. In step S131, it can be determined whether the buffer capacity is full and whether the response waiting time is longer than the threshold time (th2). If the buffer capacity is full and the response waiting time is longer than the threshold time (th2), the DVFS controller 200 may operate in memory intensive workload mode in step S132. For example, in the memory intensive workload mode, the DVFS controller 200 may divide the workload of the core 110 into a memory intensive workload and determine a scaling factor so that the voltage-frequency level is reduced.

If the buffer capacity is not full or the response waiting time is shorter than the threshold time (Th2), the DVFS controller 200 receives temperature information (T) of the core 110 from the temperature sensor in FIG. 4 in step S133. You can. If the temperature information (T) of the core 110 is higher than the threshold temperature (th3), the DVFS controller 200 may operate in computing workload mode in step S134. For example, in the computing workload mode, the DVFS controller 200 may divide the workload of the core 110 into computing workloads and determine a scaling factor so that the voltage-frequency level is reduced. If the temperature information (T) of the core 110 is not higher than the critical temperature (th3), the DVFS controller 200 may operate in normal workload mode in step S135. For example, in normal workload mode, the DVFS controller 200 may divide the workload of the core 110 into a normal workload and determine a scaling factor to increase the voltage-frequency level.

The operation mode of the DVFS controller 200 varies depending on the buffer capacity and response waiting time, and the scaling factor is determined differently depending on the operation mode, so power consumption can be adjusted according to the situation. For example, the scaling factor determined by the DVFS controller 200 when operating in the memory intensive workload mode sets the voltage-frequency level lower than the scaling factor determined by the DVFS controller 200 when operating in the computing workload mode. It may be a scaling factor that reduces it.

Figure 10 is a flowchart illustrating an example implementation of a method of operating an integrated circuit according to an exemplary embodiment of the present disclosure. As shown in FIG. 10 , an implementation example 1000 of a method of operating an integrated circuit may include a plurality of steps S210 to S250.

Referring to FIGS. 7 and 10 , the memory 250 may store training data in step S210. In an exemplary embodiment, the memory 250 may receive learning data from the monitor 130 and store it. The learning data may include buffer capacity and response latency obtained by the monitor 130 by monitoring the shared buffer 120, and includes a scaling factor determined by the DVFS controller 200 based on the buffer capacity and response latency. can do.

In step S230, an artificial neural network model can be learned using the training data. In an example embodiment, the AI accelerator 260 may execute an artificial neural network model, and the processor 280 may train the artificial neural network model using training data.

After learning is completed in step S250, the processor 280 may determine a scaling factor corresponding to the buffer capacity and response waiting time received from the monitor. In an exemplary embodiment, the processor 280 may receive the buffer capacity and response waiting time from the monitor 130. If the received buffer capacity and response latency correspond to the buffer capacity and response latency stored in the memory 250, a scaling factor corresponding to the buffer capacity and response latency can be determined using the learned artificial neural network model. After the artificial neural network model is learned, the DVFS controller 200 can determine the scaling factor without distinguishing the workload of the core 110, thereby quickly generating a clock control signal and a voltage control signal.

Figure 11 is a block diagram showing a system according to an exemplary embodiment of the present disclosure.

Referring to FIG. 11, system 30 may be used in a mobile phone, a smartphone, a tablet computer, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, or a digital video camera. (digital video camera), portable multimedia player (PMP), personal navigation device (PDN) or portable navigation device (PDN), handheld game console, or e-book. It can be implemented as a handheld device.

System 30 may include SoC 3100 and memory device 3200. The SoC (3100) includes a central processing unit (CPU) (3110), a graphic processing unit (GPU) (3120), a neural processing unit (NPU) (3130), an image signal processor (ISP) (3140), and a memory interface (MIF). It may include (3150), a clock management unit (CMU) (3160), and a power management unit (PMU) (3170). The CPU 3110, GPU 3120, NPU 3130, ISP 3140, and MIF 3150 may be examples of implementations of the integrated circuit 10 described above with reference to FIGS. 1 to 10. Accordingly, the CPU 3110, GPU 3120, NPU 3130, ISP 3140, and MIF 3150 may each include a monitor 130 and a DVFS controller 200, and the DVFS controller 200 DVFS operations can be performed based on the buffer capacity and response waiting time monitored by the monitor 130.

The CPU 3110 may process or execute instructions and/or data stored in the memory device 3200 in response to a clock signal generated by the CMU 3160.

The GPU 3120 may obtain image data stored in the memory device 3200 in response to a clock signal generated by the CMU 3160. The GPU 3120 may generate data for an image output through a display device (not shown) from image data provided by the MIF 3150, and may encode the image data.

NPU 3130 may refer to any device that executes a machine learning model. The NPU 3130 may be a hardware block designed to execute a machine learning model. The machine learning model may be a model based on an artificial neural network, decision tree, support vector machine, regression analysis, Bayesian network, genetic algorithm, etc. Artificial neural networks include, but are not limited to, convolution neural network (CNN), region with convolution neural network (R-CNN), region proposal network (RPN), recurrent neural network (RNN), and stacking-based deep neural network (S-DNN). network), S-SDNN (state-space dynamic neural network), Deconvolution Network, DBN (deep belief network), RBM (restricted Boltzmann machine), Fully Convolutional Network, LSTM (long short-term memory) Network, and Classification Network. can do.

The ISP 3140 may perform a signal processing operation on raw data received from an image sensor (not shown) located outside the SoC 3100 and generate digital data with improved image quality.

The MIF 3150 may provide an interface to a memory device 3200 located outside the SoC 3100. The memory device 3200 may be Dynamic Random Access Memory (DRAM), Phase-change Random Access Memory (PRAM), Resistive Random Access Memory (ReRAM), or flash memory.

The CMU 3160 may generate a clock signal and provide the clock signal to components of the SoC 3100. The CMU 3160 may include a clock generation device such as a phase locked loop (PLL), a delayed locked loop (DLL), and a crystal. The PMU (3170) can convert external power to internal power and supply internal power to components of the SoC (3100).

Figure 12 is a block diagram showing a communication device including an application processor according to an example embodiment of the present disclosure.

Referring to FIG. 12, the communication device 40 may include an application processor 4010, a memory device 4020, a display 4030, an input device 4040, and a wireless transceiver 4050. The application processor 4010 may be an implementation example of the integrated circuit 10 described above with reference to FIGS. 1 to 11 .

The wireless transceiver 4050 can transmit or receive wireless signals through the antenna 4060. For example, the wireless transceiver 4050 can change a wireless signal received through the antenna 4060 into a signal that can be processed by the application processor 4010.

Accordingly, the application processor 4010 can process the signal output from the wireless transceiver 4050 and transmit the processed signal to the display 4030. Additionally, the wireless transceiver 3250 can change the signal output from the application processor 4010 into a wireless signal and output the changed wireless signal to an external device through the antenna 4060.

The input device 4040 is a device that can input control signals for controlling the operation of the application processor 4010 or data to be processed by the application processor 4010, and includes a touch pad and a computer mouse. ) may be implemented with a pointing device, keypad, or keyboard.

At this time, the application processor 4010 may further include a monitor 130 and a DVFS controller 200 according to an embodiment of the present disclosure, and the DVFS controller 200 may monitor the buffer capacity and response latency monitored by the monitor 130. DVFS operations can be performed based on .

Although not shown in FIG. 12, the communication device 40 may further include a clock management unit that provides clock signals and a power management unit that provides a power supply voltage to various components provided in the communication device 40.

Using the integrated circuit 10 according to the present disclosure as described above, it is possible to classify the workload of the core and determine a scaling factor for the voltage-frequency level based on the divided workload, thereby efficiently consuming power according to the situation. can be adjusted.

As above, exemplary embodiments have been disclosed in the drawings and specification. Although embodiments have been described in this specification using specific terms, this is only used for the purpose of explaining the technical idea of the present disclosure and is not used to limit the meaning or scope of the present disclosure as set forth in the claims. . Therefore, those skilled in the art will understand that various modifications and other equivalent embodiments are possible therefrom.

Claims (10)

at least one core configured to process instructions according to voltage-frequency levels;
a shared buffer that receives a request from the at least one core, accesses an external memory according to the request, and receives a response from the external memory;
a monitor that monitors the shared buffer to obtain a buffer capacity of the shared buffer and a response waiting time for the response received from the external memory; and
Receive the buffer capacity and the response waiting time from the monitor, classify the workload of the at least one core based on the buffer capacity and the response waiting time, and set the voltage-frequency level based on the divided workload. An integrated circuit including a Dynamic Voltage and Frequency Scaling (DVFS) controller that determines a scaling factor for . According to claim 1,
The DVFS controller divides the workload of the at least one core into a first workload or a second workload based on the buffer capacity and the response waiting time,
The first workload is,
An integrated circuit comprising more requests to access the external memory than the second workload. According to clause 2,
The DVFS controller is,
An integrated circuit that classifies the workload of the at least one core as a first workload when the buffer capacity indicates a full state and the response waiting time is longer than a threshold time. According to clause 3,
The shared buffer includes a plurality of blocks,
In the state where the buffer capacity is full,
An integrated circuit indicating a state in which the number of blocks using more than a critical capacity among the plurality of blocks is greater than a critical number. According to clause 2,
Further comprising a temperature sensor that measures the temperature of the at least one core and transmits the measured temperature to the DVFS controller,
The DVFS controller is,
When the buffer capacity is not full or the response waiting time is shorter than a threshold time, an integrated circuit that divides the workload of the core whose measured temperature is higher than the threshold temperature into a second workload. According to claim 1,
The DVFS controller is,
a memory that stores training data including the buffer capacity, the response latency, and the scaling factor;
Further comprising a processor that trains an artificial neural network model using the training data,
The processor,
An integrated circuit that determines a scaling factor corresponding to the buffer capacity and the response latency received from the monitor using the learned artificial neural network model after the learning is completed. A method of operating an integrated circuit, comprising:
Monitoring a shared buffer and obtaining a buffer capacity of the shared buffer and a response waiting time for a response that the shared buffer receives from an external memory;
Classifying workloads of cores based on the buffer capacity and the response waiting time; and
A method comprising determining a scaling factor for the voltage-frequency level of the core based on the workload of the divided core. processor;
at least one memory;
a bus connecting the processor and the at least one memory;
The workload of at least one core is divided based on the buffer capacity of the shared buffer and the response waiting time for the response received from the bus, a scaling factor is determined based on the divided workload, and based on the determined scaling factor DVFS controller that generates voltage control signals and clock control signals;
a power management unit that adjusts the size of the power supply voltage provided to the at least one core in response to the voltage control signal; and
A clock manager configured to adjust the frequency of a clock signal provided to the at least one core in response to the clock control signal,
The processor,
the at least one core configured to process instructions according to the magnitude of the power voltage and the frequency of the clock signal;
the shared buffer receiving a request from the at least one core, accessing the bus according to the request, and receiving the response from the bus; and
A computing system comprising a monitor that monitors the shared buffer to obtain the buffer capacity and the response waiting time. According to clause 8,
The DVFS controller is,
Workload classification logic that classifies the workload of the at least one core;
a DVFS governor module that determines the scaling factor;
a power management unit driver that generates a power supply voltage control signal based on the determined scaling factor; and
A computing system further comprising a clock management unit driver that generates a frequency control signal based on the determined scaling factor. In clause 8
The monitor is,
further monitor the identifier for the at least one core,
The DVFS controller is,
Identifying a core according to the identifier, and dividing the workload of the identified core into a first workload or a second workload based on the buffer capacity and the response waiting time,
The first workload is,
A computing system comprising more requests to access the at least one memory than the second workload.

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