KR20220157845A - Integrated circuit, dvfs governor and computing system including them - Google Patents

Abstract

Disclosed is an integrated circuit, which counts parameters required for a dynamic voltage frequency scaling (DVFS) operation, a DVFS control device, and a computing system including the same. The integrated circuit according to an aspect of the technical concept of the present disclosure includes: an event block accessing a bus, which connects processing devices to each other, and outputting an event signal, based on data transmitted through the bus; a clock counter counting the number of clock signals received from a clock management unit; a plurality of performance counters respectively counting parameters used to calculate a workload, based on the event signal; an interface receiving an operation signal from the DVFS control device, which determines an operation frequency and an operation voltage of a processing device based on the workload, and transmitting the number of clock signals and the parameters to the DVFS control device; and a controller controlling operations of the event block, the clock counter, and the plurality of performance counters, based on the operation signal.

Description

Integrated circuit, DVFS control device and computing system including them

The technical idea of the present disclosure relates to an integrated circuit, and more particularly, to an integrated circuit that counts parameters required for a DVFS operation, a DVFS control device, and a computing system including the same.

As computing systems such as mobile devices are miniaturized, power management becomes an important issue. In particular, as the number of processing devices included in a mobile device increases to improve the performance of the mobile device, the complexity of the power management function increases.

As an example, the application processor of the mobile device can manage power by adjusting the voltage through DVFS (Dynamic Voltage and Frequency Scaling) operation that adjusts the frequency and voltage of the processing unit according to the workload of the processing unit embedded in the application processor. have.

An object to be solved by the technical idea of the present disclosure is to provide an integrated circuit, a DVFS control device, and a computing system including the same, which can perform a DVFS operation while taking up less space and consuming less power.

In order to achieve the above object, an integrated circuit according to one aspect of the technical idea of the present disclosure accesses a bus connecting processing devices and outputs an event signal based on data transmitted through the bus. , a clock counter for counting the number of clock signals received from a clock management circuit, a plurality of performance counters for counting parameters used in workload calculation based on the event signal, and an operation of the processing device based on the workload An interface that receives an operating signal from a dynamic voltage frequency scaling (DVFS) control device that determines a frequency and an operating voltage and transmits the number of clock signals and the parameter to the DVFS control device, and based on the operating signal, the event block, a controller controlling operations of the clock counter and the plurality of performance counters.

In order to achieve the above object, a DVFS control device according to an aspect of the technical idea of the present disclosure receives a counted parameter based on data transmitted through a bus and the number of clock signals from an integrated circuit, and the clock signal A processing device profiler that calculates a workload based on the number of and the parameters, a main profiler that receives and stores the workload from the processing device profiler, and an operating frequency and operating voltage of the processing device based on the workload. It includes a main controller that determines and a processing device driver that transmits the operating frequency and the operating voltage to the processing device.

In order to achieve the above object, a computing system according to one aspect of the technical idea of the present disclosure includes a first processing device, a second processing device, a bus connecting the first processing device and the second processing device, the An integrated circuit connected to a bus, and a DVFS control device connected to the integrated circuit, wherein the integrated circuit accesses the bus and outputs an event signal based on data transmitted through the bus, and manages a clock. A clock counter counting the number of clock signals received from the circuit, a plurality of performance counters counting parameters used for workload operation based on the event signal, and receiving an operation signal from the DVFS control device, the clock signal and an interface for transmitting the number of and the parameter to the DVFS control device and a controller for controlling operations of the event block, the clock counter, and the plurality of performance counters based on the operation signal, wherein the DVFS control device comprises: A processing device profiler calculating the workload based on the number of clock signals and the parameter, a main profiler receiving and storing the workload from the processing device profiler, and operating the processing device based on the workload. and a main controller that determines a frequency and an operating voltage and a processing device driver that transmits the operating frequency and the operating voltage to the first processing device and the second processing device.

According to the integrated circuit, the DVFS control device, and the computing system including the technical features of the present disclosure, by counting parameters used for workload calculation and performing a DVFS operation based on the parameters, while taking up less space, DVFS operation can be performed while consuming power.

1 is a block diagram illustrating a computing system according to an exemplary embodiment of the present disclosure.
2 is a detailed block diagram of an integrated circuit according to an exemplary embodiment of the present disclosure.
3 is a flow diagram illustrating the operation of an integrated circuit according to an exemplary embodiment of the present disclosure.
Fig. 4 is a block diagram illustrating a DVFS control apparatus according to an exemplary embodiment of the present disclosure.
5 to 7 are graphs for explaining how a delay time is calculated in the DVFS control device according to an exemplary embodiment of the present disclosure.
8 is a flowchart illustrating an operation of a DVFS control device according to an exemplary embodiment of the present disclosure.
9 is a flowchart illustrating operation of a computing system according to an exemplary embodiment of the present disclosure.
10 is a table representing the performance of an integrated circuit according to an exemplary embodiment of the present disclosure.
11 is a block diagram illustrating a system according to an exemplary embodiment of the present disclosure.
12 is a block diagram illustrating a communication device including an application processor according to an exemplary embodiment of the present disclosure.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating a computing system according to an exemplary embodiment of the present disclosure.

Referring to FIG. 1 , a computing system 10 includes one or more integrated circuits 100_1, 100_2, and 100_3 (hereinafter referred to as 100), a dynamic voltage and frequency scaling (DVFS) control device 200, a plurality of processing devices 300_1, 300_2, 300_3, 300_4 (hereinafter referred to as 300) and one or more buses 400_1, 400_2, and 400_3 (hereinafter referred to as 400).

The computing system 10 may correspond to various types of data processing devices, and may correspond to a mobile device as an example. In addition, the computing system 10 may include a laptop computer, a mobile phone, a smart phone, a tablet PC, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, and a digital video camera. ), PMP (portable multimedia player), PND (personal navigation device or portable navigation device), handheld game console, mobile internet device (MID), wearable computer, internet of things, It may correspond to an IoT device, an internet of everything (IoE) device, or an e-book In some embodiments, the computing system 10 may include a System on Chip, SoC) can be implemented.

First, the plurality of processing devices 300 may perform preset functions in the computing system 10 . For example, the processing unit may be a Central Processing Unit (CPU), Graphic Processing Unit (GPU), Memory Interface (MIF), Neural Processing Unit (NPU), or Image Signal Processor (ISP). Meanwhile, although FIG. 1 shows a total of four processing devices 300, the number of processing devices 300 included in the computing system 10 is not limited thereto.

One or more buses 400 may connect the plurality of processing devices 300 to each other. Accordingly, the plurality of processing devices 300 may transmit and receive data through one or more buses 400 . As a standard specification of one or more buses 400, an Advanced Microcontroller Bus Architecture (AMBA) protocol from Advanced RISC Machine (ARM) may be applied. Bus types of the AMBA protocol include Advanced High-Performance Bus (AHB), Advanced Peripheral Bus (APB), Advanced eXtensible Interface (AXI), AXI4, AXI Coherency Extensions (ACE), and Coherent Hub Interface (CHI). In addition, other types of protocols such as SONICs Inc.'s uNetwork, IBM's CoreConnect, and OCP-IP's Open Core Protocol may be applied.

One or more integrated circuits 100 may be connected to one or more buses 400 respectively. One or more integrated circuits 100 may access one or more buses 400 and read data transmitted through one or more buses 400 . And one or more integrated circuits 100 may perform an operation based on the read data.

The DVFS control device 200 may adjust operating voltages and operating frequencies of the plurality of processing devices 300 based on data received from one or more integrated circuits 100 .

The DVFS control device 200 may refer to hardware capable of performing DVFS functions and operations or may refer to computer program codes capable of performing DVFS functions and operations. However, it is not limited thereto and may refer to an electronic recording medium, for example, a processor, on which a computer program code capable of performing DVFS functions and operations is loaded. That is, the DVFS control device 200 may mean a functional and/or structural combination of hardware and/or software for driving the hardware to implement the technical concept of the present invention.

2 is a detailed block diagram of an integrated circuit according to an exemplary embodiment of the present disclosure.

Referring to FIG. 2 , a computing system 20 according to an embodiment of the present disclosure includes an integrated circuit 100, a DVFS control device 200, a first processing device 300_1, a second processing device 300_2, a bus 400 and a clock management unit (CMU) 500.

The integrated circuit 100 may include an event block 110 , a clock counter 120 , a plurality of performance counters 130 , an interface 140 and a controller 150 . Also, the integrated circuit 100 may further include a flip flop 160, a clock gating block 170, and a register 180.

The event block 110 may access the bus 400 connecting the first processing device 300_1 and the second processing device 300_2. The event block 110 may read data transmitted through the bus 400 . The event block 110 may output an event signal based on data transmitted through the bus 400 .

The event signal is a signal set based on data transmitted through the bus 400, and may be set differently according to the contents of the data transmitted through the bus 400.

The event signal may include only signals necessary for counting parameters to be described later. In an embodiment of the present disclosure, the event signal may include a transmission activation signal, a multiple outstanding signal, a data read signal, a data write signal, and a request signal.

The transmission activation signal may be a signal indicating that data is being transmitted through the bus 400 . For example, the event block 110 may set a transmission enable signal to 1 when data is being transmitted through the bus 400 . Conversely, the event block 110 may set the transmission activation signal to 0 when data is not being transmitted through the bus 400 .

The multi-outstanding signal may be a signal indicating whether request data is transmitted and whether response data to the request data is transmitted. Multiple outstanding signals may change as request data and response data are transmitted over the bus 400 . For example, the event block 110 may increase the multi-outstanding signal by 1 when request data is transmitted through the bus 400 . Conversely, the event block 110 may decrease the multi-outstanding signal by 1 when all response data is transmitted through the bus 400 .

The data read signal may be a signal indicating that read response data corresponding to the read request data is transmitted through the bus 400 . For example, the event block 110 may generate a data read signal when read response data is transmitted. Conversely, the event block 110 may not generate a data read signal if read response data is not transmitted.

The write data signal may be a signal indicating that write response data corresponding to the write request data is transmitted through the bus 400 . For example, the event block 110 may generate a data write signal when write response data is transmitted. Conversely, the event block 110 may not generate a data write signal if write response data is not transmitted.

The request signal may be a signal indicating that read request data or write request data is transmitted. For example, the event block 110 may generate a request signal when read request data or write request data is transmitted. Conversely, the event block 110 may not generate a request signal if read request data and write request data are not transmitted.

The event block 110 may output an event signal based on a protocol used for communication between the first processing device 300_1 and the second processing device 300_2. That is, the event block 110 may output an event signal based on a protocol applied to the bus 400 connecting the first processing device 300_1 and the second processing device 300_2.

In an embodiment of the present disclosure, the event block 110 may perform operations included in data transmitted through a bus when a protocol used for communication between the first processing device 300_1 and the second processing device 300_2 is an operation code protocol. Based on the code, multiple outstanding signals may be set and output.

The operation code protocol may refer to a protocol in which data is transmitted and received using an operation code (opcode), such as a CHI protocol bus type among bus types of the AMBA protocol. At this time, the operation code may be coupled to the front end of the data transmitted through the bus 400 and transmitted together with the data, and may indicate the type of data.

If the operation code is an operation code indicating a data read request or data write request, the event block 110 increases the multi-outstanding signal by 1 when the read request data or write request data is transmitted through the bus 400, and Block 110 may decrease the multi-outstanding signal by 1 when first data of response data for read request data or write request data is transmitted through the bus 400 .

In addition, if the operation code is an operation code meaning atomic transaction, the event block 110 increases the multi-outstanding signal by 1 when the request data is transmitted through the bus 400, and the event block 110 ) may decrease the multi-outstanding signal by 1 when any one of read response data and write response data corresponding to the request data is transmitted through the bus 400 .

In addition, if the operation code indicates a cache maintenance operation (CMO), the event block 110 generates multiple outstanding signals by 1 when read request data or write request data is transmitted through the bus 400. and the event block 110 may decrease the multi-outstanding signal by 1 when read response data, write response data, or a response not including data is transmitted through the bus 400 .

In an embodiment of the present disclosure, the event block 110 may be included in data transmitted through a bus if the protocol used for communication between the first processing device 300_1 and the second processing device 300_2 is not an operation code protocol. Regardless of operation codes, multiple outstanding signals can be set and output.

At this time, the event block 110 may increase the multi-outstanding signal by 1 when request data is transmitted through the bus 400 . Conversely, the event block 110 may decrease the multi-outstanding signal by 1 when all response data is transmitted through the bus 400 .

The clock counter 120 may count the number of clock signals received from the clock management circuit 500 . In one embodiment of the present disclosure, the clock counter 120 may count and increment the number of clock signals whenever the clock signal transitions from 0 to 1. In another embodiment of the present disclosure, the clock counter 120 may count and increment the number of clock signals whenever the clock signal transitions from 1 to 0.

The plurality of performance counters 130_1, 130_2, 130_3, and 130_4 (hereinafter referred to as 130) may count parameters used for workload operation based on the event signal.

Parameters may include only parameters essential to the operation of a workload described below. In an embodiment of the present disclosure, parameters may include an active time, a data transmission number, a transmission request number, and a multi-outstanding accumulated value. The active time may mean a time during which data is transmitted through the bus 400 . The number of times of data transmission may mean the number of times data is transmitted through the bus 400 . The number of transmission requests may mean the number of times data requests are made through the bus 400 . The multi-outstanding cumulative value may mean the total time that the multi-outstanding signal generated by the event block 110 is 1.

The plurality of performance counters 130 may include a first performance counter 130_1, a second performance counter 130_2, a third performance counter 130_3, and a fourth performance counter 130_4.

The first performance counter 130_1 may count the active time. The first performance counter 130_1 may count the active time based on a transmission activation signal or multiple outstanding signals included in the event signal.

In this case, the first performance counter 130_1 may count the active time based on a protocol used for communication between the first processing device 300_1 and the second processing device 300_2.

In one embodiment of the present disclosure, the first performance counter 130_1 determines that if the protocol used for communication between the first processing device 300_1 and the second processing device 300_2 is not an operation code protocol, the transmission enable signal is 1 day. At this time, the active time can be counted and increased. And, if the protocol used for communication between the first processing device 300_1 and the second processing device 300_2 is an operation code protocol, the first performance counter 130_1 counts the active time when the multi-outstanding signal is 1, can increase

The second performance counter 130_2 may count the number of data transmissions. The second performance counter 130_2 may count the number of data read signals and data write signals included in the event signal as the number of data transmissions.

In an embodiment of the present disclosure, the second performance counter 130_2 may count and increase the number of data transmissions when a data read signal or data write signal is generated.

The third performance counter 130_3 may count the number of transmission requests. The third performance counter 130_3 may count the number of request signals included in the event signal as the number of transmission requests.

In an embodiment of the present disclosure, the third performance counter 130_3 may count and increase the number of transmission requests when a request signal is generated.

The fourth performance counter 130_4 may count multiple outstanding accumulated values. The fourth performance counter 130_4 may count a multi-outstanding accumulated value based on the multi-outstanding signal included in the event signal.

In an embodiment of the present disclosure, the fourth performance counter 130_4 may count and increase the multi-outstanding accumulated value when the multi-outstanding signal is 1.

The interface 140 may receive an operating signal from the DVFS control device 200 that determines operating frequencies and operating voltages of the first processing device 300_1 and the second processing device 300_2 based on the workload. The operation signal is a signal that controls the operation of the integrated circuit 100 and may include an activation signal for activating the integrated circuit 100 and a deactivation signal for inactivating the integrated circuit 100 . Also, the operation signal may include an interrupt reference value, which is a reference value for determining whether an interrupt occurs in the clock counter 120 and the plurality of performance counters 130 .

Also, the interface 140 may transmit the number of clock signals and parameters to the DVFS control device 200 . That is, the interface 140 may transmit values counted by the clock counter 120 and the plurality of performance counters 130 to the DVFS control device 200 .

The controller 150 may control the operation of the event block 110 , the clock counter 120 , and the plurality of performance counters 130 based on the operation signal.

The controller 150 may activate or deactivate the event block 110, the clock counter 120, and the plurality of performance counters 130 based on the operation signal.

In one embodiment of the present disclosure, if the operation signal is an activation signal, the controller 150 may control the clock counter 120 to count the number of clock signals and the plurality of performance counters 130 to count parameters. have. Conversely, if the operation signal is an inactivation signal, the controller 150 may control the clock counter 120 and the plurality of performance counters 130 to stop their operation.

Also, the controller 150 may determine whether an interrupt occurs in the clock counter 120 and the plurality of performance counters 130 based on the operation signal.

In one embodiment of the present disclosure, the controller 150 may compare any one of the values counted by the clock counter 120 and the plurality of performance counters 130 with an interrupt reference value to determine whether an interrupt has occurred. have. For example, the controller 150 may determine that an interrupt occurs in the clock counter 120 when the number of clock signals counted by the clock counter 120 exceeds an interrupt reference value.

The flip flop 160 may be connected between the event block 110 and the plurality of performance counters 130 . The flip flop 160 may sample and transfer the event signal to the plurality of performance counters 130 .

The clock gating block 170 may determine whether a clock signal is received. In one embodiment of the present disclosure, the clock gating block 170 may receive a clock signal when an activation signal is received through the interface 140 . Conversely, the clock gating block 170 may not receive a clock signal when an inactivation signal is received through the interface 140 .

The clock gating block 170 may transmit clock signals to the clock counter 120 and the plurality of performance counters 130 . In this case, the clock gating block 170 is illustrated as transmitting a clock signal only to the clock counter 120, but is not limited thereto. That is, the clock gating block 170 may transmit a clock signal to other blocks included in the integrated circuit 100 .

The register 180 may store operation signals, the number of clock signals, and parameters. That is, the register 180 may store the number of clock signals counted by the clock counter 120 and parameters counted by the plurality of counters 130 . Accordingly, the interface 140 may read the number of clock signals and parameters from the register 180 and transmit them to the DVFS control device 200 .

3 is a flow diagram illustrating the operation of an integrated circuit according to an exemplary embodiment of the present disclosure.

Referring to FIG. 3 , in step S310, the event block 110 may output an event signal. That is, the event block 110 may output an event signal based on data transmitted through the bus 400 connecting the first processing device 300_1 and the second processing device 300_2.

In step S320, the clock counter 120 may count the number of clock signals. That is, the clock counter 120 may count the number of clock signals received from the clock management circuit 500 .

In step S330, the plurality of performance counters 130 may count parameters based on the event signal. That is, the plurality of performance counters 130 may count parameters used for workload operation based on an event signal received from the event block 110 .

At this time, although it is shown in FIG. 3 that steps S320 and S330 are performed in sequence, it is not limited thereto, and steps S320 and S330 may be performed simultaneously.

Finally, in step S340, the interface 140 may transmit the number of clock signals and parameters. That is, the interface 140 may receive the number and parameters of clock signals from the clock counter 120 and the plurality of performance counters 130 and transmit them to the DVFS control device 200 .

Fig. 4 is a block diagram illustrating a DVFS control apparatus according to an exemplary embodiment of the present disclosure.

Referring to FIG. 4 , the DVFS control device 200 includes one or more processing device profilers 210_1, 210_2, and 210_3 (hereinafter referred to as 210), a main profiler 220, and one or more processing device drivers 230_1, 230_2, and 230_3; Hereinafter, 230) and a main controller 240 may be included.

One or more processing device profilers 210 may receive the number and parameters of clock signals from the integrated circuit 100 . In addition, one or more processing device profilers 210 may calculate a workload based on the number and parameters of clock signals. At this time, the one or more processing device profilers 210 may calculate the corresponding workload of the processing device 300 .

Although FIG. 4 illustrates three one or more processing device profilers 210, it is not limited thereto. The number of one or more processing device profilers 210 may be equal to the number of processing devices 300 controlled by the DVFS control device 200 .

The workload is an index representing the amount of work that the processing device 300 has to process. The workload is used by the main profiler 220 to calculate the operating frequency and operating voltage of the processing device 300 . The workload may include an active ratio, a bandwidth utilization value, and an average latency.

The active ratio may refer to a ratio of time in which the bus 400 to which the processing device 300 is connected is activated out of the total time. At this time, the activation time of the processing device 300 may be measured from the time when the request is transmitted through the bus 400 to the time when the response is received.

One or more processing device profilers 210 may calculate an active ratio by dividing an active time among parameters by the number of clock signals.

The bandwidth activation value may be a value representing how much the bandwidth of the bus 400 to which the processing device 300 is connected is activated.

One or more processing device profilers 210 may calculate a bandwidth activation value by dividing a result obtained by multiplying the number of data transmission among parameters by the number of clock signals and the previously stored data width by an operating frequency. In this case, the data width may be a value pre-measured and stored by one or more processing device profilers 210 of the data width of the bus 400 . Also, the operating frequency may refer to a frequency at which the processing device 300 is currently operating.

The average delay time may mean an average time from the time when request data is transmitted through the bus 400 to the time when response data is received.

The one or more processing device profilers 210 may calculate the average delay time by dividing the cumulative value of multiple outstandings among the parameters by the number of transmission requests among the parameters.

At this time, the average delay time may be calculated differently depending on the type of protocol and the type of operation code used for communication between the processing devices 300 . This can be explained in more detail with reference to FIGS. 5 to 7 .

5 to 7 are graphs for explaining how a delay time is calculated in the DVFS control device according to an exemplary embodiment of the present disclosure.

First, referring to FIG. 5, when a protocol used for communication between processing devices 300 is an operation code protocol, and the operation code is an operation code indicating a data read request or data write request, a delay time calculation method is shown. You can check the graph.

When the operation code is an operation code indicating a data read request or data write request, the delay time can be calculated from the transmission time of the request data Req to the reception time of the last response data DLast as shown by the arrow below. . However, in the present disclosure, the delay time may be calculated from the transmission time of the request data (Req) to the reception time of the first response data (DFirst) as shown by the upper arrow. In the present disclosure, by calculating the delay time in this way, even if it is not determined whether the response data is the last response data (DLast), the delay time is calculated immediately when the first response data (DFirst) is received, so that the delay time is reduced using fewer gates. can be computed.

At this time, the time difference between the transmission time of the request data Req and the reception time of the first response data DFirst is significantly different from the time difference between the reception time of the first response data DFirst and the reception time of the last response data DLast. It is shown without. However, in reality, the time difference between the transmission of the request data (Req) and the reception of the first response data (DFirst) is much larger than the time difference between the reception of the first response data (DFirst) and the reception of the last response data (DLast). has a value Therefore, even if the delay time is calculated as in the present disclosure, a large error does not occur.

6 and 7, when a protocol used for communication between processing devices 300 is an operation code protocol, and the operation code is an operation code meaning a cache maintenance operation, graphs illustrating how delay time is calculated can be checked.

In the case of a cache maintaining operation, even if the request data Req is transmitted through the bus 400, the response data Data is not necessarily received, but the response Rsp including no data may be transmitted.

When the operation code is an operation code indicating a cache maintenance operation, when a response including no data is transmitted as a response, the delay time may be calculated as 0. However, in the present disclosure, when the operation code is an operation code meaning a cache maintenance operation, and a response that does not include data is transmitted as a response, as shown in FIG. 6, the delay time is the transmission time of the request data Req. It can be calculated as from to the time of reception of the response (Rsp) not including data.

And, when the operation code is an operation code meaning cache maintenance operation, when response data (Data) is received as a response, as shown in FIG. 7, the delay time starts from the transmission time of the request data (Req) It may be calculated until the point of receiving the response data (Data).

In other cases not shown in FIGS. 5 to 7 , the delay time may be calculated from the transmission time of the request data to the time when all response data are received.

Returning to FIG. 4 again, as in the method described with reference to FIGS. 5 to 7, the delay time may be calculated differently depending on the type of protocol and the type of operation code used for communication between the processing devices 300, and the calculated An average value of delay times may be calculated as an average delay time.

At this time, the event block 110 may calculate the multiple outstanding signals differently according to the type of protocol and the type of operation code used for communication between the processing devices 300, as described above. Also, the event block 110 may output multiple outstanding signals as 1 at the same time point as the delay time. Accordingly, the one or more processing device profilers 210 simply divide the multi-outstanding accumulated value by the number of transmission requests among the parameters without considering the type of protocol and the type of operation code used for communication between the processing devices 300 and average delay. time can be calculated.

The main profiler 220 may receive and store workloads from one or more processing unit profilers 210 . Also, the main profiler 220 may transmit the stored workload to the main controller 240 .

Also, the main profiler 220 may receive the operating voltage and operating frequency of the processing device 300 from the main controller 240 and transmit the received operating voltage and operating frequency to one or more processing device drivers 230 .

The main controller 240 may control overall operations of the DVFS control device 200 . The main controller 240 may determine the operating frequency and operating voltage of the processing device 300 based on the workload received from the main profiler 220 .

In an embodiment of the present disclosure, the main controller 240 may determine an operating voltage and an operating frequency in proportion to an active ratio, a bandwidth active value, and an average delay time. That is, the main controller 240 may enable smooth operation of the processing device 300 by increasing the operating voltage and operating frequency when the workload is measured to be high. Conversely, when the workload is measured to be low, the main controller 240 may reduce power consumed by the processing device 300 by reducing the operating voltage and operating frequency.

One or more processing device drivers 230 may transmit operating frequencies and operating voltages to processing devices 300 . That is, when receiving the operating frequency and operating voltage from the main controller 240, the one or more processing device drivers 230 may transmit the operating frequency and operating voltage to the corresponding processing device 300.

Although FIG. 4 shows one or more processing device drivers 230 as three, it is not limited thereto. The one or more processing device drivers 230 may be the same as the number of processing devices 300 controlled by the DVFS control device 200, and may be the same as the number of one or more processing device profilers 210.

8 is a flowchart illustrating an operation of a DVFS control device according to an exemplary embodiment of the present disclosure.

Referring to FIG. 8 , in step S810, one or more processing device profilers 210 may calculate a workload based on the number and parameters of clock signals. One or more processing device profilers 210 may calculate an active ratio using the number of clock signals and an active time among parameters. Also, one or more processing device profilers 210 may calculate a bandwidth activity value based on the number of clock signals and the number of data transfers among the parameters. In addition, one or more processing device profilers 210 may calculate an average delay time using a multi-outstanding accumulated value among parameters and the number of transmission requests among parameters. A more detailed method of computing a workload of one or more processing device profilers 210 may be as described above with reference to FIG. 4 . And one or more processing device profilers 210 may transmit the calculated workload to the main profiler 220 .

In step S820, the main controller 240 may determine the operating frequency and operating voltage of the processing device 300 based on the workload. In this case, the main controller 240 may determine the operating frequency and operating voltage of the processing device 300 in proportion to the active ratio, the bandwidth active value, and the average delay time calculated by the one or more processing device profilers 210 .

In step S830 , one or more processing device drivers 230 may transmit operating frequencies and operating voltages to the processing device 300 . One or more processing device drivers 230 may transmit operating frequencies and operating voltages to the corresponding processing device 300 to manage power of the processing device 300 through DVFS operation.

9 is a flowchart illustrating operation of a computing system according to an exemplary embodiment of the present disclosure.

Referring to FIG. 9 , in step S910 , the DVFS control device 200 may activate the integrated circuit 100 . The DVFS control device 200 may activate the integrated circuit 100 by transmitting an activation signal to the integrated circuit 100 . Upon receiving the activation signal from the DVFS control device 200, the integrated circuit 100 may activate the event block 110, the clock counter 120, and the plurality of performance counters 130 through the controller 150. have. At this time, the controller 150 may initialize values counted up to now by the clock counter 120 and the plurality of performance counters 130 . Also, the integrated circuit 100 may set interrupt reference values for the clock counter 120 and the plurality of performance counters 130 through the controller 150 .

In step S920, the integrated circuit 100 may count the number of clock signals and parameters through the clock counter 120 and the plurality of performance counters 130. At this time, the clock counter 120 may count the number of clock signals received from the clock management circuit 500 . Also, the plurality of performance counters 130 may count parameters based on the event signal. A method of counting the number of clock signals and parameters may be as described above with reference to FIG. 2 .

In step S930, the integrated circuit 100 may determine whether an interrupt has occurred in any one of the clock counter 120 and the plurality of performance counters 130 through the controller 150. At this time, the controller 150 may compare any one of the values counted by the clock counter 120 and the plurality of performance counters 130 with an interrupt reference value to determine whether an interrupt has occurred.

If the controller 150 determines that no interrupt has occurred in both the clock counter 120 and the plurality of performance counters 130, step S930 may be repeated after the preset reference time has elapsed.

Conversely, when the controller 150 determines that an interrupt has occurred in one of the clock counter 120 and the plurality of performance counters 130, it can proceed to step S940. At this time, the controller 150 may transmit to the DVFS control device 200 that an interrupt has occurred in one of the clock counter 120 and the plurality of performance counters 130 .

In step S940, the controller 150 may deactivate the clock counter 120 and the plurality of performance counters 130. The controller 150 may deactivate the clock counter 120 and the plurality of performance counters 130 upon receiving the deactivation signal from the DVFS control device 200 .

In step S950, the controller 150 may transmit the number of clock signals and parameters to the DVFS control device 200. At this time, the controller 150 may transmit the number of clock signals and parameters to the DVFS control device 200 through the interface 140 .

10 is a table representing the performance of an integrated circuit according to an exemplary embodiment of the present disclosure.

Referring to FIG. 10 , it can be seen that the integrated circuit 100 according to the exemplary embodiment of the present disclosure consumes 4.4 mW of power and has a total of 16,120 gates. In comparison, it can be seen that the conventional integrated circuit 100 consumes 15.7 mW of power and has a total of 113,630 gates. That is, power consumption can be reduced by about 72% and an area occupied by the integrated circuit 100 can be reduced by about 85% through the integrated circuit 100 according to the exemplary embodiment of the present disclosure.

11 is a block diagram illustrating a system according to an exemplary embodiment of the present disclosure.

Referring to FIG. 11 , a system 30 includes a mobile phone, a smart phone, a tablet computer, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, and a digital video camera. (digital video camera), portable multimedia player (PMP), personal navigation device (PDN) or portable navigation device), handheld game console, or e-book. It can be implemented as a handheld device.

The system 30 may include an SoC 3100 and a memory device 3200 . The SoC 3100 includes a central processing unit (CPU) 3110, a graphic processing unit (GPU) 3120, a neural processing unit (NPU) 3130, an image signal processor (ISP) 3140, a memory interface (MIF) 3150, a clock management unit (CMU) 3160, and a power management unit (PMU) 3170. The CPU 3110, the GPU 3120, the NPU 3130, the ISP 3140, and the MIF 3150 may be an implementation example of the processing device 300 described above with reference to FIGS. 1 to 10. Accordingly, the integrated circuit 100 according to an embodiment of the present disclosure may be connected to a bus connecting the CPU 3110, the GPU 3120, the NPU 3130, the ISP 3140, and the MIF 3150, and the DVFS The control device 200 may perform a DVFS operation based on the number and parameters of clock signals received through the integrated circuit 100 .

The CPU 3110 may process or execute commands and/or data stored in the memory device 3200 in response to a clock signal generated by the CMU 3160 .

The GPU 3120 may acquire image data stored in the memory device 3200 in response to a clock signal generated by the CMU 3160 . The GPU 3120 may generate data for an image output through a display device (not shown) from image data provided from the MIF 3150 or encode the image data.

NPU 3130 may refer to any device that runs a machine learning model. The NPU 3130 may be a hardware block designed to run a machine learning model. The machine learning model may be a model based on an artificial neural network, decision tree, support vector machine, regression analysis, Bayesian network, genetic algorithm, or the like. Artificial neural networks, as non-limiting examples, include a convolution neural network (CNN), a region with convolution neural network (R-CNN), a region proposal network (RPN), a recurrent neural network (RNN), and a stacking-based deep neural network (S-DNN). network), S-SDNN (state-space dynamic neural network), deconvolution network, DBN (deep belief network), RBM (restricted Boltzmann machine), fully convolutional network, LSTM (long short-term memory) network, and classification network can do.

The ISP 3140 may perform a signal processing operation on raw data received from an image sensor (not shown) located outside the SoC 3100 and generate digital data having improved image quality.

The MIF 3150 may provide an interface to the memory device 3200 located outside the SoC 3100. The memory device 3200 may be dynamic random access memory (DRAM), phase-change random access memory (PRAM), resistive random access memory (ReRAM), or flash memory.

CMU 3160 may generate a clock signal and provide the clock signal to components of SoC 3100 . The CMU 3160 may include a clock generator such as a Phase Locked Loop (PLL), a Delayed Locked Loop (DLL), or a crystal. The PMU 3170 may convert external power to internal power and supply power to components of the SoC 3100 from the internal power.

12 is a block diagram illustrating a communication device including an application processor according to an exemplary embodiment of the present disclosure.

Referring to FIG. 12 , the communication device 40 may include an application processor 4010, a memory device 4020, a display 4030, an input device 4040, and a wireless transceiver 4050. The application processor 4010 may be an implementation example of at least one of the processing devices 300 described above with reference to FIGS. 1 to 11 .

The wireless transceiver 4050 may transmit or receive a wireless signal through the antenna 4060. For example, the wireless transceiver 4050 may change a wireless signal received through the antenna 4060 into a signal that can be processed by the application processor 4010 .

Accordingly, the application processor 4010 may process a signal output from the wireless transceiver 4050 and transmit the processed signal to the display 4030 . In addition, the wireless transceiver 3250 may change the signal output from the application processor 4010 into a wireless signal and output the changed wireless signal to an external device through the antenna 4060.

The input device 4040 is a device capable of inputting a control signal for controlling the operation of the application processor 4010 or data to be processed by the application processor 4010, and includes a touch pad and a computer mouse. ), a keypad, or a keyboard.

At this time, the integrated circuit 100 according to the embodiment of the present disclosure may be connected to a bus connected to the application processor 4010, and the DVFS control device 200 may receive the number and parameters of clock signals received through the integrated circuit 100. DVFS operation can be performed based on

Although not shown in FIG. 12 , the communication device 40 may further include a clock management unit providing clock signals to various components and a power management unit providing power voltage.

Using the integrated circuit 100, the DVFS control device 200, and the computing system 10 according to the present disclosure as described above, by counting parameters used for workload calculation and performing a DVFS operation based on the parameters , the DVFS operation can be performed while taking up less space and consuming less power.

As above, exemplary embodiments have been disclosed in the drawings and specifications. Embodiments have been described using specific terms in this specification, but they are only used for the purpose of explaining the technical spirit of the present disclosure, and are not used to limit the scope of the present disclosure described in the meaning or claims. Therefore, those of ordinary skill in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical scope of protection of the present disclosure should be determined by the technical spirit of the appended claims.

Claims (10)

an event block that accesses a bus connecting processing devices and outputs an event signal based on data transmitted through the bus;
a clock counter counting the number of clock signals received from the clock management circuit;
a plurality of performance counters counting parameters used for workload calculation based on the event signal;
Receiving an operating signal from a Dynamic Voltage Frequency Scaling (DVFS) control device that determines an operating frequency and an operating voltage of the processing device based on the workload, and transmitting the number of clock signals and the parameter to the DVFS control device interface; and
And a controller for controlling operations of the event block, the clock counter, and the plurality of performance counters based on the operation signal.
integrated circuit. According to claim 1,
The event block
Outputting the event signal based on a protocol used for communication between the processing devices.
integrated circuit. According to claim 2,
The event signal includes multiple outstanding signals,
The event block
If a protocol used for communication between the processing devices is an operation code protocol, setting and outputting the multiple outstanding signals based on operation codes included in data transmitted through the bus
integrated circuit. According to claim 1,
The parameter includes an active time, the number of data transmissions, the number of transmission requests, and a multi-outstanding cumulative value,
The plurality of performance counters
a first performance counter counting the active time;
a second performance counter counting the number of times the data is transmitted;
a third performance counter counting the number of transmission requests; and
And a fourth performance counter counting the multi-outstanding accumulated value.
integrated circuit. According to claim 1,
The controller activates or deactivates the event block, the clock counter, and the plurality of performance counters based on the operation signal, and determines whether an interrupt occurs in the clock counter and the plurality of performance counters.
integrated circuit. a processing unit profiler that receives, from an integrated circuit, parameters counted based on data transmitted through a bus and the number of clock signals, and calculates a workload based on the number of clock signals and the parameters;
a main profiler receiving and storing the workload from the processing unit profiler;
a main controller that determines an operating frequency and an operating voltage of a processing device based on the workload; and
And a processing device driver for transmitting the operating frequency and the operating voltage to the processing device.
DVFS control unit. According to claim 6,
The processing unit profiler
Calculating an active ratio by dividing the active time among the parameters by the number of clock signals
DVFS control unit. According to claim 6,
The processing unit profiler
Calculating a bandwidth utilization value by dividing the result of multiplying the number of data transfers among the parameters by the number of clock signals and the previously stored data width by the operating frequency
DVFS control unit. According to claim 6,
The processing unit profiler
Calculating an average delay time by dividing a multiple outstanding accumulated value among the parameters by the number of transmission requests among the parameters
DVFS control unit. a first processing device;
a second processing device;
a bus connecting the first processing device and the second processing device;
an integrated circuit coupled to the bus;
Including a DVFS (Dynamic Voltage Frequency Scaling) control device connected to the integrated circuit,
The integrated circuit
an event block that accesses the bus and outputs an event signal based on data transmitted through the bus;
a clock counter counting the number of clock signals received from the clock management circuit;
a plurality of performance counters counting parameters used for workload calculation based on the event signal;
an interface that receives an operation signal from the DVFS control device and transmits the number of clock signals and the parameter to the DVFS control device; and
A controller controlling operations of the event block, the clock counter, and the plurality of performance counters based on the operation signal;
The DVFS control device
a processing unit profiler calculating the workload based on the number of clock signals and the parameters;
a main profiler receiving and storing the workload from the processing unit profiler;
a main controller that determines an operating frequency and an operating voltage of a processing device based on the workload; and
And a processing device driver for transmitting the operating frequency and the operating voltage to the first processing device and the second processing device.
computing system.

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