KR20240012227A - Circuit board and semiconductor package having the same - Google Patents

Abstract

A circuit board according to an embodiment includes a first insulating layer; a first pad disposed on the first insulating layer; and a second insulating layer disposed on the first insulating layer, wherein the second insulating layer includes a first portion surrounding a portion of a side surface of the first pad on the first insulating layer, and the first insulating layer. a second portion disposed on the portion and having an opening having a width greater than the width of the first pad, wherein a side wall of the second portion includes a first slope adjacent an upper surface of the second insulating layer; It is adjacent to the lower surface of the insulating layer and includes a second slope different from the first slope.

Description

Circuit board and semiconductor package including the same {CIRCUIT BOARD AND SEMICONDUCTOR PACKAGE HAVING THE SAME}

The embodiment relates to a circuit board and a semiconductor package including the same.

Generally, a printed circuit board (PCB) is a laminated structure in which insulating layers and conductor layers are alternately laminated, and the conductor layers can be formed into a circuit pattern by patterning.

Such a printed circuit board protects the circuit formed on the outermost side of the laminate, prevents oxidation of the conductor layer, and has an insulating layer or A solder resist (SR) protective layer is provided.

In a typical solder resist, connection means such as solder or bumps are combined to form an opening area (SRO: Solder Resist Opening) that becomes an electrical connection path, and the opening area of the solder resist is an I/O area as printed circuit boards become more high-performance and higher-density. As O (Input/Output) performance improves, a greater number of opening areas are required, which requires a smaller bump pitch of the opening area. At this time, the bump pitch of the opening area refers to the center distance between adjacent opening areas.

Meanwhile, the opening area (SRO) of the solder resist includes a Solder Mask Defined type (SMD) type and a Non-Solder Mask Defined Type (NSMD) type.

The SMD type is characterized in that the width of the opening area (SRO) is smaller than the width of the pad exposed through the opening area (SRO). Accordingly, in the SMD type, at least a portion of the upper surface of the pad is exposed to the solder resist. is covered by

In addition, the NSMD type is characterized in that the width of the opening area (SRO) is larger than the width of the pad exposed through the opening area (SRO). Accordingly, in the NSMD type, the solder resist is spaced at a certain distance from the pad. They are arranged to be spaced apart, and thus have a structure in which both the top and side surfaces of the pad are exposed.

However, in the case of the SMD type, after the semiconductor package is coupled to the main board, the solder ball is separated from the pad exposed through the opening area (SRO) when testing the solder ball joint reliability for the bonding force of the solder ball. There is a problem of separation. Additionally, in the case of the NSMD type, there is a problem in that the pad on which the solder ball is placed is separated from the substrate. Accordingly, conventionally, an appropriate combination of SMD type and NSMD type is applied to one circuit board.

However, in the case of a circuit board including a conventional SMD type and NSMD type opening region (SRO), during the process of exposing the solder resist layer, light is not sufficiently transmitted to the lower area of the exposed area of the solder resist layer. Accordingly, there is a problem that the lower area of the exposed area is not sufficiently cured. In addition, when the development process is performed in a state in which the lower region of the exposed area is not sufficiently cured, there is a problem in that an undercut occurs in which the lower region of the exposed area is removed. Furthermore, as the thickness of the solder resist layer increases, the width of the undercut becomes larger, which reduces the reliability of the circuit board.

An embodiment provides a circuit board capable of reducing the width of a dam of a protective layer disposed between a plurality of pads and a semiconductor package including the same.

Additionally, the embodiment provides a circuit board capable of optimizing the slope of the sidewall of the protective layer in the open area and a semiconductor package including the same.

Additionally, the embodiment provides a circuit board capable of removing a depression formed on a sidewall of a protective layer in an open area and a semiconductor package including the same.

Additionally, an embodiment provides a circuit board that can minimize the horizontal distance of a depression formed on a sidewall of a protective layer in an open area and a semiconductor package including the same.

Additionally, an embodiment provides a circuit board that can reduce the gap between pads disposed on the uppermost side of the circuit board and a semiconductor package including the same.

The technical challenges to be achieved in the proposed embodiment are not limited to the technical challenges mentioned above, and other technical challenges not mentioned are clear to those skilled in the art from the description below. It will be understandable.

A circuit board according to an embodiment includes a first insulating layer; a first pad disposed on the first insulating layer; and a second insulating layer disposed on the first insulating layer, wherein the second insulating layer includes a first portion surrounding a portion of a side surface of the first pad on the first insulating layer, and the first insulating layer. a second portion disposed on the portion and having an opening having a width greater than the width of the first pad, wherein a side wall of the second portion includes a first slope adjacent an upper surface of the second insulating layer; It is adjacent to the lower surface of the insulating layer and includes a second slope different from the first slope.

Additionally, the second slope is inclined toward the first pad from the top to the bottom of the second insulating layer.

Additionally, the first slope is perpendicular to the top surface of the second insulating layer.

Additionally, the side wall of the second portion is provided with a depression that is recessed in the inward direction.

Additionally, the recess is provided between the first slope and the second slope.

In addition, the horizontal distance of the depression is 13 μm or less, and the horizontal distance is the horizontal distance from the lower end of the first slope adjacent to the depression to the innermost end of the depression.

Additionally, the thickness of the first portion of the second insulating layer satisfies a range of 40% to 98% of the thickness of the first pad.

Additionally, the top surface of the first portion of the second insulating layer is located lower than the top surface of the first pad, and the top surface of the second portion of the second insulating layer is located higher than the top surface of the first pad.

Additionally, the circuit board includes a trace disposed adjacent the first pad on the first insulating layer and covered by the second portion of the second insulating layer, wherein the trace and the second insulating layer The shortest horizontal distance between the side walls of the layers satisfies the range between 1 μm and 30 μm.

Meanwhile, the circuit board according to the embodiment includes a first insulating layer; a first circuit pattern layer disposed on the first insulating layer; and a second insulating layer disposed on the first insulating layer and the first circuit pattern layer, wherein the first circuit pattern layer includes a first pattern and a second pattern adjacent to the first pattern, A second insulating layer is disposed on a first portion of the first region disposed between the first pattern and the second pattern and the second pattern on the first portion of the first region, A second portion including a first opening with a width greater than the width of one pattern, wherein the first sidewall of the first opening includes different first and second inclinations, and the first and second inclinations are formed from the second pattern. 1 The shortest horizontal distance between side walls is 30㎛ or less.

Additionally, the first inclination is perpendicular to the upper surface of the second insulating layer, and the second inclination is inclined toward the first pattern as it increases from the upper surface to the lower surface of the second insulating layer.

Additionally, a depression is formed on the first side wall of the second portion in an inward direction away from the first pattern, and the horizontal distance of the depression is 13 μm or less.

Additionally, the recess is provided between the first slope and the second slope of the first side wall.

Meanwhile, the circuit board according to the embodiment includes a first insulating layer; a first pad and a second pad disposed on the first insulating layer; a second insulating layer disposed between the first pad and the second pad on the first insulating layer, the second insulating layer being disposed on the first insulating layer, the first pad and the second pad; A first part having a width equal to the gap between two pads, and a second part disposed on the first part and having a width less than the gap, wherein the second part has an upper surface, the first pad It includes a first side adjacent to and a second side adjacent to the second pad, and each of the first side and the second side includes different first and second slopes.

Additionally, the first inclination of the first side is perpendicular to the upper surface of the second portion, and the second inclination of the first side is inclined toward the first pad as it goes from the upper surface to the lower surface of the second insulating layer. Lose.

Additionally, the first inclination of the second side is perpendicular to the upper surface of the second portion, and the second inclination of the second side is inclined toward the second pad as it goes from the upper surface to the lower surface of the second insulating layer. Lose.

In addition, at least one of the first side and the second side is provided between the first slope and the second slope and includes a depression recessed in the inner direction of the first portion.

A circuit board according to an embodiment includes a first protective layer. The first protective layer includes a first part and a second part having a step. And, in an embodiment, the opening formed in the first protective layer may be formed by selectively removing only the second portion excluding the first portion. At this time, the thickness of the first portion of the first protective layer is smaller than the thickness of the first circuit pattern layer exposed through the opening. Accordingly, the opening formed in the second portion of the first protective layer may expose a portion of the side surface of the first circuit pattern layer and the top surface of the first circuit pattern layer. Accordingly, in the embodiment, the depth of the opening does not have a depth corresponding to the entire thickness of the first protective layer, but has a depth corresponding to the thickness of the second portion. Accordingly, in the embodiment, compared to the comparative example, the horizontal distance of the depression corresponding to the undercut formed on the side wall of the opening can be significantly reduced. Furthermore, the embodiment may remove the depression.

Accordingly, in the embodiment, the electrical reliability or physical reliability of the circuit board can be improved. For example, as the horizontal distance of the depression increases, a portion of the solder ball may penetrate between the depressions, and based on this, a short circuit problem may occur as neighboring circuit patterns are connected. For example, as the horizontal distance of the depression increases, the contact area between the first protective layer and the insulating layer decreases, and accordingly, the bonding force between the first protective layer and the insulating layer may decrease. In contrast, in the embodiment, by reducing the horizontal distance of the depression, electrical reliability problems such as the short circuit can be solved, and furthermore, physical reliability problems such as the reduction of bonding force can be solved.

Additionally, in the embodiment, the thickness of the first portion of the first protective layer is in the range of 40% to 98% of the first circuit pattern layer. Accordingly, in the embodiment, the upper surface of the first circuit pattern layer can be stably exposed through the opening formed in the second portion, while the horizontal distance of the depression can be dramatically reduced.

Additionally, in an embodiment, by reducing the horizontal distance of the depression, the gap between pads of the first circuit pattern layer, between a pad and a trace, or between traces can be reduced. Specifically, the spacing between the pads of the first circuit pattern layer, or between the pad and the trace, or between the traces, is determined by reflecting the horizontal distance of the depression in order to solve the electrical reliability problem. At this time, in the embodiment, as the horizontal distance of the depression is reduced, the gap between the pads of the first circuit pattern layer, or between the pad and the trace, or between the traces, which is determined by the horizontal distance of the depression, is dramatically reduced. It can be reduced.

1A is a diagram showing a circuit board according to a comparative example.
FIG. 1B is an enlarged view of the first region of the first protective layer of FIG. 1A.
FIG. 1C is a diagram for explaining a defect in the first area of the first protective layer of FIG. 1B.
FIG. 1D is an enlarged view of the second region of the first protective layer of FIG. 1A.
FIG. 1E is a diagram for explaining a defect in the second area of the first protective layer of FIG. 1D.
Figure 2a is a cross-sectional view showing a semiconductor package according to the first embodiment.
Figure 2b is a cross-sectional view showing a semiconductor package according to a second embodiment.
Figure 2c is a cross-sectional view showing a semiconductor package according to a third embodiment.
Figure 2d is a cross-sectional view showing a semiconductor package according to a fourth embodiment.
Figure 2e is a cross-sectional view showing a semiconductor package according to a fifth embodiment.
Figure 2f is a cross-sectional view showing a semiconductor package according to the sixth embodiment.
Figure 2g is a cross-sectional view showing a semiconductor package according to a seventh embodiment.
3A is a cross-sectional view of a circuit board according to an embodiment.
FIG. 3B is a plan view of the circuit board of FIG. 2A viewed from above.
Figure 4a is a diagram for explaining the exposure and curing process of the solder resist layer according to an embodiment.
Figure 4b is a diagram for explaining the horizontal distance of the depression according to the thickness of the solder resist layer.
Figure 4c is a diagram for explaining the horizontal distance of the depression according to the development depth of the solder resist layer.
Figure 5a is a diagram showing the results of an experiment on the horizontal distance of the depression in the solder resist layer made of the first insulating material.
Figure 5b is a diagram for explaining the results of an experiment on the horizontal distance of the depression in the solder resist layer composed of a second insulating material different from the first insulating material.
FIG. 6A is a diagram showing a 1-1 region in the first region of the first protective layer of FIG. 3A.
FIG. 6B is a diagram showing a SAM photograph of the circuit board corresponding to FIG. 6A.
FIG. 7A is a diagram showing regions 1-2 in the first region of the first protective layer of FIG. 3A.
FIG. 7B is a diagram showing a SAM photograph of the circuit board corresponding to FIG. 7A.
FIG. 8A is a diagram showing a second region of the first protective layer of FIG. 3A.
FIG. 8B is a diagram showing a SAM photograph of the circuit board corresponding to FIG. 8A.
FIG. 9A is a diagram illustrating a 1-1 region of the first region of the first protective layer of FIG. 3A according to the second embodiment.
FIG. 9B is a diagram showing a 1-1 region of the first region of the first protective layer of FIG. 3A according to the third embodiment.
FIG. 10A is a diagram showing regions 1-2 in the first region of the first protective layer of FIG. 3A in the second embodiment.
FIG. 10B is a diagram showing regions 1-2 in the first region of the first protective layer of FIG. 3A according to the third embodiment.
FIG. 11A is a diagram showing a second area of the first protective layer of FIG. 3A according to the second embodiment.
FIG. 11B is a diagram showing a second area of the first protective layer of FIG. 3A according to the third embodiment.
FIGS. 12A to 12J are diagrams for explaining the manufacturing method of the circuit board of FIG. 3A in process order.
Figure 13 is a diagram showing the detailed structure of a semiconductor package according to one embodiment.
14 is a diagram showing the detailed structure of a semiconductor package according to another embodiment.

Hereinafter, embodiments disclosed in the present specification will be described in detail with reference to the attached drawings. However, identical or similar components will be assigned the same reference numbers regardless of reference numerals, and duplicate descriptions thereof will be omitted. The suffixes “module” and “part” for components used in the following description are given or used interchangeably only for the ease of preparing the specification, and do not have distinct meanings or roles in themselves. Additionally, in describing the embodiments disclosed in this specification, if it is determined that detailed descriptions of related known technologies may obscure the gist of the embodiments disclosed in this specification, the detailed descriptions will be omitted. In addition, the attached drawings are only for easy understanding of the embodiments disclosed in this specification, and the technical idea disclosed in this specification is not limited by the attached drawings, and all changes included in the spirit and technical scope of the present invention are not limited. , should be understood to include equivalents or substitutes.

Terms containing ordinal numbers, such as first, second, etc., may be used to describe various components, but the components are not limited by the terms. The above terms are used only for the purpose of distinguishing one component from another.

When a component is said to be "connected" or "connected" to another component, it is understood that it may be directly connected to or connected to the other component, but that other components may exist in between. It should be. On the other hand, when it is mentioned that a component is “directly connected” or “directly connected” to another component, it should be understood that there are no other components in between.

Singular expressions include plural expressions unless the context clearly dictates otherwise.

In this application, terms such as “comprise” or “have” are intended to designate the presence of features, numbers, steps, operations, components, parts, or combinations thereof described in the specification, but are not intended to indicate the presence of one or more other features. It should be understood that this does not exclude in advance the possibility of the existence or addition of elements, numbers, steps, operations, components, parts, or combinations thereof.

Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings.

- Comparative example (circuit board of prior art) -

Before describing the embodiment, a comparative example compared to the circuit board of the embodiment of the present application will be described.

FIG. 1A is a diagram showing a circuit board according to a comparative example, FIG. 1B is an enlarged view of the first region of the first protective layer in FIG. 1A, and FIG. 1C is a defect in the first region of the first protective layer in FIG. 1B. 1D is an enlarged view of the second area of the first protective layer in FIG. 1A, and FIG. 1E is a drawing for explaining a defect in the second area of the first protective layer in FIG. 1D.

Referring to FIG. 1A, the circuit board according to the comparative example includes an insulating layer, a circuit pattern, a penetrating portion, and a protective layer.

The insulating layer includes a core layer (1), a first insulating layer (5), and a second insulating layer (8). In the circuit board of the comparative example, the first insulating layer 5 and the second insulating layer 8 are disposed in a symmetrical structure on the upper and lower portions of the core layer 1. The core layer 1 is CCL (Clad Copper Laminate) containing prepreg, or contains materials such as silicon, glass, and ceramic used in interposers.

The first insulating layer 5 and the second insulating layer 8 are disposed on the upper and lower surfaces of the core layer 1, respectively. The first insulating layer 5 and the second insulating layer 8 include prepreg. For example, the first insulating layer 5 and the second insulating layer 8 comprise a resin and reinforcing fibers within the resin.

The first circuit pattern 2 is disposed on the lower surface of the first insulating layer 5. Additionally, the first circuit pattern 2 is disposed on the upper surface of the core layer 1. The first circuit pattern 2 protrudes above the top surface of the core layer 1, and thus the side and top surfaces are covered by the first insulating layer 5. The second circuit pattern 7 is disposed on the upper surface of the first insulating layer 5. The second circuit pattern 7 is disposed to protrude above the top surface of the first insulating layer 5.

The third circuit pattern 3 is disposed on the upper surface of the second insulating layer 8. Additionally, the third circuit pattern 3 is disposed on the lower surface of the second insulating layer 8.

The fourth circuit pattern 10 is disposed on the lower surface of the second insulating layer 8. The fourth circuit pattern 10 is disposed to protrude below the lower surface of the second insulating layer 8.

At this time, in the circuit board of the comparative example, the first insulating layer 5 is an insulating layer disposed on the first outermost or uppermost side in the multilayer structure, and the second insulating layer 8 is an insulating layer disposed on the second outermost or lowermost side. It is an insulating layer placed.

The first circuit pattern 2, the second circuit pattern 7, the third circuit pattern 3, and the fourth circuit pattern 10 each include pads and traces. The pad is a part where a via is connected, a chip is mounted, or an adhesive portion (not shown) connected to the main board of an external substrate is placed. The trace is a signal line that extends long from the pad.

The via is disposed penetrating each insulating layer. For example, the first via 6 is disposed to penetrate the first insulating layer 5. One end of the first via 6 is connected to the first circuit pattern 2, and the other end is connected to the second circuit pattern 7. For example, the second via 4 is disposed penetrating the core layer 1. For example, the third via 9 is disposed to penetrate the second insulating layer 8. For example, one end of the third via 9 is connected to the third circuit pattern 3 and the other end is connected to the fourth circuit pattern 10.

The first protective layer 11 and the second protective layer 12 are disposed on the upper surface of the first insulating layer 5 and the lower surface of the second insulating layer 8, respectively. The first protective layer 11 and the second protective layer 12 have openings that expose the surfaces of the second circuit pattern 7 and the fourth circuit pattern 1, respectively. The first protective layer 11 and the second protective layer 12 are solder resist.

At this time, in the circuit board of the comparative example, one of the first and second outermost circuit patterns includes a mounting portion on which a chip is mounted, and the other includes a terminal portion connected to the main board of the external substrate.

For example, in the comparative example, the second circuit pattern 7 disposed on the first outermost side includes a mounting pad on which a chip is mounted, and the fourth circuit pattern 10 disposed on the second outermost side includes an external substrate. Includes terminal pads to which the main board is connected.

For example, the second circuit pattern 7 includes a plurality of pads and traces. The plurality of pads may be mounting pads on which chips are mounted, or may be core pads connected to a separate upper substrate. Specifically, the second circuit pattern 7 includes a first pad 7-1, a second pad 7-2, and a trace 7-3.

In addition, the first protective layer 11 is disposed on the upper surface of the first insulating layer 5, covering the upper surface of the trace 7-3 of the second circuit pattern 7. Additionally, the first protective layer 11 has an opening exposing the top surfaces of the first pad 7-1 and the second pad 7-2 of the second circuit pattern 7.

At this time, the first protective layer 11 may be divided into a plurality of regions depending on the placement location.

Referring to FIG. 1B, the first protective layer 11 includes a first region 11-1.

For example, the first protective layer 11 includes a first region 11-1 disposed between the 2-1 pad 7-21 and the 2-2 pad 7-22. And, the first region 11-1 of the first protective layer 11 has an NSMD type opening exposing the upper surfaces of the 2-1 pad 7-21 and the 2-2 pad 7-22. This is the area containing (SOR1). In addition, the first region 11-1 of the first protective layer 11 has a second circuit pattern disposed between the 2-1 pad 7-21 and the 2-2 pad 7-22 ( 7, refers to an area where traces or pads, for example, do not exist.

At this time, the opening SOR1 of the first region 11-1 of the first protective layer 11 is larger than the width of the second pad 7-2. Accordingly, the first region 11-1 of the first protective layer 11 is disposed at a predetermined distance from the second pad 7-2.

Here, the thickness t1 of the second circuit pattern 7 is 10 μm to 35 μm. Additionally, the thickness t2 of the first region 11-1 of the first protective layer 11 is greater than the thickness t1 of the second circuit pattern 7. Specifically, the thickness t2 of the first region 11-1 of the first protective layer 11 is approximately 10 μm to 30 μm larger than the thickness t1 of the second circuit pattern 7. For example, the thickness t2 of the first region 11-1 of the first protective layer 11 is 20 μm to 65 μm.

At this time, a depression is formed in the first region 11-1 of the first protective layer 11 in the comparative example.

Specifically, a first recess (u1) is formed on the first side wall (11-11) of the first region (11-1) of the first protective layer (11) adjacent to the 2-1 pad (7-21). is formed. In addition, a second recess u2 is formed on the second side wall 11-12 of the first region 11-1 of the first protective layer 11 adjacent to the 2-2 pad 7-22. is formed

At this time, in the comparative example, the depth of the opening SOR1 of the first region 11-1 of the first protective layer 11 is the depth of the first region 11-1 of the first protective layer 11. Corresponds to thickness (t2). In addition, in the comparative example, exposure and curing of the lower region of the first region 11-1 were not completely achieved, and accordingly, the first sidewall 11-11 and the second sidewall 11-11 of the first region 11-1 The first recess (u1) and the second recess (u2) are formed in the side walls 11-12.

Here, the horizontal distance w1 of the first depression u1 and the second depression u2 in the comparative example has a minimum of 40 μm or more. Here, the horizontal distance w1 of the first depression u1 is the distance of the first depression u1 from the outermost end of the first side wall 11-11 of the first area 11-1. It can mean the horizontal distance to the innermost end. And, the horizontal distance (w1) of the second depression (u2) is determined from the outermost end of the second side wall (11-12) of the first area (11-1) to the extreme edge of the second depression (u2). It may mean the horizontal distance to the medial end.

And, in the comparative example, considering the horizontal distance (w1) of the first depression (u1) and the second depression (u2), the width (w2) of the first region (11-1) is at least 90㎛. have more than

And, the separation distance w3 between the first side wall 11-11 of the first region 11-1 of the first protective layer 11 and the 2-1 pad 7-21, and the first pad 7-21. 2 The separation distance (w3) between the side wall (11-12) and the 2-2 pad (7-22) has a minimum of 15㎛ or more.

Accordingly, in the comparative example, at a position corresponding to the first region 11-1 of the first protective layer 11, the 2-1 pad 7-21 and the 2-2 pad 7 -22) The spacing (w4) between them has a minimum of 120㎛.

At this time, in the comparative example, in order to reduce the separation distance between the 2-1 pad (7-21) and the 2-2 pad (7-22), the first region of the first protective layer 11 ( The width of 11-1) was reduced.

For example, as shown in FIG. 1C, in the comparative example, the first area (11-1a) of the first protective layer 11 has a width (w2-1) smaller than 90㎛, and the second- The separation distance between the first pad (7-21) and the second-second pad (7-22) was reduced. However, when the width w2-1 of the first region 11-1a is less than 90㎛, the process of forming the opening SOR1 in the lower part of the first region 11-1a In , a communication part (CR1) is formed in which the first recess (u1) and the second recess (u2) communicate with each other.

Accordingly, in the comparative example, after placing the solder balls 13 on the 2-1 pad (7-21) and the 2-2 pad (7-22), the solder balls 13 are reflowed. In the process, there is a problem that a circuit short occurs as a part 13-1 of the solder ball 13 penetrates into the communication part CR1. For example, in the comparative example, a portion 13-1 of the solder ball 13 disposed on the 2-1 pad 7-21 penetrates into the communication portion CR1 and the 2-2 pad ( There is a problem that a short circuit occurs as the 2-1 pad 7-21 and the 2-2 circuit pattern 7, which are in contact with 7-22) and thus must be electrically separated from each other, are connected to each other.

Meanwhile, as shown in FIG. 1D, the first protective layer 11 includes a second area 11-2 disposed between the second pad 7-2 and the trace 7-3.

The second region 11-2 of the first protective layer 11 includes an NSMD-type opening SOR2 exposing the upper surface of the second pad 7-2, and the second pad 72-2 ) and may be an area covering the adjacent second circuit pattern 7 (eg, trace 7-3).

Additionally, a depression u3 is formed in the first side wall 11-21 of the second area 11-2 adjacent to the second pad 7-2. And, the horizontal distance (w1) of the depression (u3) has a minimum of 40㎛ or more.

In addition, in the comparative example, considering the horizontal distance (w1) of the depression (u3), the first side wall (11-21) of the second region (11-2) and the second region (11-2) The width (w5) between the edges (7-31) of the trace (7-3) covered by has a minimum of 45㎛.

Accordingly, in the comparative example, at a position corresponding to the second region 11-2 of the first protective layer 11, the spacing between the second pad 7-2 and the trace 7-3 The gap (w6) has a minimum of 60㎛.

At this time, in the comparative example, the width w5 was reduced to reduce the spacing between the second pad 7-2 and the trace 7-3.

For example, as shown in FIG. 1E, in the comparative example, the first sidewall 11-21 of the second area 11-2 and the trace 7- covered by the second area 11-2 3), the width (w5-1) between the edges (7-31) is smaller than 45㎛, so that the spacing (w6-) between the second pad (7-2) and the trace (7-3) 1) was reduced. However, when the width (w5-1) is smaller than 45㎛, the trace (7) is formed by the depression (u3) created in the process of forming the opening (SOR2) of the second region (11-2). A problem occurred where the edge of -3) was exposed.

And, in the comparative example, after placing the solder ball 14 on the second pad 7-2, in the process of reflowing the solder ball 14, a portion of the solder ball 14 (14) -1) penetrates into the recess (u3), and as a result, there is a problem that a short occurs as it contacts the side of the trace (7-3) exposed through the recess (u3).

In addition, the third region 11-3 of the first protective layer 11 is an SMD type disposed on the first pad 7-1 and exposes the upper surface of the first pad 7-1. It may be an area containing an opening. While exposing the central area of the top surface of the first pad 7-1 in the third area 11-3 of the first protective layer 11, the edge area of the top surface of the first pad 7-1 It functions to protect.

As described above, in the comparative example, the depth of the opening formed in the first protective layer 11 corresponds to the thickness t2 of the first protective layer 11, and accordingly, the first protective layer 11 A depression with a horizontal distance of 40 μm or more is formed on the side wall of the opening. The horizontal distance refers to the horizontal distance from the outermost end of the side wall of the opening to the innermost end of the depression. In the comparative example, as the design of the second circuit pattern 7 was designed considering the horizontal distance of the depression, the pads or traces constituting the second circuit pattern 7, or between the pad and the trace There is a problem that the separation distance between them increases. Accordingly, in the comparative example, there is a problem in that the circuit integration is lowered and the overall volume of the circuit board in the horizontal direction increases accordingly.

In addition, as the performance of electrical/electronic products has recently improved, technologies for attaching a larger number of packages to a limited-sized substrate are being researched, and thus, there is a demand for finer circuit patterns. However, in the case of a package substrate using the circuit board of the comparative example, there is a limit to reducing the spacing between the second circuit patterns 7. Additionally, as the number of functions processed in an application processor (AP) has recently increased, it has become difficult to implement them on a single chip. However, using the circuit board provided in the comparative example, it is difficult to mount two application processors (APs) performing different functions within a limited space.

The embodiment is intended to solve the problem of the comparative example, and the width of the dam of the protective layer disposed between a plurality of pads can be reduced. Additionally, embodiments may optimize the slope of the side walls of the protective layer in the open areas. Additionally, the embodiment may remove depressions formed on the sidewall of the protective layer in the open area. Additionally, the embodiment can minimize the horizontal distance of the depression formed on the side wall of the protective layer in the open area. Additionally, embodiments may reduce the spacing between pads. Through this, the embodiment provides a semiconductor package in which a plurality of logic chips are arranged on one circuit board. For example, an embodiment provides a semiconductor package in which a plurality of processor chips or memory chips performing different functions are mounted on a single circuit board.

-former device -

Before describing the embodiment, an electronic device to which the semiconductor package of the embodiment is applied will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and/or electrically connected to various components. For example, the main board may be connected to the semiconductor package of the embodiment. Various semiconductor devices may be mounted on the semiconductor package.

The semiconductor device may include active devices and/or passive devices. Active devices may be semiconductor chips in the form of integrated circuits (ICs) in which hundreds to millions of devices are integrated into one chip. Semiconductor devices may be logic chips, memory chips, etc. The logic chip may be a central processor (CPU), a graphics processor (GPU), or the like. For example, the logic chip is an application processor (AP) chip that includes at least one of a central processor (CPU), graphics processor (GPU), digital signal processor, cryptographic processor, microprocessor, microcontroller, or an analog-digital chip. It could be a converter, an application-specific IC (ASIC), or a set of chips containing a specific combination of the ones listed so far.

The memory chip may be a stack memory such as HBM. Additionally, the memory chip may include memory chips such as volatile memory (eg, DRAM), non-volatile memory (eg, ROM), and flash memory.

Meanwhile, the product lines to which the semiconductor package of the embodiment is applied include Chip Scale Package (CSP), Flip Chip-Chip Scale Package (FC-CSP), Flip Chip Ball Grid Array (FC-BGA), Package On Package (POP), and SIP ( System In Package), but is not limited to this.

In addition, the electronic devices include smart phones, personal digital assistants, digital video cameras, digital still cameras, vehicles, high-performance servers, and network systems. ), computer, monitor, tablet, laptop, netbook, television, video game, smart watch, automotive It may be, etc. However, it is not limited to this, and of course, it can be any other electronic device that processes data.

Hereinafter, a semiconductor package including a circuit board according to an embodiment will be described. The semiconductor package of the embodiment may have various package structures including a circuit board, which will be described later. And in one embodiment, the circuit board may be a package board described below, and in another embodiment, the circuit board may be an interposer described below.

FIG. 2A is a cross-sectional view showing a semiconductor package according to a first embodiment, FIG. 2B is a cross-sectional view showing a semiconductor package according to a second embodiment, FIG. 2C is a cross-sectional view showing a semiconductor package according to a third embodiment, and FIG. 2D is a cross-sectional view showing a semiconductor package according to the fourth embodiment, FIG. 2E is a cross-sectional view showing a semiconductor package according to the fifth embodiment, FIG. 2F is a cross-sectional view showing a semiconductor package according to the sixth embodiment, and FIG. 2G is a cross-sectional view showing a semiconductor package according to the sixth embodiment. This is a cross-sectional view showing a semiconductor package according to Example 7.

Referring to FIG. 2A , the semiconductor package of the first embodiment may include a first substrate 1100, a second substrate 1200, and a semiconductor device 1300.

The first substrate 1100 refers to a package substrate.

For example, the first substrate 1100 may provide a space where at least one external substrate is coupled. The external substrate may refer to a second substrate 1200 coupled to the first substrate 1100. Additionally, the external substrate may refer to a main board included in an electronic device coupled to the lower portion of the first substrate 1100.

Additionally, although not shown in the drawing, the first substrate 1100 may provide a space where at least one semiconductor device is mounted.

The first substrate 1100 includes at least one insulating layer, an electrode disposed on the at least one insulating layer, and a penetration portion penetrating the at least one insulating layer.

A second substrate 1200 is disposed on the first substrate 1100.

The second substrate 1200 may be an interposer. For example, the second substrate 1200 may provide a space where at least one semiconductor device is mounted. The second substrate 1200 may be connected to the at least one semiconductor device 1300. For example, the second substrate 1200 may provide a space where the first semiconductor device 1310 and the second semiconductor device 1320 are mounted. The second substrate 1200 electrically connects the first semiconductor device 1310 and the second semiconductor device 1320, and connects the first and second semiconductor devices 1310 and 1320 to the first substrate ( 1100) can be electrically connected. That is, the second substrate 1200 can function as a horizontal connection between a plurality of semiconductor devices and a vertical connection between the semiconductor devices and the package substrate.

In FIG. 2, two semiconductor devices 1310 and 1320 are shown disposed on the second substrate 1200, but the present invention is not limited thereto. For example, one semiconductor device may be disposed on the second substrate 1200, or alternatively, three or more semiconductor devices may be disposed on the second substrate 1200.

The second substrate 1200 may be disposed between the semiconductor device 1300 and the first substrate 1100.

In one embodiment, the second substrate 1200 may be an active interposer that functions as a semiconductor device. When the second substrate 1200 functions as a semiconductor device, the package of the embodiment may have a vertical stacked structure and a plurality of logic chips may be mounted on the first substrate 1100. And among the logic chips, a first logic chip corresponding to the active interposer functions as the corresponding logic chip and performs a signal transmission function between the second logic chip disposed on top of the logic chip and the first substrate 1100. You can.

According to another embodiment, the second substrate 1200 may be a passive interposer. For example, the second substrate 1200 may function as a signal relay between the semiconductor device 1300 and the first substrate 1100. For example, the number of terminals of the semiconductor device 1300 is gradually increasing due to 5G, Internet of Things (IOT), increased image quality, increased communication speed, etc. That is, the number of terminals provided in the semiconductor device 1300 increases, and as a result, the width of the terminal or the gap between a plurality of terminals is reduced. At this time, the first substrate 1100 is connected to the main board of the electronic device. Accordingly, in order for the electrodes provided on the first substrate 1100 to have a width and spacing for being connected to the semiconductor device 1300 and the main board, the thickness of the first substrate 1100 must be increased, or the thickness of the first substrate 1100 must be increased. There is a problem that the layer structure of the first substrate 1100 becomes complicated. Accordingly, in the first embodiment, the second substrate 1200 is disposed on the first substrate 1100 and the semiconductor device 1300. And the second substrate 1200 may include electrodes having a fine width and spacing corresponding to the terminals of the semiconductor device 1300.

The semiconductor device 1300 may be a logic chip, a memory chip, or the like. The logic chip may be a central processor (CPU), a graphics processor (GPU), or the like. For example, the logic chip is an AP that includes at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, a cryptographic processor, a microprocessor, and a microcontroller, or an analog-to-digital converter, an ASIC (application -specific IC), etc., or it may be a chip set containing a specific combination of those listed so far. And the memory chip may be a stack memory such as HBM. Additionally, the memory chip may include memory chips such as volatile memory (eg, DRAM), non-volatile memory (eg, ROM), and flash memory.

Meanwhile, the semiconductor package of the first embodiment may include a connection part.

For example, the semiconductor package includes a first connection portion 1410 disposed between the first substrate 1100 and the second substrate 1200. The first connection portion 1410 couples the second substrate 1200 to the first substrate 1100 and electrically connects them.

For example, the semiconductor package may include a second connection portion 1420 disposed between the second substrate 1200 and the semiconductor device 1300. The second connection part 1420 may couple the semiconductor device 1300 to the second substrate 1200 and electrically connect them.

The semiconductor package includes a third connection portion 1430 disposed on the lower surface of the first substrate 1100. The third connection part 1430 can connect the first substrate 1100 to the main board and electrically connect them.

At this time, the first connection part 1410, the second connection part 1420, and the third connection part 1430 electrically connect a plurality of components using at least one bonding method among wire bonding, solder bonding, and direct metal-to-metal bonding. You can connect with . That is, because the first connection part 1410, the second connection part 1420, and the third connection part 1430 have the function of electrically connecting a plurality of components, when direct bonding between metals is used, the semiconductor package is solder or It can be understood as an electrically connected part rather than a wire.

The wire bonding method may mean electrically connecting a plurality of components using conductors such as gold (Au). Additionally, the solder bonding method can electrically connect a plurality of components using a material containing at least one of Sn, Ag, and Cu. In addition, the direct bonding method between metals may mean recrystallization by applying heat and pressure between a plurality of components without the absence of solder, wire, conductive adhesive, etc., thereby directly bonding the plurality of components. . And, the direct bonding method between metals may refer to a bonding method using the second connection part 1420. In this case, the second connection portion 1420 may refer to a metal layer formed between a plurality of components through recrystallization.

Specifically, the first connection part 1410, the second connection part 1420, and the third connection part 1430 may be connected to a plurality of components using a TC (Thermal Compression) bonding method. The TC bonding may refer to a method of directly bonding a plurality of components by applying heat and pressure to the first connection part 1410, the second connection part 1420, and the third connection part 1430.

At this time, in at least one of the first substrate 1100 and the second substrate 1200, a protrusion is disposed on the electrode where the first connection portion 1410, the second connection portion 1420, and the third connection portion 1430 are disposed. It can be. The protrusion may protrude outward from the first substrate 1100 or the second substrate 1200.

The protrusion may be referred to as a bump. The protrusion may also be referred to as a post. The protrusion may also be referred to as a pillar. Preferably, the protrusion may refer to an electrode of the second substrate 1200 on which the second connection portion 1420 for coupling to the semiconductor device 1300 is disposed. That is, as the pitch of the terminals of the semiconductor device 1300 becomes finer, a short circuit may occur in the second connection portions 1420 respectively connected to the terminals of the semiconductor device 1300. Accordingly, in the embodiment, in order to reduce the volume of the second connection part 1420, the electrode of the second substrate 1200 on which the second connection part 1420 is disposed includes a protrusion. The protrusion may prevent the matching between the electrode of the second substrate 1200 and the terminal of the semiconductor device 1300 and diffusion of the second connection portion 1420.

Meanwhile, referring to FIG. 2B, the semiconductor package of the second embodiment differs from the semiconductor package of the first embodiment in that the connecting member 1210 is disposed on the second substrate 1200. The connecting member 1210 may be referred to as a bridge substrate. For example, the connecting member 1210 may include a redistribution layer.

In one embodiment, connecting member 1210 may be a silicon bridge. That is, the connecting member 1210 may include a silicon substrate and a redistribution layer disposed on the silicon substrate.

In another embodiment, the connecting member 1210 may be an organic bridge. For example, the connecting member 1210 may include an organic material. For example, the connecting member 1210 includes an organic substrate containing an organic material instead of the silicon substrate.

The connecting member 1210 may be embedded in the second substrate 1200, but is not limited thereto. For example, the connecting member 1210 may be disposed on the second substrate 1200 to have a protruding structure.

Additionally, the second substrate 1200 may include a cavity, and the connecting member 1210 may be disposed within the cavity of the second substrate 1200.

The connecting member 1210 may horizontally connect a plurality of semiconductor devices disposed on the second substrate 1200.

Referring to FIG. 2C, the semiconductor package of the third embodiment includes a second substrate 1200 and a semiconductor device 1300. At this time, the semiconductor package of the third embodiment has a structure in which the first substrate 1100 is removed compared to the semiconductor package of the second embodiment.

That is, the second substrate 1200 of the third embodiment can function as an interposer and a package substrate.

The first connection portion 1410 disposed on the lower surface of the second substrate 1200 may couple the second substrate 1200 to the main board of the electronic device.

Referring to FIG. 2D, the semiconductor package of the fourth embodiment includes a first substrate 1100 and a semiconductor device 1300.

At this time, the semiconductor package of the fourth embodiment has a structure in which the second substrate 1200 is removed compared to the semiconductor package of the second embodiment.

That is, the first substrate 1100 of the fourth embodiment can function as a package substrate and an interposer that connects the semiconductor device 1300 and the main board. To this end, the first substrate 1100 may include a connecting member 1110 for connecting a plurality of semiconductor devices. The connecting member 1110 may be a silicon bridge or an organic bridge that connects a plurality of semiconductor devices.

Referring to FIG. 2E, the semiconductor package of the fifth embodiment further includes a third semiconductor element 1330 compared to the semiconductor package of the fourth embodiment.

For this purpose, a fourth connection portion 1440 is disposed on the lower surface of the first substrate 1100.

Additionally, a third semiconductor device 1330 may be disposed on the fourth connection portion 1400. That is, the semiconductor package of the fifth embodiment may have a structure in which semiconductor devices are mounted on the upper and lower sides, respectively.

At this time, the third semiconductor device 1330 may have a structure disposed on the lower surface of the second substrate 1200 in the semiconductor package of FIG. 2C.

Referring to FIG. 2F, the semiconductor package of the sixth embodiment includes a first substrate 1100.

A first semiconductor device 1310 may be disposed on the first substrate 1100. For this purpose, a first connection portion 1410 is disposed between the first substrate 1100 and the first semiconductor device 1310.

Additionally, the first substrate 1100 includes a conductive coupling portion 1450. The conductive coupling portion 1450 may protrude further from the first substrate 1100 toward the second semiconductor device 1320. The conductive coupling portion 1450 may be referred to as a bump or, alternatively, may be referred to as a post. The conductive coupling portion 1450 may be disposed with a protruding structure on the electrode disposed on the uppermost side of the first substrate 1100.

A second semiconductor device 1320 is disposed on the conductive coupling portion 1450 of the first substrate 1100. At this time, the second semiconductor device 1320 may be connected to the first substrate 1100 through the conductive coupling portion 1450. Additionally, a second connection portion 1420 may be disposed on the first semiconductor device 1310 and the second semiconductor device 1320.

Accordingly, the second semiconductor device 1320 may be electrically connected to the first semiconductor device 1310 through the second connection portion 1420.

That is, the second semiconductor device 1320 is connected to the first substrate 1100 through the conductive coupling portion 1450 and is also connected to the first semiconductor device 1310 through the second connection portion 1420.

At this time, the second semiconductor device 1320 can receive a power signal through the conductive coupling portion 1450. Additionally, the second semiconductor device 1320 may exchange communication signals with the first semiconductor device 1310 through the second connection unit 1420.

The semiconductor package of the sixth embodiment provides a power signal to the second semiconductor device 1320 through the conductive coupling portion 1450, thereby providing sufficient power to drive the second semiconductor device 1320. Accordingly, the embodiment can improve the driving characteristics of the second semiconductor device 1320. That is, the embodiment can solve the problem of insufficient power provided to the second semiconductor device 1320. Furthermore, the embodiment allows the power signal and communication signal of the second semiconductor device 1320 to be provided through different paths through the conductive coupling portion 1450 and the second connection portion 1420. Through this, the embodiment can solve the problem of loss of the communication signal caused by the power signal. For example, embodiments may minimize mutual interference between power signals and communication signals. Meanwhile, the second semiconductor device 1320 in the sixth embodiment may have a POP structure and be disposed on the first substrate 1100. For example, the second semiconductor device 1320 may be a memory package including a memory chip. And the memory package may be coupled to the conductive coupling portion 1450. At this time, the memory package may not be connected to the first semiconductor device 1310.

Referring to FIG. 2G, the semiconductor package of the seventh embodiment includes a first substrate 1100, a first connection part 1410, a first connection part 1410, a semiconductor device 1300, and a third connection part 1430.

At this time, the semiconductor package of the seventh embodiment differs from the semiconductor package of the fourth embodiment in that the connecting member 1110 is removed and the first substrate 1100 includes a plurality of substrate layers.

The first substrate 1100 includes a plurality of substrate layers. For example, the first substrate 1100 may include a first substrate layer 1100A corresponding to the package substrate and a second substrate layer 1100B corresponding to the redistribution layer of the connection member.

That is, in the first substrate 1100, the second substrate layer 1100B corresponding to the redistribution layer is disposed on the first substrate layer 1100A.

In other words, the semiconductor package of the seventh embodiment includes a first substrate layer 1100A and a second substrate layer 1100B formed integrally. The material of the insulating layer of the second substrate layer 1100B may be different from the material of the insulating layer of the first substrate layer 1100A. For example, the material of the insulating layer of the second substrate layer 1100B may include a photocurable material. For example, the second substrate layer 1100B may be a photo imageable dielectric (PID). In addition, since the second substrate layer 1100B contains a photocurable material, the electrode can be miniaturized. Therefore, in the seventh embodiment, an insulating layer of a photo-curable material is sequentially stacked on the first substrate layer 1100A, and a micronized electrode is formed on the insulating layer of the photo-curable material, thereby forming a second substrate layer ( 1100B) can be formed. Through this, the second substrate 1100B may be a redistribution layer including miniaturized electrodes.

Below, the circuit board of the embodiment will be described.

Prior to describing the circuit board of the embodiment, the circuit board described below may refer to any one of a plurality of substrates included in a previous semiconductor package.

For example, in one embodiment, the circuit board described below may refer to the first substrate 1100 shown in any one of FIGS. 2A to 2G. Additionally, the circuit board described below in another embodiment may refer to the second substrate 1200 shown in any one of FIGS. 2A to 2G.

-Circuit board-

FIG. 3A is a cross-sectional view of a circuit board according to an embodiment, and FIG. 3B is a plan view of the circuit board of FIG. 3A viewed from above.

First, with reference to FIGS. 3A and 3B, the overall structure of the circuit board according to the embodiment will be described. However, in FIG. 3B, the entire upper surface of the trace 124 of the first circuit pattern layer 120 is shown as exposed, but this is only for convenience of explanation, and in reality, the entire upper surface of the trace 124 of the first circuit pattern layer 120 is exposed. The trace 124 is covered by the second portion 190b of the first protective layer 190.

Referring to FIGS. 3A and 3B , the circuit board may include an insulating layer 110, a circuit pattern layer, a penetration portion, and a protective layer. At this time, the protective layer may mean another insulating layer disposed on the insulating layer 110 of the circuit board. However, the embodiment will be described by referring to the other insulating layer as a protective layer to distinguish between them.

The insulating layer 110 may have a multiple layer structure. For example, the insulating layer 110 may include a first insulating layer 111, a second insulating layer 112, and a third insulating layer 113. At this time, the circuit board is shown in the drawing as having a three-layer structure based on the number of layers of the insulating layer, but the circuit board is not limited to this. For example, the circuit board may have a structure of two or less layers based on the number of insulating layers, or alternatively, it may have a structure of four or more layers. Preferably, due to the increase in functions provided in recent circuit boards, the circuit board may have 10 or more layers, 12 or more layers, 15 or more layers, or 20 or more layers based on the number of layers of the insulating layer.

For example, the first insulating layer 111 may be a first outermost insulating layer disposed on the first outermost side in a multi-layer structure. For example, the first insulating layer 111 may be an insulating layer disposed on the uppermost side of the circuit board. The second insulating layer 112 may be an inner insulating layer disposed on the inside of a multi-layered circuit board. The third insulating layer 113 may be a second outermost insulating layer disposed on the second outermost side in a multilayer structure. For example, the third insulating layer 113 may be an insulating layer disposed on the lowermost side of the circuit board. In addition, the inner insulating layer is shown as being composed of one layer, but differently, it may be composed of two or more layers.

The insulating layer 110 is a board on which an electric circuit whose wiring can be changed is organized, and may include a print, a wiring board, and an insulating board made of an insulating material capable of forming circuit patterns on the surface.

The insulating layer 110 of the circuit board 100 may be rigid or flexible. For example, the insulating layer 110 of the circuit board 100 may include glass or plastic. For example, the insulating layer 110 of the circuit board 100 may include chemically strengthened/semi-strengthened glass such as soda lime glass or aluminosilicate glass. For example, the insulating layer 110 of the substrate 100 is reinforced with polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), polycarbonate (PC), etc. May contain soft plastic. For example, the insulating layer 110 of the substrate 100 may include sapphire. For example, the insulating layer 110 of the substrate 100 may include an optically isotropic film. For example, the insulating layer 110 of the substrate 100 is made of Cyclic Olefin Copolymer (COC), Cyclic Olefin Polymer (COP), wide isotropic polycarbonate (PC), or wide isotropic polymethyl methacrylate (PMMA). It can be included. For example, the insulating layer 110 of the circuit board 100 may be formed of a material containing an inorganic filler and an insulating resin. For example, the insulating layer 110 of the substrate 100 may have a structure in which an inorganic filler of silica or alumina is disposed on a thermosetting resin or thermoplastic resin.

Specifically, in one embodiment, the insulating layer 100 of the substrate 100 includes a first insulating layer including reinforcing fibers, and a second insulating layer disposed above and below the first insulating layer and not including reinforcing fibers. May include layers. Accordingly, the circuit board 100 may be a core board.

Additionally, in another embodiment, the insulating layer 100 of the circuit board 100 may be composed only of an insulating layer that does not include reinforcing fibers. Accordingly, the circuit board 100 may be a coreless board.

The insulating layer 110 of the circuit board 100 of one embodiment has excellent processability, excellent rigidity, enables slimming of the board 100, and the circuit pattern layer 120 of the circuit board 100. It may contain an organic material that does not contain a micronizable reinforcing member. The reinforcing member may also be referred to as reinforcing fiber or glass fiber.

For example, the insulating layer 110 of the circuit board 100 may be made of Ajinomoto Build-up Film (ABF), FR-4, Bismaleimide Triazine (BT), Photo Imageable Dielectric Resin (PID), BT, etc. .

At this time, when the insulating layer 110 of the circuit board 100 is made of Ajinomoto build-up film (ABF), the bending characteristics of the circuit board 100 may be deteriorated.

Accordingly, the insulating layer 110 of the circuit board 100 in another embodiment is composed of ABF (Ajinomoto Build-up Film), and at least one ABF among the ABFs constituting the plurality of insulating layers of the circuit board 100 May contain reinforcing materials that can improve flexural properties.

For example, the insulating layer 110 of the circuit board 100 includes a layer composed of first ABF including resin and filler. Additionally, the insulating layer 110 of the circuit board 100 includes a layer composed of a second ABF in which a reinforcing material is further included in the first ABF. At this time, the reinforcing material included in the second ABF may be glass fiber and may include a GCP (Glass Core Primer) material, but is not limited thereto.

A circuit pattern layer may be disposed on the surface of the insulating layer 110.

For example, the first circuit pattern layer 120 may be disposed on the first or top surface of the first insulating layer 111. For example, the second circuit pattern layer 130 may be disposed between the second or lower surface of the first insulating layer 111 and the first or upper surface of the second insulating layer 112. For example, the third circuit pattern layer 140 may be disposed between the second or lower surface of the second insulating layer 112 and the first or upper surface of the third insulating layer 113. For example, the fourth circuit pattern layer 150 may be disposed on the second or lower surface of the third insulating layer 113. The first circuit pattern layer 120 may be a circuit pattern layer disposed on the first outermost side, the first outermost side, or the uppermost side in the thickness direction of the circuit board. Additionally, the second circuit pattern layer 130 and the third circuit pattern layer 140 may be inner circuit pattern layers disposed inside the circuit board. Additionally, the fourth circuit pattern layer 150 may be a circuit pattern layer disposed on the second outermost side, second outermost side, or lowermost side in the thickness direction of the circuit board.

The first circuit pattern layer 120, the second circuit pattern layer 130, the third circuit pattern layer 140, and the fourth circuit pattern layer 150 are wires that transmit electrical signals, and are metals with high electrical conductivity. It can be formed from materials. To this end, the first circuit pattern layer 120, the second circuit pattern layer 130, the third circuit pattern layer 140, and the fourth circuit pattern layer 150 are made of gold (Au), silver (Ag), It may be formed of at least one metal material selected from platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). In addition, the first circuit pattern layer 120, the second circuit pattern layer 130, the third circuit pattern layer 140, and the fourth circuit pattern layer 150 are gold (Au) and silver (Ag) with excellent bonding power. ), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn) may be formed as a paste or solder paste containing at least one metal material selected from among. Preferably, the first circuit pattern layer 120, the second circuit pattern layer 130, the third circuit pattern layer 140, and the fourth circuit pattern layer 150 are made of copper (which has high electrical conductivity and is relatively inexpensive). Cu).

The first circuit pattern layer 120, the second circuit pattern layer 130, the third circuit pattern layer 140, and the fourth circuit pattern layer 150 are formed using the additive method ( Additive process, subtractive process, MSAP (Modified Semi Additive Process), and SAP (Semi Additive Process) methods are available, and detailed descriptions are omitted here.

Meanwhile, each of the first to fourth circuit pattern layers 120, 130, 140, and 150 includes traces and pads.

Trace refers to a long line-shaped wiring that transmits electrical signals. Additionally, the pad may refer to a mounting pad on which components such as chips are mounted, a core pad or BGA pad for connection to an external board, or a penetrating portion pad connected to a penetrating portion.

A penetrating portion may be formed in the insulating layer 110. The penetrating portion is formed to penetrate the insulating layer 110, and thus can electrically connect circuit pattern layers disposed on different layers. The through portion may also be expressed as a through electrode or via.

For example, a first penetrating portion 160 may be formed in the first insulating layer 111. The first penetration portion 160 penetrates the first insulating layer 111, and thus can electrically connect the first circuit pattern layer 120 and the second circuit pattern layer 130.

For example, a second penetrating portion 170 may be formed in the second insulating layer 112. The second penetration portion V2 penetrates the second insulating layer 112, and thus can electrically connect the second circuit pattern layer 130 and the third circuit pattern layer 140. At this time, the second insulating layer 112 may be a core layer. Also, when the second insulating layer 112 is a core layer, the second penetration portion 170 may have an hourglass shape.

For example, a third penetration part V3 may be formed in the third insulating layer 113. The third penetration part V3 penetrates the third insulating layer 113, and thus can electrically connect the third circuit pattern layer 140 and the fourth circuit pattern layer 150.

The penetration parts 160, 170, and 180 as described above may be formed by filling the inside of the penetration hole formed in each insulating layer with a metal material. The through hole may be formed by any one of mechanical, laser, and chemical processing. When the through hole is formed by machining, methods such as milling, drilling, and routing can be used. When the through hole is formed by laser processing, UV or CO ₂ laser methods can be used. When the penetrating hole is formed through chemical processing, chemicals containing aminosilanes, ketones, etc. can be used.

Once the through hole is formed, the inside of the through hole can be filled with a conductive material to form the through portions 160, 170, and 180. The penetration portions 160, 170, and 180 are formed of any one metal material selected from copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd). It can be. In addition, the conductive material filling may be performed using any one of electroless plating, electrolytic plating, screen printing, sputtering, evaporation, ink jetting, and dispensing, or a combination thereof. .

Meanwhile, a first protective layer 190 may be disposed on the first or top surface of the first insulating layer 111. The first protective layer 190 may include solder resist. The first protective layer 190 may refer to another insulating layer disposed between the first insulating layer 111. Therefore, the first to third insulating layers 111, 112, and 113 corresponding to the insulating layer 110 may also be referred to as a 'first insulating layer', and the first protective layer 190 may be referred to as a second insulating layer. It can also be said that

The first protective layer 190 may include an opening (SOR) exposing the surface of the first circuit pattern layer 190. For example, the first protective layer 190 may include an opening SOR that exposes the pads 121, 122, and 123 of the first circuit pattern layer 120.

Correspondingly, a second protective layer 195 may be disposed on the second surface of the third insulating layer 113. The second protective layer 195 may include solder resist. The second protective layer 195 may include an opening (not shown) exposing the surface of the pad (not shown) of the fourth circuit pattern layer 150. Additionally, the second protective layer 195 may also be referred to as a ‘third insulating layer.’

At this time, the first protective layer 190 may have a stepped structure. For example, the first protective layer 190 includes a first part 190a disposed on the upper surface of the first insulating layer 111, and a second part 190b disposed on the first part 190a. ) may include.

The first portion 190a of the first protective layer 190 may contact the upper surface of the first insulating layer 111. Additionally, the first portion 190a of the first protective layer 190 may contact a portion of the side surface of the first circuit pattern layer 120. Meanwhile, the first portion 190a of the first protective layer 190 may expose at least a portion of the side surface of the first circuit pattern layer 120.

Specifically, the thickness of the first portion 190a of the first protective layer 190 may be smaller than the thickness of the first circuit pattern layer 120. For example, the top surface of the first portion 190a of the first protective layer 190 may be located lower than the top surface of the first circuit pattern layer 120. Accordingly, the first portion 190a of the first protective layer 190 covers the lower area of the side surface of the first circuit pattern layer 120 and the upper portion of the side surface of the first circuit pattern layer 120. The area can be exposed.

The second part 190b of the first protective layer 190 may be disposed on the upper surface of the first part 190a of the first protective layer 190 and a portion of the first circuit pattern layer 120. . Additionally, the second portion 190b of the first protective layer 190 may include an opening SOR that exposes the top surface of another portion of the first circuit pattern layer 120. At this time, the width of the opening SOR of the second part 190b of the first protective layer 190 is the width of the first pad 121 of the first circuit pattern layer 120 exposed through the opening SOR. It can be larger than the width. Accordingly, the opening SOR of the second part 190b of the first protective layer 190 is located in the first part 190a of the first protective layer 190 adjacent to the first pad 121. The top surface and the upper area of the side of the first pad 121 may be exposed.

At this time, the depth of the opening (SOR) formed in the first protective layer 190 in the embodiment may be smaller than the thickness of the first protective layer 190. For example, the opening SOR of the first protective layer 190 is the thickness of the second portion 190b excluding the thickness of the first portion 190a from the total thickness of the first protective layer 190. It has as much depth as thickness. Therefore, in the embodiment, the opening SOR is formed only in the second part 190b of the first protective layer 190, excluding the first part 190a.

Accordingly, the embodiment can remove the undercut formed in the first protective layer 190. In addition, the embodiment allows the sidewall of the first protective layer 190 to have an inclination, thereby improving the flowability of a connection part such as a solder ball or a molding layer. Furthermore, the embodiment allows for reducing the horizontal distance of the depressions corresponding to the undercuts even if the first protective layer 190 is provided with depressions corresponding to the undercuts. The reason why the depression corresponding to the undercut can be removed or the horizontal distance of the depression can be reduced will be explained below.

Meanwhile, the first protective layer 190 may include a first region 191, a second region 192, and a third region 193.

The first area 191 of the first protective layer 190 may be an area where an opening exposing the top surface of the first pad 121 of the first circuit pattern layer 120 is formed. Additionally, the first area 191 of the first protective layer 190 may be an area where a portion of the first circuit pattern layer 120 is disposed adjacent to the first pad 121. For example, the first area 191 of the first protective layer 190 may be an area where the first pad 121 and an adjacent pattern disposed adjacent to the first pad 121 exist. The adjacent pattern may be either the trace 124 of the first circuit pattern layer 120 or the third pad 123. Accordingly, the first area 191 of the first protective layer 190 may be formed in an area where the trace 124 is disposed adjacent to the first pad 121. For example, the first area 191 of the first protective layer 190 is formed in the area where the first pad 121 and the third pad 123 are disposed adjacent to the first pad 121. It can be. And, the second portion 190b of the first region 191 of the first protective layer 190 covers the upper surface of the trace 124 or the third pad 121, and the first pad ( It may include an opening exposing 121).

The second area 192 of the first protective layer 190 may be an area where an opening is formed to expose the top surface of the second pad 122 of the first circuit pattern layer 120. In addition, the second region 192 of the first protective layer 190 exposes the upper surfaces of the plurality of second pads 122 adjacent to each other, and a different first circuit pattern is formed between the plurality of second pads 122. This may be an area where the layer 120 is not disposed.

The third area 193 of the first protective layer 190 may be an area where an opening exposing the top surface of the third pad 123 of the first circuit pattern layer 120 is formed. For example, the third area 193 of the first protective layer 190 may be an area including an opening smaller than the width of the third pad 123. For example, the third area 193 of the first protective layer 190 exposes the central area of the upper surface of the third pad 123 and covers the edge area of the upper surface of the third pad 123. It could be an area.

The first region 191, second region 192, and third region 193 of the first protective layer 190 will be described in more detail below.

Meanwhile, in the embodiment, the first protective layer 190 includes a first part 190a and a second part 190b having a step. The step may mean a step in the horizontal direction. For example, the sidewall of the first protective layer 1900 including the first part 190a and the second part 190b may have a step in the horizontal direction.

Also, depending on the embodiment, a depression corresponding to an undercut may be formed in the first protective layer 190 on the side wall of the second portion 190b. At this time, in the comparative example, a depression was substantially formed in the side wall of the first portion of the first protective layer. Accordingly, the depression formed in the first protective layer of the comparative example has a horizontal distance of at least 40 μm or more. In contrast, in the embodiment, when forming an opening in the first protective layer 190, the opening has a depth corresponding to the thickness of the second portion 190b in the entire thickness of the first protective layer 190. Let's have it. Accordingly, the horizontal distance of the depression in the embodiment is set to be 35% or less of the horizontal distance of the depression in the comparative example. For example, the horizontal distance of the depression in the embodiment is set to be 25% or less of the horizontal distance of the depression in the comparative example. For example, the horizontal distance of the depression in the embodiment is set to be 15% or less of the horizontal distance of the depression in the comparative example. For example, the horizontal distance of the depression in the embodiment is set to be 5% or less of the horizontal distance of the depression in the comparative example.

Furthermore, the embodiment makes it possible to remove the depression. Specifically, the first protective layer 190 in the embodiment may not be provided with the recess.

Hereinafter, the first protective layer 190 will first be described as being provided with a recess having a certain horizontal distance.

Specifically, the second portion 190b of the first protective layer 190 of the first embodiment may be provided with a recess. And, the horizontal distance of the depression in the first embodiment may exceed 0 μm and be 13 μm or less. For example, the horizontal distance of the depression in the first embodiment may exceed 0 μm and be 10 μm or less. For example, the horizontal distance of the depression in the first embodiment may exceed 0 μm and be 6 μm or less. For example, the horizontal distance of the depression in the first embodiment may exceed 0 μm and be 2 μm or less.

Here, horizontal may mean a plane parallel to the plane where the first circuit pattern layer 120 extends in the circuit board of the embodiment. Accordingly, the horizontal distance may mean the distance in the direction of a plane parallel to the plane where the first circuit pattern layer 120 extends. For example, the horizontal distance may mean a distance in the first direction corresponding to the width direction of the first circuit pattern layer 120. For example, the horizontal distance may mean a distance in the second direction corresponding to the longitudinal direction of the first circuit pattern layer 120. For example, the horizontal distance may mean a distance in a third direction corresponding to the diagonal direction between the width direction and the length direction of the first circuit pattern layer 120.

Below, it will be explained why the horizontal distance of the depression in the embodiment compared to the comparative example is reduced or the depression can be removed.

FIG. 4A is a diagram for explaining the exposure and curing process of the solder resist layer, FIG. 4B is a diagram for explaining the horizontal distance of the depression according to the thickness of the solder resist layer, and FIG. 4C is a diagram for explaining the development depth of the solder resist layer. This is a drawing to explain the horizontal distance of the groove along the line.

Referring to FIG. 4A, in order to form the first protective layer 190, a solder resist layer 190L is formed on the first insulating layer 111, and an opening SOR is formed in the solder resist layer 190L. A process of exposing the remaining area 190L1 excluding the area to be formed 190L2 is performed. At this time, the solder resist layer 190L can be formed by a screen printing method, roller coating method, curtain coating method, spray coating method, and solder resist film lamination method. However, it is not limited to this. In the case of screen printing, a solder resist pattern is directly printed using plate making. In this case, exposure and development are not required, and curing can be performed immediately. In the case of the roller coating method, a photocurable resin with a lower viscosity than that used in the screen printing method can be applied thinly to a roller made of rubber or other material to coat the substrate. However, with this method, it is difficult to control the thickness of the solder resist layer coated depending on the substrate, and it may be difficult to create a uniform coating layer. In the case of the curtain coating method, a photocurable resin with a lower viscosity than that used in roller coating is used, and the photocurable resin is sent through a slit (not shown) and a solder resist layer is created while passing the substrate under the slit. This is a coating method. This method can achieve very uniform coating quality and can be applied without limitation to the size of the substrate. Spray coating is a method of coating by spraying photocurable resin ink, and may have the advantage of being easy to control the thickness of the solder resist layer.

Meanwhile, in the exposure process, a mask (not shown) is formed on the area 190L2 where the opening SOR is to be formed to prevent light such as ultraviolet rays from transmitting, and accordingly, ultraviolet rays etc. are transmitted into the remaining area 190L1. This can be done by irradiating light.

At this time, even if uniform light is irradiated to the remaining area 190L1, the amount of light irradiated in the thickness direction of the remaining area 190L1 is different, and accordingly, the exposure in the thickness direction of the remaining area 190L1 is different. The degree varies.

For example, the remaining area 190L1 where the exposure is performed includes, based on the thickness direction, an upper area 190L1T adjacent to the upper surface of the solder resist layer 190L, a lower surface of the solder resist layer 190L, and It may be divided into an adjacent lower area 190L1B, and an intermediate area 190L1C between the upper area 190L1T and the lower area 190L1B.

When light is irradiated from the upper surface of the solder resist layer 190L, the amount of light irradiated to the upper region 190L1T, the amount of light irradiated to the middle region 190L1C, and the amount of light irradiated to the lower region 190L1B The amount of light produced is different. Specifically, the amount of irradiated light decreases from the upper area 190L1T to the lower area 190L1B.

Accordingly, when the exposure degree of the upper region 190L1T of the solder resist layer 190L is 100% by the exposure process, the exposure degree of the middle region 190L1C is equal to the exposure degree of the upper region 190L1T. It has a level of about 90%, which is less than the exposure level, and the exposure level of the lower area 190L1B has a level of 80% or less, which is less than the exposure level of the middle area 190L1C.

And, after the exposure process as described above, a curing process may be performed on the remaining exposed area 190L1. At this time, as the degree of exposure in each area is different, the degree of curing also appears different. For example, when the curing degree of the upper region (190L1T) of the solder resist layer (190L) is 100%, the curing degree of the middle region (190L1C) is about 90%, which is less than the curing degree of the upper region (190L1T). and the degree of curing of the lower region (190L1B) is less than the degree of curing of the middle region (190L1C) of 80% or less.

Accordingly, after the curing process proceeds, when developing the area 190L2 where the uncured opening SOR is to be formed, the lower area 190L1B where the curing has not been completely completed is also performed. As the development progresses, etching occurs, resulting in the formation of a depression such as an undercut.

In addition, recently, in order to stably protect the first circuit pattern layer 120, the thickness of the solder resist layer 190L is gradually increasing. Accordingly, as the thickness of the solder resist layer 190L increases, the degree of curing of the lower region 190L1B decreases, and accordingly, the horizontal distance of the depression formed in the lower region 190L1B gradually increases.

Specifically, referring to FIG. 4B, the horizontal distance of the depression may increase in proportion to the thickness of the solder resist layer 190L. I in FIG. 4B refers to the uppermost insulating layer, and S1, S2, and S3 refer to solder resist layers formed on the uppermost insulating layer.

For example, as shown in (a) of FIG. 4B, when forming an opening having a first depth (Ta) in the solder resist layer (S1) having a first thickness (Ta), the depression is 'a ' It can have a horizontal distance (Wa).

And, as shown in (b) of FIG. 4B, a second depth greater than the first depth Ta is added to the solder resist layer S2 having a second thickness Tb greater than the first thickness Ta. When forming the opening (Tb), the recess has a 'b' horizontal distance (Wb) that is greater than the 'a' horizontal distance.

In addition, as shown in (c) of FIG. 4B, the solder resist layer S3 having a third thickness Tc greater than the second thickness Tb has a third depth greater than the second depth Tb. When forming an opening of (Tc), the recess has a 'c' horizontal distance (Wc) greater than the 'a' and 'b' horizontal distances.

As shown in Figure 4b, when the opening is formed to have a depth corresponding to the thickness of the solder resist layer, it can be seen that the horizontal distance of the depression increases in proportion to the thickness of the solder resist layer.

Additionally, referring to FIG. 4C, the horizontal distance of the depression may increase in proportion to the thickness in proportion to the depth of the opening formed in the solder resist layer 190L.

For example, as shown in (a) of FIG. 4C, when an opening is formed while leaving a first residual area (Td-1) in a solder resist layer having a fourth thickness (Td), the depression is 'd' ' It can have a horizontal distance (Wd).

And, as shown in (b) of FIG. 4C, a second residual region (Td-2) thinner than the first residual region (Td-1) is left in the solder resist layer having the fourth thickness (Td). When forming an opening, the recess has an 'e' horizontal distance (We) greater than the 'd' horizontal distance (Wd).

And, as shown in (c) of FIG. 4C, a third residual region thinner than the first and second residual regions Td-1 and Td-2 in the solder resist layer having the fourth thickness Td. When forming an opening leaving (Td-3), the recess has a 'f' horizontal distance (Wf) that is greater than the 'd' horizontal distance (Wd) and the e horizontal distance (We).

As shown in FIG. 4C, when a portion of the solder resist layer is removed to form an opening, it can be seen that the horizontal distance of the depression decreases in inverse proportion to the thickness of the remaining area that is not removed from the solder resist layer.

Accordingly, in the embodiment, as described above, the opening SOR is not formed to correspond to the entire thickness of the first protective layer 190, but rather the first portion 190a of the first protective layer 190. By forming the opening SOR only in the second part 190b excluding , the horizontal distance of the depression formed in the second part 190b can be reduced compared to the comparative example. Furthermore, the embodiment allows removal of the depression.

Hereinafter, the experimental results of the horizontal distance of the depression in the case of forming the first protective layer according to the embodiment will be described.

Figure 5a is a diagram showing the results of an experiment on the horizontal distance of the recess in the solder resist layer made of a first insulating material, and Figure 5b shows the recess in the solder resist layer made of a second insulating material different from the first insulating material. This is a drawing to explain the experimental results for the horizontal distance.

At this time, the first insulating material and the second insulating material may be materials constituting the solder resist layer, and may be different from each other. For example, the fact that the first insulating material and the second insulating material are different from each other may mean that the type or content of the filler included in the solder resist layer is different from each other, but is not limited to this.

First, (A) of FIG. 5A shows a depression provided in the first protective layer of the first insulating material under the first condition. The first condition may mean a condition in which the first pad has a 1-1 width and the width of the opening has a 1-2 width (e.g., 80㎛) that is larger than the 1-1 width. . At this time, the difference value between the 1-1 width and the 1-2 width may be 'A'. And, the horizontal distance of the depression formed in the second part when an opening having the 1-2 width is formed by developing only the second part excluding the first part of the first protective layer under the first conditions as described above. I looked into it.

Figure 5A (B) shows a depression provided in the first protective layer of the first insulating material under the second condition. The second condition is that the width of the first pad has a 2-1 width greater than the 1-1 width and the width of the opening has a 2-2 width greater than the 2-1 width (for example, 95 ㎛) may mean the condition of having ㎛. At this time, the difference value between the 2-1 width and the 2-2 width may be 'A', which is the same as (A) in FIG. 5A. In addition, in the case where an opening having the 2-2 width is formed by developing only the second portion excluding the first portion of the first protective layer under the second condition as described above, the depression formed in the second portion We looked at the horizontal distance.

(C) of FIG. 5A shows a depression provided in the first protective layer of the first insulating material under the third condition. The third condition is that the width of the first pad has a 3-1 width that is larger than the 2-1 width and the width of the opening is a 3-2 width that is larger than the 3-1 width (for example, 100 ㎛) may mean the condition of having At this time, the difference value between the 3-1 width and the 3-2 width may be the same 'A' as in (A) and (B) of FIG. 5A. And, in the case where an opening having the 1-2 width is formed by developing only the second portion excluding the first portion of the first protective layer under the third condition as described above, the depression formed in the second portion is horizontal. I looked at the street.

Figure 5a (D) shows a depression provided in the first protective layer of the first insulating material under the fourth condition. The fourth condition is that the width of the first pad has a 4-1 width that is larger than the 3-1 width and the width of the opening is a 4-2 width that is larger than the 4-1 width (for example, 110㎛). ) can mean a condition that has. At this time, the difference value between the 4-1 width and the 4-2 width may be the same 'A' as in (A) to (C) of Figure 5A. And, in the case where an opening having the width 1-2 is formed by developing only the second part excluding the first part of the first protective layer under the above conditions, the horizontal distance of the depression formed in the second part I looked at it.

And, referring to (A) of FIG. 5A, the minimum horizontal distance of the depression was 0.57㎛, the maximum horizontal distance was 1.82㎛, and the average horizontal distance of the depression was 1.40㎛. Accordingly, it was confirmed that the horizontal distance of the depression of the example was significantly reduced compared to the comparative example.

In addition, referring to (B) of FIG. 5A, the minimum horizontal distance of the depression was 0.62㎛, the maximum horizontal distance was 2.25㎛, and the average horizontal distance of the depression was 1.37㎛. Accordingly, it was confirmed that the horizontal distance of the depression of the example was significantly reduced compared to the comparative example.

Referring to (C) of FIG. 5A, the minimum horizontal distance of the depression was 0.10 ㎛, the maximum horizontal distance was 2.22 ㎛, and the average horizontal distance of the depression was 1.05 ㎛. Accordingly, it was confirmed that the horizontal distance of the depression of the example was significantly reduced compared to the comparative example.

Referring to (D) of FIG. 5A, the minimum horizontal distance of the depression was 0.68 ㎛, the maximum horizontal distance was 2.44 ㎛, and the average horizontal distance of the depression was 1.44 ㎛. Accordingly, it was confirmed that the horizontal distance of the depression of the example was significantly reduced compared to the comparative example.

Additionally, (A) of FIG. 5B shows a depression provided in the first protective layer of the second insulating material under the first condition. The first condition may mean a condition in which the first pad has a 1-1 width and the width of the opening has a 1-2 width (e.g., 80㎛) that is larger than the 1-1 width. . At this time, the difference value between the 1-1 width and the 1-2 width may be 'A'. And, the horizontal distance of the depression formed in the second part when an opening having the 1-2 width is formed by developing only the second part excluding the first part of the first protective layer under the first conditions as described above. I looked into it.

Figure 5b (B) shows a depression provided in the first protective layer of the second insulating material under the second condition. The second condition is that the width of the first pad has a 2-1 width greater than the 1-1 width and the width of the opening has a 2-2 width greater than the 2-1 width (for example, 95 ㎛) may mean the condition of having At this time, the difference value between the 2-1 width and the 2-2 width may be 'A', which is the same as (A) in FIG. 5B. In addition, in the case where an opening having the 2-2 width is formed by developing only the second portion excluding the first portion of the first protective layer under the second condition as described above, the depression formed in the second portion We looked at the horizontal distance.

Figure 5b (C) shows a depression provided in the first protective layer of the second insulating material under the third condition. The third condition is that the width of the first pad has a 3-1 width that is larger than the 2-1 width and the width of the opening is a 3-2 width that is larger than the 3-1 width (for example, 100 ㎛) may mean the condition of having At this time, the difference value between the 3-1 width and the 3-2 width may be the same 'A' as in (A) and (B) of FIG. 5B. And, in the case where an opening having the 1-2 width is formed by developing only the second portion excluding the first portion of the first protective layer under the third condition as described above, the depression formed in the second portion is horizontal. I looked at the street.

Figure 5b (D) shows a depression provided in the first protective layer of the second insulating material under the fourth condition. The fourth condition is that the width of the first pad has a 4-1 width that is larger than the 3-1 width and the width of the opening is a 4-2 width that is larger than the 4-1 width (for example, 110㎛). ) can mean a condition that has. At this time, the difference value between the 4-1 width and the 4-2 width may be the same 'A' as in (A) to (C) of Figure 5B. And, in the case where an opening having the width 1-2 is formed by developing only the second part excluding the first part of the first protective layer under the above conditions, the horizontal distance of the depression formed in the second part I looked at it.

And, in the case of Figure 5b (A), the minimum horizontal distance of the depression was 4.40㎛, the maximum horizontal distance was 5.83㎛, and the average horizontal distance of the depression was 4.61㎛. Accordingly, it was confirmed that the horizontal distance of the depression of the example was significantly reduced compared to the comparative example.

In addition, in the case of Figure 5b (B), the minimum horizontal distance of the depression was 3.35 ㎛, the maximum horizontal distance was 5.50 ㎛, and the average horizontal distance of the depression was 4.74 ㎛. Accordingly, it was confirmed that the horizontal distance of the depression of the example was significantly reduced compared to the comparative example.

In the case of Figure 5b (C), the minimum horizontal distance of the depression was 4.11 ㎛, the maximum horizontal distance was 6.07 ㎛, and the average horizontal distance of the depression was 5.07 ㎛. Accordingly, it was confirmed that the horizontal distance of the depression of the example was significantly reduced compared to the comparative example.

In the case of Figure 5b (D), the minimum horizontal distance of the depression was 4.11㎛, the maximum horizontal distance was 6.12㎛, and the average horizontal distance of the depression was 5.36㎛. Accordingly, it was confirmed that the horizontal distance of the depression of the example was significantly reduced compared to the comparative example.

Specifically, the embodiment removes only a portion of the total thickness of the first protective layer 190. That is, in the embodiment, only the second part 190b of the first protective layer 190 excluding the first part 190a is opened to form an opening exposing the pad of the first circuit pattern layer 120. Accordingly, the embodiment can significantly reduce the horizontal distance of the depression compared to the comparative example, and furthermore, the depression can be removed.

Hereinafter, the structure of each region of the first protective layer of the first embodiment will be described.

FIG. 6A is a diagram showing a 1-1 region of the first region of the first protective layer of FIG. 3A of the first embodiment, and FIG. 6B is a diagram showing a SAM photograph of the circuit board corresponding to FIG. 6A. FIG. 6A is a cross-sectional view taken along line L1 of FIG. 3B.

Prior to the description of FIGS. 6A and 6B, the first region 191 of the first protective layer 190 of the embodiment includes first parts 191-1a and 191-2a and second parts 191-1b and 191. Includes -2b).

For example, the first region 191 of the first protective layer 190 includes the first portion 191-1a on one side of the first pad 121 and the first portion 191-1a on the other side of the first pad 121. It may include a first part 191-2a. In addition, the first region 191 of the first protective layer 190 includes a second portion 191-1b on the first portion 191-1a on one side of the first pad 121, and the second portion 191-1b on one side of the first pad 121. 1 It may include a second part 191-2b on the first part 191-2a on the other side of the pad 121.

Hereinafter, for convenience of explanation, based on the first pad 121, the first area 191 on one side will be referred to as the 1-1 area 191-1, and the first area on the other side will be referred to as ( 191) is called the 1-2 area (191-2).

6A and 6B, the first region 191 of the first protective layer 190 has a first opening (SOR1) exposing the top surface of the first pad 121 of the first circuit pattern layer 120. ) may be a formed area. In addition, the first region 191 of the first protective layer 190 has a portion (e.g., adjacent pattern) of the first circuit pattern layer 120 disposed adjacent to the first pad 121. It could be an area.

The adjacent pattern may be either the trace 124 of the first circuit pattern layer 120 or the third pad 123. Accordingly, the first area 191 of the first protective layer 190 may be an area where the trace 124 is disposed adjacent to the first pad 121 or an area where the third pad 123 is disposed. You can.

Accordingly, the first area 191 of the first protective layer 190 includes a 1-1 area 191-1 between the first pad 121 and the trace 124, and the first pad 190. It may include a 1-2 region 191-2 between 121 and the third pad 123. And, FIG. 6A may show a 1-1 area 191-1, which is part of the first area 191.

And, the 1-1 region 191-1 of the first protective layer 190 is a first pad 121 of the first circuit pattern layer 120 and the trace 124. Includes part 1-1 (191-1a). The 1-1 portion 191-1a may also be referred to as the first portion of the first region 191 of the first protective layer 190.

In addition, the 1-1 region 191-1 of the first protective layer 190 has the trace (191-1a) of the 1-1 region 191-1. 124) and may include a 1-2 portion 191-1b having an opening SOR exposing the top surface of the first pad 121. The 1-2 part 191-1b may also be referred to as the second part of the first region 191 of the first protective layer 190.

At this time, the thickness T1 of the first pad 121 of the first circuit pattern layer 120 may be 10 μm to 35 μm. For example, the thickness T1 of the first pad 121 of the first circuit pattern layer 120 may be 12 μm to 30 μm. For example, the thickness T1 of the first pad 121 of the first circuit pattern layer 120 may be 15 μm to 25 μm. If the thickness T1 of the first pad 121 of the first circuit pattern layer 120 is less than 10㎛, the resistance of the first pad 121 may increase, and signal loss may increase accordingly. there is. If the thickness T1 of the first pad 121 of the first circuit pattern layer 120 is greater than 35㎛, it is difficult to miniaturize the first pad 121, and accordingly, the degree of integration of the circuit board is lowered, thereby reducing the overall Volume may increase.

Meanwhile, the thickness T2 of the 1-1 region 191-1 of the first protective layer 190 may be 110% to 200% of the thickness T1 of the first pad 121. For example, the thickness T2 of the 1-1 region 191-1 of the first protective layer 190 may be 120% to 190% of the thickness T1 of the first pad 121. there is. The thickness T2 of the 1-1 region 191-1 of the first protective layer 190 may be 130% to 180% of the thickness T1 of the first pad 121.

If the thickness T2 of the 1-1 region 191-1 of the first protective layer 190 is less than 110% of the thickness T1 of the first pad 121, the first protective layer A problem may occur in which the trace 124 is not stably protected due to (190). In addition, if the thickness T2 of the 1-1 region 191-1 of the first protective layer 190 is greater than 200% of the thickness T1 of the first pad 121, the entire circuit board Thickness may increase. In addition, if the thickness T2 of the 1-1 region 191-1 of the first protective layer 190 is greater than 200% of the thickness T1 of the first pad 121, the The thickness T4 of the 1-2 part 191-1b increases, and accordingly, the horizontal undercut (UC) formed on the side wall 191-1bs of the 1-2 part 191-1b increases. Distance (W1) may increase.

The thickness T3 of the 1-1 portion 191-1a in the 1-1 region 191-1 may be smaller than the thickness T1 of the first pad 121. In addition, the thickness T4 of the 1-2 portion 191-1b is the thickness T2 of the 1-1 region 191-1 of the first protective layer 190. It may be the thickness (T4) minus the thickness (T3) of (191-1a). Additionally, the depth of the opening SOR1 formed in the 1-2 part 191-1b may correspond to the thickness T4 of the 1-2 part 191-1b.

At this time, the thickness T3 of the 1-1 portion 191-1a may range from 40% to 98% of the thickness T1 of the first pad 121. For example, the thickness T3 of the 1-1 portion 191-1a may range from 45% to 95% of the thickness T1 of the first pad 121. For example, the thickness T3 of the 1-1 portion 191-1a may range from 50% to 90% of the thickness T1 of the first pad 121.

At this time, the upper surface of the 1-1 part 191-1a may have a curved surface or an inclined surface rather than a flat surface. And, when the upper surface of the 1-1 part 191-1a has a flat surface or an inclined surface, the thickness T3 of the 1-1 part 191-1a is ) can mean the average thickness of.

If the thickness T3 of the 1-1 part 191-1a is less than 40% of the thickness T1 of the first pad 121, the 1-2 part 191-1b correspondingly The thickness T4 and the depth of the opening SOR1 increase, and the horizontal distance of the depression UC formed on the side wall 191-1bs of the first-2 part 191-1b increases accordingly. You can. In addition, when the thickness T3 of the 1-1 portion 191-1a of the 1-1 region 191-1 is greater than 98% of the thickness T1 of the first pad 121, the opening Due to process deviation in the process of forming (SOR1), a problem may occur in which the 1-1 part (191-1a) covers the upper surface of the first pad 121, and as a result, the first pad (191-1a) may cover the upper surface of the first pad 121. 121), a circuit disconnection problem may occur due to the upper surface not being completely exposed.

The 1-1 portion 191-1a of the first protective layer 190 may contact the upper surface of the first insulating layer 111. Additionally, the 1-1 portion 191-1a of the first protective layer 190 may cover a portion of a side surface of the first pad 121 and a portion of a side surface of the trace 124. Additionally, the 1-1 portion 191-1a of the first protective layer 190 may expose the remaining part of the side surface of the first pad 121 and the remaining part of the side surface of the trace 124. .

The 1-2 part 191-1b of the first protective layer 190 is positioned at a predetermined distance W3 from the first pad 121, and the 1-1 part 191-1a and may be placed on the trace 124. For example, the side wall 191-1bs of the 1-2 portion 191-1b may be spaced apart from the first pad 121 by the distance W3. Accordingly, the upper surface of the 1-1 portion 191-1a of the first protective layer 190 adjacent to the first pad 121 may be exposed corresponding to the gap W3.

Meanwhile, a depression UC may be formed in the side wall 191-1bs of the first-2 part 191-1b. For example, the depression UC is connected to the upper surface of the 1-1 part 191-1a and the 1-2 part 191- connected to the upper surface of the 1-1 part 191-1a. It may be formed between the side walls 191-1bs of 1b). For example, the depression UC may be formed in a step portion between the side wall 191-1bs of the 1-1 part 191-1a and the 1-2 part 191-1b. .

The width of the depression UC may have a value greater than 0. At this time, in the embodiment, etching according to the development is performed only for the 1-2 part (191-1b) excluding the 1-1 part (191-1a), not the entire thickness of the first protective layer 190. do. As a result, the horizontal distance W1 of the depression UC can be reduced. The horizontal distance W1 of the depression UC is the horizontal distance from the innermost end of the depression UC to the outermost end of the side wall 191-1bs of the first-2 portion 191-1b. It can mean.

The horizontal distance W1 of the depression UC may be 13 μm or less. For example, the horizontal distance W1 of the depression UC in the embodiment may be 10 μm or less. For example, the horizontal distance W1 of the depression UC in the embodiment may be 6 μm or less. For example, the horizontal distance W1 of the depression UC in the embodiment may be 2㎛ or less.

Accordingly, the 1-2 part 191-1b of the embodiment reduces the width W2 between the outermost end 124-1 of the trace 124 and the side wall 191-1bs compared to the comparative example. You can.

For example, in the comparative example, the horizontal distance of the depression had to be at least 40 ㎛, and thus the width between the outermost end of the trace and the side wall had to be at least 45 ㎛.

In contrast, in the embodiment, the opening SOR1 of the 1-1 region 191-1 of the first protective layer 190 is formed by opening only the 1-2 portion 191-1b, The horizontal distance (W1) of the depression (UC) can be significantly reduced compared to the comparative example. Accordingly, in the embodiment, the shortest distance between the outermost end 124-1 of the trace 124 and the outermost end of the side wall 191-1bs of the opening of the 1-2 portion 191-1b is The width W2 may range from 1 μm to 30 μm (eg, greater than 1 μm and less than or equal to 30 μm). For example, in the embodiment, the shortest distance between the outermost end (124-1) of the trace 124 and the outermost end of the side wall (191-1bs) of the opening of the first-2 portion (191-1b) The width (W2) may range from 2 ㎛ to 25 ㎛ (for example, 2 ㎛ or more and 25 ㎛ or less). For example, in the embodiment, the shortest distance between the outermost end (124-1) of the trace 124 and the outermost end of the side wall (191-1bs) of the opening of the first-2 portion (191-1b) The width (W2) may range from 3 ㎛ to 20 ㎛ (for example, 3 ㎛ or more and 20 ㎛ or less). For example, in the embodiment, the shortest distance between the outermost end (124-1) of the trace 124 and the outermost end of the side wall (191-1bs) of the opening of the first-2 portion (191-1b) The width (W2) may range from 5 ㎛ to 18 ㎛ (for example, 5 ㎛ or more and 18 ㎛ or less). For example, in the embodiment, the shortest distance between the outermost end (124-1) of the trace 124 and the outermost end of the side wall (191-1bs) of the opening of the first-2 portion (191-1b) The width (W2) may range from 7 ㎛ to 16 ㎛ (for example, 7 ㎛ or more and 16 ㎛ or less).

The width W2 of the shortest distance between the outermost end 124-1 of the trace 124 and the outermost end of the side wall 191-1bs of the opening of the first-2 portion 191-1b is 1. If it is less than ㎛, a portion of the outermost end of the trace 124 may be exposed by the depression, and electrical reliability problems such as circuit short may occur as a result. In addition, the width (W2) of the shortest distance between the outermost end (124-1) of the trace (124) and the outermost end of the side wall (191-1bs) of the opening of the first-2 portion (191-1b) If it exceeds 30㎛, the gap between the first pad and the trace increases correspondingly, the circuit integration degree of the circuit board decreases, and the width of the circuit board in the horizontal direction may increase.

Accordingly, in the embodiment, the distance W4 of the shortest distance between the first pad 121 and the trace 124 can be significantly reduced compared to the comparative example. For example, even if the separation distance W3 between the side wall 191-1bs of the 1-2 portion 191-1b and the first pad 121 is at the same level of 15 ㎛ as in the comparative example, The shortest distance between the first pad 121 and the trace 124 (W4) is set to 45 ㎛ or less, further 30 ㎛ or less, further 27 ㎛ or less, further 22 ㎛ or less, and further 18 ㎛ or less. It can be reduced.

Accordingly, in the embodiment, if the planar area of the circuit board is the same as that of the comparative example, the degree of integration of the circuit pattern layer disposed on the circuit board can be increased, and thus more circuit patterns can be arranged compared to the comparative example. There is an effect. Additionally, in the case where the embodiment includes the same number of circuit patterns as the comparative example, the structure of the first protective layer 190 as described above can reduce the spacing between the circuit pattern layers, thereby reducing the distance between the circuit pattern layers in the horizontal direction of the circuit board. The width can be reduced.

FIG. 7A is a diagram showing regions 1-2 in the first region of the first protective layer of FIG. 3A of the first embodiment, and FIG. 7B is a diagram showing a SAM photograph of the circuit board corresponding to FIG. 7A. FIG. 7A is a cross-sectional view taken along line L2 of FIG. 3B.

7A and 7B, the first region 191 of the first protective layer 190 has a first opening (SOR1) exposing the top surface of the first pad 121 of the first circuit pattern layer 120. ) may be a formed area. Additionally, the first area 191 of the first protective layer 190 may be an area where a portion of the first circuit pattern layer 120 is disposed adjacent to the first pad 121. For example, the first region 191 of the first protective layer 190 is adjacent to the first pad 121 and the trace 124 of the first circuit pattern layer 120. ) may be an area where is placed. For example, the first area 191 of the first protective layer 190 may be an area where the first pad 121 and the third pad 123 are disposed adjacent to the first area 191. there is.

Accordingly, the first area 191 of the first protective layer 190 includes a 1-1 area 191-1 between the first pad 121 and the trace 124, and the first pad 190. It may include a 1-2 region 191-2 between 121 and the third pad 123. And, Figure 6a may show the 1-2nd area 191-2 in the first area 191.

And, the 1-2 region 191-2 of the first protective layer 190 is disposed between the first pad 121 and the third pad 123 of the first circuit pattern layer 120. It includes the 2-1 part (191-2a). The 2-1 portion 191-2a may also be referred to as the first portion of the first region 191 of the first protective layer 190.

In addition, the 1-2 region 191-2 of the first protective layer 190 covers a portion of the upper surface of the third pad 123 on the 2-1 portion 191-2a. The 2-2 part is disposed and includes a first opening (SOR1) exposing the upper surface of the first pad 121 and a second opening (SOR2) exposing the upper surface of the third pad 123 ( 191-2b) may be included. The 2-2 part 191-2b may also be referred to as the second part of the first region 191 of the first protective layer 190 disposed on the 2-1 part 191-2a.

Here, the thickness T1 of the third pad 123, the thickness T2 of the 1-2 region 191-2 of the first protective layer 190, and the 2-1 portion 191- Since the thickness T3 of 2a) and the 2-2 portion 191-2b have already been described in the 1-1 region 191-1, detailed description thereof will be omitted.

Meanwhile, the 2-2 portion 191-2b includes a first side wall 191-2bs1 corresponding to the first opening SOR1 and a second side wall 191-2bs2 corresponding to the second opening SOR2. ) includes.

Additionally, a first depression (UC1) may be formed in the first side wall (191-2bs1), and a second depression (UC2) may be formed in the second side wall (191-2bs2).

At this time, the horizontal distance W1 of the first depression UC1 may be 13 μm or less. For example, in the embodiment, the horizontal distance W1 of the first depression UC1 may be 10 μm or less. For example, in the embodiment, the horizontal distance W1 of the first depression UC1 may be 6 μm or less. For example, in the embodiment, the horizontal distance W1 of the first depression UC1 may be 2 μm or less.

Accordingly, the 2-2 portion 191-2b of the embodiment compares the width W2 between the outermost end 123-1 of the third pad 123 and the first side wall 191-2bs1. Yes, it can be reduced.

For example, in the embodiment, the first opening SOR1 of the 1-2 region 191-2 of the first protective layer 190 is formed by opening only the 2-2 portion 191-2b. Therefore, the horizontal distance W1 of the first depression UC1 can be significantly reduced compared to the comparative example. Accordingly, in the embodiment, the shortest distance between the outermost end of the first side wall 191-2bs1 of the 2-2 portion 191-2b and the outermost end 123-1 of the third pad 123 The width (W2) may range from 1 ㎛ to 30 ㎛ (for example, greater than 1 ㎛ and less than or equal to 30 ㎛). For example, in the embodiment, the shortest distance between the outermost end of the first side wall 191-2bs1 of the 2-2 portion 191-2b and the outermost end 123-1 of the third pad 123 The width W2 of the distance may range from 2 ㎛ to 25 ㎛ (for example, 2 ㎛ or more and 25 ㎛ or less). For example, the width of the shortest distance between the outermost end of the first side wall 191-2bs1 of the 2-2 portion 191-2b and the outermost end 123-1 of the third pad 123. (W2) may have a range between 3 ㎛ and 20 ㎛ (for example, 3 ㎛ or more and 20 ㎛ or less). For example, in the embodiment, the shortest distance between the outermost end of the first side wall 191-2bs1 of the 2-2 portion 191-2b and the outermost end 123-1 of the third pad 123 The width (W2) of the distance may range from 5 ㎛ to 18 ㎛ (for example, 5 ㎛ or more and 18 ㎛ or less). For example, in the embodiment, the shortest distance between the outermost end of the first side wall 191-2bs1 of the 2-2 portion 191-2b and the outermost end 123-1 of the third pad 123 The width (W2) of the distance may range from 7 ㎛ to 16 ㎛ (for example, 7 ㎛ or more and 16 ㎛ or less).

Accordingly, in the embodiment, the distance W4 of the shortest distance between the first pad 121 and the third pad 123 can be significantly reduced compared to the comparative example. For example, even if the separation distance W3 between the first side wall 191-2bs1 of the 2-2 portion 191-2b and the first pad 121 is at the same level of 15 ㎛ as in the comparative example. , the shortest distance W4 between the first pad 121 and the third pad 123 is 45 ㎛ or less, further 30 ㎛ or less, further 27 ㎛ or less, further 22 ㎛ or less, further Furthermore, it can be reduced to 18㎛ or less.

Meanwhile, a second depression UC2 may be formed in the second side wall 191-2bs2 of the 2-2 portion 191-2b.

At this time, the position where the second depression (UC2) is formed is higher than the position where the first depression (UC1) is formed. That is, the first depression UC1 is formed at a lower height than the upper surface of the third pad 123, while the second depression UC2 is formed at the same height as the upper surface of the third pad 123. Or formed at a high height. Accordingly, the horizontal distance W1-1 of the second depression UC2 may be smaller than the horizontal distance of the first depression UC1.

FIG. 8A is a diagram illustrating the second area of the first protective layer of FIG. 3A of the first embodiment, and FIG. 8B is a diagram illustrating a SAM photograph of the circuit board corresponding to FIG. 8A. FIG. 8A is a cross-sectional view taken along line L3 in FIG. 3B.

Referring to FIGS. 8A and 8B, the second region 192 of the first protective layer 190 is a region where an opening is formed to expose the upper surface of the second pad 122 of the first circuit pattern layer 120. It can be. For example, the second region 192 of the first protective layer 190 may be disposed between the plurality of second pads 122. For example, the second area 192 of the first protective layer 190 may be an area between the plurality of second pads 122 where the first circuit pattern layer 120 is not disposed. The second area 192 of the first protective layer 190 may function as a dam to partition the area between the plurality of second pads 122.

For example, the second region 192 of the first protective layer 190 may be disposed between the 2-1 pad 122-1 and the 2-2 pad 122-2.

The second region 192 of the first protective layer 190 is located on the upper surface of the first insulating layer 111 between the 2-1 pad 121 and the 2-2 pad 122-2. It includes a first portion 192-1 of the second area 192 disposed.

In addition, the second area 192 may include a second part 192-2 of the second area 192 disposed on the first part 192-1 of the second area 192. there is. The width of the second part 192-2 of the second area 192 may be smaller than the width of the first part 192-1 of the second area 192. Accordingly, a portion of the upper surface of the first portion 192-1 of the second area 192 may be exposed.

One end of the first portion 192-1 of the second area 192 may contact the side of the 2-1 pad 122-1. Additionally, the other end of the first portion 192-1 of the second region 192 may contact the side of the 2-2 pad 122-2.

The thickness T3 of the first portion 192-1 of the second region 192 is equal to the thickness T1 of the 2-1 pad 122-1 and the 2-2 pad 122-2. It can range from 40% to 98%. For example, the thickness T3 of the first portion 192-1 of the second region 192 is the thickness of the 2-1 pad 122-1 and the 2-2 pad 122-2. It may range from 45% to 95% of (T1). For example, the thickness T3 of the first portion 192-1 of the second region 192 is the thickness of the 2-1 pad 122-1 and the 2-2 pad 122-2. It may range from 50% to 90% of (T1).

At this time, the upper surface of the first portion 192-1 of the second region 192 may have a curved surface or an inclined surface rather than a flat surface. In addition, when the upper surface of the first part 192-1 of the second area 192 has a flat or inclined surface, the thickness T3 of the first part 192-1 of the second area 192 is It may refer to the average thickness of the first portion 192-1 of the second region 192.

The thickness T3 of the first portion 192-1 of the second area 192 is greater than the thickness T1 of the 2-1 pad 122-1 and the 2-2 pad 122-2. If it is less than 40%, the horizontal distance of the depression formed on the side wall of the second part 192-2 of the second area 192 may increase. The thickness T3 of the first portion 192-1 of the second area 192 is greater than the thickness T1 of the 2-1 pad 122-1 and the 2-2 pad 122-2. If it is greater than 98%, the upper surfaces of the 2-1 pad 122-1 and the 2-2 pad 122-2 are not completely exposed due to process deviation in the process of forming the opening. Circuit disconnection problems may occur.

The second portion 192-2 of the second area 192 exposes the top surface of the 2-1 pad 122-1 and a portion of the side surface of the 2-1 pad 122-1. It includes a first side wall 192-21 corresponding to the opening.

Additionally, the second portion 192-2 of the second area 192 exposes the top surface of the 2-2 pad 122-2 and a portion of the side surface of the 2-2 pad 122-2. It includes a second side wall 192-22 corresponding to the opening.

In addition, a first recess (U1) is formed in the first side wall (192-21) of the second portion (192-2) of the second area (192), and a second recess (U1) is formed in the second side wall (192-22). A depression (U2) may be formed.

At this time, the horizontal distance W1 of the first depression (U1) and the second depression (U2) may be 13㎛ or less. For example, in the embodiment, the horizontal distance W1 between the first recess U1 and the second recess U2 may be 10 μm or less. For example, the horizontal distance W1 of the first recess U1 and the second recess U2 may be 6 μm or less. For example, the horizontal distance W1 of the first recess U1 and the second recess U2 may be 2 μm or less.

Accordingly, the width W5 of the second portion 192-2 of the second area 192 of the embodiment can be reduced compared to the comparative example.

For example, in the embodiment, the opening of the second region 192 of the first protective layer 190 is formed by opening only the second portion 192-2, so that the first recess U1 and The horizontal distance of the second recess (U2) can be reduced compared to the comparative example.

For example, in the comparative example, the width of the first protective layer in the second region was 90 μm or more. In contrast, the width W5 of the second portion 192-2 of the second region 192 of the first protective layer 190 in the embodiment may be 40 μm or less. The width W5 of the second portion 192-2 of the second region 192 of the first protective layer 190 in the embodiment may be 30 μm or less. The width W5 of the second portion 192-2 of the second region 192 of the first protective layer 190 in the embodiment may be 20 μm or less. The width W5 of the second portion 192-2 of the second region 192 of the first protective layer 190 in the embodiment may be 10 μm or less. The width W5 of the second portion 192-2 of the second region 192 of the first protective layer 190 in the embodiment may be 5 μm or less.

Accordingly, in the embodiment, the separation distance W6 between the 2-1 pad 122-1 and the 2-2 pad 122-2 can be significantly reduced compared to the comparative example. For example, the separation distance W3 between the first side wall 192-21 of the second portion 192-2 of the second area 192 and the 2-1 pad 122-1 and the 2 Even if the spacing (W3) between the side wall (192-22) and the 2-2 pad (122-2) is at the same level of 15 ㎛ as in the comparative example, the 2-1 pad (122-1) and the 2-1 pad (122-1) The shortest distance W6 between the 2-2 pads 122-2 can be reduced to 70 ㎛ or less, further 60 ㎛ or less, further 50 ㎛ or less, and further 35 ㎛ or less.

FIG. 9A is a diagram showing the 1-1 region of the first region of the first protective layer of FIG. 3A of the second embodiment, and FIG. 9B is a diagram showing the 1-1 region of the first region of the first protective layer of FIG. 3A of the third embodiment. This is a drawing showing the -1 area.

The 1-1 region in the previous embodiment was described as including a depression corresponding to an undercut.

However, in the second embodiment, as the depression is removed, the slope of the side wall of the first protective layer may be changed. That is, in the second embodiment, the depression is removed, and accordingly, the inclination of the side wall of the first protective layer may be different from the previous embodiment for removal of the depression.

The 1-1 region 191-1 of the first protective layer 190 has the trace 124 on the 1-1 portion 191-1a of the 1-1 region 191-1. It may include a 1-2 part 191-1b that is disposed to cover and has an opening SOR exposing the top surface of the first pad 121. The 1-2 part 191-1b may also be referred to as the second part of the first region 191 of the first protective layer 190.

Meanwhile, in the previous embodiment, only the depression UC was formed in the side wall 191-1bs of the first-2 part 191-1b. Differently, the side wall of the 1-2 part 191-1b of the second embodiment includes a first side wall 191-1bs1 having a first slope whose width does not change from the upper surface of the first protective layer to the lower surface, and , It may include a second side wall (191-1bs2) extending from the first side wall (191-1bs1) and having a second slope different from the first slope.

The first side wall 191-1bs1 may be right-angled. For example, the first side wall 191-1bs1 may be perpendicular to the top surface of the first protective layer 190.

The second side wall 191-1bs2 may have a first slope different from the first slope of the first side wall 191-1bs1. And the second side wall 191-1bs2 may have an inclination inclined toward the first pad 121. For example, the width of the first protective layer at a portion corresponding to the second side wall 191-1bs2 may be increased. For example, the width of the opening provided in the first protective layer in a portion corresponding to the second side wall 191-1bs2 may be reduced.

The lower end of the second side wall 191-1bs2 may be positioned lower than the upper surface of the first pad 121. Additionally, the top of the second side wall 191-1bs2 may be located lower than the top surface of the first pad 121. Through this, the embodiment can remove the undercut. Through this, the embodiment can improve the physical reliability and electrical reliability of the circuit board.

Meanwhile, referring to FIG. 9B, in the third embodiment, a depression may be formed in the opening of the first protective layer 190.

For example, a recess UC may be provided between the first side wall 191-1bs1 and the second side wall 191-1bs2 of the protective layer of the third embodiment.

In other words, the opening provided in the first protective layer 190 includes a first embodiment including only an undercut, a second embodiment having a foot shape with a first slope and a second slope, and the undercut and the foot. It can be divided into a third embodiment that includes all shapes.

FIG. 10A is a diagram showing the 1-2 region in the first region of the first protective layer in FIG. 3A of the second embodiment, and FIG. 10B is a diagram showing the 1-2 region in the first region of the first protective layer in FIG. 3A of the third embodiment. This is a drawing showing the -2 area.

That is, the first recess UC1 was formed in the first side wall 191-2bs1 in FIG. 7A of the previous embodiment.

Alternatively, referring to FIG. 10A, the first side wall 191-2bs1 may not be provided with the first recess UC1. However, the side wall corresponding to the first opening SOR1 includes a first part 191-2bs11 having a first slope and a second part 191-2bs12 having a second slope different from the first slope. can do. And, the first slope and the second slope may correspond to FIGS. 9A and 9B. Accordingly, detailed description thereof will be omitted.

Additionally, referring to FIG. 10B, a recess UC1 may be provided between the first part 191-2bs11 and the second part 191-2bs12.

FIG. 11A is a diagram showing a second area of the first protective layer in FIG. 3A in a second embodiment, and FIG. 11B is a diagram showing a second area in the first protective layer in FIG. 3A in a third embodiment.

Referring to FIG. 11A, the second portion 192-2 of the second region 192 of the first protective layer 190 is the upper surface of the 2-1 pad 122-1 and the 2-1 It includes a first side wall corresponding to an opening exposing a portion of the side surface of the pad 122-1.

Additionally, the second portion 192-2 of the second area 192 exposes the top surface of the 2-2 pad 122-2 and a portion of the side surface of the 2-2 pad 122-2. and a second side wall corresponding to the opening.

At this time, the first side wall and the second side wall in FIG. 8A were each provided with a recess.

Alternatively, the first side wall of the second embodiment may not be provided with a recess. Correspondingly, the second side wall may not be provided with a recess.

However, the first side wall may include a first part 192-211 having a first slope and a second part 192-212 having a second slope different from the first slope.

Additionally, the second side wall may include a first part 192-221 having a first slope and a second part 192-222 having a second slope different from the first slope.

Since the first slope and the second slope have already been described, detailed description thereof will be omitted.

Additionally, referring to FIG. 11B, a recess may be provided between the first portion 192-211 and the second portion 192-212 of the first side wall.

Additionally, a recess may be provided between the first portion 192-221 and the second portion 192-222 of the second side wall.

As described above, the circuit board according to the embodiment includes a first protective layer. The first protective layer includes a first part and a second part having a step. And, in an embodiment, the opening formed in the first protective layer may be formed by selectively removing only the second portion excluding the first portion. At this time, the thickness of the first portion of the first protective layer is smaller than the thickness of the first circuit pattern layer exposed through the opening. Accordingly, the opening formed in the second portion of the first protective layer may expose a portion of the side surface of the first circuit pattern layer and the top surface of the first circuit pattern layer. Accordingly, in the embodiment, the depth of the opening does not have a depth corresponding to the entire thickness of the first protective layer, but has a depth corresponding to the thickness of the second portion. Accordingly, in the embodiment, compared to the comparative example, the horizontal distance of the depression corresponding to the undercut formed on the side wall of the opening can be significantly reduced. Furthermore, the embodiment may remove the depression.

Accordingly, in the embodiment, the electrical reliability or physical reliability of the circuit board can be improved. For example, as the horizontal distance of the depression increases, a portion of the solder ball may penetrate between the depressions, and based on this, a short circuit problem may occur as neighboring circuit patterns are connected. For example, as the horizontal distance of the depression increases, the contact area between the first protective layer and the insulating layer decreases, and accordingly, the bonding force between the first protective layer and the insulating layer may decrease. In contrast, in the embodiment, by reducing the horizontal distance of the depression, electrical reliability problems such as the short circuit can be solved, and furthermore, physical reliability problems such as the reduction of bonding force can be solved.

Additionally, in the embodiment, the thickness of the first portion of the first protective layer is in the range of 40% to 98% of the first circuit pattern layer. Accordingly, in the embodiment, the upper surface of the first circuit pattern layer can be stably exposed through the opening formed in the second portion, while the horizontal distance of the depression can be dramatically reduced.

Additionally, in an embodiment, by reducing the horizontal distance of the depression, the gap between pads of the first circuit pattern layer, between a pad and a trace, or between traces can be reduced. Specifically, the spacing between the pads of the first circuit pattern layer, or between the pad and the trace, or between the traces, is determined by reflecting the horizontal distance of the depression in order to solve the electrical reliability problem. At this time, in the embodiment, as the horizontal distance of the depression is reduced, the gap between the pads of the first circuit pattern layer, or between the pad and the trace, or between the traces, which is determined by the horizontal distance of the depression, is dramatically reduced. It can be reduced.

Hereinafter, a method of manufacturing a circuit board according to an embodiment will be described.

FIGS. 12A to 12J are diagrams for explaining the manufacturing method of the circuit board of FIG. 3A in process order.

Referring to FIG. 12A, in the embodiment, the second insulating layer 112 is prepared. The second insulating layer 112 may be a core layer. Accordingly, the second insulating layer 112 may be CCL (Copper Clad Laminate). And, in the embodiment, a process of forming a second through hole VH2 penetrating the second insulating layer 112 may be performed. At this time, the second insulating layer 112 is a core layer having a certain thickness or more. Accordingly, the process of forming the second through hole VH2 is performed by forming the second through hole VH2 on the upper side of the second insulating layer 112. A first process of forming the first part of (VH2), and a second process of forming a second part connected to the first part of the second through hole (VH2) on the lower side of the second insulating layer 112. May include processes. Accordingly, the second through hole VH2 may have an hourglass shape based on the combination of the first part and the second part. Meanwhile, although not shown in FIG. 12A, copper foil layers (not shown) may be laminated on the upper and lower surfaces of the second insulating layer 112, respectively.

Next, in the embodiment, a second through portion 170 fills the second through hole VH2 of the second insulating layer 112, and a second circuit pattern disposed on the upper surface of the second insulating layer 112. A process of forming the third circuit pattern layer 140 disposed on the lower surface of the layer 130 and the second insulating layer 112 may be performed.

For this purpose, as shown in FIG. 12b, in the embodiment, the area where the second circuit pattern layer 130 and the third circuit pattern layer 140 will be formed on the upper and lower surfaces of the second insulating layer 112, respectively. A dry film (DF1) having an opening exposing can be formed.

In the embodiment, as shown in FIG. 12C, plating is performed to fill the second through hole VH2 and the opening of the dry film DF1, thereby forming the second through hole 170 and the second circuit pattern layer. 130 and a third circuit pattern layer 140 may be formed. At this time, the plating is performed by performing electroless plating on the second insulating layer 112 or the copper foil layer (not shown) to form a chemical copper plating layer (not shown), and then using the chemical copper plating layer as a seed layer. It can proceed.

Next, as shown in FIG. 12D, in the embodiment, the first insulating layer 111 is stacked on the first or top surface of the second insulating layer 112, and the second insulating layer 112 is A process of laminating the third insulating layer 113 on two or the lower surfaces may be performed.

At this time, the first insulating layer 111 and the third insulating layer 113 may be prepreg or, alternatively, may be RCC.

In addition, although not shown in the drawing, a copper foil layer (not shown) may be formed on the first surface of the first insulating layer 111 and the second surface of the third insulating layer 113, respectively.

Next, in the embodiment, a process of forming through holes VH1 and VH3 in the first insulating layer 111 and the third insulating layer 113 may be performed.

Next, as shown in FIG. 12F, in the embodiment, plating is performed to form a first through portion 160 and a third through portion 180 that fill the through holes VH1 and VH3, and the first insulating layer. A process of forming the first circuit pattern layer 120 on the upper surface of 111 and the fourth circuit pattern layer 150 on the lower surface of the third insulating layer 113 may be performed.

Next, as shown in FIG. 12g, in the embodiment, a first solder resist layer 190L is formed on the upper surface of the first insulating layer 111, and a second solder resist layer 190L is formed on the lower surface of the third insulating layer 113. The process of forming the solder resist layer 195L may proceed. At this time, the first solder resist layer 190L and the second solder resist layer 195L may be formed entirely on the upper part of the first insulating layer 111 and the lower part of the third insulating layer 113.

Next, as shown in FIG. 12h, in the embodiment, a process of exposing the first solder resist layer 190L and the second solder resist layer 195L, respectively, may be performed.

For example, in an embodiment, a process of exposing the remaining area 190L2 of the first solder resist layer 190L, excluding the area 190L1 where the opening is to be formed, may be performed. Additionally, in the embodiment, a process of exposing the remaining area 195L2 of the second solder resist layer 195L, excluding the area 195L1 where the opening is to be formed, may be performed.

Thereafter, in the embodiment, a process of curing the remaining exposed areas 190L2 and 195L2 may be performed according to the exposure process. However, the curing process may not be carried out separately but may be carried out together with the exposure process.

Next, in the embodiment, as shown in FIG. 12I, a process of forming an opening may be performed by developing the uncured areas 190L1 and 195L1 excluding the cured areas 190L2 and 195L2.

At this time, in the embodiment, in order to form the opening, a process may be performed to reduce the thickness of the uncured areas 190L1 and 195L1 by thinning the uncured areas 190L1 and 195L1. At this time, the thinning is performed on the unexposed area using an organic alkaline compound containing tetramethylammonium hydroxide (TMAH) or trimethyl-2-hydroxyethylammonium hydroxide (choline). It can proceed.

Accordingly, in the embodiment, in the thinning process, the entire uncured area 190L1 of the first solder resist layer 190L is controlled by controlling the thickness of the uncured area 190L1. You can only remove part of it without removing it.

Accordingly, the first solder resist layer 190L includes a first part 190a having a thickness smaller than that of the first circuit pattern layer 120, and an opening SOR on the first part 190a. It can be divided into two parts (190b). Specifically, in the embodiment, it corresponds to the first area 191 and the second area 192 shown in FIGS. 6A, 7A, 8A, 9A, 9B, 10A, 10B, 11A, and 11B. The thinning process may be performed to obtain the shape.

Hereafter, in the embodiment, the area (190N, specifically the first portion (190a) exposed through the opening (SOR)) that was not removed in the thinning process among the uncured area (190L1) is The hardening process can proceed.

And, in the embodiment, the first protective layer 190 and the second protective layer 195 may be formed through the above process.

Figure 13 is a diagram showing the detailed structure of a semiconductor package according to one embodiment. For example, FIG. 13 is a diagram showing the detailed structure of a partial region of one of the semiconductor packages of FIGS. 2A to 2G.

The semiconductor package may include a connection portion 210 disposed on the pads 121 , 122 , and 123 of the first circuit pattern layer 120 .

The connection part 210 may have a spherical shape. For example, the cross section of the connection part 210 may include a circular shape or a semicircular shape. For example, the cross section of the connection portion 210 may include a partially or entirely rounded shape. The cross-sectional shape of the connection part 210 may be flat on one side and curved on the other side. The connection portion 210 may be a solder ball, but is not limited thereto.

Alternatively, the connection portion 210 may have a hexahedral shape. For example, the cross section of the connection part 210 may have a rectangular shape. The cross section of the connection part 210 may include a rectangle or square.

Meanwhile, the connection portion 210 may fill at least a portion of the recess formed in the first protective layer 190 of the circuit board. For example, at least a portion of the connection portion 210 may penetrate into the depression formed in the first protective layer 190 during a reflow process.

The semiconductor package of the embodiment may include a chip 220 disposed on the connection portion 210. The chip 220 may be a processor chip. For example, the chip 220 may be an application processor (AP) chip of any one of a central processor (e.g., CPU), graphics processor (e.g., GPU), digital signal processor, cryptographic processor, microprocessor, and microcontroller. there is.

At this time, a terminal 225 may be included on the lower surface of the chip 220, and the terminal 225 is connected to the pads 121 and 122 of the first circuit pattern layer 120 of the circuit board through the connection portion 210. , 123) can be electrically connected.

Meanwhile, the semiconductor package of the embodiment may have a plurality of chips arranged at a certain distance from each other on one circuit board. For example, the chip 220 may include a first chip and a second chip that are spaced apart from each other.

Also, the first chip and the second chip may be different types of application processor (AP) chips.

Meanwhile, the first chip and the second chip may be spaced apart from each other at a certain distance on the circuit board. For example, the gap between the first chip and the second chip may be 150 μm or less. For example, the gap between the first chip and the second chip may be 120 μm or less. For example, the gap between the first chip and the second chip may be 100 μm or less.

Preferably, for example, the gap between the first chip and the second chip may range from 60 ㎛ to 150 ㎛. For example, the gap between the first chip and the second chip may range from 70 μm to 120 μm. For example, the gap between the first chip and the second chip may range from 80 μm to 110 μm. For example, if the gap between the first chip and the second chip is less than 60㎛, the first chip or the second chip may be damaged due to mutual interference between the first chip and the second chip. Problems with operation reliability may occur. For example, if the gap between the first chip and the second chip is greater than 150㎛, signal transmission loss may increase as the distance between the first chip and the second chip increases.

The semiconductor package may include a molding layer 230. The molding layer 230 may be disposed to cover the chip 220 . For example, the molding layer 230 may be EMC (Epoxy Mold Compound) formed to protect the mounted chip 220, but is not limited thereto.

Meanwhile, at least one depression UC is formed in the protective layer 190 of the circuit board. And, the depression UC of the first embodiment may be filled with the connection part 210 or the molding layer 230.

For example, as shown in the first enlarged view of FIG. 13, the depression UC may be filled by the connection portion 210. That is, a reflow process of the connection unit 210 may be performed during the process of mounting the chip 220 on the connection unit 210. In addition, the connection part 210 may spread during the reflow process, and accordingly, the depression UC may be filled by the connection part 210.

For example, as shown in the second enlarged view of FIG. 13, during the reflow process of the connection portion 210, the connection portion 210 may not spread to the recess UC. At this time, the depression UC may be filled with the molding layer 230.

At this time, the molding layer 230 may have a low dielectric constant to increase heat dissipation characteristics. For example, the dielectric constant (Dk) of the molding layer 230 may be 0.2 to 10. For example, the dielectric constant (Dk) of the molding layer 230 may be 0.5 to 8. For example, the dielectric constant (Dk) of the molding layer 230 may be 0.8 to 5. Accordingly, in the embodiment, the molding layer 230 has a low dielectric constant to improve heat dissipation characteristics for heat generated from the chip 220.

Meanwhile, the semiconductor package may include a solder ball 240 disposed on the lowermost side of the circuit board. The solder ball 240 may be used for bonding between the semiconductor package and an external substrate (eg, a main board of an external device).

14 is a diagram showing the detailed structure of a semiconductor package according to another embodiment. For example, FIG. 14 is a diagram showing the detailed structure of a partial region of one of the semiconductor packages of FIGS. 2A to 2G.

The semiconductor package according to the second embodiment of FIG. 14 is substantially the same as that of FIG. 13, but may differ in that a fillet layer 250 is additionally disposed within the molding layer 230.

The fillet layer 250 may be formed on a circuit board to surround the connection portion 210 and the terminal 225 of the chip 220. The fillet layer 250 may be additionally formed to prevent foreign substances (e.g., moisture, etc.) from penetrating into the space between the circuit board and the chip 220 after the chip 220 is mounted. You can.

In addition, when the fillet layer 250 is included, the recess UC of the protective layer of the circuit board can be filled by the connection portion 210, as shown in the first and second enlarged views of FIG. 14. Alternatively, it may be filled with the fillet layer 250.

Meanwhile, when a semiconductor package having the characteristics of the above-described invention is used in IT devices or home appliances such as smartphones, server computers, and TVs, functions such as signal transmission or power supply can be stably performed. For example, the semiconductor package having the characteristics of the present invention can safely protect the semiconductor chip from external moisture or contaminants, and can prevent problems such as leakage current or electrical short circuits between terminals, or terminals supplying the semiconductor chip. The problem of electrical openness can be solved. Additionally, if it is responsible for the function of signal transmission, the noise problem can be solved. Through this, the semiconductor package having the characteristics of the above-described invention can maintain the stable function of IT devices or home appliances, so that the entire product and the semiconductor package to which the present invention is applied can achieve functional integrity or technical interoperability with each other.

When a semiconductor package having the characteristics of the above-mentioned invention is used in a transportation device such as a vehicle, it is possible to solve the problem of distortion of signals transmitted to the transportation device, or to safely protect the semiconductor chip that controls the transportation device from the outside and prevent leakage. The stability of the transport device can be further improved by solving the problem of electrical short-circuiting between currents or terminals, or the problem of electrical opening of the terminal supplying the semiconductor chip. Accordingly, the transportation device and the semiconductor package to which the present invention is applied can achieve functional unity or technical interoperability with each other.

The features, structures, effects, etc. described in the embodiments above are included in at least one embodiment and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc. illustrated in each embodiment can be combined or modified and implemented in other embodiments by a person with ordinary knowledge in the field to which the embodiments belong. Therefore, contents related to such combinations and modifications should be interpreted as being included in the scope of the embodiments.

Although the above description focuses on the embodiment, this is only an example and does not limit the embodiment, and those skilled in the art will understand that there are various options not exemplified above without departing from the essential characteristics of the present embodiment. You will see that variations and applications of branches are possible. For example, each component specifically shown in the examples can be modified and implemented. And these variations and differences related to application should be interpreted as being included in the scope of the embodiments set forth in the appended claims.

Claims (18)

first insulating layer;
a first pad disposed on the first insulating layer; and
Comprising a second insulating layer disposed on the first insulating layer,
The second insulating layer is,
a first portion surrounding a portion of a side surface of the first pad on the first insulating layer;
a second portion disposed on the first portion and having an opening having a width greater than the width of the first pad;
The side wall of the second part is,
Comprising a first slope adjacent to the upper surface of the second insulating layer, and a second slope adjacent to the lower surface of the second insulating layer and different from the first slope,
circuit board. According to paragraph 1,
The second slope is inclined toward the first pad from the upper surface to the lower surface of the second insulating layer.
circuit board. According to paragraph 1,
The first slope is perpendicular to the upper surface of the second insulating layer,
circuit board. According to paragraph 1,
The side wall of the second portion is provided with a depression recessed in the inward direction,
circuit board. According to paragraph 4,
The depression is,
Provided between the first slope and the second slope,
circuit board. According to paragraph 4,
The horizontal distance of the depression is 13㎛ or less,
The horizontal distance is,
The horizontal distance from the bottom of the first slope adjacent to the depression to the innermost end of the depression,
circuit board. According to clause 4,
The thickness of the first portion of the second insulating layer is,
Satisfying the range of 40% to 98% of the thickness of the first pad,
circuit board. According to paragraph 1,
The top surface of the first portion of the second insulating layer is located lower than the top surface of the first pad,
The upper surface of the second portion of the second insulating layer is located higher than the upper surface of the first pad,
circuit board. According to paragraph 4,
a trace disposed adjacent to the first pad on the first insulating layer and covered by the second portion of the second insulating layer;
The shortest horizontal distance between the trace and the sidewall of the second insulating layer satisfies the range of 1㎛ to 30㎛,
circuit board. first insulating layer;
a first circuit pattern layer disposed on the first insulating layer; and
Comprising a second insulating layer disposed on the first insulating layer and the first circuit pattern layer,
The first circuit pattern layer includes a first pattern and a second pattern adjacent to the first pattern,
The second insulating layer is,
A first portion of the first area disposed between the first pattern and the second pattern,
A second part is disposed on the first part of the first area and covers the second pattern, and includes a first opening with a width greater than the width of the first pattern,
The first side wall of the first opening includes different first and second slopes,
The shortest horizontal distance between the second pattern and the first side wall is 30 μm or less,
circuit board. According to clause 10,
The first slope is perpendicular to the upper surface of the second insulating layer,
The second slope is inclined toward the first pattern from the upper surface to the lower surface of the second insulating layer,
circuit board. According to clause 10,
A depression is formed in the first side wall of the second portion in an inward direction away from the first pattern,
The horizontal distance of the depression is 13㎛ or less,
circuit board. According to clause 12,
The recess is provided between the first slope and the second slope of the first side wall,
circuit board. first insulating layer;
a first pad and a second pad disposed on the first insulating layer;
A second insulating layer disposed between the first pad and the second pad on the first insulating layer,
The second insulating layer is,
a first portion disposed on the first insulating layer and having a width equal to the gap between the first pad and the second pad;
a second portion disposed on the first portion and having a width less than the gap;
The second portion includes a top surface, a first side adjacent the first pad, and a second side adjacent the second pad,
Each of the first side and the second side includes different first and second slopes,
circuit board. According to clause 14,
The first slope of the first side is perpendicular to the upper surface of the second portion,
The second slope of the first side is inclined toward the first pad from the upper surface to the lower surface of the second insulating layer,
circuit board. According to clause 14,
The first slope of the second side is perpendicular to the upper surface of the second portion,
The second slope of the second side is inclined toward the second pad from the upper surface to the lower surface of the second insulating layer.
circuit board. According to clause 14,
At least one of the first side and the second side,
It is provided between the first slope and the second slope and includes a depression recessed in the inner direction of the first part,
circuit board. A first substrate corresponding to the circuit board according to any one of claims 1 to 17;
Including any one of a second substrate and a semiconductor device disposed on the first substrate,
Semiconductor package.