KR20230172994A - Semiconducter device - Google Patents

Abstract

A semiconductor device according to an embodiment includes a memory cell, a page buffer, and a first switch whose one end is electrically connected to a bonding point of the memory cell at a first node and the other end is connected to the page buffer at a second node. memory device; and applying a precharge voltage to the first node and the second node in a first section, turning on the first switch in a second section following the first section, and turning on the first switch. and a memory controller that determines whether bonding between the memory cell and the first switch is defective based on the voltage of the second node.

Description

Semiconductor device {SEMICONDUCTER DEVICE}

The disclosure relates to semiconductor devices.

Increasing demand for high-capacity memory such as big data, high-capacity servers, and AI has led to demands for new memory structures. For example, a new memory structure was developed in which the memory cell die and the peripheral circuit die are manufactured in separate processes and the two dies are bonded. This structure allows peripheral circuit dies to be manufactured in a relatively low-temperature process, thereby benefiting from technology scaling.

This structure has millions of junctions for communication between the cell die and the surrounding circuit die, and if the connection of the junctions is unstable, the yield of the memory can be reduced.

One embodiment is intended to provide a semiconductor device to prevent yield reduction due to defective bonding connection.

A semiconductor device according to an embodiment to solve this technical problem has one end electrically connected to a memory cell, a page buffer, and a bonding point of the memory cell at a first node, and the other end to the page buffer at a second node. a memory device including a first switch connected; and applying a precharge voltage to the first node and the second node in a first section, turning on the first switch in a second section following the first section, and turning on the first switch. It may include a memory controller that determines whether bonding between the memory cell and the first switch is defective based on the voltage of the second node.

The memory controller may turn off the first switch in the first section.

The semiconductor device includes a second switch that transmits the precharge voltage to the first node in the first section; And it may further include a third switch transmitting the precharge voltage to the second node in the first section.

The memory controller may turn off the second switch and the third switch in the second section.

The page buffer includes a latch maintaining a first level in the first section; and a transistor connected between the input terminal of the latch and a line transmitting a second level, and operating in response to the voltage of the second node, wherein the memory controller determines the logic level of the latch in the second section. Based on this, it can be determined whether the bonding is defective.

The page buffer includes a latch maintaining a first level in the first section; and a transistor that causes the logic level of the latch to maintain the first level or switch to a second level based on the voltage of the second node in the second section, wherein the memory controller is configured to maintain the logic level of the latch in the second section. It is possible to determine whether the bonding is defective based on the logic level of the latch.

The transistor may have a gate connected to the second node and a source or drain connected to the latch.

The memory controller may determine that the bonding is defective if the latch maintains the first level, and may determine that the bonding is normal if the latch switches from the first level to the second level.

The time and voltage value for applying the precharge voltage may be determined in advance so that the voltage of the second node exceeds the threshold voltage of the transistor at the end of the first period.

The semiconductor device further includes a sensing circuit that measures the voltage of the first node at the end of the first section, and the memory controller is configured to adjust the voltage of the first node to the transistor when the first section ends. If it exceeds the threshold voltage, it may be determined that the bonding is defective, and if the voltage of the first node does not exceed the threshold voltage at the end of the first section, it may be determined that the bonding is normal.

A semiconductor device according to an embodiment includes a plurality of bit lines connected to a plurality of memory cells; a precharge circuit that precharges a first bit line among the plurality of bit lines to a first voltage and precharges a second bit line to a second voltage lower than the first voltage; and a sense amplifier that amplifies the difference between the voltages of the first bit line and the second bit line and outputs the amplified voltage difference. and a memory controller that determines whether bonding of the plurality of memory cells is defective based on the output from the sense amplifier.

The memory controller may control the precharge circuit so that the first bit line precharges the first voltage and the second bit line precharges the second voltage in a first section.

The memory controller may determine whether the bonding is defective based on the output from the sense amplifier in the second section following the first section.

The plurality of memory cells are located in a first area, the precharge circuit and the sense amplifier are located in a second area bonded to the first area, and the memory controller is configured to bond the first area and the second area. You can decide whether this is defective or not.

The memory controller may determine that the bonding is normal when the voltage of the first bit line is higher than the voltage of the second bit line.

The memory controller may determine that the bonding is defective when the voltage of the second bit line is higher than the voltage of the first bit line.

The memory controller may determine that the bonding is normal when the voltage of the first bit line is higher than the first voltage.

If the voltage of the first bit line is lower than the second voltage, the memory controller may determine that the bonding is defective.

The sense amplifier is connected to the first bit line, the second bit line, and a third bit line among the plurality of bit lines, and has an average value of the voltage of the second bit line and the voltage of the third bit line and , the difference with the voltage of the first bit line can be amplified.

A semiconductor device according to an embodiment includes a memory cell; page buffer; a first switch having one end connected to the memory cell at a first node and the other end connected to the page buffer at a second node; a second switch connected between a power source supplying a precharge voltage and the first node; and a third switch connected between the power source and the second node, wherein the page buffer includes: a latch; and a transistor connected between the input terminal of the latch and the ground terminal, and through which the voltage of the second node is transmitted to the gate.

1 is a schematic block diagram of a memory system according to one embodiment.
Figure 2 is a schematic block diagram of a memory device according to one embodiment.
Figure 3 is a circuit diagram showing a portion of a memory device according to an embodiment.
FIG. 4 is a diagram for explaining the operation of a memory device according to an embodiment.
FIG. 5 is a diagram for explaining the operation of a memory device according to an embodiment.
Figure 6 is an example of a graph showing a change in voltage at a bonding node in a bonding area.
Figure 7 is a schematic block diagram of a memory device according to one embodiment.
Figure 8 shows a portion of a circuit diagram of a memory device according to one embodiment.
Figure 9 is an example of a graph showing a change in voltage at a bonding node in a bonding area.
Figure 10 is an example of a graph showing a change in voltage at a bonding node in a bonding area.
Figure 11 shows a portion of a circuit diagram of a memory device according to one embodiment.
Figure 12 is a flowchart of a defect detection method according to an embodiment.
13 is a flowchart of a defect detection method according to an embodiment.
Figure 14 is a schematic block diagram of a computing system according to one embodiment.

Below, with reference to the attached drawings, embodiments of the present invention will be described in detail so that those skilled in the art can easily implement the present invention. However, the present invention may be implemented in many different forms and is not limited to the embodiments described herein.

In order to clearly explain the present invention in the drawings, parts that are not related to the description are omitted, and similar parts are given similar reference numerals throughout the specification. In the flowchart described with reference to the drawings, the order of operations may be changed, several operations may be merged, certain operations may be divided, and certain operations may not be performed.

Additionally, expressions written in the singular may be interpreted as singular or plural, unless explicit expressions such as “one” or “single” are used. Terms containing ordinal numbers, such as first, second, etc., may be used to describe various components, but the components are not limited by these terms. These terms may be used for the purpose of distinguishing one component from another.

1 is a schematic block diagram of a memory system according to one embodiment.

Referring to Figure 1, a memory system (memory system) 10 may include a memory controller (memory controller) 100 and a memory device (memory device) 200.

The memory controller 100 can generally control the operation of the memory system 10. The memory controller 100 can write data to or read data from the memory device 200 using commands and addresses. For example, the memory controller 100 and the memory device 200 may be connected using individual pins and individual transmission lines to exchange commands, addresses, or data.

The memory controller 100 may control the memory device 200 in response to commands from a host. The host may request a data processing operation of the memory system 10, for example, a data read operation, a data write (program) operation, and a data erase operation. For example, the host may be a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a microprocessor, or an Application Processor (AP).

The host communicates with the memory controller 100 using an interface protocol such as Peripheral Component Interconnect express (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), or Serial Attached SCSI (SAS). can do. Additionally, the interface protocols between the host and the memory controller 100 are not limited to the above-described examples, and may include USB (Universal Serial Bus), MMC (Multi-Media Card), ESDI (Enhanced Small Disk Interface), or IDE (Integrated Drive Electronics). ), etc. may also be implemented as one of the other interface protocols.

The memory device 200 may be a volatile memory or a non-volatile memory.

As an example, the memory device 200 may include Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate (LPDDR) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR), and RDRAM ( It may be a dynamic random access memory (DRAM) such as Rambus Dynamic Random Access Memory.

As another example, the memory device 200 may include NAND flash memory, vertical NAND (VNAND) flash memory, Bonding Vertical NAND (BVNAND) flash memory, and Noah flash memory (NOR Flash). Memory), Resistive Random Access Memory (RRAM), Phase-Change RAM (PRAM), Magneto resistive RAM (MRAM), Ferroelectric RAM (FRAM), spin injection magnetization reversal It may be RAM (Spin Transfer Torque RAM, STT-RAM), or Conductive Bridging RAM (CBRAM).

The memory device 200 may include a cell area and a peripheral circuit area. The cell area may include a memory cell array, and the peripheral circuit area may include components excluding the memory cell array. Each region can be formed as an individual die. In the memory device 200, the cell area and the peripheral circuit area may be connected using bonding. That is, a bonding area may be located between the cell area and the peripheral circuit area. For example, the cell region and the surrounding circuit region can be connected using Cu-to-Cu bonding. The memory device 200 may include a plurality of bonding points for communication in the bonding area.

The memory controller 100 may detect a defective bonding point in the bonding area of the memory device 200. The memory controller 100 may detect a defective bonding point using at least one of a voltage of a node in a cell area of the memory device 200 or a voltage of a node in a peripheral circuit area.

For example, parasitic resistance and parasitic capacitance may exist at bonding points in the bonding area of the memory device 200. Parasitic capacitance and parasitic resistance between two components electrically connected by bonding may be formed at the bonding point. Hereinafter, in order to explain the electrical characteristics of the bonding point, the bonding point can be represented as an electrical node, and the node can be understood as connected to a resistor and a capacitor representing the parasitic resistance and parasitic capacitance of the bonding point. there is.

The capacitor according to the parasitic capacitance of the bonding point may be charged in the first section, and charging or discharging may be performed in the second section following the first section. The memory controller 100 may detect whether the bonding point is defective based on the voltage value of the capacitor in the second section. The memory controller 100 may determine that bonding is normal when the voltage value of the capacitor exceeds the reference voltage, and that bonding is defective if the voltage value of the capacitor does not exceed the reference voltage.

When the memory controller 100 detects a defective bonding point, it can perform a repair operation. For example, the memory controller 100 may be configured to detour a bit line connected to a defective bonding point to another bit line.

Figure 2 is a schematic block diagram of a memory device according to one embodiment.

Referring to FIG. 2, the memory device 200 of FIG. 1 may be implemented as a memory device 300.

The memory device 300 includes a memory cell array (310), a voltage generator (320), an ), a Y decoder (or column decoder) 350, and control logic (control logic) 360.

The memory cell array 310 may be placed on a first die corresponding to the cell area, and components such as the page buffer 340 and the Y decoder 350 may be placed on a second die corresponding to the peripheral circuit area. The first die and the second die may be bonded through a process such as Cu-to-Cu bonding. That is, a bonding area may be located between the first die and the second die.

The bonding area may include a plurality of bonding points for communication between the first die and the second die. Parasitic resistance and parasitic capacitance due to bonding may exist at each bonding point. Parasitic resistance and parasitic capacitance can be expressed as a resistance and capacitor, respectively, in an equivalent circuit.

The memory cell array 310 may include a plurality of memory blocks. Each of the plurality of memory blocks is connected to the It can be connected to the Y decoder 350 and the page buffer 340 through bitline (BL).

The memory cell array 310 may include a plurality of memory cells disposed in areas where a plurality of word lines (WL) and a plurality of bit lines (BL) intersect. Each memory cell may be used as a cell type, such as single level cell (SLC), multi level cell (MLC), triple level cell (TLC), or quad level cell (QLC).

Memory cell array 310 may include non-volatile memory cells. For example, the memory cell array 310 may include a two-dimensional (2D) NAND memory array or a three-dimensional (3D) vertical NAND (VNAND) memory array.

The voltage generator 320 receives power, regulates the voltage signal (Vg) for memory operation based on the voltage control signal (VCTRL), and transmits the voltage signal (Vg) to the memory cell array through the It can be provided at (310).

The X decoder 330 may be connected to the memory cell array 310 through a word line (WL), a string select line (SSL), and a ground select line (GSL). The X decoder 330 may select at least one of a plurality of memory blocks by decoding the row address (R_ADDR). That is, the row decoder 330 can select the word line (WL), string select line (SSL), and ground select line (GSL) using the row address (R_ADDR). The X decoder 330 may provide the voltage signal (Vg) supplied from the voltage generator 320 to the word line (WL).

The page buffer 340 may include first to sth page buffers 340_1 to 340_s. The first to sth page buffers 340_1 to 340_s may each be connected to a plurality of memory cells through a plurality of bit lines BL (s is an integer greater than or equal to 3). The page buffer 340 may select at least one bit line among the plurality of bit lines BL based on the column address C_ADDR. The page buffer 340 may operate as a write driver or a sense amplifier depending on the operation mode. For example, during a program operation, the page buffer 340 may receive data (DATA) from the memory controller 100 and apply a bit line voltage corresponding to the data (DATA) to the selected bit line. During a read operation, the page buffer 340 may detect data (DATA) stored in the memory cell array 310 by detecting the current or voltage of the selected bit line and provide the data to the memory controller 100.

The page buffer 340 may include a capacitor, a transistor, and a latch. The capacitor may be an element due to parasitic capacitance. Capacitors, transistors, and latches can output data through their respective operations in the pre-charge section and sensing section. The operations of the capacitor, transistor, and latch will be described later with reference to FIGS. 3 to 6.

The memory device 300 may include a precharge circuit that outputs a precharge voltage in the precharge section, and switches that are closed in the precharge section and open in the sensing section. Closing a switch can be understood as turning the switch on, and opening a switch can be understood as turning the switch off. The precharge circuit may generate a precharge voltage based on the power output by a power management integrated circuit (PMIC) in the peripheral circuit area. For example, the memory device 300 is disposed in the peripheral circuit area and includes a first switch that transmits a precharge voltage to the memory cell array 310 in the precharge section, and a first switch that is disposed in the peripheral circuit area and transmits a precharge voltage to the page buffer 340. It may include a second switch that transmits the precharge voltage. The first switch and the second switch may be opened in the sensing section. The control logic 360 can control the switches using an internal signal that distinguishes the precharge period and the sensing period.

The memory controller 100 can detect defective bonding points in the bonding area through data acquired during sensing. For example, if a value different from the value set in the page buffer 340 before sensing is sensed, the memory controller 100 may determine that bonding is normal. If the value set in the page buffer 340 before sensing remains unchanged, the memory controller 100 may determine that bonding is defective.

The Y decoder 350 may include first to sth Y decoders (350_1 to 350_s). Each of the first to s Y decoders 350_1 to 350_s may include a transistor. The transistor may be connected between the page buffer 340 and the memory cell array 310. The transistor may operate based on voltage (Vyd) from control logic 360. For example, when the voltage Vyd exceeds the threshold voltage of the transistor, it may be closed to connect the memory cell array 310 and the page buffer 340. If the voltage Vyd does not exceed the threshold voltage of the transistor, the memory cell array 310 and the page buffer 340 may be opened.

The control logic 360 may provide each control signal related to memory operation to the voltage generator 320, the X decoder 330, the page buffer 340, and the Y decoder 350. The control logic 360 may control the overall operation of the memory device 300. The control logic 360 controls the memory device 300 by generating an internal control signal based on at least one of an address (ADDR), a command (CMD), and a control signal (CTRL) received from the memory controller 100. You can. For example, control logic 360 generates a voltage control signal (VCTRL) to control voltage generator 320, generates a voltage (Vyd) to control Y decoder 350, and/or addresses Based on (ADDR), the row address (R_ADDR) and column address (C_ADDR) can be generated. The control logic 360 may output a row address (R_ADDR) to the X decoder 330 or a column address (C_ADDR) to the page buffer 340.

FIG. 3 is a circuit diagram showing a portion of a memory device according to an embodiment, FIG. 4 is a diagram for explaining the operation of the memory device according to an embodiment, and FIG. 5 is a diagram showing the operation of the memory device according to an embodiment. It is a drawing for explanation, and FIG. 6 is an example of a graph showing a change in voltage at a bonding node in a bonding area.

Referring to FIG. 3 , the memory device may include a page buffer area 410, a Y decoder area 420, a bonding area 430, and a cell area 440. Here, the page buffer area 410 and the Y decoder area 420 may be formed on one die as peripheral circuit areas, and the cell area 440 may be formed on another die. The bonding area 430 is an area where the cell area 440 and the peripheral circuit area are bonded, and may include numerous bonding points. In Figure 3, one bonding point is shown for convenience of explanation.

The page buffer area 410 may include a latch 411 and a transistor TR2. Although the capacitor C _s is shown in the page buffer area 410 , it represents parasitic capacitance, and the capacitor C _s may not actually be located in the page buffer area 410 .

The page buffer area 410 may be connected to the Y decoder area 420 through a node (N _s ). A capacitor (C _s ) and a transistor (TR2) may be connected to the node (N _s ). The capacitor (C _s ) can be charged using the voltage (VDD) applied in the pre-charge section. The voltage (VDD) may be a precharge voltage. The gate of the transistor TR2 may be connected to the node N _s . Either the drain or source of the transistor TR2 may be connected to the latch 411. The other of the drain or source of transistor TR2 may be connected to ground. That is, the transistor TR2 may be connected between the input terminal of the latch 411 and the ground terminal. The latch 411 may store a preset value. For example, the latch 411 may be storing a '1' bit.

The memory device 300 may further include a switch between the transistor TR2 and the latch 411. The switch is open in the precharge section to electrically separate the transistor TR2 and the latch 411, and is closed in the sensing section following the precharge section to electrically connect the transistor TR2 and the latch 411.

Y decoder area 420 may include a transistor TR1. The transistor TR1 may be closed when a voltage Vyd higher than the threshold voltage is applied to connect the cell area 440 and the page buffer area 410.

Bonding area 430 may include a node (N _bd ). If the bonding of the bonding area 430 is defective, electrons cannot pass through smoothly, so resistance may occur at the node N _bd .

The cell region 440 may include a cell string 441 and a capacitor (C _bd ). Although the capacitor C _bd is shown in the cell area 440, it represents parasitic capacitance, and the capacitor C _bd may not actually be located in the cell area 440.

The cell string 441 may include a plurality of memory cells connected in series. Capacitor (C _bd ) may be connected to node (N _bd ). The capacitor (C _bd ) can be charged using the voltage (VDD) applied in the pre-charge section.

The memory device can output data through the precharge section and the sensing section. The precharge section may precede the sensing section.

The operation of the memory device in the precharge period will be described with reference to FIG. 4.

Referring to FIG. 4, the memory device may further include switches 450 and 460. In FIG. 4 , transistor TR1 of FIG. 3 is shown as a switch 470 . If the bonding of the memory device is poor, the parasitic resistance of the bonding node of the memory device may be large. In FIG. 4 , the parasitic resistance of the bonding node is shown as being electrically connected between the node N _bd and the switch 470. This is merely an equivalent representation of the parasitic resistance for convenience of explanation, and the invention is not limited to this. A resistance connection that prevents electrical flow between the switch 470 and the bit line at the actual bonding point may be formed in various ways. If the bonding of the memory device is normal, the resistance value is so small that it can be considered negligible, so there is no resistance (R _bd ).

Voltage (Vyd) may not be supplied in the precharge section. That is, the transistor TR1 (switch 470) is open, so the page buffer area 410 and the cell area 440 can be electrically separated. In the precharge section, the capacitor (C _s ) and the capacitor (C _bd ) may be respectively charged. In the precharge section, the switches 450 and 460 are closed, so that the capacitor C _s and capacitor C _bd can be charged, respectively.

The power supply may apply voltage (VDD). The magnitude and application time of voltage (VDD) may be adjustable. For example, when bonding is normal, the size and application time of the voltage VDD may be set in advance so that the voltage of the capacitor C _s exceeds the threshold voltage of the transistor TR2 after the precharge period.

If the bonding is defective and a resistor (R _bd ) with a large resistance value occurs, a voltage drop may occur and a voltage smaller than the voltage (VDD) may be applied to the node (N _bd ). That is, the capacitor C _bd can be charged based on a voltage less than the voltage VDD. If the capacitance of the capacitor (C _bd ) is C1 (F) and the voltage applied to the capacitor (C _bd ) is V1 (V), the charge charged to the capacitor (C _bd ) in the precharge section is C1*V1 (Q) It can be.

A voltage (VDD) may be applied to the node (N _s ). If the capacitance of the capacitor (C _s ) is C2 (F) and the voltage applied to the capacitor (C _s ) is V2 (V), the charge charged to the capacitor (C _s ) in the precharge section is C2*V2 (Q) It can be. V2 may be substantially identical to VDD.

Referring to FIG. 6, the change in voltage (Vbd) over time at the node (N _bd ) can be confirmed. Since the capacitor C _bd is charged based on the voltage VDD in the precharge period t1, the voltage Vbd value may increase over time.

The magnitude and application time of the voltage VDD may be determined based on the voltage Vbd charged in the capacitor C _bd . For example, when a fixed first voltage is applied to the capacitor (C _bd ), if the voltage of the capacitor (C _bd ) exceeds the reference voltage (Vref) after the first time, the first time is extended to the voltage (VDD). It may be determined as the minimum value of the application time, and the first voltage may be determined as the magnitude of the voltage (VDD). As another example, when the voltage is applied for a fixed time, the second voltage at which the voltage of the capacitor (C _bd ) exceeds the reference voltage (Vref) is determined as the minimum value of the voltage (VDD), and the fixed time is determined as the minimum value of the voltage (VDD). It can be determined by the application time of voltage (VDD).

At this time, if the bonding is defective and the resistance value of the resistor (R _bd ) is large, the voltage (Vbd) value may not exceed the reference voltage (Vref) due to the voltage drop. In one embodiment, the reference voltage (Vref) may be a voltage (Vbd) value that causes the voltage (V _S ) of the node (N _s ) to exceed the threshold voltage of the transistor (TR2) in the sensing period (t2) when bonding is normal. there is. In one embodiment, the reference voltage Vref may be set to the threshold voltage of the transistor TR2.

In one embodiment, the memory device may further include a sensing circuit that measures the voltage (Vbd) charged in the capacitor (C _bd ) at the end of the pre-charge period (ta). The sensing circuit may determine whether the voltage Vbd exceeds the reference voltage Vref at time ta. The sensing circuit may determine that bonding is normal if the voltage (Vbd) exceeds the reference voltage (Vref). The sensing circuit may determine that the bonding is defective if the voltage (Vbd) does not exceed the reference voltage (Vref).

The operation of the memory device in the sensing section will be described with reference to FIG. 5.

Referring to FIG. 5, voltage (Vyd) may be supplied in the sensing section. The voltage Vyd may be higher than the threshold voltage of the transistor TR1. That is, the switch 470 is closed, and the page buffer area 410 and the cell area 440 can be electrically connected. At this time, since the node (N _bd ) and the node (N _s ) are connected, the capacitor (C _s ) and the capacitor (C _bd ) can share charge.

The voltage (V _S ) of the capacitor (C _s ) in the sensing section may be equal to Equation 1.

V _S is the voltage of the node (N _s ) in the sensing section, C1 is the capacitance of the capacitor (C _bd ), C2 is the capacitance of the capacitor (C _s ), and V1 is the capacitor (C _bd ) charged in the precharge section. This is the voltage charged, and V2 may be the voltage charged in the capacitor (C _s ) in the precharge section. C1 can be larger than C2.

When the voltage V _S is higher than the threshold voltage of the transistor TR2 in FIG. 3, the transistor TR2 passes current, so the logic level of the latch 411 may be switched. The threshold voltage of the transistor TR2 may be determined based on the distribution. For example, the latch 411 maintaining a high level in the precharge period may transition to a low level when the voltage V _S is higher than the threshold voltage of the transistor TR2 in the sensing period.

That is, when the bonding of the bonding area 430 is normal, the logic level of the latch 411 is switched, and when the bonding is defective, the logic level of the latch 411 is not switched and can maintain a previously set value.

Accordingly, the memory controller 100 may determine whether bonding is defective based on the logic level (or logic value) of the latch 411 in the sensing section. For example, the memory controller 100 determines that bonding is normal when the value of the latch 411 switches from '1' to '0', and if the value of the latch 411 does not switch and maintains the previous value, bonding is established. This can be judged to be defective. The memory controller 100 may perform a repair operation when bonding is defective.

Referring to FIG. 6, since the capacitor C _bd and the capacitor C _s share charge in the sensing period t2, the voltage Vbd value may decrease over time. At this time, if the capacitor C _bd is not sufficiently charged due to poor bonding, the voltage of the capacitor C _s may not exceed the threshold voltage of the transistor TR2 after charge sharing. Accordingly, since the transistor TR2 is open, the latch 411 can maintain the logic level. The memory controller 100 may determine whether bonding is defective based on the logic level of the latch 411.

Figure 7 is a schematic block diagram of a memory device according to one embodiment.

Referring to FIG. 7, the memory device 200 of FIG. 1 may be implemented as a memory device 700.

The memory device 700 includes a control logic (710), an address register (720), a row address multiplexer (730), a bank control logic (740), and a plurality of row decoders. (row decoder; 750), a plurality of column decoders (760), an input/output gating circuit (770), a plurality of sense amplifiers (780), a plurality of memory cell arrays array; 790), and a data input/output buffer (data input/output buffer; 795).

A plurality of memory cell arrays 790 may be placed on a first die corresponding to the cell area, and components such as a plurality of sense amplifiers 780 may be placed on a second die corresponding to the peripheral circuit area. The first die and the second die may be bonded through a process such as Cu-to-Cu bonding. That is, a bonding area may be located between the first die and the second die.

The bonding area may include a plurality of bonding points for communication between the first die and the second die. Parasitic resistance and parasitic capacitance due to bonding may exist at each bonding point. Parasitic resistance and parasitic capacitance can be expressed as resistors and capacitors, respectively, in a circuit.

The plurality of memory cell arrays 790 and the plurality of sense amplifiers 780 may be connected through a bit line and a complementary bit line (or bitline bar). In the equivalent circuit, the bit line and the complementary bit line can each be expressed as having a capacitor connected to them due to parasitic capacitance. For one bit line, at least one corresponding complementary bit line may be located. The memory controller 100 may determine whether the bonding is defective based on at least one of the voltage of a capacitor connected to a bit line or the voltage of a capacitor connected to a complementary bit line.

The capacitor of the bit line, the capacitor of the complementary bit line, and the plurality of sense amplifiers 780 may output data through their respective operations in the precharge period and the sense amplification period. The operations of the bit line capacitor, the complementary bit line capacitor, and the plurality of sense amplifiers 780 will be described later with reference to FIGS. 8 to 11.

The control logic 710 decodes the command (CMD) received from the memory controller 100, generates a refresh row address (REF_ADDR) based on the address received from the address register 720, and generates a refresh row address (REF_ADDR). Can be output to the row address multiplexer 730. The command (CMD) may include a write enable signal (WEB), a row address strobe signal (RASB), a column address strobe signal (CASB), a chip select signal (CSB), and a clock enable signal (CKE).

The row address multiplexer 730 can receive a refresh row address (REF_ADDR) and an operation row address (OPR_ADDR). The row address multiplexer 730 may selectively output the refresh row address (REF_ADDR) or the operation row address (OPR_ADDR) as the row address (RA) to the row decoder 750. The refresh row address (REF_ADDR) may be an address subject to self-refresh, and the operation row address (OPR_ADDR) may be an address subject to writing, reading, or erasing.

The address register 720 may receive an address (ADDR) from the memory controller 100. The address (ADDR) may include a bank address (BANK_ADDR), an operation row address (OPR_ADDR), and a column address (COL_ADDR). The address register 720 provides an operating row address (OPR_ADDR) to the row address multiplexer 730, a bank address (BANK_ADDR) to the bank control logic 740, and a column address (COL_ADDR) to the column decoder 760. can be provided to.

The bank control logic 740 may generate a bank control signal in response to the bank address (BANK_ADDR) and output it to a plurality of row decoders 750 and a plurality of column decoders 760. The plurality of row decoders 750 may include first to rth row decoders 750_1 to 750_r (r is an integer greater than 1). The plurality of column decoders 760 may include first to r-th column decoders 760_1 to 760_r (r is an integer greater than 1). In response to the bank control signal, the row decoder corresponding to the bank address (BANK_ADDR) among the first to r-th row decoders (750_1 to 750_r) is activated, and the bank address (BANK_ADDR) among the first to r-th column decoders (760_1 to 760_r) The column decoder corresponding to BANK_ADDR) may be activated.

The plurality of memory cell arrays 790 may include first to rth memory cell arrays 790_1 to 790_r (r is an integer greater than 1). That is, the number of memory cell arrays 790 may be equal to the number of row decoders 750 and the number of column decoders 760. For example, r can be implemented as 8, 16, 32, etc.

The first to rth row decoders 750_1 to 750_r may be connected to the first to rth memory cell arrays 790_1 to 790_r, respectively. The first to rth column decoders 760_1 to 760_r may be connected to the first to rth memory cell arrays 790_1 to 790_r, respectively. Additionally, the plurality of sense amplifiers 780 may include first to rth sense amplifiers 780_1 to 780_r respectively connected to first to rth memory cell arrays 790_1 to 790_r.

First to rth row decoders (750_1 to 750_r), first to rth column decoders (760_1 to 760_r), first to rth sense amplifiers (780_1 to 780_r), and first to rth memory cell arrays (790_1) ~790_r) may respectively constitute the first to rth banks. Each of the first to rth memory cell arrays 790_1 to 790_r may include a plurality of word lines, a plurality of bit lines, and a plurality of memory cells formed at points where the word lines and the bit lines intersect. Each memory cell may have a DRAM cell structure. The word line to which memory cells are connected can be designated as a row, and the bit line to which memory cells are connected can be designated as a column.

Among the first to r th row decoders (750_1 to 750_r), the row decoder activated by the bank control logic 740 decodes the row address (RA) output from the row address multiplexer 730 and corresponds to the row address (RA). You can activate the word line. For example, the activated row decoder may apply a word line driving voltage to the word line corresponding to the row address (RA).

The column decoder 760 may activate the sense amplifier 780 through the input/output gating circuit 770. For example, among the first to rth column decoders (760_1 to 760_r), the column decoder activated by the bank control logic 740 is connected to the first to rth sense amplifiers (780_1 to 780_r) through the input/output gating circuit 770. The sense amplifier corresponding to the middle bank address (BANK_ADDR) and column address (COL_ADDR) can be activated.

The input/output gating circuit 770 includes a circuit for gating input/output data, input data mask logic, a read data latch for storing data output from the memory cell array 790, and a circuit for writing data to the memory cell array 790. May contain write drivers.

Data DQ read from one of the first to rth memory cell arrays 790_1 to 790_r may be sensed by a sense amplifier corresponding to the memory cell array and stored in the read data latch. Data DQ stored in the read data latch may be provided to the memory controller 100 through the data input/output buffer 795. Additionally, data DQ to be written in one of the first to rth memory cell arrays 790_1 to 790_r may be provided from the memory controller 100 to the data input/output buffer 795. Data DQ provided to the data input/output buffer 795 may be written to one memory cell array through write drivers.

Figure 8 shows a portion of a circuit diagram of a memory device according to one embodiment. Figure 9 is an example of a graph showing a change in voltage at a bonding node in a bonding area. Figure 10 is an example of a graph showing a change in voltage at a bonding node in a bonding area.

Referring to FIG. 8 , the memory device may include a sense amplifier region 810, a bonding region 820, and a cell region 830. Here, the sense amplifier region 810 may be formed on one die as a peripheral circuit region, and the cell region 830 may be formed on another die. The bonding area 820 is an area where the cell area 830 and the peripheral circuit area are bonded, and may include numerous bonding points. In FIG. 8, two bonding points for the bit line (BL) and the complementary bit line (BLB) are shown for convenience of explanation.

The sense amplifier area 810 may include a bit line (BL), a complementary bit line (BLB), a latch 811, and a precharge circuit 813. Although the capacitor C _bl and C _blb are shown in the sense amplifier region 810, they represent the parasitic capacitance of the bonding region 820, and the capacitor may not actually be located in the sense amplifier region 810. . The bit line (BL), complementary bit line (BLB), capacitor (C _bl ), capacitor (C _blb ), latch 811, and precharge circuit 813 perform their respective operations in the precharge section and sense amplification section. Data can be output through.

The bit line BL may connect the sense amplifier area 810 and the cell area 830. In the precharge period, the precharge circuit 813 may apply the first voltage to the bit line BL.

The capacitor C _bl is connected to the bit line BL through the node N _bl and can be charged based on the first voltage in the precharge period.

A complementary bit line (BLB) may connect the sense amplifier area 810 and the cell area 830. In the precharge period, the precharge circuit 813 may apply a second voltage to the complementary bit line (BLB). The second voltage may be lower than the first voltage. The precharge circuit 813 may not apply voltage to the bit line (BL) and the complementary bit line (BLB) during the sensing period. For example, a switch may be placed between the precharge circuit 813 and the bit line (BL) and complementary bit line (BLB).

The capacitor (C _blb ) is connected to the complementary bit line (BLB) through the node (N _blb ) and can be charged based on the second voltage in the precharge period.

If the bonding to the node (N _bl ) of the bonding area 820 is defective and the bonding to the node (N _blb ) is normal, the charge charged in the capacitor (C _bl ) will be smaller than the charge charged in the capacitor (C _blb ). You can.

If the bonding to the node N _bl and node N _blb of the bonding area 820 are both normal, the charge charged in the capacitor C _bl may be greater than the charge charged in the capacitor C _blb .

The latch 811 may be connected to the bit line (BL) and the complementary bit line (BLB). For example, the latch 811 may include a first inverter and a second inverter. The output terminal of the first inverter and the input terminal of the second inverter may be connected to the bit line BL. The input terminal of the first inverter and the output terminal of the second inverter may be connected to a complementary bit line (BLB).

The latch 811 may operate in the sense amplification section following the precharge section. The latch 811 may be in an off state during the precharge period. The latch 811 may amplify the difference between the voltage of the bit line (BL) and the voltage of the complementary bit line (BLB) in the sense amplification section. That is, if the voltage of the capacitor (C _bl ) in the precharge section is higher than the voltage of the capacitor (C _blb ), the bit line (BL) becomes high level as a result of amplification in the sense amplification section, and the complementary bit line (BLB) becomes low. It can be level. If the voltage of the capacitor (C _bl ) in the precharge section is lower than the voltage of the capacitor (C _blb ), the bit line (BL) becomes low level as a result of amplification in the sense amplification section, and the complementary bit line (BLB) becomes high level. It can be.

The memory controller 100 may determine whether the bonding of the bonding area 820 is defective based on the output from the latch 811 in the sense amplification section. For example, the memory controller 100 determines whether the bonding of the bonding region 820 is defective based on at least one of the voltage of the bit line BL or the voltage of the complementary bit line BLB according to the amplification result in the sense amplification section. can be judged. When the bit line BL becomes low level as a result of amplification, the memory controller 100 may determine that the bonding of the node N _bl in the bonding area 820 is defective.

The cell area 830 may include a cell string 831 and a cell string 832. The cell string 831 is connected to the bit line BL and may include a plurality of memory cells connected in series. The cell string 832 is connected to a complementary bit line (BLB) and may include a plurality of memory cells connected in series.

The bonding region 820 may connect the sense amplifier region 810 and the cell region 830 through a bit line (BL) and a complementary bit line (BLB).

Referring to FIG. 9, when the bonding to the node (N _bl ) of the bonding area 820 is defective and the bonding to the node (N _blb ) is normal, the voltage change of the bit line (BL) and the complementary bit line (BLB) ) can be seen in the voltage change.

In the precharge period t3, the capacitor C _bl is charged based on the first voltage and the capacitor C _blb is charged based on the second voltage, so that the voltage of the bit line BL and the complementary bit line ( BLB) voltage may rise. Even though the first voltage is higher than the second voltage, it can be seen that the capacitor (C _bl ) is not sufficiently charged at the end (tb) of the pre-charge period (t3) because the bonding to the node ( _N bl) is defective. there is.

In the sense amplification period t4, the latch 811 may amplify the difference between the voltage of the bit line BL and the voltage of the bit line BLB. Since the voltage of the bit line (BL) at time tb was lower than the voltage of the bit line (BLB), the bit line (BL) becomes low level in the sense amplification section (t4), and the complementary bit line (BLB) becomes low. It can be high level. Accordingly, the memory controller 100 may determine that the bonding of the node N _bl is defective based on the low level bit line BL.

Referring to FIG. 10, when the bonding for the node (N _bl ) and the node (N _blb ) of the bonding area 820 are both normal, the voltage change of the bit line (BL) and the voltage change of the complementary bit line (BLB) are Able to know.

In the precharge period t5, as the capacitor C _bl is charged based on the first voltage and the capacitor C _blb is charged based on the second voltage, the voltage of the bit line BL and the complementary bit line ( BLB) voltage may rise. Since the first voltage is higher than the second voltage, it can be seen that the voltage of the bit line BL is higher than the voltage of the complementary bit line BLB at the end of the precharge period t5 (tc).

In the sense amplification period t6, the latch 811 may amplify the difference between the voltage of the bit line BL and the voltage of the bit line BLB. Since the voltage of the bit line (BL) was higher than the voltage of the bit line (BLB) at time tc, the bit line (BL) becomes high level in the sense amplification section (t6), and the complementary bit line (BLB) becomes high. It can be low level. Accordingly, the memory controller 100 may determine that the bonding of the node N _bl is normal based on the high level bit line BL.

9 and 10, for convenience of explanation, the voltage value of the complementary bit line (BLB) is VDD/2 (V) at time tb, or the voltage value of the bit line BL is VDD at time tc. /2 (V) is shown, but it is not necessarily limited to this. For example, the first voltage applied to the bit line (BL) is implemented to be higher than the second voltage applied to the complementary bit line (BLB), and the first voltage and/or the second voltage is VDD/2 (V) It could be higher or lower. In addition, the time points (tb and tc) are not necessarily determined by the time when the voltage of the bit line (BL) or the voltage of the complementary bit line (BLB) becomes VDD/2 (V), but rather the time when the voltage of the bit line (BL) becomes VDD/2 (V). The voltage of the complementary bit line (BLB) may be determined by the time at which a difference occurs.

Figure 11 shows a portion of a circuit diagram of a memory device according to one embodiment.

Referring to FIG. 11 , the memory device may include a sense amplifier region 1110, a bonding region 1120, and a cell region 1130. Here, the sense amplifier area 1110 may be formed on one die as a peripheral circuit area, and the cell area 1130 may be formed on another die. The bonding area 1120 is an area where the cell area 830 and the peripheral circuit area are bonded, and may include numerous bonding points. Figure 11 shows N+2 bonding points for a bit line (BL) and N+1 complementary bit lines (BLB#0 to BLB#N). Here, N may be an integer greater than 1.

The sense amplifier area 1110 may include a bit line (BL), complementary bit lines (BLB#0 to BLB#N), a latch 1111, and a precharge circuit 1113. Although the capacitor (C' _bl ) and the capacitor (C' _blb0 ~C' _blbn ) are shown within the sense amplifier region 1110, they represent the parasitic capacitance of the bonding region 1120, and in reality, the capacitor is in the sense amplifier region 1110. It may not be located. The bit line (BL), complementary bit lines (BLB#0 to BLB#N), capacitor (C' _bl ), capacitor (C' _blb0 to C' _blbn ), latch (1111), and precharge circuit (1113) are Data can be output through individual operations in the precharge section and sense amplification section.

The bit line BL may connect the sense amplifier area 1110 and the cell area 1130. In the precharge period, the precharge circuit 1113 may apply the first voltage to the bit line BL.

The capacitor C' _bl may be connected to the bit line BL through the node N' _bl of the bonding area 1120. The capacitor C' _bl may be charged based on the first voltage in the precharge period.

Complementary bit lines (BLB#0 to BLB#N) may connect the sense amplifier area 1110 and the cell area 1130. In the precharge period, the precharge circuit 1113 may apply a second voltage to the complementary bit lines (BLB#0 to BLB#N). The second voltage may be lower than the first voltage. The precharge circuit 1113 may not apply voltage to the bit line (BL) and complementary bit lines (BLB#0 to BLB#N) during the sensing period. For example, a switch may be placed between the precharge circuit 1113 and the bit line (BL) and complementary bit lines (BLB#0 to BLB#N).

The capacitors (C' _blb0 to C' _blbn ) may be connected to the complementary bit lines (BLB#0 to BLB#N) through the nodes (N' _blb0 to N' _blbn ) of the bonding region 1120 . The capacitors (C' _blb0 ~C' _blbn ) may be charged based on the second voltage in the precharge period.

If the bonding to the node (N' _bl ) of the bonding area 1120 is defective and the bonding to the nodes (N' _blb0 ~N' _blbn ) is normal, the charge charged in the capacitor (C' _bl ) is the capacitor (C' _blb0 ~C' _blbn ) may be smaller than the charge charged to each.

If the bonding to the node (N' _bl ) and the node (N' _blb0 ~N' _blbn ) of the bonding area 1120 is normal, the charge charged in the capacitor (C' _bl ) is the capacitor (C' _blb0 ~C' _blbn) ) can be larger than the charge charged to each.

The latch 1111 may be connected to the bit line (BL) and the complementary bit lines (BLB#0 to BLB#N). For example, the latch 1111 may include a first inverter and a second inverter. The output terminal of the first inverter and the input terminal of the second inverter may be connected to the bit line BL. The input terminal of the first inverter and the output terminal of the second inverter may be connected to complementary bit lines (BLB#0 to BLB#N). The latch 1111 may operate in the sense amplification period following the precharge period. The latch 1111 may be in an off state during the precharge period. The latch 1111 may amplify the difference between the voltage of the bit line BL and the average value (average voltage value) of the voltages of the complementary bit lines BLB#0 to BLB#N in the sense amplification section. That is, if the voltage of the capacitor (C' _bl ) in the pre-charge section is higher than the average voltage value of the capacitors (C' _blb0 ~C' _blbn ), the bit line (BL) becomes high level as a result of amplification in the sense amplification section, The complementary bit lines (BLB#0 to BLB#N) may be at low level. If the voltage of the capacitor (C' _bl ) in the precharge section is lower than the average voltage value of the capacitors (C' _blb0 ~C' _blbn ), the bit line (BL) becomes low level as a result of amplification in the sense amplification section, and the complementary bit The line (BLB#0~BLB#N) can be high level.

The memory controller 100 controls the bonding of the bonding area 1120 based on at least one of the voltage of the bit line BL or the voltage of the complementary bit lines (BLB#0 to BLB#N) according to the amplification result in the sense amplification section. You can determine whether it is defective or not.

For example, if the bonding for the node (N' _bl ) is normal and the bonding for the nodes (N' _blb0 ~N' _blbn ) is normal, the first voltage applied to the bit line (BL) is the complementary bit line ( Since it is higher than the second voltage applied to BLB#0~BLB#N), the bit line BL may be at a high level as a result of amplification in the sense amplification section. The memory controller 100 may determine that bonding to the node N' _bl is normal in response to the bit line BL being at a high level.

If the bonding to the node (N' _bl ) is normal and at least one of the bondings to the nodes (N' _blb0 to N' _blbn ) is defective, the bit line (BL) is at a high level as a result of the amplification in the sense amplification section. It can be. The memory controller 100 may determine that bonding to the node N' _bl is normal in response to the bit line BL being at a high level.

If the bonding to the node (N' _bl ) is defective and the bonding to the node (N' _blb0 ~N' _blbn ) is normal, the voltage of the node (N' _bl ) is equal to that of the node (N' _blb0 ~N' _blbn ). As the voltage value becomes lower than the average, the bit line (BL) may become low level as a result of amplification in the sense amplification section. The memory controller 100 may determine that the bonding to the node N' _bl is defective in response to the bit line BL being at a low level.

If the bonding to the node (N' _bl ) is defective and at least one of the bondings to the nodes (N' _blb0 to N' _blbn ) is defective, the voltage of the node (N' _bl ) is lower than the node (N' _blb0 to N' blbn). N' _blbn ) is lower than the average voltage value, so the bit line (BL) may become low level as a result of amplification in the sense amplification section. The memory controller 100 may determine that the bonding to the node N' _bl is defective in response to the bit line BL being at a low level. Even if at least one of the bondings for the nodes (N' _blb0 to N' _blbn ) is defective, the average voltage value of the complementary bit lines (BLB#0 to BLB#N) is close to the voltage value when the bonding is normal. This is because it is higher than the voltage of the node (N' _bl ).

In the above, it has been described that the memory controller 100 determines whether the bonding of the node (N' _bl ) is defective according to the level of the bit line (BL), but the level of the complementary bit line (BLB#0 to BLB#N) Depending on this, it may be implemented by determining whether the bonding of the node (N' _bl ) is defective.

The cell area 1130 may include cell strings 1131 to 1134. Cell strings 1131 to 1134 may include a plurality of memory cells connected in series. The cell string 1131 may be connected to a bit line (BL), and the cell strings 1132 to 1134 may be connected to complementary bit lines (BLB#0 to BLB#N), respectively.

The bonding area 1120 may connect the sense amplifier area 1110 and the cell area 1130 through the bit line (BL) and the complementary bit lines (BLB#0 to BLB#N).

Figure 12 is a flowchart of a defect detection method according to an embodiment.

Referring to FIG. 12, the memory device may precharge each memory cell and a peripheral circuit bonded to the memory cell by applying the same voltage (S1210). Memory cells may be formed in the first area, and peripheral circuits may be formed in the second area. Each of the first region and the second region may be implemented with a different die. A bonding area may be located between the first area and the second area.

The memory device may connect memory cells and peripheral circuits (S1220). In one embodiment, the peripheral circuit may include a switch connected to the first region. The switch may be open in the precharge section and closed in the sensing section following the precharge section. The switch connects the memory cell and the peripheral circuit and may be disposed in the second area. The memory device may open the switch in the precharge section and close the switch in the sensing section. The switch may be implemented with a first transistor. The memory device can open and close the switch based on the threshold voltage.

The memory device may determine whether the bonding between the memory cell and the peripheral circuit is defective based on the voltage value at the bonding point of the peripheral circuit (S1230). The peripheral circuit may further include a latch storing a preset value and a second transistor connected to the latch at the source or drain. For example, the preset value may be '1'. The gate of the transistor may be connected to the switch at the sensing node. After connecting the memory cell and the peripheral circuit, if the voltage of the sensing node exceeds the threshold voltage of the second transistor, the second transistor may be turned on and the preset value may be switched. After connecting the memory cell and the peripheral circuit, if the voltage of the sensing node does not exceed the threshold voltage of the transistor, the second transistor is turned off and the preset value is not switched and the existing value can be maintained. The memory controller may determine that bonding is normal if the value of the latch switches, and may determine that bonding is bad if the latch maintains its value.

13 is a flowchart of a defect detection method according to an embodiment.

Referring to FIG. 13, the memory device may apply different voltages to the first bit line and the second bit line (S1310). For example, the memory device may apply a first voltage to the first bit line and apply a second voltage lower than the first voltage to the second bit line. The first bit line and the second bit line may connect the cell area and peripheral circuit area of the memory device. The cell area and the peripheral circuit area may be divided into different dies. That is, a bonding area may be located between the cell area and the peripheral circuit area. The first bit line and the second bit line can be understood as having resistors, capacitors, etc. depending on the parasitic resistance and parasitic capacitance of the bonding area. The memory device may apply a voltage to the bit line during the precharge period.

The memory device may amplify the voltage difference between the first bit line and the second bit line (S1320). In one embodiment, when the bonding to the first bit line is defective, the voltage of the first bit line may be lower than the voltage of the second bit line at the end of the precharge period due to a voltage drop due to parasitic resistance. . As a result of amplification of the memory device, the voltage of the first bit line may be at a low level and the voltage of the second bit line may be at a high level. In one embodiment, when all bonding is normal, the voltage of the first bit line may be higher than the voltage of the second bit line at the end of the precharge period. As a result of amplification of the memory device, the voltage of the first bit line may be at a high level and the voltage of the second bit line may be at a low level. The memory device may amplify the voltage difference in the sense amplification section following the precharge section.

The memory device may determine whether bonding is defective based on the amplification result (S1330). If the voltage of the first bit line is at a low level as a result of amplification, the memory device may determine that the bonding to the first bit line is defective. If the voltage of the first bit line is at a high level as a result of amplification, the memory device may determine that bonding to the first bit line is normal.

Figure 14 is a schematic block diagram of a computing system according to one embodiment.

Referring to FIG. 14, the computing device 2000 includes a processor 2010, a memory 2020, a memory controller 2030, a storage device 2040, a communication interface 2050, and a bus 2060. Computing device 2000 may further include other general-purpose components.

The processor 2010 controls the overall operation of each component of the computing device 2000. The processor 2010 may be implemented as at least one of various processing units, such as a central processing unit (CPU), an application processor (AP), and a graphic processing unit (GPU).

The memory 2020 stores various data and commands. The memory 2020 may be implemented as a memory device described with reference to FIGS. 1 to 13. Memory controller 2030 controls the transfer of data or commands to and from memory 2020 . The memory controller 2030 may be implemented as the memory controller described with reference to FIGS. 1 to 13 . In some embodiments, the memory controller 2030 may be provided as a separate chip from the processor 2010. In some embodiments, the memory controller 2030 may be provided as an internal component of the processor 2010.

The storage device 2040 non-temporarily stores programs and data. In some embodiments, storage device 2040 may be implemented with non-volatile memory. The communication interface 2050 supports wired and wireless Internet communication of the computing device 2000. Additionally, the communication interface 2050 may support various communication methods other than Internet communication. The bus 2060 provides communication functions between components of the computing device 2000. Bus 2060 may include at least one type of bus depending on the communication protocol between components.

In some embodiments, each component or combination of two or more components described with reference to FIGS. 1-14 may be a digital circuit, a programmable or non-programmable logic device or array, or an application specific integrated circuit. , ASIC), etc.

Although the embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements can be made by those skilled in the art using the basic concept of the present invention defined in the following claims. It falls within the scope of rights.

Claims (10)

A memory device including a memory cell, a page buffer, and a first switch, one end of which is electrically connected to a bonding point of the memory cell at a first node, and the other end of which is connected to the page buffer at a second node; and
A precharge voltage is applied to the first node and the second node in a first section, the first switch is turned on in a second section following the first section, and after the first switch is turned on, the first switch is turned on. A memory controller that determines whether the bonding between the memory cell and the first switch is defective based on the voltage of the two nodes.
A semiconductor device including. According to paragraph 1,
The page buffer is,
a latch maintaining a first level in the first section; and
A transistor that causes the logic level of the latch to maintain the first level or switch to the second level based on the voltage of the second node in the second section.
Including,
The memory controller is,
Determining whether the bonding is defective based on the logic level of the latch in the second section,
semiconductor device. According to paragraph 2,
The transistor is,
A gate is connected to the second node, and a source or drain is connected to the latch,
semiconductor device. According to paragraph 2,
The memory controller is,
determining that the bonding is defective if the latch maintains the first level;
determining that the bonding is normal if the latch transitions from the first level to the second level,
semiconductor device. A plurality of bit lines connected to a plurality of memory cells; a precharge circuit that precharges a first bit line among the plurality of bit lines to a first voltage and precharges a second bit line to a second voltage lower than the first voltage; and a sense amplifier that amplifies the difference between the voltages of the first bit line and the second bit line and outputs the amplified voltage difference. and
A memory controller that determines whether bonding of the plurality of memory cells is defective based on the output from the sense amplifier.
A semiconductor device containing a. According to clause 5,
The memory controller is,
Controlling the precharge circuit so that the first bit line precharges the first voltage and the second bit line precharges the second voltage in a first section,
semiconductor device. According to clause 5,
The memory controller is,
If the voltage of the first bit line is higher than the voltage of the second bit line, determining that the bonding is normal,
semiconductor device. According to clause 5,
The memory controller is,
If the voltage of the second bit line is higher than the voltage of the first bit line, determining that the bonding is defective,
semiconductor device. According to clause 5,
The sense amplifier is,
It is connected to the first bit line, the second bit line, and a third bit line among the plurality of bit lines, and has an average value of the voltage of the second bit line and the voltage of the third bit line, and the first bit line. amplifying the difference from the line voltage,
semiconductor device. memory cell;
page buffer;
a first switch having one end connected to the memory cell at a first node and the other end connected to the page buffer at a second node;
a second switch connected between a power source supplying a precharge voltage and the first node; and
A third switch connected between the power source and the second node
Includes,
The page buffer is,
latch; and
A transistor connected between the input terminal of the latch and the ground terminal, and transmitting the voltage of the second node to the gate.
A semiconductor device containing a.