KR20230159182A - Ceramic ring for semiconductor etching process and manufacturing method thereof - Google Patents
Ceramic ring for semiconductor etching process and manufacturing method thereof Download PDFInfo
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- KR20230159182A KR20230159182A KR1020220059219A KR20220059219A KR20230159182A KR 20230159182 A KR20230159182 A KR 20230159182A KR 1020220059219 A KR1020220059219 A KR 1020220059219A KR 20220059219 A KR20220059219 A KR 20220059219A KR 20230159182 A KR20230159182 A KR 20230159182A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 238000005530 etching Methods 0.000 title description 15
- 239000000919 ceramic Substances 0.000 title description 3
- 238000003672 processing method Methods 0.000 title 1
- 239000000463 material Substances 0.000 claims abstract description 39
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 19
- 239000010453 quartz Substances 0.000 claims abstract description 13
- 235000012239 silicon dioxide Nutrition 0.000 claims description 15
- CPLXHLVBOLITMK-UHFFFAOYSA-N Magnesium oxide Chemical compound [Mg]=O CPLXHLVBOLITMK-UHFFFAOYSA-N 0.000 claims description 12
- 239000000395 magnesium oxide Substances 0.000 claims description 6
- 238000001020 plasma etching Methods 0.000 claims description 5
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 5
- INAHAJYZKVIDIZ-UHFFFAOYSA-N boron carbide Chemical compound B12B3B4C32B41 INAHAJYZKVIDIZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 4
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 3
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 3
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052594 sapphire Inorganic materials 0.000 claims description 3
- 239000010980 sapphire Substances 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 229910052580 B4C Inorganic materials 0.000 claims description 2
- 238000000034 method Methods 0.000 description 12
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000007792 addition Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000005685 electric field effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
- H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
- H01L21/68757—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by a coating or a hardness or a material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/32715—Workpiece holder
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
- H01L21/67063—Apparatus for fluid treatment for etching
- H01L21/67069—Apparatus for fluid treatment for etching for drying etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6831—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using electrostatic chucks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
- H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
- H01L21/68721—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by edge clamping, e.g. clamping ring
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Analytical Chemistry (AREA)
- Drying Of Semiconductors (AREA)
Abstract
본 발명은 제1 소재로 형성된 제1 링 부분과 제2 소재로 형성된 제2 링 부분을 포함하는 반도체 제조공정용 유지링에 관한 것으로서, 제1 소재는 합성쿼츠로 형성되고, 제2 소재는 상기 제1 소재보다 내식각성이 높은 소재로 형성되는 것을 특징으로 한다. The present invention relates to a retaining ring for a semiconductor manufacturing process comprising a first ring portion formed of a first material and a second ring portion formed of a second material, wherein the first material is formed of synthetic quartz, and the second material is the above. It is characterized by being made of a material with higher etch resistance than the first material.
Description
본 발명은 내식각 특성이 향상된 반도체 공정용 세라믹링 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a ceramic ring for semiconductor processing with improved etch resistance properties.
반도체 제조공정 중 식각 공정은 빈번한 부품 교환이 요구된다. 구체적으로, 식각 공정은 웨이퍼를 이용하여 반도체 칩을 제조하면서 원하는 부분의 산화막 제거를 위한 플라즈마 식각을 수반하는데, 이때 웨이퍼뿐 아니라 웨이퍼를 지지하는 세라믹 링도 식각되어 웨이퍼의 위치가 어긋나는 문제가 발생한다. 아울러, 웨이퍼가 특정 위치에 고정되지 않는 경우, 불균일 식각이 발생하게 되므로 반도체 공정의 정확도와 효율이 감소할 수 있다.The etching process in the semiconductor manufacturing process requires frequent replacement of parts. Specifically, the etching process involves plasma etching to remove the oxide film from a desired area while manufacturing a semiconductor chip using a wafer. At this time, not only the wafer but also the ceramic ring that supports the wafer is etched, causing the problem of the wafer being misaligned. . Additionally, if the wafer is not fixed in a specific position, non-uniform etching may occur, which may reduce the accuracy and efficiency of the semiconductor process.
한편, 식각공정에서 사용되는 유지링의 소재는 쿼츠소재가 대부분을 차지하고 있다. 단결정 실리콘이나 산화 알루미나를 사용하던 일부 국가 또는 장비의 경우에도 12인치 웨이퍼 제조공정에서는 쿼츠로 변경되는 추세이다. 특히, 쿼츠소재를 사용하는 기업은 점차 천연쿼츠에서 합성쿼츠로 소재를 변경하고 있다. Meanwhile, the majority of retaining ring materials used in the etching process are quartz. Even in some countries or equipment that used single crystal silicon or alumina oxide, there is a trend of changing to quartz in the 12-inch wafer manufacturing process. In particular, companies using quartz materials are gradually changing their materials from natural quartz to synthetic quartz.
한편, 반도체 제조기업들은 칩의 집적도 향상을 위해 적층수를 증가하거나, 선폭을 미세화하고 있다. 식각공정과 관련하여, 적층수의 증가는 식각되는 깊이가 깊어지는 것을 의미하며, 선폭의 미세화는 식각되는 부분과 식각되지 않는 부분의 구분이 보다 명확해지는 것을 의미한다.Meanwhile, semiconductor manufacturing companies are increasing the number of stacks or narrowing the line width to improve chip integration. Regarding the etching process, an increase in the number of layers means a deeper etching depth, and a narrower line width means that the distinction between the etched part and the non-etched part becomes clearer.
위와 같이 직접도 향상을 위한 공정에서는 더 강해진 균일 플라즈마 시스가 사용된다. 즉, 플라즈마 파워가 증가함으로써 웨이퍼 유지링의 식각을 빠르게 하여 쿼츠소재의 사용시간 및 교체주기가 짧아지는 문제점이 발생하고 있다.In the process for improving directivity as above, a stronger uniform plasma sheath is used. In other words, as the plasma power increases, the etching of the wafer retaining ring is accelerated, causing the problem of shortening the usage time and replacement cycle of the quartz material.
상기 문제점을 해결하기 위한 본 발명의 기술적 과제는, 쿼츠소재와 내식각 특성이 우수한 별도의 소재의 결합에 의해 제조된 웨이퍼 유지링을 제공하는 것이다.The technical problem of the present invention to solve the above problems is to provide a wafer retaining ring manufactured by combining a quartz material and a separate material with excellent etch resistance properties.
본 발명은 제1 소재로 형성된 제1 링 부분과 제2 소재로 형성된 제2 링 부분을 포함하는 반도체 제조공정용 유지링을 제공한다. 특히, 제1 소재는 합성쿼츠로 형성되고, 제2 소재는 상기 제1 소재보다 내식각성이 높은 소재로 형성되는 것을 특징으로 한다.The present invention provides a retaining ring for a semiconductor manufacturing process including a first ring portion formed of a first material and a second ring portion formed of a second material. In particular, the first material is made of synthetic quartz, and the second material is made of a material with higher etch resistance than the first material.
일 실시예에 있어서, 제2 소재는 사파이어로 형성되는 것을 특징으로 한다.In one embodiment, the second material is formed of sapphire.
일 실시예에 있어서, 반도체 제조공정용 유지링은, 플라즈마 에칭이 수행되는 플라즈마 챔버 내에 설치되고, 상기 제2 링 부분은 상기 제1 링 부분의 상면에 접하도록 구성되며, 상기 제2 링 부분의 상면은 상기 제1 링 부분의 상면보다 상기 플라즈마 챔버의 플라즈마 유입구 측에 더 가깝게 위치하도록 구성되는 것을 특징으로 한다.In one embodiment, the retaining ring for a semiconductor manufacturing process is installed in a plasma chamber where plasma etching is performed, the second ring portion is configured to contact the upper surface of the first ring portion, and the second ring portion is configured to contact the upper surface of the first ring portion. The upper surface is configured to be located closer to the plasma inlet side of the plasma chamber than the upper surface of the first ring portion.
일 실시예에 있어서, 상기 제1 링 부분의 외경은, 상기 제2 링 부분의 외경보다 더 크게 형성되어 상기 플라즈마 챔버의 내벽과 접하도록 구성되는 것을 특징으로 한다.In one embodiment, the outer diameter of the first ring portion is larger than the outer diameter of the second ring portion and is configured to contact the inner wall of the plasma chamber.
일 실시예에 있어서, 상기 제1 링 부분의 하면은, 상기 플라즈마 챔버의 정전척과 접하도록 구성되는 것을 특징으로 한다.In one embodiment, the lower surface of the first ring portion is configured to contact the electrostatic chuck of the plasma chamber.
일 실시예에 있어서, 상기 제1 링 부분과 상기 제2 링 부분이 서로 접하는 면에 의해 형성되는 접면내경의 높이는, 상기 접면외경의 높이 보다 더 낮도록 형성되는 것을 특징으로 한다.In one embodiment, the height of the inner diameter of the contact surface formed by the surface where the first ring part and the second ring part contact each other is formed to be lower than the height of the outer diameter of the contact surface.
일 실시예에 있어서, 상기 제1 링 부분과 상기 제2 링 부분이 서로 접하는 면은 계단 형태로 굴곡지게 형성되는 것을 특징으로 한다.In one embodiment, a surface where the first ring portion and the second ring portion contact each other is curved in a step shape.
본 발명에 따르면 강한 플라즈마 환경에서 증대된 내구성을 바탕으로 반도체 제조공정용 유지링의 교체 주기를 증가시킬 수 있는 장점이 있다.According to the present invention, there is an advantage in that the replacement cycle of the retaining ring for the semiconductor manufacturing process can be increased based on increased durability in a strong plasma environment.
또한, 본 발명에 따르면 반도체 제조공정용 유지링의 내구성이 증가되므로, 반도체 공정 불량률을 줄이는 효과가 있다.In addition, according to the present invention, the durability of the retaining ring for the semiconductor manufacturing process is increased, which has the effect of reducing the defect rate in the semiconductor process.
도 1은 본 발명의 일 실시예에 따른 반도체 제조공정용 유지링을 나타내는 사시도이다.
도 2는 본 발명의 일 실시예에 따른 반도체 제조공정용 유지링의 단면을 나타내는 단면도이다.
도 3은 종래 반도체 제조공정용 유지링 나타낸 개념도이다.
도 4는 본 발명의 일 실시예에 따른 반도체 제조공정용 유지링을 나타내는 개념도이다.1 is a perspective view showing a retaining ring for a semiconductor manufacturing process according to an embodiment of the present invention.
Figure 2 is a cross-sectional view showing a cross-section of a retaining ring for a semiconductor manufacturing process according to an embodiment of the present invention.
Figure 3 is a conceptual diagram showing a conventional retaining ring for a semiconductor manufacturing process.
Figure 4 is a conceptual diagram showing a retaining ring for a semiconductor manufacturing process according to an embodiment of the present invention.
이하, 첨부된 도면을 참조하여 본 발명의 실시 예에 대하여 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자가 용이하게 실시할 수 있도록 상세히 설명한다. 그러나 본 발명은 여러 가지 상이한 형태로 구현될 수 있으며 이하에서 개시되는 실시 예에 한정되지 않는다. 또한 도면에서 본 발명을 명확하게 개시하기 위해서 본 발명과 관계없는 부분은 생략하였으며, 도면에서 동일하거나 유사한 부호들은 동일하거나 유사한 구성요소들을 나타낸다.Hereinafter, with reference to the attached drawings, embodiments of the present invention will be described in detail so that those skilled in the art can easily implement the present invention. However, the present invention may be implemented in various different forms and is not limited to the embodiments disclosed below. In addition, in order to clearly disclose the present invention in the drawings, parts not related to the present invention are omitted, and identical or similar symbols in the drawings indicate identical or similar components.
본 발명의 목적 및 효과는 하기의 설명에 의해서 자연스럽게 이해되거나 보다 분명해질 수 있으며, 하기의 기재만으로 본 발명의 목적 및 효과가 제한되는 것은 아니다.The purpose and effect of the present invention can be naturally understood or become clearer through the following description, and the purpose and effect of the present invention are not limited to the following description.
본 발명의 목적, 특징 및 장점은 다음의 상세한 설명을 통하여 보다 분명해질 것이다. 또한, 본 발명을 설명함에 있어서 본 발명과 관련된 공지 기술에 대한 구체적인 설명이, 본 발명의 요지를 불필요하게 흐릴 수 있다고 판단되는 경우에는 그 상세한 설명을 생략하기로 한다. 이하, 첨부된 도면을 참조하여 본 발명에 따른 실시예를 상세히 설명하기로 한다.The purpose, features and advantages of the present invention will become clearer through the following detailed description. Additionally, in describing the present invention, if it is determined that a detailed description of known techniques related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description will be omitted. Hereinafter, embodiments according to the present invention will be described in detail with reference to the attached drawings.
도 1은 본 발명의 일 실시예에 따른 반도체 제조공정용 유지링(10)을 나타내는 사시도이며, 도 2는 상기 반도체 제조공정용 유지링(10)의 단면을 나타낸 것이다.FIG. 1 is a perspective view showing a retaining ring 10 for a semiconductor manufacturing process according to an embodiment of the present invention, and FIG. 2 shows a cross section of the retaining ring 10 for a semiconductor manufacturing process.
도 1 및 도 2를 참조하면, 반도체 제조공정용 유지링(10)은, 제1 소재로 제1 링 부분(1)과, 제2 소재로 형성된 제2 링 부분(2)을 포함할 수 있다.Referring to Figures 1 and 2, the retaining ring 10 for a semiconductor manufacturing process may include a first ring part 1 made of a first material and a second ring part 2 formed of a second material. .
구체적으로, 제1 소재는 합성쿼츠로 형성될 수 있으며, 제2 소재는 제1 소재보다 내식각성이 높은 소재로 형성될 수 있다.Specifically, the first material may be made of synthetic quartz, and the second material may be made of a material with higher etch resistance than the first material.
예를 들어, 제1 소재는 단결정 및 주상정 실리콘(Silicon)이나 쿼츠(Quartz) 또는 화학기상증착 실리콘 카바이드(CVD-SiC)로 형성될 수 있다.For example, the first material may be formed of single crystal and columnar silicon, quartz, or chemical vapor deposition silicon carbide (CVD-SiC).
다른 예에서, 제1 소재는 탄화규소, 탄화붕소, 질화규소 등 비산화물계 구조 재료를 소결하여 제조한 소결체에 의해 구성될 수도 있다.In another example, the first material may be composed of a sintered body manufactured by sintering a non-oxide-based structural material such as silicon carbide, boron carbide, or silicon nitride.
다른 예에서, 제1 소재는 석영(쿼츠) 재질로 제작되거나 보론카바이드(boron carbide, B4C) 재질일 수 있다.In another example, the first material may be made of quartz or boron carbide (B4C).
또한, 일 예에서, 제2 소재는 사파이어, SiC(Silicon Carbide), B4C(Boron Carbide), Al2O3(Aluminum Oxide), SiO2(Silicon Dioxide) 및 MgO(Magnesia Oxide) 중 적어도 하나를 포함하여 구성될 수 있다.Additionally, in one example, the second material is at least one of sapphire, silicon carbide (SiC), boron carbide (B 4 C), aluminum oxide (Al 2 O 3 ), silicon dioxide (SiO 2 ), and magnesia oxide (MgO). It may be configured to include.
한편, 플라즈마 에칭이 실시되는 플라즈마 챔버는 상부 전극과 하부에 전극을 포함하는 정전 척, 그리고 플라즈마 공정 챔버 내에서 발생하는 플라즈마로부터 정전 척을 보호하도록 정전 척을 둘러싸는 커버링 어셈블리로 구성되며, 반도체 웨이퍼 혹은 유리 기판 등과 같은 기판은 정전 척의 상부 표면에 지지된다. Meanwhile, the plasma chamber in which plasma etching is performed consists of an electrostatic chuck including an upper electrode and a lower electrode, and a covering assembly surrounding the electrostatic chuck to protect the electrostatic chuck from the plasma generated within the plasma process chamber, and the semiconductor wafer Alternatively, a substrate such as a glass substrate is supported on the upper surface of the electrostatic chuck.
이에 상부 전극과 하부의 정전 척 사이에 전원이 인가되면 전계효과에 의해 플라즈마 공정 챔버 내에 플라즈마(P)가 발생하여 이온들이 정전 척을 향하는 방향으로 입사되며, 플라즈마 이온의 화학 반응 및 운동에너지로 기판 상에 에칭이 실시되게 된다.Accordingly, when power is applied between the upper electrode and the lower electrostatic chuck, plasma (P) is generated in the plasma process chamber due to the electric field effect, and ions are incident in the direction toward the electrostatic chuck, and the chemical reaction and kinetic energy of the plasma ions Etching is performed on the image.
이때, 반도체 제조공정용 유지링(10)은 플라즈마 에칭이 수행되는 플라즈마 챔버 내에 설치될 수 있다.At this time, the retaining ring 10 for the semiconductor manufacturing process may be installed in a plasma chamber where plasma etching is performed.
아울러, 유지링의 제2 링 부분(2)은 제1 링 부분(1)의 상면에 접하도록 구성될 수 있다.In addition, the second ring part 2 of the retaining ring may be configured to contact the upper surface of the first ring part 1.
특히, 제2 링 부분(2)의 상면은 제1 링 부분(1)의 상면보다 플라즈마 챔버의 플라즈마 유입구 측에 더 가깝게 위치하도록 구성될 수 있다.In particular, the upper surface of the second ring part 2 may be configured to be located closer to the plasma inlet side of the plasma chamber than the upper surface of the first ring part 1.
일 실시예에서, 제1 링 부분(1)의 외경은, 제2 링 부분(2)의 외경보다 더 크게 형성되어 플라즈마 챔버의 내벽과 접하도록 구성될 수 있다.In one embodiment, the outer diameter of the first ring portion 1 may be larger than the outer diameter of the second ring portion 2 and may be configured to contact the inner wall of the plasma chamber.
또한, 제1 링 부분(1)의 하면은, 플라즈마 챔버의 정전척과 접하도록 구성될 수 있다.Additionally, the lower surface of the first ring portion 1 may be configured to contact the electrostatic chuck of the plasma chamber.
다른 실시예에서, 제1 링 부분(1)과 제2 링 부분(2)이 서로 접하는 면에 의해 형성되는 접면내경의 높이는, 상기 접면외경의 높이 보다 더 낮도록 형성될 수 있다.In another embodiment, the height of the inner diameter of the contact surface formed by the surface where the first ring part 1 and the second ring part 2 contact each other may be formed to be lower than the height of the outer diameter of the contact surface.
도 2에는 이러한 접면의 형태와 관련된 일 실시예가 도시된다.Figure 2 shows an embodiment related to the shape of this contact surface.
도 2를 참조하면, 제1 링 부분(1)과 제2 링 부분(2)이 서로 접하는 면은 계단 형태로 굴곡지게 형성될 수 있다.Referring to Figure 2, the surface where the first ring part 1 and the second ring part 2 contact each other may be curved in a step shape.
도시되지는 않았으나, 제1 링 부분(1)과 제2 링 부분(2)이 서로 접하는 면은 외경 측이 내경 측보다 플라즈마 유입구에 가깝도록 경사진 형태로 구성될 수도 있다.Although not shown, the surface where the first ring part 1 and the second ring part 2 contact each other may be inclined so that the outer diameter side is closer to the plasma inlet than the inner diameter side.
도 3은 종래 유지링의 식각량을 나타낸 개념도이며, 도 4는 본 발명에 따른 유지링(10)의 식각량을 나타낸 개념도이다.Figure 3 is a conceptual diagram showing the etching amount of a conventional retaining ring, and Figure 4 is a conceptual diagram showing the etching amount of the retaining ring 10 according to the present invention.
도 3을 참조하면, 유지링의 내경에 가까울수록 식각량(3)이 증가하는 것을 확인할 수 있으며, 이와 같이 불균일한 식각량에 의해 불량률이 증가하는 문제점이 있다.Referring to FIG. 3, it can be seen that the etching amount 3 increases as it approaches the inner diameter of the retaining ring. As such, there is a problem in that the defect rate increases due to the non-uniform etching amount.
반면, 도 4에 도시된 것과 같이, 본 발명에 따른 유지링(10)의 경우, 내식각성이 우수한 제2 링 부분에 의해 식각량(4)이 상대적으로 일정하게 유지됨을 알 수 있다.On the other hand, as shown in FIG. 4, in the case of the retaining ring 10 according to the present invention, it can be seen that the etching amount 4 is maintained relatively constant due to the second ring portion having excellent etching resistance.
한편, 상술한 소재 이외에도 Al2O3(Aluminum Oxide)와 SiO2(Silicon Dioxide) 및 MgO(Magnesia Oxide)를 함유하는 소재를 포함하여 상술한 바와 같이 제1 링 부분(1)을 구성하는 방식도 가능하다.Meanwhile, in addition to the materials described above, there is also a method of constructing the first ring portion 1 as described above, including materials containing Al 2 O 3 (Aluminum Oxide), SiO 2 (Silicon Dioxide), and MgO (Magnesia Oxide). possible.
상기한 본 발명의 바람직한 실시 예는 예시의 목적으로 개시된 것이고, 본 발명에 대해 통상의 지식을 가진 당업자라면 본 발명의 사상과 범위 안에서 다양한 수정, 변경 및 부가가 가능할 것이며, 이러한 수정, 변경 및 부가는 상기의 특허청구 범위에 속하는 것으로 보아야 할 것이다.The preferred embodiments of the present invention described above have been disclosed for illustrative purposes, and those skilled in the art will be able to make various modifications, changes, and additions within the spirit and scope of the present invention, and such modifications, changes, and additions will be possible. should be regarded as falling within the scope of the above patent claims.
본 발명이 속하는 기술분야에서 통상의 지식을 가진 자라면, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서, 여러 가지 치환, 변형 및 변경이 가능하므로, 본 발명은 전술한 실시 예 및 첨부된 도면에 의해 한정되는 것이 아니다.Those of ordinary skill in the technical field to which the present invention pertains can make various substitutions, modifications and changes without departing from the technical spirit of the present invention. Therefore, the present invention is limited to the above-described embodiments and the accompanying drawings. It is not limited by
상술한 예시적인 시스템에서, 방법들은 일련의 단계 또는 블록으로써 순서도를 기초로 설명되고 있지만, 본 발명은 단계들의 순서에 한정되는 것은 아니며, 어떤 단계는 상술한 바와 다른 단계와 다른 순서로 또는 동시에 발생할 수 있다. 또한, 당업자라면 순서도에 나타낸 단계들이 배타적이지 않고, 다른 단계가 포함되거나 순서도의 하나 또는 그 이상의 단계가 본 발명의 범위에 영향을 미치지 않고 삭제될 수 있음을 이해할 수 있을 것이다.In the above-described exemplary system, the methods are described on a flowchart basis as a series of steps or blocks; however, the invention is not limited to the order of the steps, and some steps may occur simultaneously or in a different order than other steps as described above. You can. Additionally, those skilled in the art will understand that the steps shown in the flowchart are not exclusive and that other steps may be included or one or more steps in the flowchart may be deleted without affecting the scope of the present invention.
Claims (7)
상기 제1 소재는 합성쿼츠로 형성되고,
상기 제2 소재는 상기 제1 소재보다 내식각성이 높은 소재로 형성되는 것을 특징으로 하는 반도체 제조공정용 유지링.A retaining ring for a semiconductor manufacturing process comprising a first ring portion formed of a first material and a second ring portion formed of a second material,
The first material is formed of synthetic quartz,
A retaining ring for a semiconductor manufacturing process, wherein the second material is formed of a material with higher etch resistance than the first material.
상기 제2 소재는 사파이어, SiC(Silicon Carbide), B4C(Boron Carbide), Al2O3(Aluminum Oxide), SiO2(Silicon Dioxide) 및 MgO(Magnesia Oxide) 중 적어도 하나를 포함하여 구성되는 것을 특징으로 하는 반도체 제조공정용 유지링.According to paragraph 1,
The second material includes at least one of sapphire, SiC (Silicon Carbide), B 4 C (Boron Carbide), Al 2 O 3 (Aluminum Oxide), SiO 2 (Silicon Dioxide), and MgO (Magnesia Oxide). A retaining ring for a semiconductor manufacturing process, characterized in that.
상기 반도체 제조공정용 유지링은,
플라즈마 에칭이 수행되는 플라즈마 챔버 내에 설치되고,
상기 제2 링 부분은 상기 제1 링 부분의 상면에 접하도록 구성되며,
상기 제2 링 부분의 상면은 상기 제1 링 부분의 상면보다 상기 플라즈마 챔버의 플라즈마 유입구 측에 더 가깝게 위치하도록 구성되는 것을 특징으로 하는 반도체 제조공정용 유지링.According to paragraph 1,
The retaining ring for the semiconductor manufacturing process is,
Installed in a plasma chamber where plasma etching is performed,
The second ring portion is configured to contact the upper surface of the first ring portion,
A retaining ring for a semiconductor manufacturing process, characterized in that the upper surface of the second ring portion is located closer to the plasma inlet side of the plasma chamber than the upper surface of the first ring portion.
상기 제1 링 부분의 외경은, 상기 제2 링 부분의 외경보다 더 크게 형성되어 상기 플라즈마 챔버의 내벽과 접하도록 구성되는 것을 특징으로 하는 반도체 제조공정용 유지링.According to paragraph 3,
A retaining ring for a semiconductor manufacturing process, wherein the outer diameter of the first ring portion is larger than the outer diameter of the second ring portion and is configured to contact the inner wall of the plasma chamber.
상기 제1 링 부분의 하면은, 상기 플라즈마 챔버의 정전척과 접하도록 구성되는 것을 특징으로 하는 반도체 제조공정용 유지링.According to paragraph 3,
A retaining ring for a semiconductor manufacturing process, characterized in that the lower surface of the first ring portion is configured to contact the electrostatic chuck of the plasma chamber.
상기 제1 링 부분과 상기 제2 링 부분이 서로 접하는 면에 의해 형성되는 접면내경의 높이는, 상기 접면외경의 높이 보다 더 낮도록 형성되는 것을 특징으로 하는 반도체 제조공정용 유지링.According to paragraph 3,
A retaining ring for a semiconductor manufacturing process, wherein the height of the inner diameter of the contact surface formed by the surface where the first ring part and the second ring part are in contact with each other is formed to be lower than the height of the outer diameter of the contact surface.
상기 제1 링 부분과 상기 제2 링 부분이 서로 접하는 면은 계단 형태로 굴곡지게 형성되는 것을 특징으로 하는 반도체 제조공정용 유지링.According to clause 6,
A retaining ring for a semiconductor manufacturing process, wherein a surface where the first ring portion and the second ring portion contact each other is curved in a step shape.
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| KR102102131B1 (en) | 2019-10-31 | 2020-04-20 | 주식회사 테크놀로지메이컬스 | Combined focus ring |
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| KR102102131B1 (en) | 2019-10-31 | 2020-04-20 | 주식회사 테크놀로지메이컬스 | Combined focus ring |
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