KR20230158420A - Filter module - Google Patents

Abstract

The filter module of the embodiment includes a first ground layer, a second ground layer disposed to be spaced apart from the first ground layer, a first conductive pattern layer disposed between the first ground layer and the second ground layer, and a first ground layer. A second conductive pattern layer disposed on one side of the ground layer or the second ground layer and a via connecting at least two of the first ground layer, the second ground layer, the first conductive pattern layer, and the second conductive pattern layer. Includes.

Description

Filter module {Filter module}

The embodiment relates to an antenna module having a filter module or a Wi-Fi and Bluetooth antenna, and a high-frequency module having the same.

A filter that filters signals in a desired frequency band can be applied to various devices or fields, including antennas, etc. These bandpass filters require inductors and capacitors.

If such a band-pass filter is implemented using inductors and capacitors, which are lumped constant elements, various problems are involved, such as increased insertion loss, increased signal distortion, increased thickness, and increased size, so research on this is in progress.

Bluetooth communication consists of a series of chips and antennas, and refers to a device that communicates in the approximately 2.4 to 2.5 GHz band according to the Bluetooth wireless interface standard at a distance of approximately 10 to 100 meters.

Wi-Fi (Wireless Fidelity) is a short-distance communication device that communicates in the approximately 2.4-2.5 GHz band or 5 GHz band, and uses radio waves or infrared transmission in places where a wireless access point (AP) is installed. It refers to a device that enables access to the Internet or directly connects (Wi-Fi Direct) with other Wi-Fi modules in a P2P concept.

These Bluetooth and Wi-Fi modules were previously configured as independent modules and installed in electronic products. Accordingly, when it is necessary to install both BT and Wi-Fi modules in a specific electronic product, the product needs to be miniaturized. , various problems could occur in aspects such as system stability.

Specifically, the Bluetooth and Wi-Fi modules are all devices that communicate through RF signals, and there are elements that can be included in common with each other. When constructing an independent module, these elements can be used redundantly. there was. Therefore, it could hinder the miniaturization of products, cause social waste of electronic components, and cause instability in the system due to the overlapping configuration of devices.

Additionally, while Bluetooth uses channels that overlap with Wi-Fi channels, it does not use the 5-6 GHz band. Therefore, a Bluetooth antenna requires a filter capable of filtering the 5-6 GHz band, but if the circuit is constructed using passive elements, the size may increase and price competitiveness may decrease.

Embodiments provide a filter module with improved performance and structure.

Embodiments of the invention provide a new antenna module that can solve the above problems.

An embodiment of the invention provides an antenna module with a Bluetooth filter built into a board without using passive elements.

An embodiment of the invention provides an antenna module that does not use passive elements and has a low-pass filter built into a board and connected to a Bluetooth antenna.

A filter module according to one embodiment includes a first ground layer; a second ground layer disposed to be spaced apart from the first ground layer; a first conductive pattern layer disposed between the first ground layer and the second ground layer; a second conductive pattern layer disposed on one side of the first ground layer or the second ground layer; and a via connecting at least two of the first ground layer, the second ground layer, the first conductive pattern layer, and the second conductive pattern layer.

For example, the first conductive pattern layer may include a capacitance pattern formed to have capacitance while facing at least one of the first ground layer and the second ground layer.

For example, the first conductive pattern layer may include a first inductance pattern formed to have inductance.

For example, the second conductive pattern layer may include a second inductance pattern formed to have inductance.

For example, the width of the inductance pattern may be smaller than the width of the capacitance pattern.

For example, it includes a first opening where the second inductance pattern is disposed,

The first ground layer may include a second opening that vertically overlaps the first opening.

For example, each of the first or second inductance patterns includes an inductance pattern having a planar shape that is bent in the horizontal direction at least once, and the maximum number of times the first inductance pattern is bent in the horizontal direction is the second inductance pattern. It may be greater than the maximum number of bending times.

For example, the capacitance pattern may include a second capacitor pattern forming a second capacitor;

a first capacitor pattern disposed to be spaced apart from one side of the second capacitor pattern and forming a first capacitor; and a third capacitor pattern disposed to be spaced apart from the other side of the second capacitor pattern and forming a third capacitor.

For example, the second capacitor pattern may include a first stub; a second stub disposed on one side of the first stub; And it may include a third stub disposed on the other side opposite to the one side of the first stub.

For example, the first inductance pattern may include a first inductor pattern arranged to connect a first via and a second via to form a first inductor; a second inductor pattern disposed to connect the first via and the first capacitor pattern to form a second inductor;

a fifth inductor pattern disposed to connect a third via and the third capacitor pattern to form a fifth inductor; and a sixth inductor pattern disposed to connect the third via and the fourth via to form a sixth inductor.

For example, the second inductance pattern may include a third inductor pattern arranged to connect the first via and the fifth via and to connect the fifth via and the sixth via to form a third inductor; and a fourth inductor pattern disposed to connect the sixth via and the third via to form a fourth inductor, and the sixth via may be connected to the second capacitor pattern.

For example, the line width of at least one of the first to sixth inductor patterns may be 250 μm or less.

For example, the line width of at least one of the first and third capacitor patterns may be 300 μm or more.

For example, the length of at least one of the first to sixth inductor patterns may be less than one eighth of the wavelength at the fundamental frequency.

A filter module according to another embodiment includes a second ground layer; a first conductive pattern layer stacked on the second ground layer and having a pattern implementing an inductor and a capacitor; a first ground layer stacked on the first conductive pattern layer; a second conductive pattern layer stacked on the first ground layer and including a transmission line with a pattern implementing an inductor; and a via connecting the inductor and the capacitor of the first conductive pattern layer and the inductor of the second conductive pattern portion in a vertical direction.

An antenna module according to an embodiment of the invention includes a substrate to which a first antenna is coupled; a low-pass filter unit embedded in a portion of the substrate; and a first transmission line connecting the first antenna and the low-pass filter unit, wherein the low-pass filter unit includes first to fourth conductive layers and a first transmission line disposed between the first to fourth conductive layers, respectively. to a third dielectric layer, wherein the first conductive layer includes a first pattern having a first via, a second pattern connected between one end of the first pattern and a second via, and a third pattern connected to the third via. wherein the second conductive layer has a ground pattern having a gap with first to third vias therein, and the third conductive layer has a fourth pattern opposite to the first pattern and spaced apart from the fourth pattern. and includes a fifth pattern opposite the second via and the third pattern, wherein the fourth conductive layer includes a sixth pattern connected between the internal second via and the ground via, and the second via and the third via. and a seventh pattern connected therebetween, wherein the first and third patterns of the first conductive layer, the fourth and fifth patterns of the third conductive layer, and the first and second dielectric layers include the first and third patterns. Forming two capacitors, the second pattern, the sixth pattern, and the seventh pattern have a line shape and may form first to third inductors.

According to an embodiment of the invention, the first and third patterns of the first conductive layer and the fourth and fifth patterns of the third conductive layer may have a polygonal plate shape.

According to an embodiment of the invention, the top surface area of the fifth pattern may be smaller than the top surface area of the third pattern and larger than the top surface area of the first pattern.

According to an embodiment of the invention, the top surface area of the third pattern may be smaller than the top surface area of the first pattern.

According to an embodiment of the invention, the first conductive layer is connected to a first input/output pattern connected to the other end of the first pattern and the first transmission line, and to a second transmission line connected to the second pattern and the other end of the low-pass filter unit. It may include a second input/output pattern.

According to an embodiment of the invention, the length of the sixth pattern may be longer than the length of the second pattern.

According to an embodiment of the invention, the number of bends of the sixth pattern may be greater than the number of bends of the second and seventh patterns.

According to an embodiment of the invention, the first capacitor is a first capacitance due to the first dielectric layer between the first pattern of the first conductive layer and the first circular pattern connected to the first via of the second conductive layer, and It may have a second capacitance due to the second dielectric layer between the first circular pattern and the fourth pattern.

According to an embodiment of the invention, the second capacitor includes a fifth pattern through a third via connected to the seventh pattern of the fourth conductive layer, a third circular pattern connected to the third via of the second conductive layer, and the first capacitor. It is connected to the third pattern of the conductive layer, and the second capacitor has a third capacitance between the third circular pattern and the fourth pattern, and a fourth capacitance due to the first dielectric layer between the fifth pattern and the third circular pattern. may include.

According to an embodiment of the invention, the second capacitor has a fifth capacitance due to the first dielectric layer between the first via of the first conductive layer and the second circular pattern connected to the second via of the second conductive layer, and the It may include a sixth capacitance caused by a second dielectric layer between the second circular pattern and the fourth circular pattern connected to the second via of the third conductive layer.

According to an embodiment of the invention, the third and fifth capacitances may be connected in parallel with each other, and the fourth and sixth capacitances may be connected in parallel with each other.

According to an embodiment of the invention, a Wi-Fi module connected to the low-pass filter and a second transmission line; and a second antenna connected to the Wi-Fi module, wherein the first antenna may be a Bluetooth antenna and the second antenna may be a Wi-Fi antenna.

According to an embodiment of the invention, the low-pass filter unit may pass the 2402 to 2480 MHz band and filter the 5 to 6 GHz band.

A high-frequency module according to an embodiment of the invention includes a low-pass filter unit in which a first input/output pattern is electrically connected to a Bluetooth antenna and a second input/output pattern is electrically connected to a Wi-Fi module, wherein the low-pass filter unit includes first to fourth filter units. A conductive layer, a plurality of dielectric layers respectively disposed between the first to fourth conductive layers, and a plurality of dielectric layers penetrating perpendicularly to the first to fourth conductive layers and the dielectric layers to selectively connect patterns of different conductive layers. It includes a via, and the dielectric layers disposed between one side pattern of the first to third conductive layers and one side pattern of the first to third conductive layers face each other, and a first branch node connected to the first input/output pattern. forming a first capacitor connected in parallel, the first line pattern of the first conductive layer forms a first inductor connected in series to the first branch node, and the second line pattern of the fourth conductive layer is A second inductor is connected in parallel from a third branch node connected to the other end of the first inductor, and a third line pattern of the fourth conductive layer is formed from a second branch node connected to the second input/output pattern and the third branch node. Forming a third inductor connected in parallel, the dielectric layers disposed between the other side pattern of the first to third conductive layers and the other side pattern of the first to third conductive layers are opposed to each other and are in series with the third inductor. A second capacitor is connected, and the other end of the first capacitor, the other end of the second inductor, and the other end of the second capacitor may be connected to a ground pattern.

According to an embodiment of the invention, the low-pass filter unit may pass the 2402 to 2480 MHz band and filter the 5 to 6 GHz band.

According to an embodiment of the invention, each of the first to third branch nodes may be formed by a via disposed in the low-pass filter unit.

The filter module according to the embodiment can secure a sufficient length of the inductor in a limited space, so that an inductor with a desired inductance can be designed, the frequency component can be improved, the insertion loss can be improved, etc., and the efficiency of the antenna is improved. Thus, the transmission distance can increase and the transmission speed can also be improved, and the delay can be improved and the signal distortion rate can be lowered. Additionally, the filter module can be implemented with a smaller thickness than when implementing the filter module by placing passive elements.

The invention can reduce the size of the antenna module by embedding a filter in the board without using inductor and capacitor components. Additionally, the cost of the antenna module can be reduced. In addition, the low-pass filter (LPF) built into the antenna module's board can be connected to the Bluetooth antenna to filter the 5~6GHz band, and the insertion loss characteristics of the 5~6GHz band are set to -3dB or less. There are configurable effects.

Figure 1 schematically shows a conceptual diagram of a filter module according to an embodiment.
FIG. 2 shows a circuit diagram of an embodiment of the filter module shown in FIG. 1.
Figures 3a and 3b show a perspective view and a plan view, respectively, of the second conductive pattern layer shown in Figure 1.
Figures 4a and 4b show a perspective view and a plan view, respectively, of the first ground layer shown in Figure 1.
FIGS. 5A and 5B show a perspective view and a top view, respectively, of the first conductive pattern layer shown in FIG. 1.
Figures 6a and 6b show a perspective view and a top view, respectively, of the second ground layer shown in Figure 1.
Figure 7 is a graph showing insertion loss by frequency of a filter module according to an embodiment.
Figure 8 is a graph showing inductance for each frequency implemented by the first and sixth inductor patterns.
Figure 9 is a graph showing capacitance for each frequency of the second capacitor pattern.
Figure 10 is a graph showing the insertion loss of the filter module according to the comparative example and the insertion loss of the filter module according to the embodiment.
Figure 11 shows the connection structure of a filter module according to an embodiment.
Figure 12 is a block diagram of an antenna module according to an embodiment of the invention.
FIG. 13 is a plan view showing a portion of the antenna module of FIG. 12.
Figure 14 is a perspective view showing the low-pass filter unit of Figure 13.
Figure 15 is another side view of the low-pass filter unit of Figure 14.
Figure 16 is an example of the circuit configuration of a low-pass filter according to the present invention.
Figure 17 is an exploded perspective view of the low-pass filter part of Figure 14.
FIG. 18 is a diagram showing the pattern shape of the first to fourth conductive layers of the low-pass filter unit of FIG. 17.
FIG. 19 is an example of a cross section on the AA side of the low-pass filter part of FIG. 14.
Figure 20 is an example of a cross section on the BB side of the low-pass filter part of Figure 14.
Figure 21 is a graph showing the operating characteristics of the low-pass filter unit of the antenna module according to an embodiment of the invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings.

However, the technical idea of the present invention is not limited to some of the described embodiments, but may be implemented in various different forms, and as long as it is within the scope of the technical idea of the present invention, one or more of the components may be optionally used between the embodiments. It can be used by combining and replacing.

In addition, terms (including technical and scientific terms) used in the embodiments of the present invention, unless specifically defined and described, are generally understood by those skilled in the art to which the present invention pertains. It can be interpreted as meaning, and the meaning of commonly used terms, such as terms defined in a dictionary, can be interpreted by considering the contextual meaning of the related technology.

Additionally, the terms used in the embodiments of the present invention are for describing the embodiments and are not intended to limit the present invention. In this specification, the singular may also include the plural unless specifically stated in the phrase, and when described as “at least one (or more than one) of A, B, and C”, it is combined with A, B, and C. It can contain one or more of all possible combinations.

Additionally, when describing the components of an embodiment of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are only used to distinguish the component from other components, and are not limited to the essence, sequence, or order of the component.

And, when a component is described as being 'connected', 'coupled' or 'connected' to another component, the component is not only directly connected, coupled or connected to that other component, but also is connected to that component. It may also include cases where other components are 'connected', 'coupled', or 'connected' by another component between them.

Additionally, when described as being formed or disposed “above” or “below” each component, “above” or “below” means not only when two components are in direct contact with each other, but also when two components are in direct contact with each other. This also includes cases where another component described above is formed or placed between two components. In addition, when expressed as “up (above) or down (down),” it can include not only the upward direction but also the downward direction based on one component.

Hereinafter, the filter modules 10 and 10A according to the embodiment will be described as follows with reference to the attached drawings. For convenience, the filter modules 10 and 10A are described using a Cartesian coordinate system (x-axis, y-axis, z-axis), but of course, they can also be described using other coordinate systems. Additionally, according to the Cartesian coordinate system, the x-axis, y-axis, and z-axis are orthogonal to each other, but the embodiment is not limited thereto. That is, the x-axis, y-axis, and z-axis may intersect each other.

Figure 1 schematically shows a conceptual diagram of the filter module 10 according to an embodiment.

The filter module 10 shown in FIG. 1 includes a first ground (or ground, or reference potential) layer GL1, a second ground layer GL2, a first conductive pattern layer TL1, and a second conductive layer. It may include a pattern layer (TL2) and a via (VA). Each layer may be expressed as a first to fourth layer.

The first ground layer GL1 and the second ground layer GL2 are arranged to be spaced apart from each other.

The first conductive pattern layer TL1 is disposed between the first ground layer GL1 and the second ground layer GL2.

The second conductive pattern layer TL2 may be disposed on one side of the first ground layer GL1 or the second ground layer GL2. For example, as shown in FIG. 1, the second conductive pattern layer TL2 may be disposed on the first ground layer GL1.

As shown, the filter module 10 according to the embodiment includes a second conductive pattern layer TL2, a first ground layer GL1, and a first conductive pattern stacked in a vertical direction (eg, z-axis direction). It may include a layer TL1 and a second ground layer GL2. That is, the second conductive pattern layer TL2 is disposed at the top of the filter module 10, the second ground layer GL2 is disposed at the bottom of the filter module 10, and the first ground layer GL1 and the second ground layer GL1 are disposed at the bottom of the filter module 10. 1 The conductive pattern layer TL1 may be stacked and disposed between the second conductive pattern layer TL2 and the second ground layer GL2.

The via VA may be disposed between the first ground layer GL1, the second ground layer GL2, the first conductive pattern layer TL1, and the second conductive pattern layer TL2, respectively. Vias can be formed in the form of grooves or holes and can serve as an electrical signal connection path between layers.

The first conductive pattern layer TL1 has a pattern implementing an inductor and a capacitor, and the second conductive pattern layer TL1 includes a transmission line having a pattern implementing an inductor. At this time, the via VA serves to vertically connect the inductor and capacitor of the first conductive pattern layer TL1 and the inductor of the second conductive pattern portion TL2. In addition, the via (VA) also serves to vertically connect the first ground layer (GL1), the second ground layer (GL2), the first conductive pattern layer (TL1), and the second conductive pattern layer (TL2). You can.

A filter (for example, a band-pass filter) having various circuits can be implemented using the filter module 10 shown in FIG. 1 described above.

Hereinafter, the configuration and operation of the band-pass filter 10A according to an embodiment implemented by the filter module 10 shown in FIG. 1 will be described as follows, but the embodiment is not limited thereto. That is, the filter module 10 shown in FIG. 1 may implement a filter having a different configuration or role from the band-pass filter 10A shown in FIG. 2.

FIG. 2 shows a circuit diagram of an embodiment 10A of the filter module 10 shown in FIG. 1.

The filter module 10A shown in FIG. 2 includes first, second, and third capacitors C1, C2, and C3 and first, second, third, fourth, fifth, and sixth inductors (L1, L2). , L3, L4, L5, L6).

The first inductor L1 is connected between the first port P1 and ground, and the sixth inductor L6 is connected between the second port P2 and ground.

The second inductor (L2) and the first capacitor (C1) are connected in series between the first port (P1) and ground, and the fifth inductor (L5) and the third capacitor (C3) are connected to the second port (P2) and ground. can be connected in series.

The third inductor (L3) and the fourth inductor (L4) are connected in series between the first port (P1) and the second port (P2). The second capacitor C2 may be connected between the node N between the third inductor L3 and the fourth inductor L4 and ground.

Hereinafter, the configuration of a specific embodiment of the filter module 10 shown in FIG. 1 that implements the band-pass filter shown in FIG. 2 will be described with reference to FIGS. 3A to 6B, but the embodiment is not limited thereto. In addition, as shown in FIG. 1, the filter module 10 according to the embodiment includes a second ground layer (GL2), a first conductive pattern layer (TL1), a first ground layer (GL1), and a second ground layer (GL1) from bottom to top. Although it is explained that the conductive pattern layers TL2 are stacked and arranged in order, the embodiment is not limited to this.

FIGS. 3A and 3B show a perspective view and a top view, respectively, of the second conductive pattern layer TL2 shown in FIG. 1, and FIGS. 4A and 4B show a perspective view and a top view of the first ground layer GL1 shown in FIG. 1. 5A and 5B respectively show a perspective view and a plan view of the first conductive pattern layer TL1 shown in FIG. 1, and FIGS. 6A and 6B show a perspective view of the second ground layer GL2 shown in FIG. 1. and floor plan are shown, respectively.

Referring to FIGS. 3A and 3B , the second conductive pattern layer TL2 includes a first body B1 having a first opening OP1 and a second inductance pattern. The first body B1 may be connected to ground. In this specification, the opening may be an area where a conductive material is not disposed by etching, etc., and the body may be a ground area, which is a relatively large area.

The second inductance pattern may be formed to have inductance by being disposed in the first opening OP1. That is, the second conductive pattern layer TL2 can form the inductance of each of the third and fourth inductors L3 and L4 shown in FIG. 2 using a transmission line. At this time, if the width of the transmission line becomes too thick, the overall length of the lines of the third and fourth inductors (L3, L4) becomes longer, which may increase the size of the product, so the line width is implemented to be thin. The specific line width will be described later.

For example, the second inductance pattern may include a third inductor pattern LP3 and a fourth inductor pattern LP4.

The third inductor pattern LP3 is arranged to connect the first via VA1 and the fifth via VA5 to each other to form a 3-1 inductor, and the third via (LP31) and the fifth via ( It may include a 3-2 inductor pattern LP32 arranged to connect VA5) and the sixth via VA6 to form a 3-2 inductor. The third inductor formed by the 3-1 inductor and the 3-2 inductor corresponds to the third inductor L3 shown in FIG. 2.

The fourth inductor pattern LP4 may be arranged to connect the sixth via VA6 and the third via VA3 to form a fourth inductor. The fourth inductor formed by the fourth inductor pattern LP4 corresponds to the fourth inductor L4 shown in FIG. 2.

The first, fifth, sixth, and third vias (VA1, VA5, VA6, VA3) and the third and fourth inductor patterns (LP3, LP4) disposed in the first opening (OP1) are connected to the first body (B1). It is placed away from the

The first and second ports P1 and P2 shown in FIG. 3B correspond to the first and second ports P1 and P2 shown in FIG. 2, respectively. The first port (P1) may be an input port (Rx) and the second port (P2) may be an output port (Tx), or the first port (P1) may be an output port (Tx) and the second port (P2) may be an input port. It may be a port (Rx). For example, the first port (P1) may be connected to an IC pad (not shown) and the second port (P2) may be connected to a Bluetooth (BT) antenna (not shown), but they may also be connected in the opposite direction. The embodiment is not limited to this.

Referring to FIGS. 4A and 4B , the first ground layer GL1 includes a second body B2 having a second opening OP2. The second body B2 is connected to ground or a reference potential. The second opening OP2 may be arranged to overlap the first opening OP1 in the z-axis direction, which is perpendicular to the first opening OP1. Accordingly, the first, fifth, sixth, and third vias VA1, VA5, VA6, and VA3 disposed in the first opening OP1 and spaced apart from the first body B1 are spaced apart from the second body B2. and can be deployed.

If the first ground layer (GL1) is shielded by ground without forming the second opening (OP2), the pattern can be implemented without interference in the first conductive pattern layer (TL1), but the third and fourth inductor patterns The length to implement (LP3, LP4) can be increased. Therefore, as shown in FIG. 4B, a coplanar waveguide structure can be realized by forming the second opening OP2 in the first ground layer GL1.

Referring to FIGS. 5A and 5B , the first conductive pattern layer TL1 includes a capacitance pattern and a first inductance pattern.

The capacitance pattern is formed to have capacitance while facing at least one of the first ground layer GL1 or the second ground layer GL2. In the embodiment, the first ground layer and the second ground layer are formed to face each other in both directions at the same time.

The first inductance pattern is formed to have inductance.

The capacitance pattern may include a first capacitor pattern (CP1), a second capacitor pattern (CP2), and a third capacitor pattern (CP3).

The first, second, and third capacitor patterns CP1, CP2, and CP3 form first, second, and third capacitors, respectively. At this time, the first, second, and third capacitors may correspond to the first, second, and third capacitors C1, C2, and C3 shown in FIG. 2, respectively.

The first capacitor pattern CP1 may be disposed to be spaced apart from one side of the second capacitor pattern CP2, and the third capacitor pattern CP3 may be disposed to be spaced apart from the other side of the second capacitor pattern CP2. Although each of the first and third capacitor patterns CP1 and CP3 is shown as having a rectangular planar shape, the embodiment is not limited to a specific planar shape of the pattern.

According to an embodiment, the second capacitor pattern CP2 may include a plurality of stubs. For example, the second capacitor pattern CP2 may include first, second, and third stubs CP21, CP22, and CP23. With the first stub CP21 at the center, the second stub CP22 and the third stub CP23 may be arranged on both sides of the first stub CP21. That is, the second stub CP22 may be placed on one side of the first stub CP21, and the third stub CP23 may be placed on the other side opposite to one side of the first stub CP21.

The sixth via VA6 connected between the third inductor pattern LP3 and the fourth inductor pattern LP4 may be connected to the second capacitor pattern CP2 in a vertical direction.

The first inductance pattern may include a first inductor pattern LP1, a second inductor pattern LP2, a fifth inductor pattern LP5, and a sixth inductor pattern LP6.

The first inductor pattern LP1 may be arranged to connect the first via VA1 and the second via VA2 to form a first inductor. Here, the first inductor corresponds to the first inductor L1 shown in FIG. 2.

The second inductor pattern LP2 may be arranged to connect the first via VA1 and the first capacitor pattern CP1 to form a second inductor. Here, the second inductor corresponds to the second inductor L2 shown in FIG. 2. The second inductor pattern LP2 may be connected to the third inductor pattern LP3 through the first via VA1.

The fifth inductor pattern LP5 may be arranged to connect the third via VA3 and the third capacitor pattern CP3 to form a fifth inductor. Here, the fifth inductor corresponds to the fifth inductor L5 shown in FIG. 2.

The sixth inductor pattern LP6 may be arranged to connect the third via VA3 and the fourth via VA5 to form a sixth inductor. Here, the sixth inductor corresponds to the sixth inductor L6 shown in FIG. 2.

The fifth inductor pattern LP5 and the sixth inductor pattern LP6 may be connected to the fourth inductor pattern LP4 through the third via VA3.

According to an embodiment, the first or second inductance pattern may have a planar shape that is bent in the horizontal direction at least once. For example, the first inductor pattern LP1 and the sixth inductor pattern LP6 shown in FIG. 5B have a planar shape bent twice in the horizontal direction, and the second inductor pattern LP2 and the fifth inductor pattern ( LP5) Each may have a planar shape bent once in the horizontal direction.

Referring to FIGS. 6A and 6B , the second ground layer GL2 includes a third body B3. The body B3 may be connected to ground.

The above-described bodies B1, B2, and B3 shown in FIGS. 3B, 4B, and 6B may be made of an electrically conductive material, and the capacitance pattern shown in FIG. 5B and the first inductance pattern shown in FIG. 3B Each of the second inductance patterns may also be implemented with an electrically conductive material.

Referring to FIGS. 4B and 6B, the body B2 of the first ground layer GL1 and the body B3 of the second ground layer GL2 each have a third opening OP3 into which a shield can is inserted. ), but the third opening OP3 may be omitted.

In addition, among the first to fifteenth vias (VA1 to VA15), vias excluding the first, third, fifth, and sixth vias (VA1, VA3, VA5, and VA6) are connected to the second conductive pattern layer (TL2) and the second conductive pattern layer (TL2). It may also serve to connect the ground layer GL1, the first conductive pattern layer TL1, and the second ground layer GL2 to each other in the vertical direction.

The first to fifteenth vias VA1 to VA15 may be made of an electrically conductive material. The portion having a donut plane shape in each of FIGS. 3B, 4B, and 5B is a conductive line area corresponding to a via.

The electrically conductive material described above may be copper (Cu), but the embodiment is not limited to a specific material.

Additionally, in FIGS. 3B, 4B, 5B, and 6B, the portion marked with a white background and the first and second openings (OP1, OP2) may be filled with a dielectric material (or dielectric) (EM), and the second conductive material (EM) may be filled with a dielectric material (EM). Between the conductive pattern layer TL2 and the first ground layer GL1, between the first ground layer GL1 and the first conductive pattern layer TL1, between the first conductive pattern layer TL1 and the second ground layer ( Each space between GL2) can also be filled with genetic material.

As the line width of each of the above-described first to sixth inductor patterns (LP1, LP2, LP3, LP4, LP5, and LP6) is smaller, the length can be designed to be shorter. Considering this, according to the embodiment, if the line width of each of the first to sixth inductor patterns LP1, LP2, LP3, LP4, LP5, and LP6 is greater than 250㎛, the efficiency of the inductor may be reduced. Accordingly, the line width of each of the first to sixth inductor patterns (LP1, LP2, LP3, LP4, LP5, and LP6) may be 250㎛ or less, but the embodiment is not limited thereto.

Conversely, if the line width of the first and third capacitor patterns CP1 and CP3 is less than 300㎛, the efficiency of the capacitor may decrease. Therefore, according to the embodiment, the line width of each of the first and third capacitor patterns CP1 and CP3 may be 300 μm or more, but the embodiment is not limited thereto.

The length of each of the first to sixth inductor patterns (LP1, LP2, LP3, LP4, LP5, and LP6) may be less than one-eighth the wavelength at the fundamental frequency (eg, 2.4 GHz). Here, the fundamental frequency means the frequency at which the insertion loss becomes 0.

For example, the length of each of the first to sixth inductor patterns LP1, LP2, LP3, LP4, LP5, and LP6 may be the length disposed between vias. For example, referring to FIG. 3B, the length of the 3-1 inductor pattern LP31 disposed between the first via VA1 and the fifth via VA5 is 8 minutes at the fundamental frequency, for example, 2.4 GHz. is less than 1 wavelength, and the length of the 3-2 inductor pattern LP32 disposed between the fifth via VA5 and the sixth via VA6 is less than one eighth of the wavelength at the fundamental frequency, for example, 2.4 GHz. You can. Additionally, the length of each of the first and third capacitor patterns CP1 and CP3 in the x-axis direction and the y-axis direction may be less than one eighth of the wavelength at the fundamental frequency, for example, 2.4 GHz. For example, the length of each of the first to sixth inductor patterns (LP1, LP2, LP3, LP4, LP5, LP6) and the first and third capacitor patterns (CP1, CP3) may be 4.5 mm or less.

The areas of each of the first to sixth inductor patterns LP1 to LP6 and the first to third capacitor patterns CP1, CP2, and CP3 are dependent on the length and line width.

Hereinafter, with reference to the attached drawings, the operation of the filter modules 10 and 10A according to an embodiment that performs the role of the band-pass filter shown in FIG. 2 by the configuration shown in FIGS. 3A to 6B will be described as follows. Let’s explain together.

Figure 7 is a graph showing insertion loss by frequency of the filter module 10A according to an embodiment, where the horizontal axis represents frequency and the vertical axis represents insertion loss.

FIG. 8 is a graph showing inductance for each frequency implemented by the first and sixth inductor patterns LP1 and LP6, where the horizontal axis represents frequency and the vertical axis represents inductance.

By adjusting the line width and length of each of the first and sixth inductor patterns (LP1, LP6), the self-resonance frequency (SRF) of the first inductor pattern (LP1) is 2 times that of the Bluetooth antenna or WIFI signal. The second harmonic frequency is f1 as shown in FIG. 7, and the self-resonant frequency (SRF) of the sixth inductor pattern LP6 is the second harmonic frequency of the Bluetooth antenna or Wi-Fi signal, as shown in FIG. 8. It can be designed to be f2 together. Here, when the basic frequency is 2.4 GHz, the frequency f1, which is the transmission zero point, is 4.8 GHz, and f2 may be 5 GHz or 5.5 GHz. The line width for this may be 80㎛ to 200㎛ and the length may be a quarter of the wavelength at 4.8GHz. The point at which the transfer functions of the first inductor (L1), the second inductor (L2), and the first capacitor (C1) become zero corresponds to f1 shown in FIGS. 7 and 8, and the fifth inductor (L5) and the first capacitor (C1) correspond to f1 shown in FIGS. 6 The point where the transfer function of the inductor L6 and the third capacitor C3 becomes zero corresponds to f2 shown in FIGS. 7 and 8.

Additionally, the first and sixth inductors L1 and L6 may serve to remove low-frequency noise such as direct current components and may also serve to match impedance.

The second inductor L2 implemented by the second inductor pattern LP2 and the first capacitor C1 implemented by the first capacitor pattern CP1 generate a transmission zero point at the resonance frequency. Likewise, the fifth inductor L5 implemented by the fifth inductor pattern LP5 and the third capacitor C3 implemented by the third capacitor pattern CP3 generate a transmission zero point at the resonance frequency. It can be designed so that the resonant frequency is the second harmonic frequency of a Bluetooth antenna or Wi-Fi antenna.

FIG. 9 is a graph showing the capacitance of the second capacitor pattern CP2 by frequency, where the horizontal axis represents frequency and the vertical axis represents capacitance.

A third inductor (L3) implemented by the third inductor pattern (LP3), a fourth inductor (L4) implemented by the fourth inductor pattern (LP4), and a second capacitor implemented by the second capacitor pattern (CP2) (C2) generates transmission zero at the resonant frequency. The third inductor (L3), fourth inductor (L4), and second capacitor (C2) can determine the bandwidth of the filter.

When designing the second capacitor (C2) as a parasitic component, there are two perfect matching points (Pole) in the pass band, and when designing the second capacitor (C2) as a resonator, there are three perfect matching points (Pole) in the pass band. There is.

The second capacitor C2 may have the form of a three band stub. Referring to FIG. 9, the 2-1 capacitor C21 implemented by the first stub CP21, the 2-2 capacitor C22 and the third stub CP23 implemented by the second stub CP22. The second capacitor C2 can be implemented to have a transmission zero point at the frequency f3 by combining the 2-3 capacitor C23 implemented by . In Figure 9, the resonance point (f4) of the 2-1 capacitor (C21) is 9.6 GHz, the resonance point (f5) of the 2-3 capacitor (C23) is 12 GHz, and the resonance point (f5) of the 2-2 capacitor (C22) is 9.6 GHz. f6) is 14.4 GHz, and the total resonance point (f3) of the second capacitor C2 may be 7.2 GHz.

The second capacitor C2 has a composition of three resonators, and can be designed to have a self-resonant frequency at a harmonic frequency of 2.4 GHz to 2.5 GHz, and multiple resonators can be synthesized as needed.

Hereinafter, the filter module according to the comparative example and the filter module according to the embodiment will be described as follows with reference to the attached drawings.

Figure 10 is a graph showing the insertion loss 200 of the filter module according to the comparative example and the insertion loss 210 of the filter module according to the embodiment, where the horizontal axis represents frequency and the vertical axis represents insertion loss.

Referring to FIG. 10, the filter module 210 according to the embodiment has a pass band of 2.4 GHz to 2.5 GHz, and a bandwidth of 3 dB is 2.2 GHz to 3.2 GHz.

The filter module 200 of the comparative example configures a band-pass filter using a capacitor or inductor, which is a lumped constant element. Referring to FIG. 10, it can be seen that the Example 210 shows excellent blocking performance of at least -30 dB in the harmonic generation section after 4.8 GHz compared to the Comparative Example 200.

In the case of the embodiment, each of the first, second, third, fifth and sixth inductor patterns (LP1, LP2, LP3, LP5, LP6) is formed by bending at least once in the horizontal direction, so that it has a sufficient length in a limited space. This ensures that the inductance of each inductor (L1, L2, L3, L5, L6) can be designed as desired.

In addition, according to the filter modules 10 and 10A according to the embodiment, harmonic components other than the original signal resulting from an oscillator (not shown) and a mixer (not shown) inside the IC can be improved.

In addition, according to the filter modules 10 and 10A according to the embodiment, the insertion loss can be improved by improving impedance matching compared to the transmission line by controlling the pole point. That is, since the consistency is improved when connecting an antenna or element to the first port (P1) and the second port (P2), the efficiency of the antenna is improved, the transmission distance can be increased, and the transmission speed can also be improved.

The filter module in the comparative example uses a capacitor or inductor, which is a lumped constant element, to form a band-pass filter, and a separate transmission line exists, resulting in a large insertion loss. On the other hand, in the case of the embodiment, the band-pass filter is formed by inductors (L3, L4) implemented using the transmission line itself, so the wavelength is shortened, group delay is improved, and signal distortion rate can be lowered.

Ultimately, in the filter modules 10 and 10A according to the embodiment, the second conductive pattern layer TL2 is designed to minimize signal distortion by combining with the transmission line, and the configuration for blocking harmonic components is connected to the first ground. Since it is shielded and positioned between the layer GL1 and the second ground layer GL2, noise is not radiated and can be easily removed through grounding. That is, according to the embodiment, it is designed so that a signal with a main frequency of 2.4 GHz to 2.5 GHz can be directly connected to the existing transmission line, and by improving impedance matching, insertion loss can be reduced and signal distortion can be improved, and the blocked The signal can be allowed to flow to the ground so that it does not re-enter or radiate.

The filter module according to the embodiment is modularized and includes, for example, a television for Organic Light Emitting Diodes (OLED), a WIFI/BT combo module, a multi-antenna system, and a repeater for LTE/WIFI 5G and 6G. It can be applied to communication devices or filters inside communication devices.

Figure 11 shows an example of a connection structure of a filter module according to an embodiment and is a diagram to aid understanding of the present invention. Although it overlaps with the above-mentioned content, it represents the connection structure of the challenge pattern and was added to aid structural understanding.

FIG. 12 is a block diagram of an antenna module according to an embodiment of the invention, FIG. 13 is a plan view showing a part of the antenna module of FIG. 12, FIG. 14 is a perspective view showing the low-pass filter unit of FIG. 13, and FIG. 15 is a Figure 16 is another side view of the low-pass filter part of Figure 14, Figure 16 is an example of the circuit configuration of the low-pass filter according to the present invention, Figure 17 is an exploded perspective view of the low-pass filter part of Figure 14, and Figure 18 is the low-pass filter of Figure 17. It is a diagram showing the pattern shape of the first to fourth conductive layers of the negative part, FIG. 19 is an example of a cross section from the A-A side of the low-pass filter unit of FIG. 14, and FIG. 20 is an example of a cross-section from the B-B side of the low-pass filter unit of FIG. 14, Figure 21 is a graph showing the operating characteristics of the low-pass filter unit of the antenna module according to an embodiment of the invention.

Referring to FIG. 12, the antenna module includes a first antenna 210 that transmits and receives a first high-frequency signal, a low-pass filter unit 100 connected to transmission lines 251 and 252 of the first antenna 210, and It includes a second antenna 220 that transmits and receives a second high-frequency signal, and a communication signal processor 200 that generates and processes the transmitted and received signals of the first and second antennas 210 and 220.

The first antenna 210 is a Bluetooth antenna, the second antenna 220 is a Wi-Fi antenna, and the communication signal processor 200 may be implemented as a Wi-Fi module.

The first high-frequency signal includes a Bluetooth signal, for example, a band of 2402 to 2480 MHz. The second high-frequency signal includes a Wi-Fi signal, for example, a band of 2400-2483 MHz and 5-6 GHz. Here, the first high-frequency signal uses a channel that overlaps with the low frequency band (e.g., 2402 to 2480 MHz) of the second high-frequency signal, and does not use a channel that overlaps with the high frequency band (e.g., 5 to 6 GHz). It is not happening.

13 to 15, the low-pass filter unit 100 is connected to the transmission lines 251 and 252 between the first antenna 210 and the communication signal processing unit 200, and passes low frequency bands and transmits high frequencies. Frequency bands can be filtered. The low-pass filter unit 100 may be connected between a first transmission line 251 connected to the first antenna 210 and a second transmission line 252 connected to the communication signal processing unit 200. The first and second transmission lines 251 and 252 are feed lines that feed signals.

The low-pass filter unit 100 may form a resonance circuit using an inductor and a capacitor, and the inductor and the capacitor may be implemented by a pattern of a conductive layer and a dielectric layer, rather than by passive components. Accordingly, since passive components are not used, cost can be reduced and the size of the low-pass filter unit 100 can be reduced.

The first and second antennas 210 and 220 may be coupled to the substrate 250. The first antenna 210 may be coupled to a coupling portion 255 of the substrate 250, and the coupling portion 255 may be a coupling hole into which a lower coupling protrusion of the first antenna 210 is coupled. Any one of the coupling portions 255 of the substrate 250 may be connected to the first transmission line 251. Additionally, the low-pass filter unit 100 may be embedded in the substrate 250 of the communication signal processing unit 200. The substrate 250 may be a multilayer substrate having multiple conductive layers.

As shown in FIG. 16, the circuit configuration of the low-pass filter unit 100 is implemented as a passive filter having a first input and output port and a second input and output port for transmitting and receiving signals, and a first branch connected to the first input and output port A first capacitor C1 is connected in parallel to the node N1, and the other end of the first capacitor C1 is grounded. One end of the first inductor (N1) is connected in series to the first branch node (N1), and a third branch node (N3) is connected to the other end of the first inductor (N1), and the third branch node ( One end of the second inductor (L2) is connected in parallel to N3), and the other end of the second inductor (L2) is grounded.

One end of a third inductor (L3) is connected in parallel to the second branch node (N2) connected to the second input/output port, and a second capacitor (C2) is connected in series to the other end of the third inductor (L3), The other end of the second capacitor C2 is connected to ground. The second branch node (N2) is connected in series with the third branch node (N3).

Here, the first input/output port may be connected to or formed integrally with the first transmission line 251. The second input/output port may be connected to or formed integrally with the second transmission line 252. The low-pass filter unit 100 passes the first frequency band (e.g., 2400 to 2483 MHz) transmitted to the first and second input/output ports and filters the second frequency band (e.g., 5 to 6 GHz).

The first to third inductors (L1, L2, L3) may have a range of 0.5 to 4 nH and may have different inductances. For example, the first inductor (L1) may have a range of 1.3nH±0.2nH, the second inductor (L2) may have a range of 2.7nH±0.2nH, and the third inductor (L3) may have a range of 1.5nH±0.2nH. The first and second capacitors C1 and C2 have a range of 0.3 to 2.5 pF and may be different from each other. For example, the first capacitor C1 may have 0.9pF±0.05pF, and the second capacitor C2 may have 0.5pF±0.01pF.

As shown in FIGS. 14, 15, and 17 to 20, the low-pass filter unit 100 may be a portion of the substrate 250 of FIG. 13 or a substrate area buried within the substrate 250.

The low-pass filter unit 100 may include a plurality of conductive layers 110, 120, 130, and 140 and a plurality of dielectric layers 151, 152, and 153 respectively disposed between the conductive layers 110, 120, 130, and 140. The plurality of conductive layers 110, 120, 130, and 140 may be made of copper, or may be a layer in which at least one plating layer is laminated on the surface of the copper material. The plating layer may include at least one of nickel, gold, tin, lead, palladium, silver, and mixtures thereof.

The material of the dielectric layers 151, 152, and 153 may include at least one of insulating materials such as FR-4, CEM-1, RF-35, Teflon, polyimide, and PTEE (Polytetrafluoroethylene). The dielectric layers 151, 152, and 153 may include capacitor dielectrics such as Ta2O5, BaO4SrTi, TiO2, BaO, Al2O3, PbO, CaO, and B2O3.

The plurality of conductive layers (110, 1201, 130, 140) include first to fourth conductive layers (110, 1201, 130, 140) stacked from the top to the bottom of the substrate 250, and the plurality of dielectric layers (151, 152, 153) may include first to third dielectric layers 151, 152, and 153 respectively disposed between the first to fourth conductive layers 110, 1201, 130, and 140. The first and second dielectric layers 151 and 152 may include the dielectric of the capacitor, and the thickness of the second dielectric layer 152 may be greater than the thickness of the first dielectric layer 151. For example, the thickness of the first and third dielectric layers 151 and 153 may be 300 μm or less, for example, in the range of 100 to 300 μm, and the thickness of the second dielectric layer 152 may be 300 μm or more, for example, in the range of 300 to 500 μm. It can be formed as

The first dielectric layer 151 is disposed between the first conductive layer 110 and the second conductive layer 120, and the second dielectric layer 152 is disposed between the second conductive layer 120 and the third conductive layer 120. It is disposed between the conductive layers 130, and the third dielectric layer 153 is disposed between the third conductive layer 130 and the fourth conductive layer. A first conductive layer 110 may be exposed on the upper surface of the substrate, and a fourth conductive layer 140 may be exposed on the lower surface.

14 and 15, the low-pass filter unit 100 has a width between the first side (S1) and a third side (S3) and a length between the second side (S2) and the fourth side (S4). It can be smaller than Accordingly, the conductive pattern of the long inductor can be arranged long in the first direction (longitudinal direction) from the second side S2 to the fourth side S4. Additionally, a conductive pattern of a short-length inductor may be disposed in a second direction (width direction) from the first side S1 to the third side S3. The first conductive layer 110 may be exposed on the upper surface of the substrate, and the fourth conductive layer 140 may be exposed on the lower surface of the substrate. As shown in FIG. 15 , a portion of the pattern 132 of the second conductive layer 140 may be exposed on the side surface S3.

15 and 17, the first conductive layer 110 includes a first pattern 111, a second pattern 112, and a third pattern 119, and the second conductive layer 120 is It has a ground pattern 121, and the third conductive layer 130 includes a fourth pattern 131 and a fifth pattern 132 spaced apart from each other, and the fourth conductive layer 140 includes a first via ( It may include a sixth pattern 141 and a seventh pattern 142 connected to V2).

The first pattern 111 and the second pattern 112 of the first conductive layer 110 are connected to the first via V1 and the first via V2 spaced apart in the first direction, and the first pattern 111 is a plate-shaped pattern having a polygonal shape, and the second pattern 112 is a line-shaped pattern having a width narrower than the width of the plate-shaped pattern. The first pattern 111 has a first via V1 therein and is connected to one end of the second pattern 112, and the other end of the second pattern 112 is connected to the first via V2. . The second pattern 112 has a bent structure, for example, has two or more bends or three or more bends. This second pattern 112 can increase or decrease the value of the inductance depending on the bend shape and length. The length of the second pattern 112 (L1) may range from 0.5 to 3 mm. Here, the length of the second pattern 112 (L1) extends from one end to the other end. The width of the second pattern 112 (L1) may range from 10 to 200 ㎛.

One end of the first pattern 111 is connected to the second pattern 112 and the other end is connected to the first input/output pattern 113, and the second pattern 112 and the second via (V2) are connected to the second input/output pattern 113. Connected to pattern 114. The first and second input/output patterns 113 and 114 are first and second input/output ports. The second via V2 has a circular pattern around its circumference, and the diameter of the circular pattern may be larger than the width of the second pattern 112 .

The third pattern 119 is a plate-shaped pattern having a third via V3, and may be spatially spaced apart from the first and second patterns 111 and 112. The third pattern 119 may have a polygonal shape. A hemispherical pattern may be formed around one side of the third via V3. The top surface area of the third pattern 119 may be smaller than the top surface area of the first pattern 111. The third via (V3) is disposed between the fifth via (V5) and the seventh via (V7) in the first direction, and is closer to the seventh via (V7) than the fifth via (V5). can be positioned.

Patterns 115, 116, 117, and 118 having fifth to eighth vias V5 to V8 are disposed at each corner of the first conductive layer 110, and are physically spaced apart from the first to third patterns 111, 112, and 119. The patterns 115, 116, 117, and 118 having the fifth to eighth vias V5 to V8 in the first conductive layer 110 may have a polygonal shape.

17 and 18, the second conductive layer 120 is a ground pattern 121, and within the ground pattern 121 is a first circular pattern (P1) connected to the first via (V1), It includes a second circular pattern (P2) connected to the first via (V2) and a third circular pattern (P3) connected to the third via (V3).

Each of the first to third circular patterns P1, P2, and P3 may be spaced apart from the ground pattern 121 with a predetermined gap Q1, Q2, and Q3. Each of the first to third circular patterns P1, P2, and P3 is not physically connected to the ground pattern 121.

The ground pattern 121 is connected to the fifth to eighth vias V5 to V8, and is larger than the top surface area of the patterns of the first conductive layer 110 or the third conductive layer 130. It may be larger than the top surface area of the patterns.

The third conductive layer 130 includes a fourth pattern 131 connected to the first via V1, a fifth pattern 132 connected to the second via V2 and the third via V3. The fourth pattern 131 and the first pattern 111 of the first conductive layer 110 face each other on both sides of the ground pattern 121 . The top surface area of the fourth pattern 131 may be smaller than that of the first pattern 111.

The first via V2 disposed in the fifth pattern 132 may have a fourth circular pattern P4 and may be spaced apart from the fifth pattern 132 with a predetermined gap Q4. The fourth circular pattern P4 is not physically connected to the fifth pattern 132. The fifth pattern 132 may be connected to the third pattern 119 on the inside. The fifth pattern 132 and the second and third patterns 111 and 112 face each other on both sides of the ground pattern 121.

The fourth pattern 131 and the fifth pattern 132 may be implemented as a plate-shaped pattern with a polygonal shape. The top surface area of the fourth pattern 131 may be larger than that of the first pattern 111 and may be larger than that of the fifth pattern 132 . Additionally, the top surface area of the fifth pattern 132 may be larger than that of the first pattern 111. Here, the polygonal shape may include a square shape.

Fifth to eighth vias (V5 to V8) may be disposed at each corner of the third conductive layer 130, and the fifth to eighth vias (V5 to V8) of the third conductive layer 130 are It may have a circular pattern. The gaps (Q1, Q2, Q3, Q4) may be filled with materials of the dielectric layer, as shown in FIGS. 19 and 20.

The fourth conductive layer 140 includes a sixth pattern 141 and a seventh pattern 142, and the sixth pattern 141 and the seventh pattern 142 are connected to the first via V2. . The sixth pattern 141 is a line pattern, extends between the first via (V2) and the sixth via (V6), and may be in the shape of a line with a bending structure of 2 or more times, for example, a bending structure of 4 or more times. The branches may have a line shape.

The total length of the sixth pattern 141 may be greater than the total length of the second pattern 112. The number of bends of the sixth pattern 141 may be greater than the number of bends of the second pattern 112, for example, two or more times. The length of the sixth pattern (141, L2) is 3 to 10 mm, which represents the total length. The width of the sixth pattern 141 (L2) is 10 to 200 ㎛.

The seventh pattern 142 is a line pattern, connected between the first via (V2) and the third via (V3), and has a line shape with one or more bending structures, for example, two or three bending structures. It can be. The length of the seventh pattern (142, L3) is 0.5 to 3 mm, which represents the total length. The width of the seventh pattern (142, L3) is 10 to 200 ㎛.

Fifth to eighth vias (V5 to V8) may be disposed at each corner of the fourth conductive layer 140, and the fifth to eighth vias (V5 to V8) of the fourth conductive layer 140 are It may have a circular pattern.

Here, the first capacitor C1 is a first dielectric layer 151 between the first pattern 111 of the first conductive layer 110 and the first circular pattern P1 of the second conductive layer 120. It may include a first capacitance due to and a second capacitance due to the second dielectric layer 152 between the first circular pattern P1 and the fourth pattern 131. The first pattern 111 of the first conductive layer 110 and the fourth pattern 131 of the third conductive layer 130 may function as both electrode terminals of the first capacitor. The first and second capacitances may be connected in series.

Here, the first inductor L1 is implemented as a second pattern 112 connected between the first pattern 111 and the first via V2. The inductance value of the first inductor L1 may vary depending on the length and/or area of the first pattern 111. The second pattern 112, sixth pattern 116, and seventh pattern 117 may each be a line pattern for an inductor.

The second inductor L2 is implemented as a line-shaped sixth pattern 141 connected between the first via V2 and the sixth via V6 of the fourth conductive layer 140, and the sixth pattern ( The inductance value may vary depending on the length or/and area of 141). The second inductor L2 may be connected to the ground pattern 121 through the sixth via V6. The inductance value of the sixth pattern 141 may be greater than the inductance value of the second pattern 112.

The third inductor L3 is implemented as a line-shaped seventh pattern 142 connected between the first via V2 and the third via V3, and the length of the seventh pattern 142 or/and The inductance value may vary depending on the area. The inductance value of the seventh pattern 142 may be greater than the inductance value of the second pattern 112.

The second capacitor C2 is formed by being connected to the fifth pattern 132, the third circular pattern P3, and the third pattern 119 through a third via V3 connected to the seventh pattern 142. It may be, in this case, the third capacitance due to the first dielectric layer 151 between the third pattern 119 and the third circular pattern (P3), and the third capacitance between the third circular pattern (P3) and the fifth pattern 132. It may have a fourth capacitance due to the second dielectric layer 152. In addition, the second capacitor C2 has a fifth capacitance due to the first dielectric layer 151 between the first via V2 and the second circular pattern P2, and the second circular pattern P2 and the fourth circular pattern ( It may have a sixth capacitance due to the second dielectric layer 152 between P4). The third and fourth capacitances may be connected in series, and the fifth and sixth capacitances may be connected in series. The third and fifth capacitances may be connected in parallel with each other, and the fourth and sixth capacitances may be connected in parallel with each other. Accordingly, the second capacitor C2 may have third to sixth capacitances due to the patterns on both sides of the first and second dielectric layers 151 and 152 and may be connected in series to the seventh pattern 142.

Since the first pattern 111 is larger than the area of the third pattern 119 and the fourth pattern 131 is larger than the area of the fifth pattern 132, the capacitance of the second capacitor C2 is It may be smaller than the capacitance value of the first capacitor C1.

As shown in FIG. 19, the first pattern 111, the second circular pattern (P2), and the fourth pattern 131 are connected to the first via (V1), and the second pattern 112 is connected to the first via (V2). , the second circular pattern (P2), the fourth circular pattern (P4), and the sixth pattern (141) are connected.

As shown in FIG. 20 , the third via V3 connects the third pattern 119, the third circular pattern P3, the fifth pattern 132, and the seventh pattern 142. The fifth via V5 may be connected to the ground pattern 121 and connected to the via patterns of the first, third, and fourth conductive layers 110, 130, and 140. The fifth via V5 may not be connected to the via patterns of the third and fourth conductive layers 130 and 140. That is, the 5th, 7th, and 8th vias (V5, V7, and V8) of the third and fourth conductive layers may be a pattern arranged to support between two dielectric layers. The seventh via V7 is connected to the ground pattern 121 and may be connected to via patterns of the first, third, and fourth conductive layers 110, 130, and 140.

Each of the first to third branch nodes N1, N2, and N3 may be formed by first to third vias V1, V2, and V3 disposed in the low-pass filter unit 100.

As another example of the invention, the conductive layer/dielectric layer of Figure 17 may be arranged in reverse, for example, the patterns of the first conductive layer 110 are arranged in the pattern of the fourth conductive layer, and the patterns of the second conductive layer 110 are arranged in the pattern of the third conductive layer, the patterns of the third conductive layer 130 are arranged in the pattern of the second conductive layer, and the patterns of the fourth conductive layer 140 are implemented by the patterns of the first conductive layer. You can. That is, the pattern of each layer can be implemented by embedding the configuration shown in FIG. 17 in a substrate with the structure upside down or rotated 180 degrees. In this case, the input/output pattern may be disposed on the fourth conductive layer 140 and connected to the transmission lines 251 and 252 through the lower surface of the substrate 250.

The low-pass filter unit 100 embedded in the substrate as described above may have frequency response characteristics as shown in FIG. 21. In the S-parameter, S21 represents the insertion loss of the low-pass filter, and is a comparison of the size of the signal output from the first input/output port to the signal output from the second input/output port, and has a minimum value in the 5~6GHz band. It can be seen that less than -3dB is satisfied. In other words, it can be seen that the low-pass filter unit 100 has a high filtering effect in the 5 to 6 GHz band. As the insertion loss approaches 0, the signal flows better. In the S-parameter, S11 represents the reflection coefficient or return loss at the first input/output port, and S22 represents the reflection coefficient or return loss at the second input/output port. The frequencies of the transmission zero point (-22.41, -26.01) in the curves of S11 and S22 can be adjusted, and the transmission zero point of 4.25 GHz is adjusted lower than the transmission zero point of 2.45 GHz, and the input power is transmitted as much as possible in the band above 5 GHz. It can be set to a value for bandwidth control and frequency suppression.

The antenna module according to an embodiment of the invention is a Wi-Fi module having a Bluetooth and Wi-Fi antenna, and can be applied to high-frequency modules such as mobile phones, TVs that receive high-frequency signals, and mobile vehicles.

The features, structures, effects, etc. described in the embodiments above are included in at least one embodiment of the present invention and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc. illustrated in each embodiment can be combined or modified and implemented in other embodiments by a person with ordinary knowledge in the field to which the embodiments belong. Therefore, contents related to such combinations and modifications should be construed as being included in the scope of the present invention.

Although the above description focuses on examples, this is only an example and does not limit the present invention, and those skilled in the art will understand that the examples are as follows without departing from the essential characteristics of the present example. You will see that various variations and applications are possible. For example, each component specifically shown in the examples can be modified and implemented. And these variations and differences in application should be construed as being included in the scope of the present invention as defined in the appended claims.

100: low-pass filter unit 200: communication signal processing unit
210: first antenna 220: second antenna
250: Substrate for antenna module
251,252: Transmission lines
110: first conductive layer 120: second conductive layer
130: third conductive layer 140: fourth conductive layer
151,152,153: dielectric layer 111: first pattern
112: 2nd pattern 119: 3rd pattern
113,114: Input/output port 121: Ground pattern
131: 4th pattern 142: 5th pattern
141: 6th pattern 142: 7th pattern
V1-V4, V5-V9: via P1-P4: circular pattern

Claims (15)

first ground layer;
a second ground layer disposed to be spaced apart from the first ground layer;
a first conductive pattern layer disposed between the first ground layer and the second ground layer;
a second conductive pattern layer disposed on one side of the first ground layer or the second ground layer; and
A filter module comprising a via connecting at least two of the first ground layer, the second ground layer, the first conductive pattern layer, and the second conductive pattern layer. According to claim 1,
The first conductive pattern layer is a filter module comprising a capacitance pattern formed to have capacitance while facing at least one of the first ground layer and the second ground layer. According to clause 2,
The first conductive pattern layer is a filter module including a first inductance pattern formed to have inductance. According to claims 2 to 3,
The second conductive pattern layer is a filter module including a second inductance pattern formed to have inductance. According to clause 4,
A filter module wherein the width of the inductance pattern is smaller than the width of the capacitance pattern. According to clause 5,
It includes a first opening where the second inductance pattern is disposed,
The first ground layer includes a second opening that vertically overlaps the first opening. According to clause 5,
Each of the first or second inductance patterns includes an inductance pattern having a planar shape bent in the horizontal direction at least once,
A filter module in which the maximum number of bendings of the first inductance pattern in the horizontal direction is greater than the maximum number of bendings of the second inductance pattern. According to clause 5,
The capacitance pattern is
a second capacitor pattern forming a second capacitor;
a first capacitor pattern disposed to be spaced apart from one side of the second capacitor pattern and forming a first capacitor; and
A filter module including a third capacitor pattern disposed to be spaced apart from the other side of the second capacitor pattern and forming a third capacitor. According to clause 8,
The second capacitor pattern is
first stub;
a second stub disposed on one side of the first stub; and
A filter module including a third stub disposed on the other side opposite to the one side of the first stub. According to clause 5,
The first inductance pattern is
a first inductor pattern disposed to connect the first via and the second via to form a first inductor;
a second inductor pattern disposed to connect the first via and the first capacitor pattern to form a second inductor;
a fifth inductor pattern disposed to connect a third via and the third capacitor pattern to form a fifth inductor; and
A filter module comprising a sixth inductor pattern disposed to connect the third via and the fourth via to form a sixth inductor. According to clause 5,
The second inductance pattern is
a third inductor pattern arranged to connect the first via and the fifth via and to connect the fifth via and the sixth via to form a third inductor; and
a fourth inductor pattern disposed to connect the sixth via and the third via to form a fourth inductor;
The sixth via is a filter module connected to the second capacitor pattern. According to claim 10,
A filter module wherein at least one of the first to sixth inductor patterns has a line width of 250㎛ or less. According to clause 8,
A filter module wherein at least one of the first and third capacitor patterns has a line width of 300 ㎛ or more. According to claim 10,
A filter module wherein the length of at least one of the first to sixth inductor patterns is less than one-eighth the wavelength at the fundamental frequency. second ground layer;
a first conductive pattern layer stacked on the second ground layer and having a pattern implementing an inductor and a capacitor;
a first ground layer stacked on the first conductive pattern layer;
a second conductive pattern layer stacked on the first ground layer and including a transmission line with a pattern implementing an inductor; and
A filter module comprising a via vertically connecting the inductor and the capacitor of the first conductive pattern layer and the inductor of the second conductive pattern portion.

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