KR20230149691A - Semiconductor die for controlling on-die-termination of another semiconductor die, and semiconductor devices having the same - Google Patents

Abstract

A semiconductor die is started. The semiconductor die has a first pin for outputting a first ODT control signal for controlling the ODT of the second ODT circuits included in the second semiconductor die to the second semiconductor die, and an ODT of the first ODT circuits included in the semiconductor die. It includes a second pin that receives a second ODT control signal output from the second semiconductor die for control.

Description

Semiconductor dies that control the ODT of other semiconductor dies and semiconductor devices including the same {SEMICONDUCTOR DIE FOR CONTROLLING ON-DIE-TERMINATION OF ANOTHER SEMICONDUCTOR DIE, AND SEMICONDUCTOR DEVICES HAVING THE SAME}

Embodiments according to the concept of the present invention relate to semiconductor dies, and in particular, to semiconductor dies capable of controlling on-die termination (ODT) of other semiconductor dies and semiconductor devices including the same.

Although termination resistors on the mother board can reduce some signal reflections on the signal lines, they do not affect the components of the module card (e.g., a DRAM module). Signal reflection from connected stub (or connection) lines cannot be prevented.

Signals propagating from the controller to the components of the module card encounter impedance discontinuities at the stubs (or connection nodes) connected to the components. A signal propagating to components (eg, DRAM components) along the signal line and stub is reflected back to the signal line, introducing unwanted noise into the signal.

However, on-die termination (ODT) instead of placing a termination resistor for impedance matching of a transmission line on a printed circuit board (PCB) or motherboard, the termination resistor is placed on a semiconductor chip (i.e., a semiconductor die). ) is a technology that is placed inside.

Therefore, ODT can reduce the number of resistor elements and complex wiring placed on the motherboard. Therefore, using ODT, system design is simpler and more cost-effective.

The technical problem to be achieved by the present invention is to provide a semiconductor die that controls the ODT of another semiconductor die to reduce power consumption and semiconductor devices including the same.

The semiconductor die according to an embodiment of the present invention includes a first pin for outputting a first ODT control signal for controlling the ODT of the second ODT (On-die termination) circuits included in the second semiconductor die to the second semiconductor die, and , and a second pin that receives a second ODT control signal output from the second semiconductor die to control the ODT of the first ODT circuits included in the semiconductor die.

The semiconductor die is activated before the first bit of read data corresponding to the burst length is output from the first semiconductor die performing the first read operation and is deactivated after the last bit of the read data is output. It further includes an ODT control signal generation circuit that generates a 1ODT control signal and outputs it to the first pin.

A multi-chip package according to an embodiment of the present invention includes a first semiconductor die and a second semiconductor die, wherein the first semiconductor die performs ODT of second ODT (On-die termination) circuits included in the second semiconductor die. A first pin for outputting a first ODT control signal for control to the second semiconductor die, and a 2ODT control output from the second semiconductor die to control the ODT of the first ODT circuits included in the first semiconductor die. It includes a second pin that receives a signal.

The second semiconductor die includes a third pin that receives the first ODT control signal output from the first semiconductor die, and a fourth pin that outputs the second ODT control signal to the first semiconductor die.

A memory system according to an embodiment of the present invention includes a multi-chip package including a first semiconductor die and a second semiconductor die, and a memory controller that controls the operation of the multi-chip package, wherein the first semiconductor die is A first pin for outputting a first ODT control signal for controlling the ODT of second ODT (On-die termination) circuits included in the second semiconductor die to the second semiconductor die, and a first pin included in the first semiconductor die. It includes a second pin that receives a second ODT control signal output from the second semiconductor die to control the ODT of the 1ODT circuits.

The second semiconductor die includes a third pin that receives the first ODT control signal output from the first semiconductor die, and a fourth pin that outputs the second ODT control signal to the first semiconductor die.

A semiconductor die according to an embodiment of the present invention provides a signal indicating that the read operation or write operation is performed asynchronously to another semiconductor die through a dedicated pin when a read operation or write operation is performed on the semiconductor die, that is, ODT ( Since an on-die termination) control signal can be generated and transmitted, the other semiconductor die can use the ODT control signal to control the ODT of the ODT circuit included in each of the input/output pads of the other semiconductor die. Accordingly, the power consumption of other semiconductor dies has the effect of being reduced.

In order to more fully understand the drawings cited in the detailed description of the present invention, a detailed description of each drawing is provided.
1 is a block diagram of a memory system including semiconductor dies according to an embodiment of the present invention.
FIG. 2 is a conceptual diagram showing the connection relationship between the first semiconductor die and the second semiconductor die when the first semiconductor die of FIG. 1 is used as the first rank.
FIG. 3 is a conceptual diagram showing the connection relationship between the first semiconductor die and the second semiconductor die when the second semiconductor die of FIG. 1 is used as the first rank.
FIG. 4A is a conceptual diagram of a data input/output pad included in each of the semiconductor dies of FIG. 1 and including an ODT circuit.
FIG. 4B is a conceptual diagram of a data input/output pad included in each of the semiconductor dies of FIG. 1 and including an ODT circuit.
FIG. 5 is a block diagram of an ODT control signal generation circuit included in the first rank shown in FIG. 2.
FIG. 6 is an embodiment of a circuit diagram of a latency control circuit included in the ODT control signal generation circuit of FIG. 5.
FIG. 7 is an embodiment of a circuit diagram of a replica circuit included in the ODT control signal generation circuit of FIG. 5.
FIG. 8 is an embodiment of a circuit diagram of the ODT circuit control circuit included in the second rank shown in FIG. 2.
FIG. 9 is an embodiment of a circuit diagram of a latency control circuit included in the ODT circuit control circuit shown in FIG. 8.
FIG. 10 is an embodiment of a circuit diagram of a replica circuit included in the ODT circuit control circuit shown in FIG. 8.
FIG. 11 is a timing diagram illustrating a method of training a first ODT control signal using the ODT circuit control circuit shown in FIG. 8.
FIG. 12 is a timing diagram explaining the operation of the memory system shown in FIG. 1.
Figure 13 is a table showing the ODT control results of the ODT circuit for each operating state for target and non-target.
FIG. 14 is a block diagram of a data processing system including the memory system shown in FIG. 1.
FIG. 15 is a block diagram of a data processing system including the memory system shown in FIG. 1.

1 is a block diagram of a memory system including semiconductor dies according to an embodiment of the present invention.

Referring to FIG. 1, the memory system 100 includes a memory device 110 and a memory controller 400, and the memory device 110 includes a printed circuit board (PCB) 120, It includes a first semiconductor die 200 and a second semiconductor die 300.

In the case of dynamic random access memory (DRAM), a two-rank configuration in which two semiconductor dies (200 and 300) are connected in parallel to the input/output interface 122 to increase the memory capacity of the memory device 110. (2-rank configuration) is used. For example, each semiconductor die 200 and 300 may be Low-Power Double Data Rate (LPDDR) DRAM or LPDDR Synchronous DRAM (SDRAM).

As used herein, semiconductor die refers to a die, a semiconductor chip, or an integrated circuit (IC). Depending on embodiments, the memory device 110 may refer to a multi-chip package, a semiconductor package, or a memory module.

The PCB 120 includes a first connection pin 121, an input/output interface 122, and a second connection pin 123.

The input/output interface 122 includes first data input/output pads (CP1), a read data strobe signal pad (CP2), a light clock signal pad (CP3), second data input/output pads (CP4), a clock signal pad (CP5), and command/address pads (CP6). For example, when each pad CP2, CP3, and CP5 are pads related to transmission of differential signals, each pad CP2, CP3, and CP5 represents a plurality of pads.

The first data input/output pads CP1 are pads for inputting and outputting the first group of data (DQ[11:7]), and the read data strobe signal pad CP2 is a read data strobe related to a read operation. It is a pad for transmission of signal (RDQS). The light clock signal pad (CP3) is a pad for transmitting a light clock signal (WCK) related to a write operation, and the second data input/output pads (CP4) are used to transmit the second group of data (DQ[6:0 ]), the clock signal pad (CP5) is a pad for transmission of the clock signal (CK), and the command/address pads (CP6) are pads for command signals or addresses (CA[3:0] ) are pads for transmission. At this time, command signals refer to signals related to a read command or write command.

Included in the first group of data (DQ[11:7]), the second group of data (DQ[6:0]), and the command signals or addresses (CA[3:0]) described herein Numbers (e.g., 11, 7, 6, 3, and 0) are illustrative numbers for convenience of explanation, so depending on the embodiments, numbers (e.g., 11, 7, 6, 3, and 0) may be changed.

According to embodiments, the configuration of each of the data input/output pads (CP1 and CP4) related to the input and output of data (DQ[11:7] and DQ[6:0]) is composed of each pad (CP2, CP3, CP5, and CP6). It may be different from the composition of . Depending on embodiments, a pad may also be simply called a pin.

In FIG. 1, each pad (LP1 to LP6) included in the first semiconductor die 200 used as the first rank (RANK1) is wire bonded with each pad (CP1 to CP6) of the input/output interface 122. Each pad (UP1 to UP6) included in the second semiconductor die 300, which is electrically connected through and used as the second rank (RANK2), is wire bonded to each pad (CP1 to CP6) of the input/output interface 122. It is electrically connected through. Depending on embodiments, the configuration of each of the pads LP1 and LP4, and UP1 and UP4 may be different from the configuration of each of the pads LP2, LP3, LP5, LP6, UP2, UP3, UP5, and UP6.

The first pin (P1_1) of the first semiconductor die 200 is electrically connected to the first connection pin 121 through wire bonding, and the first connection pin 121 is connected to the second semiconductor die 300 through wire bonding. ) is electrically connected to the third pin (P2_1). The transmission line that electrically connects the pins (P1_1 and P2_1) and the first connection pin 121 is called the first transmission line (TL1).

In addition, the second pin (P1_2) of the first semiconductor die 200 is electrically connected to the second connection pin 123 through wire bonding, and the second connection pin 123 is connected to the second semiconductor die through wire bonding. It is electrically connected to the fourth pin (P2_2) of (300). The transmission line that electrically connects the pins (P1_2 and P2_2) and the second connection pin 123 is called the second transmission line (TL2).

In the present invention, two pins (P1_1 and P1_2, and P2_1 and P2_2) are additionally disposed (or formed) for each semiconductor die (200 and 300).

FIG. 2 is a conceptual diagram showing the connection relationship between the first semiconductor die and the second semiconductor die when the first semiconductor die of FIG. 1 is used as the first rank, and FIG. 3 is a conceptual diagram showing the connection relationship between the first semiconductor die of FIG. 1 and the second semiconductor die when used as the first rank. This is a conceptual diagram showing the connection relationship between the first semiconductor die and the second semiconductor die.

1 to 3, the physical structures of each semiconductor die 200 and 300 are manufactured to be identical to each other. That is, the structure of each ODT control signal generation circuit (210 and 310), the structure of each ODT circuit control circuit (250 and 350), the structure of each logic circuit and memory cell array (270 and 370), and each connection circuit (280) and 380) structures are manufactured in the same way.

After each semiconductor die 200 and 300 is manufactured, each connection circuit 280 and 380 is connected depending on whether each semiconductor die 200 and 300 is used as a first rank (RANK1) or a second rank (RANK2). ) The connection relationship is determined depending on whether the bonding wire or fuse (or anti-fuse, etc.) is cut.

The first semiconductor die 200 includes a plurality of pads (LP1 to LP6), a first pin (P1_1), a second pin (P1_2), a first ODT control signal generation circuit 210, and a first ODT circuit control circuit 250. , a first logic circuit and a memory cell array 270, and a first connection circuit 280.

The first logic circuit and memory cell array 270 includes a memory cell array 272 including a plurality of memory cells, and a control logic circuit 274 that controls write and read operations for the memory cell array 272. Includes.

For example, under the control of the memory controller 400, the control logic circuit 274 writes the data (DQ[11:0]) output from the memory controller 400 to the memory cell array 272 during a write operation. And, during a read operation, the data (DQ[11:0]) read from the memory cell array 272 is transmitted to the memory controller 400.

In addition, according to the control of the memory controller 400, the control logic circuit 274 operates the first ODT control signal generation circuit 210 (e.g., each selection signal TRAIN_ON, SELN, SELP, SELN', and SELP' ), etc.) is controlled.

The second semiconductor die 300 includes a plurality of pads (UP1 to UP6), a third pin (P2_1), a fourth pin (P2_2), a second ODT control signal generation circuit 310, and a second ODT circuit control circuit 350. , a second logic circuit and a memory cell array 370, and a second connection circuit 380.

The second logic circuit and memory cell array 370 includes a memory cell array 372 including a plurality of memory cells, and a control logic circuit 374 that controls write and read operations for the memory cell array 372. Includes.

For example, under the control of the memory controller 400, the control logic circuit 374 writes the data (DQ[11:0]) output from the memory controller 400 to the memory cell array 372 during a write operation. And, during a read operation, the data (DQ[11:0]) read from the memory cell array 372 is transmitted to the memory controller 400.

In addition, under the control of the memory controller 400, the control logic circuit operates the second ODT control signal generation circuit 310 (e.g., generates each selection signal (TRAIN_ON, SELN, SELP, SELN', and SELP'). etc.) is controlled.

For write operation or read operation, command signals and addresses output from the memory controller 400 are transmitted to each control logic circuit 274 and 374 through command/address pads CP6.

As shown in FIG. 2, the first semiconductor die 200 is used as the first rank (RANK1) and the second semiconductor die 300 is used as the second rank (RANK2). However, as shown in FIG. 3, the first semiconductor die 200 is used as the second rank (RANK2) and the second semiconductor die 300 is used as the first rank (RANK1).

The first connection circuit 280 includes a first group of terminals (T11, T12, T13, and T14), and determines whether the first semiconductor die 200 is used as the first rank (RANK1) or the second rank (RANK1). Depending on whether it is used as RANK2), the first terminal (T11) is connected to the fourth terminal (T14) or the third terminal (T13), and the second terminal (T12) is connected to the third terminal (T13) or the fourth terminal (T14). ) is connected to.

As shown in FIG. 2, the first terminal (T11) and the fourth terminal (T14) are connected using wire bonding (BW1), or as shown in FIG. 3, the first terminal (T11) and the third terminal (T13) are connected. ) is connected. In addition, as shown in FIG. 2, the second terminal (T12) and the third terminal (T13) are connected using wire bonding (BW2), or as shown in FIG. 3, the second terminal (T12) and the fourth terminal are connected. (T14) is connected.

According to embodiments, when the first fuse is connected between the first terminal (T11) and the fourth terminal (T14) and the second fuse is connected between the first terminal (T11) and the third terminal (T13), A desired connection can be formed depending on whether the first fuse or the second fuse is cut. In addition, when the third fuse is connected between the second terminal (T12) and the third terminal (T13) and the fourth fuse is connected between the second terminal (T12) and the fourth terminal (T14), the third fuse is connected between the second terminal (T12) and the fourth terminal (T14). A desired connection can be formed depending on whether the fuse or the fourth fuse is cut.

Depending on embodiments, a desired connection may be formed using first to fourth antifuses instead of the first to fourth fuses.

The second connection circuit 380 includes a second group of terminals (T21, T22, T23, and T24), and determines whether the second semiconductor die 300 is used as the first rank (RANK1) or the second rank (RANK1). Depending on whether it is used as RANK2), the first terminal (T21) is connected to the third terminal (T23) or the fourth terminal (T24), and the second terminal (T22) is connected to the third terminal (T23) or the fourth terminal (T24). ) is connected to.

As shown in FIG. 2, the first terminal (T21) and the third terminal (T23) are connected using wire bonding (BW3), or as shown in FIG. 3, the first terminal (T21) and the fourth terminal (T24) are connected. ) is connected. In addition, as shown in FIG. 2, the second terminal (T22) and the fourth terminal (T24) are connected using wire bonding (BW4), or as shown in FIG. 3, the second terminal (T22) and the third terminal are connected. (T23) is connected.

According to embodiments, when the fifth fuse is connected between the first terminal (T21) and the fourth terminal (T24) and the sixth fuse is connected between the first terminal (T21) and the third terminal (T23), A desired connection can be formed depending on whether the fifth fuse or the sixth fuse is cut. In addition, when the seventh fuse is connected between the second terminal (T22) and the third terminal (T23) and the eighth fuse is connected between the second terminal (T22) and the fourth terminal (T24), the seventh fuse A desired connection can be formed depending on whether the fuse or the eighth fuse is cut.

Depending on the embodiment, the desired connection may be formed using the 5th to 8th antifuses instead of the 5th to 6th fuses.

As shown in FIG. 2, when the first semiconductor die 200 is used as the first rank (RANK1), two terminals (T11 and T14) among the first group of terminals (T11, T12, T13, and T14) ) is connected and two terminals (T12 and T13) are connected.

As shown in FIG. 2, when the second semiconductor die 300 is used as the second rank (RANK2), two terminals (T21 and T23) among the second group of terminals (T21, T22, T23, and T24) ) is connected and two terminals (T22 and T24) are connected.

As shown in FIG. 3, when the second semiconductor die 300 is used as the first rank (RANK1), two terminals (T21 and T24) among the second group of terminals (T21, T22, T23, and T24) ) is connected and two terminals (T22 and T23) are connected.

As shown in FIG. 3, when the first semiconductor die 200 is used as the second rank (RANK2), two terminals (T11 and T13) among the first group of terminals (T11, T12, T13, and T14) ) is connected and two terminals (T12 and T14) are connected.

In Figure 2, the first pin (P1_1) is used as an output pin that outputs the first ODT control signal (ODT_CT1) to the second rank (RANK2 or 300), and the third pin (P2_1) is used as an output pin to output the first ODT control signal (ODT_CT1) to the second rank (RANK2 or 300). Alternatively, it is used as an input pin to receive the first ODT control signal (ODT_CT1) output from 200).

However, in Figure 3, the first pin (P1_1) is used as an input pin to receive the 2nd ODT control signal (ODT_CT2) output from the 1st rank (RANK1 or 300), and the 3rd pin (P2_1) is used as an input pin to receive the 2nd ODT control signal (ODT_CT2) output from the first rank (RANK1 or 300). It is used as an output pin to output ODT_CT2) as the second rank (RANK2 or 200).

In addition, in Figure 2, the second pin (P1_2) is used as an input pin to receive the second ODT control signal (ODT_CT2) output from the second rank (RANK2 or 300), and the fourth pin (P2_2) is used as an input pin to receive the second ODT control signal (ODT_CT2) output from the second rank (RANK2 or 300). It is used as an output pin to output ODT_CT2) to the first rank (RANK1 or 200), but in Figure 3, the second pin (P1_2) is an output to output the first ODT control signal (ODT_CT1) to the first rank (RANK1 or 300). It is used as a pin, and the fourth pin (P2_2) is used as an input pin to receive the first ODT control signal (ODT_CT1) output from the second rank (RANK2 or 200).

By the first connection circuit 280, the output terminal (OT1) of the first ODT control signal generation circuit 210 is connected to one of the first pin (P1_1) and the second pin (P1_2) and the first ODT circuit control circuit The input terminal (IT1) of 250 is connected to the other one of the first pin (P1_1) and the second pin (P1_2).

By the second connection circuit 380, the output terminal (OT2) of the second ODT control signal generation circuit 310 is connected to one of the third pin (P2_1) and the fourth pin (P2_2) and the second ODT circuit control circuit The input terminal (IT2) of 350 is connected to the other one of the third pin (P2_1) and the fourth pin (P2_2).

FIG. 4A is a conceptual diagram of a data input/output pad included in each of the semiconductor dies of FIG. 1 and including an ODT circuit. Referring to FIGS. 1 to 4A , it is assumed that the structures of each of the data input/output pads LP1, LP4, UP1, and UP4 are the same.

Accordingly, the data input/output pad (DQ_PAD), which represents each data input/output pad (LP1, LP4, UP1, and UP4) representatively (or collectively), includes the transmission circuit 201, the selection circuit 204, and the receiver 207. , and an input/output pin 209, and the transmission circuit 201 includes an ODT circuit 202 and a transmitter 205.

The memory controller 400 can exchange data with the corresponding memory cell array 270 or 370 through the input/output pin 209.

The ODT circuit 202 includes a switch control circuit 203, a resistor (OR), and a switch (OSW), where the resistor (OR) and the switch (OSW) are connected to a voltage supply line (PL) that supplies a termination voltage (VTT). ) and the input/output pin 209.

The switch control circuit 203 controls the on or off of the switch OSW according to the level of the first selection signal TRAIN_ON and the level of the output signal MUXO1 or MUXO2 of the ODT circuit control circuit 250 or 350. do.

When a training operation is performed in the training mode, the level of the first selection signal (TRAIN_ON) is the first level (e.g., high level), and in the normal operation mode, the normal operation (e.g., a light operation or When a read operation) is performed, the level of the first selection signal (TRAIN_ON) is the second level (eg, low level).

For example, when the training operation is not performed (i.e., when the level of the first selection signal (TRAIN_ON) is low level or the training function is off), the switch control circuit 203 outputs the output signal (MUXO1 or MUXO2). ) Turn off the switch (OSW) regardless of the level. For example, the switch control circuit 203 may be an AND gate that receives the first selection signal (TRAIN_ON) and the output signal (MUXO1 or MUXO2), but is not limited to this.

Depending on the embodiment, the switch (OSW) may be implemented with an NMOS transistor or a PMOS transistor. For example, when the switch (OSW) is turned on, the resistor (OR) is connected to the input/output pin 209, so the resistance value of the ODT circuit 203 is the resistance value of the resistor (OR) (for example, 40Ω). can be set.

The selection circuit 204 transmits the output signal of the logic circuit and the memory cell array 270 or 370 or the output signal MUXO1 or MUXO2 to the transmitter 205 according to the level of the first selection signal TRAIN_ON.

For example, when the level of the first selection signal (TRAIN_ON) is the first level (i.e., when the training function is on), the selection circuit 204 sends the output signal (MUXO1 or MUXO2) to the transmitter (205) ) and is transmitted to the memory controller (400) through the input/output pin (209). However, when the level of the first selection signal TRAIN_ON is the second level (i.e., when the training function is off), the selection circuit 204 selects the output of the logic circuit and the memory cell array 270 or 370. The signal is transmitted to the memory controller 400 through the transmitter 205 and the input/output pin 209.

In FIG. 4A, for convenience of explanation, the data input/output pad DQ_PAD including the switch control circuit 203 and the selection circuit 204 is shown as an example, but depending on the embodiment, the switch control circuit 203 and the selection circuit 204 are shown as examples. At least one of the circuits 204 may be included in the corresponding ODT circuit control circuits 250 and 350.

FIG. 4B is a conceptual diagram of a data input/output pad included in each of the semiconductor dies of FIG. 1 and including an ODT circuit.

Referring to FIGS. 1, 2, 3, and 4B, it is assumed that the structures of each of the data input/output pads LP1, LP4, UP1, and UP4 are the same.

Accordingly, the data input/output pad (DQ_PAD), which represents each data input/output pad (LP1, LP4, UP1, and UP4) representatively (or collectively), includes the transmission circuit 201, the selection circuit 204, and the receiver 207. , and an input/output pin 209, and the transmitting circuit 201 includes an ODT circuit 202A and a transmitter 205.

The ODT circuit 202A includes a switch control circuit 203A, resistors (OR1 to ORt, t is a natural number of 2 or more), and switches (SW1 to SWt).

The first resistor (OR1) and the first switch (SW1) connected in series are connected between the voltage supply line (PL) and the input/output pin 209, and the second resistor (OR2) and the second switch ( SW2) is connected between the voltage supply line (PL) and the input/output pin 209, and the t resistor (ORt) and the t switch (SWt) connected in series are connected to the voltage supply line (PL) and the input/output pin (209). connected between.

The resistance values of each of the resistors (OR1 to ORt) may be designed differently. Each of the switches (SW1 to SWt) can be implemented with an NMOS transistor or a PMOS transistor.

The switch control circuit 203A turns each switch SW1 to SWt on or off depending on the level of the first selection signal TRAIN_ON and the level of the output signal MUXO1 or MUXO2 of the ODT circuit control circuit 250 or 350. Control off.

When at least one of the switches SW1 to SWt is turned on under the control of the switch control circuit 203A, at least one resistor connected to at least one switch that is turned on among the resistors OR1 to ORt is input/output. Connected to pin 209. Accordingly, the resistance value of the ODT circuit 202A can be set to a specific value (eg, 40Ω or 240Ω).

For example, when the training function is off, the switch control circuit 203A turns on at least one of the switches SW1 to SWt to set the resistance value of the ODT circuit 202A.

The ODT circuit (202 or 202A) included in each of the data input/output pads (LP1 and LP4) of the first semiconductor die 200 is referred to as the first ODT circuit, and the data input/output pads (UP1 and UP1) of the second semiconductor die 300 are referred to as the first ODT circuit. UP4) The ODT circuit (202 or 202A) included in each is called the second ODT circuit.

Controlling the ODT of the ODT circuit (202 or 202A) means turning off the switch (OSW, or at least one of SW1 to SWt) included in the first ODT circuit or the second ODT circuit, or turning off the switch (OSW, or SW1 to SWt). This means turning on (at least one of SWt) to make the resistance value of the first ODT circuit or the second ODT circuit to a specific resistance value or high impedance (Hi-Z).

In FIG. 4B, for convenience of explanation, the data input/output pad DQ_PAD including the switch control circuit 203A and the selection circuit 204 is shown as an example, but depending on the embodiment, the switch control circuit 203A and the selection circuit 204 are shown as examples. At least one of the circuits 204 may be included in the corresponding ODT circuit control circuits 250 and 350.

When the structure of each data input/output pad (LP1 and LP4) of the first semiconductor die 200 is the same as the structure of the data input/output pad (DQ_PAD) of FIG. 4A or 4B, the output signal of the first ODT circuit control circuit 250 (MUXO1) is supplied to the data input/output pad (DQ_PAD) in Figure 4a or 4b.

In addition, when the structure of each data input/output pad (UP1 and UP4) of the second semiconductor die 300 is the same as the structure of the data input/output pad (DQ_PAD) of FIG. 4A or 4B, the structure of the second ODT circuit control circuit 350 The output signal (MUXO2) is supplied to the data input/output pad (DQ_PAD) in Figure 4a or 4b.

FIG. 5 is a block diagram of an ODT control signal generation circuit included in the first rank shown in FIG. 2.

1 to 5, the first ODT control signal generation circuit 210 included in the first semiconductor die 200 includes a clock buffer 212, a command decoder 214, a latency control circuit 216, and a replica. It includes a circuit 230 and a first selection circuit 240.

The clock buffer 212 buffers the clock signal CK input through the clock signal pad LP5 and transmits the buffered clock signal to the command decoder 214 and the latency control circuit 216. In this specification, for convenience of explanation, the clock signal and the buffered clock signal are denoted as CK.

The command decoder 214 uses the clock signal CK and command signals CA[3:0] input through the command/address pads LP6 to generate command signals CA[3:0]. ) is decoded to generate a first decoded signal (DCMD1) and transmitted to the latency control circuit 216.

FIG. 6 is an embodiment of a circuit diagram of a latency control circuit included in the ODT control signal generation circuit of FIG. 5.

Referring to FIG. 6, the latency control circuit 216 includes a first group of flip-flops (218_1 to 218_m) connected in series, a second group of flip-flops (220_1 to 220_m) connected in series, and a first memory. It includes a device 222, a second selection circuit 224, a second memory device 226, a third selection circuit 228, and a pulse width determination circuit 229. Here, m is a natural number of 4 or more. Depending on the embodiment, the number of flip-flops (218_1 to 218_m) in the first group and the number of flip-flops (220_1 to 220_m) in the second group may be different.

The memory controller 400 adjusts (or sets) values stored in memory devices (222 and 226 in FIG. 6, and/or 222' and 226' in FIG. 9) to generate latency or a latency signal (TCTL_i). The pulse width (this is also called the 'activation interval') can be adjusted (or set).

The clock signal (CK) buffered by the clock buffer 212 is supplied to the clock terminal of each flip-flop (218_1 to 218_m, and 220_1 to 220_m).

The first decoded signal (DCMD1) is supplied to the input terminal (D) of the first flip-flop (218_1) of the first group, and the output terminal (Q) of the first flip-flop (218_1) is supplied to the second flip-flop (218_2) ), and according to this connection method, the output terminal (Q) of the (m-1)th flip-flop (218_(m-1)) is the input terminal (Q) of the m-th flip-flop (218_m). Connected to terminal (D).

From a time perspective, it is assumed that the delay from the first flip-flop (218_1) to the m-th flip-flop (218_m) corresponds to read latency (RL).

The output terminal (Q) of the m-th flip-flop (218_m) of the first group is connected to the input terminal (D) of the first flip-flop (220_1) of the second group, and the output terminal of the first flip-flop (220_1) (Q) is connected to the input terminal (D) of the second flip-flop (220_2), and according to this connection method, the output terminal (Q) of the (m-1)th flip-flop (220_(m-1)) is It is connected to the input terminal (D) of the m-th flip-flop (220_m).

The output signal of each of the first group of flip-flops (218_1 to 218_m) is transmitted to the second selection circuit 224, and the output signal of at least one flip-flop among the first group of flip-flops (218_1 to 218_m) is It is transmitted to the third selection circuit 228. Among the first group of flip-flops (218_1 to 218_m), how many output signals of the flip-flops are transmitted to the third selection circuit 228 varies depending on design specifications.

The output signal of each of the second group of flip-flops 220_1 to 220_m is transmitted to the third selection circuit 228.

The second selection circuit 224 selects any one output signal from among the first group of flip-flops 218_1 to 218_m in response to the second selection signals SELN output from the first memory device 222. It is transmitted to the pulse width determination circuit 229.

The pulse width determination circuit 229 activates the latency signal TCTL_i according to the output signal of the second selection circuit 224 and deactivates the activated latency signal TCTL_i according to the output signal of the third selection circuit 228. I order it.

The pulse width determination circuit 229 uses the output signal of the second selection circuit 224 and the output signal of the third selection circuit 228 to determine the pulse width (or activation time and deactivation time) of the latency signal TCTL_i. Control (or decide).

The pulse width determination circuit 229 may be implemented as an SR latch 229. The second selection circuit 224 selects any one output signal from among the first group of flip-flops 218_1 to 218_m to SR according to the second selection signals SELN output from the first memory device 222. It is output to the set input terminal (S) of the latch 229. The first memory device 222 may be implemented as a mode register set.

For example, the control logic circuit 274 included in the first logic circuit and memory cell array 270 may receive data from the memory controller 400 and store the data in the first memory device 222. Second selection signals SELN may be generated according to data stored in the first memory device 222.

The third selection circuit 228 selects at least one flip-flop from among the first group of flip-flops 218_1 to 218_m and a One output signal from among the two groups of flip-flops (220_1 to 220_m) is output to the reset input terminal (R) of the SR latch (229). The second memory device 226 may be implemented as a mode register set. Each selection circuit 224 and 228 may be implemented as a multiplexer.

For example, the control logic circuit 274 included in the first logic circuit and the memory cell array 270 may receive data transmitted from the memory controller 400 and store it in the second memory device 226. Third selection signals SELP may be generated according to data stored in the second memory device 226.

The latency signal TCTL_i output from the output terminal Q of the SR latch 229 is supplied to the first input terminal 1 of the first selection circuit 240 and the replica circuit 230.

As shown in FIG. 12, the replica circuit 230 stores the first bit of data (RDATA1 or RDATA2) corresponding to the burst length from the first time corresponding to a specific rising edge of the light clock signal (WCK). It is a delay circuit that replicates the delay time (tWCKDQo) up to the second point in time when is output.

FIG. 7 is an embodiment of a circuit diagram of a replica circuit included in the ODT control signal generation circuit of FIG. 5.

Referring to FIG. 7, the replica circuit 230 includes delay circuits (232_1 to 232_n, n is a natural number of 2 or more) connected in series. Depending on the embodiment, each delay circuit (232_1 to 232_n) may be implemented as a buffer or inverter.

For example, the replica circuit 230 receives the latency signal (TCTL_i) output from the latency control circuit 216, delays the latency signal (TCTL_i) by a set delay time (tWCKDQo), and delays the delayed latency signal (DTCTL). ) is supplied to the second input terminal (0) of the first selection circuit (240). The first selection circuit 240 may be implemented as a multiplexer.

The first selection circuit 240 outputs the latency signal TCTL_i or the delayed latency signal DTCTL as the first ODT control signal ODT_CT1, depending on the level of the first selection signal TRAIN_ON.

As shown in FIG. 2, the activation point of the first ODT control signal (ODT_CT1) generated in the first semiconductor die 200 used as the first rank (RANK1) and the second semiconductor used as the second rank (RANK2) When a training operation that adjusts the activation point of the second ODT control signal (ODT_CT2) generated in the die 300 is performed, the first selection signal (TRAIN_ON) is at the first level (e.g., high level). is set to .

Therefore, during the training operation, the first selection circuit 240 controls the latency signal TCTL_i input to the first input terminal 1 in response to the first selection signal TRAIN_ON having the first level to the first ODT. It is output as a signal (ODT_CT1).

However, when the training operation is not performed, the first selection signal TRAIN_ON is set to the second level. Accordingly, the first selection circuit 240 selects the delayed latency signal DTCTL input to the second input terminal 0 in response to the first selection signal TRAIN_ON having a second level (e.g., low level). ) is output as the first ODT control signal (ODT_CT1).

As described with reference to FIG. 2, the first ODT control signal (ODT_CT1) generated in the first semiconductor die 200 used as the first rank (RANK1) is generated by the components (T11, T14, P1_1, TL1, 121, It is transmitted to the input terminal (IT2) of the second ODT circuit control circuit 350 of the second semiconductor die 300 used as the second rank (RANK2) through P2_1, T24, and T22).

FIG. 8 is an embodiment of a circuit diagram of the ODT circuit control circuit included in the second rank shown in FIG. 2.

Referring to FIG. 8, the second ODT circuit control circuit 350 includes a training circuit 351, a first buffer 364, a third buffer 366, and a fourth selection circuit 368.

The training circuit 351 includes a clock buffer 352, a command decoder 354, a latency control circuit 356, a replica circuit 358, a sampling circuit 360, and a second buffer 362.

The clock buffer 352 buffers the clock signal CK input through the clock signal pad UP5 and transmits the buffered clock signal to the command decoder 354 and the latency control circuit 356. As described previously, the clock signal and buffered clock signal are denoted as CK.

The command decoder 354 generates command signals (CA[3:0]) using the clock signal (CK) and command signals (CA[3:0]) input through the command/address pads (UP6). ) is decoded to generate a second decoded signal (DCMD2) and transmitted to the latency control circuit 356.

FIG. 9 is an embodiment of a circuit diagram of a latency control circuit included in the ODT circuit control circuit shown in FIG. 8.

Referring to Figures 6 and 9, except for the input/output signals (DCMD1 and DCMD2, TCTL_i, and T_ODT) and drawing numbers, the structure and operation of the latency control circuit 216 shown in Figure 6 is as shown in Figure 9. The structure and operation of the latency control circuit 356 are the same.

FIG. 10 is an embodiment of a circuit diagram of a replica circuit included in the ODT circuit control circuit shown in FIG. 8.

7 and 10, the input terminal of the first delay circuit 232_1' of the replica circuit 358 is connected to the output terminal of the third buffer 366, and the nth delay of the replica circuit 358 is connected to the output terminal of the third buffer 366. Except that the output terminal of the circuit 232_n' is connected to the control terminal of the sampling circuit 360 and the drawing numbers, the structure and operation of the replica circuit 230 shown in FIG. 7 is similar to that of the replica circuit shown in FIG. 10. The structure and operation of the circuit 358 are the same.

FIG. 11 is a timing diagram illustrating a method of training a first ODT control signal using the ODT circuit control circuit shown in FIG. 8.

1 to 3, the first ODT control signal ODT_CT1, which is an asynchronous signal generated in the first semiconductor die 200, is connected to the second ODT control signal ODT_CT1 through an off-chip connection (for example, TL1 and 121). A delay occurs in the process of being transmitted to the semiconductor die 300, and the second ODT control signal ODT_CT2, which is an asynchronous signal generated in the second semiconductor die 300, is connected to an off-chip connection (for example, TL2 and 123). ), a delay occurs in the process of being transmitted to the first semiconductor die 200.

Each ODT control signal generation circuit (210 and 310) of each die (200 and 300) takes this delay into consideration and adjusts (or sets) the activation and deactivation timing of each ODT control signal (ODT_CT1 and ODT_CT2).

It is activated before the first bit of the first read data (RDATA1) corresponding to the burst length is output in the first semiconductor die 200, which is used as the first rank (RANK1) that performs the read operation. The process of training the timing of the first ODT control signal (ODT_CT1), which is deactivated after the last bit of the first read data (RDATA1) is output, is described in detail with reference to FIGS. 1, 2, and 4A to 12.

Here, activation means transition or change from the second level to the first level, and deactivation means transition from the first level to the second level.

In order to generate a reference ODT signal (T_ODT) with an activation period from (RL-4tCK) to (RL+4tCK) for read data corresponding to the burst length, the memory controller 400 uses a first value and a second value. is transmitted to the second semiconductor die 300 used as the second rank (RANK2), and the control logic circuit 374 of the second semiconductor die 300 is transmitted to the third semiconductor die 300 included in the latency control circuit 356 of FIG. 8. Assume that the first value is set in the memory device 222' and the second value is set in the fourth memory device 226'. Here, tCK is the period of the clock signal (CK) and the training resolution.

In this specification, value refers to digital signals related to the generation of selection signals (SELN and SELP' in FIG. 6, and SELN' and SELP' in FIG. 9).

Assuming that the decoder 354 of FIG. 8 generates the activated second decoded signal DCMD2 by decoding the command signals CA[3:0], the decoder 354 of each semiconductor die 200 or 300 in training mode It is assumed that the control logic circuits 274 and 374 generate a first selection signal (TRAIN_ON) having a first level, and the command signals (CA[3:0]) are assumed to be read command signals for read operation. .

In addition, for convenience of explanation, the number of the first group of flip-flops (218_1 to 218_m, and 218_1' to 218_m') and the second group of flip-flops (220_1 to 220_m, and 220_1'~220_m') is assumed to be 13 (i.e., m is 13).

The fifth selection circuit 224' included in the latency control circuit 356 of FIG. 9 selects the fifth selection signals SELN' generated based on the first value set in the third memory device 222'. In response, the output signal (RL-4tCK) of the ninth flip-flop (218_9') of the first group is output to the set input terminal (S) of the SR latch (229'). Accordingly, as shown in FIG. 11, the reference ODT signal (T_ODT) is activated.

The sixth selection circuit 228' included in the second latency control circuit 356 of FIG. 9 selects sixth selection signals SELP' generated based on the second value set in the fourth memory device 226'. ), the output signal (RL+4tCK) of the fourth flip-flop (220_4') of the second group is output to the reset input terminal (R) of the SR latch (229'). Therefore, as shown in FIG. 11, the reference ODT signal (T_ODT) is deactivated.

That is, as shown in FIG. 11, the pulse width of the reference ODT signal (T_ODT) is from (RL-4tCK) to (RL+4tCK). Here, CK_t and CK_c are differential clock signals.

The memory controller 400 transmits the third and fourth values to the first semiconductor die 200 used as the first rank (RANK1), and the control logic circuit 274 of the first semiconductor die 200 is shown in FIG. Assume that the third value is set to the first memory device 222 included in the first latency control circuit 216 of Figure 6 and the fourth value is set to the second memory device 226.

In the first training operation (TRAINING_1), the selection circuit 224 included in the first latency control circuit 216 of FIG. 6 selects a second selection generated based on the third value set in the first memory device 222. In response to the signals SELN, the output signal RL-12tCK of the first flip-flop 218_1 of the first group is output to the set input terminal S of the SR latch 229.

The third selection circuit 228 included in the first latency control circuit 216 of FIG. 6 responds to the third selection signals SELP generated based on the fourth value set in the second memory device 226. Thus, the output signal (RL-4tCK) of the ninth flip-flop (218_9) of the first group is output to the reset input terminal (R) of the SR latch (229). As shown in FIG. 11, in the first training operation (TRAINING_1), the pulse width of the first latency signal (TCTL_i, i=1) is from (RL-12tCK) to (RL-4tCK).

For simplification of the drawing and convenience of explanation, the delay of the first buffer 364, the delay of the third buffer 366, and the delay (tWCKDQo) of the replica circuit 358 in FIG. 8 are not considered.

In the first training operation (TRAINING_1), the sampling circuit 360 samples the reference ODT signal (T_ODT) using the rising edge of the first latency signal (TCTL_1). Depending on the embodiment, the sampling circuit 360 may be a D-flip-flop.

The sampling circuit 360 outputs a sampling signal (SPL) having a low level (L) to the second buffer 362. The fourth selection circuit 368 in FIG. 8 inputs and outputs the output signal of the second buffer 362 (i.e., the output signal having a low level) in response to the first selection signal (TRAIN_ON) having the first level. Output to pads (UP1 and UP4). Embodiments of the data input/output pads UP1 and UP4 are shown in FIGS. 4A and 4B.

The memory controller 400 receives data (DQ[11:0]) output asynchronously from the data input/output pads (UP1 and UP4) of the second semiconductor die 300, and data (DQ[11:0]). :0]), determines performance of the second training operation (TRAINING_2) when each of the bits included is low (or 'data 0'), and uses the 5th and 6th values as the first rank (RANK1) It is transmitted to the first semiconductor die 200.

The control logic circuit 274 of the first semiconductor die 200 sets the fifth value to the first memory device 222 included in the first latency control circuit 216 of FIG. 6 and sets the fifth value to the second memory device 226. Set the sixth value.

In the second training operation (TRAINING_2), the second selection circuit 224 included in the first latency control circuit 216 of FIG. 6 selects the first selection circuit 224 generated based on the fifth value set in the first memory device 222. In response to the 2 selection signals SELN, the output signal RL-11tCK of the second flip-flop 218_2 of the first group is output to the set input terminal S of the SR latch 229.

The third selection circuit 228 included in the first latency control circuit 216 of FIG. 6 responds to the third selection signals SELP generated based on the sixth value set in the second memory device 226. Thus, the output signal (RL-3tCK) of the tenth flip-flop (218_10) of the first group is output to the reset input terminal (R) of the SR latch (229). As shown in FIG. 11, in the second training operation (TRAINING_2), the pulse width of the second latency signal (TCTL_i, i=2) is from (RL-11tCK) to (RL-3tCK).

In the second training operation (TRAINING_2), the sampling circuit 360 samples the reference ODT signal (T_ODT) using the rising edge of the second latency signal (TCTL_2).

The sampling circuit 360 outputs a sampling signal (SPL) having a low level (L) to the second buffer 362. The fourth selection circuit 368 in FIG. 8, in response to the first selection signal (TRAIN_ON) having the first level, sends the output signal of the second buffer 362, that is, the output signal having a low level, to the data input/output pads. Output as (UP1 and UP4).

The memory controller 400 receives data (DQ[11:0]) output asynchronously from the data input/output pads (UP1 and UP4) of the second semiconductor die 300, and receives data (DQ[11:0]) When each of the bits included in ) is low, it is determined to perform the third training operation (TRAINING_3), and the seventh and eighth values are transmitted to the first semiconductor die 200 used as the first rank (RANK1) do.

In the same manner as the first training operation (TRAINING_1) and the second training operation (TRAINING_2), the third training operation (TRAINING_3) to the eighth training operation (TRAINING_8) are performed sequentially.

The memory controller 400 receives data (DQ[11:0]) output from the data input/output pads UP1 and UP4 of the second semiconductor die 300 according to the result of the eighth training operation (TRAINING_8), Since each of the bits included in the data (DQ[11:0]) is low, the performance of the ninth training operation (TRAINING_9) is determined, and the 19th and 20th values are used as the first rank (RANK1). 1Transmitted to semiconductor die 200.

In the ninth training operation (TRAINING_9), the second selection circuit 224 included in the first latency control circuit 216 of FIG. 6 selects the first selection circuit 224 generated based on the 19th value set in the first memory device 222. In response to the two selection signals SELN, the output signal RL-4tCK of the ninth flip-flop 218_9 of the first group is output to the set input terminal S of the SR latch 229.

The third selection circuit 228 included in the first latency control circuit 216 of FIG. 6 responds to the third selection signals SELP generated based on the 20th value set in the second memory device 226. Thus, the output signal (RL+4tCK) of the fourth flip-flop (220_4) of the second group is output to the reset input terminal (R) of the SR latch (229). As shown in FIG. 11, in the ninth training operation (TRAINING_9), the pulse width of the ninth latency signal (TCTL_i, i=9) is from (RL-4tCK) to (RL+4tCK).

In the ninth training operation (TRAINING_9), the sampling circuit 360 samples the reference ODT signal (T_ODT) using the rising edge of the ninth latency signal (TCTL_9). Depending on the embodiment, the sampling circuit 360 may output a sampling signal (SPL) having a high level (H), but as shown in FIG. 11, the sampling circuit 360 may output a sampling signal (SPL) having a low level (L). Assume that a signal (SPL) is output.

The sampling circuit 360 outputs a sampling signal (SPL) having a low level (L) to the second buffer 362. The fourth selection circuit 368 in FIG. 8, in response to the first selection signal (TRAIN_ON) having the first level, sends the output signal of the second buffer 362, that is, the output signal having a low level, to the data input/output pads. Output as (UP1 and UP4).

The memory controller 400 asynchronously outputs data (DQ[11:0]) from the data input/output pads (UP1 and UP4) of the second semiconductor die 300 according to the result of the ninth training operation (TRAINING_9). When each of the bits included in the data (DQ[11:0]) is low, it is determined to perform the tenth training operation (TRAINING_10), and the 21st and 22nd values are set to the first rank (RANK1). It is transmitted to the first semiconductor die 200 to be used. The resolution in each training operation (TRAINING_1 to TRAINING_10) is 1tCK.

In the tenth training operation (TRAINING_10), the second selection circuit 224 included in the first latency control circuit 216 of FIG. 6 selects the first selection circuit 224 generated based on the 21st value set in the first memory device 222. In response to the two selection signals SELN, the output signal RL-3tCK of the tenth flip-flop 218_10 of the first group is output to the set input terminal S of the SR latch 229.

The third selection circuit 228 included in the first latency control circuit 216 of FIG. 6 responds to the third selection signals SELP generated based on the 22nd value set in the second memory device 226. Thus, the output signal (RL+5tCK) of the fifth flip-flop (220_5) of the second group is output to the reset input terminal (R) of the SR latch (229).

As shown in FIG. 11, in the tenth training operation (TRAINING_10), the pulse width of the tenth latency signal (TCTL_i, i=10) is from (RL-3tCK) to (RL+5tCK).

In the tenth training operation (TRAINING_10), the sampling circuit 360 samples the reference ODT signal (T_ODT) using the rising edge of the tenth latency signal (TCTL_10).

The sampling circuit 360 outputs a sampling signal (SPL) having a high level (H) to the second buffer 362. The fourth selection circuit 368 in FIG. 8, in response to the first selection signal (TRAIN_ON) having the first level, sends the output signal of the second buffer 362, that is, the output signal having a high level, to the data input/output pads. Output as (UP1 and UP4).

The memory controller 400 receives data (DQ[11:0]) output from the data input/output pads UP1 and UP4 of the second semiconductor die 300 according to the result of the tenth training operation (TRAINING_10), Since each of the bits included in the data (DQ[11:0]) is high, it is decided to stop further training operations.

For example, when the training target is (RL-4tCK), an error of up to 1tCK may occur. Even if the above error occurs, the first ODT control signal generation circuit 210 is activated before the first bit of the first read data (RDATA1) corresponding to the burst length is output, and the last bit of the first read data (RDATA1) is output. It is deactivated after being activated. Accordingly, the second ODT circuit control circuit 350 of the second semiconductor die 300 can control the ODT of the second ODT circuit included in each of the data input/output pads UP1 and UP4 at (RL-3tCK).

In the same way as the first training operation (TRAINING_1) to the tenth training operation (TRAINING_10) shown in FIG. 11, the first ODT circuit control circuit 250 receives the second ODT control signal output from the second ODT control signal generation circuit 310. The pulse width of (ODT_CT2) (or the activation time of the second ODT control signal (ODT_CT2) and the deactivation time of the second ODT control signal (ODT_CT2)) can be adjusted.

When a normal operation (e.g., a light operation or a read operation) is performed on each semiconductor die 200 or 300, the control logic circuits 274 and 374 of each semiconductor die 200 or 300 have a second level. Generates the first selection signal (TRAIN_ON).

When a read operation is performed on the first semiconductor die 200, the latency control circuit 216 of the first ODT control signal generation circuit 210 of FIG. 5 moves from (RL-3tCK) to (RL+) illustrated in FIG. 11. The tenth latency signal (TCTL_10) having a pulse width of up to 5tCK) is output to the replica circuit 230.

The replica circuit 230 delays the tenth latency signal TCTL_10 by the delay time tWCKDQo and outputs the delayed latency signal DTCTL to the first selection circuit 240.

The first selection circuit 240 outputs the delayed latency signal DTCTL as the first ODT control signal ODT_CT1 according to the first selection signal TRAIN_ON having the second level. Accordingly, the first ODT control signal (ODT_CT1) is activated at (RL-3tCK) + tWCKDQo.

As shown in FIG. 2, the first ODT control signal ODT_CT1 is transmitted to the second ODT circuit of the second semiconductor die 300 through the components T11, T14, P1_1, TL1, 121, P2_1, T24, and T22. It is transmitted to the input terminal (IT2) of the control circuit 350.

The first buffer 364 shown in FIG. 8 receives and buffers the first ODT control signal (ODT_CT1) transmitted from the first semiconductor die 200, and sends the buffered first ODT control signal (ODT_CT1) to the third buffer ( 366).

The fourth selection circuit 368 outputs the output signal ODT_CT1 of the third buffer 366 to the data input/output pads UP1 and UP4 according to the first selection signal TRAIN_ON having the second level.

Referring to FIG. 4A, the switch control circuit 203 controls the on or off of the switch OSW according to the level of the first selection signal TRAIN_ON and the level of the output signal MUXO2 of the fourth selection circuit 368. do.

Additionally, referring to FIG. 4B, the switch control circuit 203A controls each switch (SW1 to SWt) according to the level of the first selection signal (TRAIN_ON) and the level of the output signal (MUXO2) of the fourth selection circuit 368. Control on or off.

FIG. 12 is a timing diagram explaining the operation of the memory system shown in FIG. 1.

Referring to FIGS. 1, 2, and 12, the first semiconductor die selection signal CS1 output from the memory controller 400 is a signal that controls the enable of the first semiconductor die 200, The second semiconductor die selection signal CS2 output from the memory controller 400 is a signal that controls enabling of the second semiconductor die 300.

RD(RANK1) is the first read command (CMD) for the first rank (RANK1), RD(RANK2) is the second read command (CMD) for the second rank (RANK2), and DES is a deselect command. ), WCK_t and WCK_c are differential write clock signals, and DQ[11:0] is read data (RDATA1 or RDATA2), and RDQS_t and RDQS_c are differential read data strobe signals. Ta0~Ta3, Tb0~Tb6, and Tc0~Tc4 represent the time points.

1, 2, and 4A to 12, the memory controller 400 outputs a first read command (RD(RANK1)) to the first semiconductor die 200 used as the first rank (RANK1). It is assumed that the second read command (RD(RANK2)) is then output to the second semiconductor die 300 used as the second rank (RANK2). WCK:CK is a 2:1 ratio or 4. It may be a :1 ratio, but in Figure 12, WCK and CK are displayed in a 2:1 ratio.

When a read operation is performed on the first semiconductor die 200, the first ODT control signal generation circuit 210 is activated before the first bit of the first read data RDATA1 is output, and the first ODT control signal generation circuit 210 is activated before the first bit of the first read data RDATA1 is output. ) generates a first ODT control signal (ODT_CT1) that is deactivated after the last bit of is output, and transmits the second semiconductor die 300 through the components (T11, T14, P1_1, TL1, 121, P2_1, T24, and T22). ) is transmitted to the second ODT circuit control circuit 350.

Accordingly, the first buffer 364 of the second ODT circuit control circuit 350 shown in FIG. 8 receives the first ODT control signal (ODT_CT1), buffers it, and sends the buffered first ODT control signal (ODT_CT1) to the third buffer ( 366), the second ODT circuit included in each of the input/output pads (UP1 and UP4) of the second semiconductor die 300 that does not perform a read operation while the first semiconductor die 200 performs a read operation ODT is set to the ODT read active state (ODT_READ).

As shown in FIG. 12, when the level of the corresponding ODT control signal (ODT_CT1 or ODT_CT2) is low, the input/output pads (LP1 and LP4, or UP1 and UP4) of the corresponding semiconductor dies 200 and 300 are included The ODT in the ODT circuit is set to the idle state (IDLE) or the ODT write state (ODT_WRITE).

Figure 13 is a table showing the ODT control results of the ODT circuit for each operating state for target and non-target.

Target rank (TARGET) refers to a rank on which a read operation or write operation is currently performed, and non-target rank (NON-TARGET) refers to a rank on which the read operation or write operation is not currently performed. Accordingly, when one of the semiconductor dies 200 and 300 is a target rank (TARGET), the other one of the semiconductor dies 200 and 300 is a non-target rank (NON-TARGET).

The ODT control signals (ODT_CT1 and ODT_CT2) transmitted from the target rank (TARGET) to the non-target rank (NON-TARGET) determine whether a read or write operation is performed on the target rank (TARGET). NON-TARGET) and performs the function of controlling the ODT of the ODT circuit included in each of the data input/output pads of the non-target rank (NON-TARGET).

As shown in FIGS. 12 and 13, in the idle state (IDLE), the ODT of the first ODT circuit included in each of the input/output pads (LP1 and LP4) of the first semiconductor die 200 corresponding to the target rank (TARGET) has a first resistance value (e.g., 40Ω) and is a second ODT circuit included in each of the input/output pads (UP1 and UP4) of the second semiconductor die 300 corresponding to the non-target rank (NON-TARGET). The ODT has a first resistance value (for example, 40Ω).

12 and 13, in the write operation state (WRITE) or the ODT write operation state (ODT_WRITE), the input/output pads (LP1 and LP4) of the first semiconductor die 200 corresponding to the target rank (TARGET) ) The ODT of the first ODT circuit included in each is in the OFF state, and the input/output pads (UP1 and UP4) of the second semiconductor die 300 corresponding to the non-target rank (NON-TARGET) are each included. The ODT of the second ODT circuit has a first resistance value (for example, 40Ω).

12 and 13, in the read operation state (READ) or the ODT read operation state (ODT_READ), the input/output pads (LP1 and LP4) of the first semiconductor die 200 corresponding to the target rank (TARGET) , the ODT of the first ODT circuit included in each (collectively DQ_OAD) is in the OFF state, and the input/output pads (UP1 and UP4) of the second semiconductor die 300 corresponding to the non-target rank (NON-TARGET) ) The ODT of the second ODT circuit included in each is in an off state (OFF) or has a second resistance value (for example, 240Ω).

As shown in FIGS. 12 and 13, the ODT read operation state (ODT_READ) for the second semiconductor die 300 is the second semiconductor die 300 even if the second semiconductor die 300 is a non-target rank (NON-TARGET). The die 300 turns off the ODT of the second ODT circuit included in each of the data input/output pads (UP1 and UP4, collectively DQ_OAD) according to the first ODT control signal (ODT_CT1) transmitted from the first semiconductor die 200 ( OFF) or controlling with the second resistance value (for example, 240Ω).

Conversely, while the read operation for the second semiconductor die 300 is performed, the second ODT control signal generation circuit 310 is activated before the first bit of the second read data RDATA2 is output and the second read data RDATA2 is not output. After the last bit of (RDATA2) is output, a second ODT control signal (ODT_CT2), which is deactivated, is generated to generate the first semiconductor die through the components (T21, T23, P2_2, TL2, 123, P1_2, T13, and T12). It is transmitted to the first ODT circuit control circuit 250 of 200.

Therefore, as described with reference to FIG. 8, the first buffer 364 of the first ODT circuit control circuit 250 receives the second ODT control signal (ODT_CT2), buffers it, and transmits the buffered second ODT control signal (ODT_CT2). Since the output is output to the third buffer 366, the ODT of the first ODT circuit included in each of the input/output pads LP1 and LP4 of the first semiconductor die 300 is set to the ODT read operation state (ODT_READ).

The ODT read operation state (ODT_READ) for the first semiconductor die 200 shown in FIGS. 12 and 13 is the first semiconductor die (ODT_READ) even if the first semiconductor die 200 is a non-target rank (NON-TARGET). 200) turns off the ODT of the first ODT circuit included in each of the data input/output pads (LP1 and LP4, collectively DQ_OAD) according to the second ODT control signal (ODT_CT2) transmitted from the second semiconductor die 300. Or, it means controlling with the second resistance value (for example, 240Ω).

Referring to FIGS. 4A, 4B, 8, 12, and 13, the ODT of the ODT circuit of each rank (TARGET and NON-TARGET) in each operating state (IDEL, WRITE, ODT_WRITE, READ, and ODT_READ) How to control (eg, 40Ω, OFF, and 240Ω) may be understood.

As shown in FIG. 12, when the level of the second ODT control signal ODT_CT2 is low in the normal operating mode, the first ODT circuit included in each of the input/output pads LP1 and LP4 of the first semiconductor die 200 ODT is set to idle state (IDLE) or ODT light running state (ODT_WRITE).

As described previously, the ODT control signal (ODT_CT1 or ODT_CT2) generated in the target rank (either RANK1 or RANK2) is transmitted to the non-target rank (non-target rank, the other one among RANK1 and RANK2) in an asynchronous manner. Accordingly, the non-target rank not only does not require separate decoding of command signals related to the read operation or the write operation, but also controls the ODT of the ODT circuit included in each of the data input/output pins included in the non-target rank. Since there is no need to generate a switch control signal on its own, power consumption of the non-target rank can be reduced.

Although, in FIG. 12, when a read operation is performed on the first semiconductor die 200 or the second semiconductor die 300, the activation and deactivation times of the first ODT control signal (ODT_CT1) or the second ODT control signal (ODT_CT2) are shown. Although the timing diagram is shown as an example, the technical idea of the present invention is that when a light operation is performed on the first semiconductor die 200 or the second semiconductor die 300, the first ODT control signal (ODT_CT1) or the second ODT control signal ( It can be applied to the timing diagram related to the activation and deactivation times of ODT_CT2).

For example, the timing of the first ODT control signal (ODT_CT1) is activated before the first bit of the first write data is transmitted to the first semiconductor die 200 and the last bit of the first write data is transmitted to the first semiconductor die ( 200) and can then be adjusted to be deactivated. In addition, the timing of the second ODT control signal (ODT_CT2) is activated before the first bit of the second write data is transmitted to the second semiconductor die 300, and the last bit of the second write data is transmitted to the second semiconductor die 300. It can be adjusted to be deactivated after being transferred to .

FIG. 14 is a block diagram of a data processing system including the memory system shown in FIG. 1. 1 and 14, the data processing system 500A may be a System On Chip (SoC), the CPU 510A includes a memory controller 400, and the memory controller 400 operation can be controlled. Depending on embodiments, the memory controller 400 may be placed outside the CPU 510A.

FIG. 15 is a block diagram of a data processing system including the memory system shown in FIG. 1. 1 and 15, the data processing system 501 includes a SoC (500B) and a memory device 110, and the SoC (500B) includes a CPU (510B) and a memory controller 400, and the memory Device 110 may be placed external to SoC 500B.

The CPUs 510A and 510B shown in FIGS. 14 and 15 may be processors or application processors, and the data processing system 500A or 501 may be included inside a mobile device, and the mobile device may be a smart This could be a phone, laptop computer, wearable computer, Internet of Things (IoT) device, or drone.

The present invention has been described with reference to the embodiments shown in the drawings, but these are merely illustrative, and those skilled in the art will understand that various modifications and other equivalent embodiments are possible therefrom. Therefore, the true scope of technical protection of the present invention should be determined by the technical spirit of the attached registration claims.

100: memory system
200: First semiconductor die
P1_1: 1st pin
P1_2: 2nd pin
210: 1st ODT control signal generation circuit
250: 1st ODT circuit control circuit
270: First logic circuit and memory cell array
280: First connection circuit
300: Second semiconductor die
P2_1: 3rd pin
P2_2: 4th pin
310: 2nd ODT control signal generation circuit
350: 2nd ODT circuit control circuit
370: Second logic circuit and memory cell array
880: Second connection circuit

Claims (20)

In a semiconductor die,
A first pin for outputting a first ODT control signal for controlling the ODT of second ODT (On-die termination) circuits included in the second semiconductor die to the second semiconductor die; and
A semiconductor die including a second pin that receives a second ODT control signal output from the second semiconductor die to control the ODT of the first ODT circuits included in the semiconductor die. According to paragraph 1,
The first bit is activated before the first bit of read data corresponding to the burst length is output from the first semiconductor die performing the first read operation and is deactivated after the last bit of the read data is output. A semiconductor die further comprising an ODT control signal generation circuit that generates a 1ODT control signal and outputs it to the first pin. According to paragraph 2,
data input/output pads; and
It further includes an ODT circuit control circuit that controls the ODT of each of the first ODT circuits included in each of the data input/output pads according to the second ODT control signal transmitted from the second semiconductor die performing a second lead operation. semiconductor die. According to paragraph 3,
a connection circuit for transmitting the first ODT control signal generated by the ODT control signal generation circuit to the first pin and transmitting the second ODT control signal received through the second pin to the ODT circuit control circuit; A semiconductor die containing. first semiconductor die; and
Includes a second semiconductor die,
The first semiconductor die is,
a first pin for outputting a first ODT control signal for controlling ODTs of second ODT (On-die termination) circuits included in the second semiconductor die to the second semiconductor die; and
A multi-chip package including a second pin that receives a second ODT control signal output from the second semiconductor die to control the ODT of the first ODT circuits included in the first semiconductor die. The method of claim 5, wherein the first semiconductor die is:
The first ODT control signal that is activated before the first bit of read data corresponding to the burst length is output from the first semiconductor die performing the first read operation and is deactivated after the last bit of the read data is output. A multi-chip package further comprising an ODT control signal generation circuit that generates and outputs the ODT control signal to the first pin. The method of claim 6, wherein the first semiconductor die is:
data input/output pads; and
It further includes an ODT circuit control circuit that controls the ODT of each of the first ODT circuits included in each of the data input/output pads according to the second ODT control signal transmitted from the second semiconductor die performing a second lead operation. multi-chip package. The method of claim 7, wherein the first semiconductor die is:
a connection circuit for transmitting the first ODT control signal generated by the ODT control signal generation circuit to the first pin and transmitting the second ODT control signal received through the second pin to the ODT circuit control circuit; Multi-chip package containing. The method of claim 5, wherein the second semiconductor die is:
a third pin that receives the first ODT control signal output from the first semiconductor die; and
A multi-chip package including a fourth pin that outputs the second ODT control signal to the first semiconductor die. According to clause 9,
A printed circuit board including a first PCB pin and a second PCB pin;
a first transmission line connecting the first pin, the first PCB pin, and the third pin; and
A multi-chip package further comprising a second transmission line connecting the second pin, the second PCB pin, and the fourth pin. The method of claim 9, wherein the second semiconductor die is:
The second ODT control signal is activated before the first bit of read data corresponding to the burst length is output from the second semiconductor die performing the first read operation and is deactivated after the last bit of the read data is output. A multi-chip package further comprising an ODT control signal generation circuit that generates and outputs to the fourth pin. 12. The method of claim 11, wherein the second semiconductor die is:
data input/output pads; and
It further includes an ODT circuit control circuit that controls the ODT of each of the second ODT circuits included in each of the data input/output pads according to the first ODT control signal transmitted from the first semiconductor die performing a second lead operation. multi-chip package. 13. The method of claim 12, wherein the second semiconductor die is:
a connection circuit for transmitting the second ODT control signal generated by the ODT control signal generation circuit to the fourth pin and transmitting the first ODT control signal received through the third pin to the ODT circuit control circuit; Multi-chip package containing: A multi-chip package including a first semiconductor die and a second semiconductor die; and
Comprising a memory controller that controls the operation of the multi-chip package,
The first semiconductor die is,
a first pin for outputting a first ODT control signal for controlling ODTs of second ODT (On-die termination) circuits included in the second semiconductor die to the second semiconductor die; and
A memory system comprising a second pin that receives a second ODT control signal output from the second semiconductor die to control the ODT of the first ODT circuits included in the first semiconductor die. 15. The method of claim 14, wherein the second semiconductor die is:
a third pin that receives the first ODT control signal output from the first semiconductor die; and
A memory system including a fourth pin that outputs the second ODT control signal to the first semiconductor die. The method of claim 15, wherein the multi-chip package:
A printed circuit board including a first PCB pin and a second PCB pin;
a first transmission line connecting the first pin, the first PCB pin, and the third pin; and
A memory system further comprising a second transmission line connecting the second pin, the second PCB pin, and the fourth pin. According to clause 15,
When a second lead operation is not performed on the second semiconductor die while a first lead operation is performed on the first semiconductor die,
The first semiconductor die is,
The first ODT control signal, which is activated before the first bit of read data corresponding to the burst length is output from the first semiconductor die and is deactivated after the last bit of read data is output, is generated and transmitted to the first pin. A memory system further comprising an ODT control signal generation circuit that outputs. 18. The method of claim 17, wherein the second semiconductor die is:
data input/output pads; and
A memory further comprising an ODT circuit control circuit that controls the ODT of each of the second ODT circuits included in each of the data input/output pads to an ODT read operation state according to the first ODT control signal received through the third pin. system. According to clause 15,
When a first lead operation is not performed on the first semiconductor die while a second lead operation is performed on the second semiconductor die,
The second semiconductor die is,
The 2ODT control signal, which is activated before the first bit of read data corresponding to the burst length is output from the second semiconductor die and is deactivated after the last bit of the read data is output, is transmitted to the fourth pin. A memory system further comprising an ODT control signal generation circuit that outputs. 20. The method of claim 19, wherein the first semiconductor die is:
data input/output pads; and
A memory further comprising an ODT circuit control circuit that controls the ODT of each of the first ODT circuits included in each of the data input/output pads to an ODT read operation state according to the second ODT control signal received through the second pin. system.

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