KR20230147669A - Wafer for uniform CVD growth of graphene and manufacturing method thereof - Google Patents

Abstract

Wafer for uniform CVD growth of graphene and manufacturing method thereof
A wafer is provided for uniform CVD growth of graphene at temperatures exceeding 700°C, the wafer comprising a planar silicon substrate, an insulating layer provided across the silicon substrate, and a barrier layer provided across the insulating layer, in that order. The insulating layer is a silicon nitride and/or aluminum nitride layer, and the barrier layer has a constant thickness of 50 nm or less and provides a growth surface for uniform CVD growth of graphene.

Description

Wafer for uniform CVD growth of graphene and manufacturing method thereof

The present invention provides a wafer for CVD growth of graphene. More specifically, the present invention provides wafers suitable for growing uniform graphene at temperatures above 700°C. The invention also relates to a laminate comprising at least a portion of the wafer and a graphene layer formed thereon, particularly by CVD at a temperature above 700°C. The present invention further provides a method of manufacturing the wafer and the laminate.

Two-dimensional materials, of which graphene is one of the most prominent, are currently the focus of strong research. Graphene in particular has been shown to demonstrate remarkable properties both theoretically and, in recent years, in practice. Graphene's electronic properties are particularly noteworthy and have enabled the production of electronic devices that are significantly improved compared to non-graphene-based devices. However, there remains a need in the art for wafers, also known as substrates, that facilitate the production of high quality, uniform graphene. In particular, there remains a need in the microelectronics industry for wafers suitable for use in well-established semiconductor fabrication plants that can be used to grow graphene and subsequently fabricate graphene-based electronic devices on an industrial scale.

A semiconductor fabrication plant (also known as a "fab") is a factory where devices such as integrated circuits are manufactured. The cost of building and equipping a fab typically runs into the billions of dollars. In 2020, one fab was reported to cost over $17 billion. Each fab is kitted out for a specific manufacturing method and there is very little room for introducing new technologies or methodologies. Typically, during the historical development of silicon-based devices, new fabs were built with each technological development to enable the use of these new technologies. Therefore, worldwide, fabs are built primarily to manufacture electronic devices from silicon wafers.

It is known in the art that graphene can be synthesized, manufactured, and formed directly on the non-metallic surface of a substrate. These include silicon and sapphire, along with other more exotic surfaces such as group III-V semiconductors. The present inventors have found that the most effective method for producing high quality graphene, especially directly on such non-metallic surfaces, is disclosed in WO 2017/029470. The method of WO 2017/029470 is ideally carried out using a MOCVD reactor. MOCVD stands for metal-organic chemical vapor deposition due to its origin for preparing semiconductor materials such as AlN and GaN from metal-organic precursors such as AlMe ₃ (TMAl) and GaMe ₃ (TMGa), while these devices and reactors are also used for the preparation of semiconductor materials such as AlN and GaN from metal-organic precursors such as AlMe 3 (TMAl) and GaMe 3 (TMGa). It is well known and understood by those skilled in the art that they are suitable for use together. MOCVD can be used synonymously with metal organic vapor phase epitaxy (MOVPE).

There is a need to use silicon wafers to meet the stringent requirements of existing semiconductor fabrication plants, but at the same time there is a need to grow graphene, an excellent conductor, directly on the insulating surface for many electronic devices. It is known in the art that silicon wafers can be provided with an insulating surface, for example silicon with a silicon oxide or silicon nitride surface (i.e. Si/SiO ₂ or Si/SiN _x wafers are well known).

US 2005/142715 discloses a semiconductor device comprising a silicon substrate, a silicon oxide layer formed on the surface of the silicon substrate and a first oxide layer having a higher dielectric constant than the silicon oxide formed on the silicon oxide layer. This disclosure makes no mention of graphene growth.

US 2011/175060 discloses a substrate on which a graphene film has been grown, comprising a base substrate, a patterned aluminum oxide film and a graphene film preferentially grown on the patterned aluminum oxide film, the base substrate comprising silicon oxide. It may be a single crystal silicon substrate on which a film is formed.

US 2001/029092 relates to a method of forming a gate structure and makes no mention of graphene growth. The method includes thermally growing a thin silicon dioxide layer on top of the semiconductor device by using wet H ₂ /O ₂ or dry O ₂ and then doping a dopant in-situ to form an aluminum oxide layer on top of the semiconductor device. It includes forming a layer.

The present inventors bridge the gap between the need for silicon-based wafers and insulating surfaces for graphene growth to facilitate the adoption of graphene in industrial electronic device manufacturing, especially commercial fabs, and provide improved wafers and methods for manufacturing such wafers. Efforts have been made to develop both. Accordingly, the present invention overcomes or at least substantially reduces various problems associated with the prior art, or at least provides a commercially useful alternative.

Accordingly, in a first aspect, a wafer is provided for uniform CVD growth of graphene at temperatures above 700° C., the wafer comprising:

planar silicon substrate,

an insulating layer provided across the silicon substrate; and

comprising, in order, a barrier layer provided throughout the insulating layer,

The insulating layer is a silicon nitride and/or aluminum nitride layer,

The barrier layer has a constant thickness of 50 nm or less and provides a growth surface for uniform CVD growth of graphene.

The present disclosure will now be further described. In the passages below, different aspects/implementations of the present disclosure are defined in more detail. Each aspect/embodiment so defined may be combined with any other aspect/embodiment or aspects/implementations unless explicitly indicated to the contrary. In particular, any feature indicated as being preferred or advantageous may be combined with any other feature or features indicated as being preferred or advantageous.

The present invention relates to wafers. Wafer is a standard term in the art and is equivalent to substrate. In this context, the wafer comprises a number of distinct layers (i.e. a silicon layer, an insulating layer and a barrier layer). Wafers are used for fabrication and manufacturing of electronic devices. Specifically, the wafer of the present invention is based on silicon, making the wafer suitable for use in existing fabs. In other words, the wafer of the present invention includes a silicon substrate. The silicon substrate has a substantially constant thickness and is planar composed of a single layer of elemental silicon. However, silicon can be doped with small amounts of other elements such as boron, nitrogen and phosphorus, as is well known in the art. When doped, the semiconductor substrate may be p-type or n-type doped. Preferably, the doped semiconductor substrate has a dopant concentration greater than 10 ¹⁵ cm ^-3 , more preferably greater than 10 ¹⁶ cm ^-3 and/or less than 10 ²⁰ cm ^-3 , preferably 10 ¹⁹ cm ^-3 . The most preferred range is 10 ¹⁶ cm ^-3 to 10 ¹⁸ cm ^-3 . Silicon substrates may also include CMOS substrates, which are silicon-based substrates that include various additional layers or circuits embedded therein.

The wafer is suitable for the growth of uniform graphene by CVD at temperatures exceeding 700°C. Typically, graphene is grown at temperatures exceeding 700°C when using CVD to achieve high quality and uniformity, so wafers suitable for this subsequent processing are needed.

The present inventors have found that when using known hybrid wafers suitable for fabs such as Si/SiO ₂ , the conditions used to grow graphene on the insulating side, especially high temperatures exceeding 700° C., result in damage to the insulating layer, resulting in its failure as an insulator. Reduces function. This effect is naturally more pronounced at the higher preferred growth temperatures, such that wafers of the present invention are preferably used at higher temperatures above 1000°C, such as above 800°C, above 900°C, and even more preferably above 1100°C. It is suitable for

The wafer of the present invention solves this problem through the presence of both an insulating layer and a barrier layer as described herein. Specifically, the wafer includes a planar silicon substrate provided with an insulating layer throughout the silicon substrate. Additionally, the wafer includes these three layers so that an insulating layer is sandwiched between the planar silicon substrate and the barrier layer, so that the barrier layer is spread across the insulating layer so that graphene can be grown directly by CVD in the barrier layer. provided throughout. As a result, there are no intervening layers between the layers of the wafer or laminate as described herein. Accordingly, a layer may therefore be described as being directly on the associated adjacent layer.

The insulating layer may not be particularly limited in some aspects. Therefore, the conductivity of the insulating layer is less than that of silicon, a semiconductor. For example, the conductivity of the insulator may be less than 10 ^-5 S/cm, preferably less than 10 ^-6 S/cm. Alternatively, it can be measured against the material band gap; Silicon has a band gap of about 1.1 eV to about 1.6 eV, while the band gap of insulators is much larger, typically greater than 3 eV, preferably greater than 4 eV.

According to a first aspect, the insulating layer is silicon nitride and/or aluminum nitride. Such silicon wafers are well known and commercially available. Equally, an insulating layer can be formed over the surface of the silicon substrate using conventional techniques. The thickness of the insulating layer is not particularly limited, and a wide range of thicknesses are available, for example in Si/SiO ₂ and Si/SiN _x wafers. The thickness may preferably be 10 nm to 100 μm, such as 20 nm to 10 μm. More preferably, the thickness is 50 to 500 nm, and in some embodiments may be 100 to 250 nm or 100 to 200 nm. The advantage of the present invention is that the relatively thin barrier layer is capable of combining graphene and silicon without being dependent on the bulk of the insulating layer (e.g. 20 nm to 500 nm, 20 nm to 250 nm or preferably 20 nm to 200 nm). This is most noticeable for the by far thinner insulating layers as they are sufficient to provide adequate insulation between the substrates. That is, there is an unexpected synergy between the combination of insulating and barrier layers as described herein, preferably formed by ALD.

In an alternative embodiment, the insulating layer is silicon oxide, and descriptions referring to silicon nitride and aluminum nitride may be interpreted to apply equally to silicon oxide. The inventors have discovered additional unexpected advantages when using silicon and/or aluminum nitride, but in certain embodiments, those described herein with thin barrier layers (e.g., 5 nm or less), especially insulating Silicon oxide insulating layers were also advantageous if the layer was at least 10 nm thick. Combinations of silicon oxide and silicon nitride and/or aluminum nitride may be desirable in silicon photonics in certain embodiments, for example for the production of electro-optic modulators, wherein the silicon nitride can be used to form waveguides within the silicon oxide (thereby forming regions of silicon nitride and silicon oxide). , i.e. providing an insulating layer with a different surface area on which a barrier layer is provided as opposed to the layer) or the insulating layer may consist of a layer of nitride on a layer of silicon oxide.

The wafer further includes a barrier layer provided throughout the insulating layer; The barrier layer is that of the wafer, which provides a growth surface suitable for uniform CVD growth of graphene. The barrier layer may also be referred to as an additional insulating layer, but is nevertheless separate from the insulating layer of the silicon substrate. As will be understood, the opposite side of the barrier layer is the surface that directly contacts and spans the surface of the underlying insulating layer.

Additionally, the barrier layer is relatively thin, at least with respect to the thickness of a standard silicon substrate, with a constant thickness of less than 50 nm. As described herein, the thickness of the barrier layer can be at least 1 nm, or at least 2 nm. Accordingly, in some embodiments, the thickness of the barrier layer may be 1 to 10 nm, especially for aluminum nitride insulating layers, preferably 1 to 5 nm, 2 to 10 nm or even 2 to 5 nm. In an exemplary embodiment, a silicon nitride insulating layer, for example having a thickness of 10 to 50 nm, is combined with a barrier layer having a thickness of 10 to 50 nm, preferably 30 to 50 nm. In another exemplary embodiment, an aluminum nitride insulating layer having a thickness of, for example, 100 to 250 nm is combined with a barrier layer having a thickness of 2 to 5 nm.

The barrier layer is made of metal oxide Al ₂ O ₃ , HfO ₂ , MgAl ₂ O ₄ , MgO, ZnO, Ga ₂ O ₃ , aluminum gallium oxide (AGO), TiO ₂ , SrTiO ₃ , LaAlO ₃ , Ta ₂ O ₅ , LiNbO ₃ , Y ₂ O ₃ , Y-stabilized ZrO ₂ (YSZ), ZrO ₂ , Y ₃ Al ₅ O ₁₂ (YAG), CeO ₂ and/or h-BN, GaN, and/or SiC and/or CaF ₂ It can be any one or more. Preferably, the barrier layer is Al ₂ O ₃ , HfO ₂ , MgAl ₂ O ₄ , MgO, Ga ₂ O ₃ , AGO, Ta ₂ O ₅ , Y ₂ O ₃ , Y-stabilized ZrO ₂ (YSZ), ZrO ₂ , Y ₃ Al ₅ O ₁₂ (YAG), CeO ₂ and/or h-BN and/or CaF ₂ , more preferably alumina, yttria, zirconia and/or YSZ, most preferably alumina (and some embodiments For example, alumina and/or hafnium oxide). All passages herein in the description of a barrier layer referring to alumina and/or hafnium oxide should be interpreted as applying equally to barrier layers formed from any of these additional materials, and in some embodiments, include alumina and/or hafnium oxide. Can be combined. Alumina and hafnium oxide may be referred to as Al ₂ O ₃ or HfO ₂ , respectively, although the exact stoichiometry of these and other materials disclosed herein may be referred to as normal boundaries (and thus, for example, as AlO _x ). It must be understood that things can change within.

Preferably, the barrier layer consists of one material, most preferably alumina. However, in some embodiments, the barrier layer may include multiple insulating layers, for example, the barrier layer consists of one or more layers of alumina and one or more hafnium oxide layers (the total thickness of the barrier layer is described herein). with a constant thickness of less than 50 nm as shown). Accordingly, the barrier layer may be a nanoamine such as Al ₂ O ₃ -HfO ₂ nanoamine.

Without wishing to be bound by theory, the present inventors believe that when growing graphene at temperatures above 1000°C, especially above 700°C, such as above 1100°C, the insulating layer may be damaged. Typically, graphene is grown using a hydrocarbon precursor, or an organic compound containing at least carbon and hydrogen and/or a carrier gas containing hydrogen. The presence of hydrogen and radical hydrocarbon species in the reaction chamber during graphene growth can etch the insulating layer, which has been found to reduce the function of the insulating layer as an effective insulator. The etching then creates channels that can be filled with conductive carbon during graphene growth, providing a path for current to leak into the underlying silicon. The present inventors have discovered that a barrier layer on the surface of an insulating layer can protect its insulating properties. The inventors were particularly surprised that this was true even for the small thicknesses described herein.

The inventors have also discovered that silicon nitride and aluminum nitride offer additional advantages over other insulating layers such as silicon oxide for wafers to be used for CVD growth of graphene at temperatures above 700°C, especially above 1000°C or above 1100°C. . At this relatively high growth temperature, we found that the silicon oxide surface can react with the silicon substrate to produce volatile species. For example, without wishing to be bound by theory, an insulating silicon dioxide layer can be used to support silicon oxide gas (e.g., SiO), especially in the presence of hydrogen, which may be liberated or otherwise incorporated as an inert carrier gas during graphene synthesis. It can be liberated. The formation of these gases was found to lead to damage in the insulating layer, which would otherwise fill with conductive carbon, providing a path for current leakage from the graphene to the underlying silicon substrate. Advantageously, the present invention avoids this risk through the use of silicon and/or aluminum nitride insulating layers.

The present inventors also investigated whether a barrier layer could be provided directly on the silicon substrate. However, we believe that lattice mismatch between the silicon and the desired barrier layer is likely responsible for defects/dislocations at the interface that can diffuse through the layer, thereby providing a path for the conductive carbon to charge during graphene growth. It was discovered that by providing again, graphene does not provide an effective insulator.

Alumina and hafnium oxide are common materials for the formation of dielectric layers in electronic device fabrication. These layers are ubiquitous in electronic devices and are known to be a suitable material for deposition on graphene as a protective layer or in the formation of graphene transistors, for example in graphene Hall sensors. The barrier layer can be grown using ALD (atomic layer deposition). Other suitable techniques include physical vapor deposition methods such as sputtering, e-beam and thermal evaporation, and chemical methods such as MOCVD. ALD is a technique known in the art and involves the reaction of at least two suitable precursors in a sequential, self-limiting manner. Repeated cycles of distinct precursors enable the growth of thin barrier layers due to the layer-by-layer growth mechanism that makes ALD particularly advantageous.

Despite the advantages provided by ALD, the inventors have found that thicker barrier layers, such as thicknesses greater than 50 nm, provide poor quality graphene. This was surprising in itself, since in much of our previous work we had used at least sapphire substrates (Al ₂ O ₃ ) to provide a non-metallic surface suitable for the growth of exceptionally high quality graphene. The thicker barrier layer was found to have a surface roughness greater than that of the thinner barrier layer, which then propagated as defects in any graphene subsequently formed thereon. The inventors have shown that a barrier layer as thin as less than 50 nm is sufficient to protect the insulating properties of the insulating layer and is further essential to facilitate the growth of graphene thereon at temperatures above 700°C, more particularly above 1100°C. I was surprised to find it.

Without wishing to be bound by theory, the inventors believe that by reducing the thickness of the barrier layer grown by ALD, the variation between different crystal sizes during the growth of the barrier layer is reduced, resulting from adjacent crystals of polycrystalline alumina or hafnium oxide. I believe that the intensity of illumination has been reduced. However, a balance remains in providing barrier layers containing larger crystal sizes. In general, larger crystal sizes can be provided by the growth of thicker barrier layers, which are also believed to affect graphene quality.

Accordingly, in a second aspect of the present invention, a method is provided for making wafers for uniform CVD growth of graphene at temperatures above 700° C., comprising:

providing a planar silicon substrate having an insulating layer provided across its surface;

forming a barrier layer across the insulating layer by ALD using water or ozone as an oxidizing agent precursor,

The insulating layer is a silicon nitride and/or aluminum nitride layer,

The barrier layer has a constant thickness of less than 50 nm and provides a growth surface for uniform CVD growth of graphene at temperatures above 700°C.

Preferably, the method is for the production of wafers according to the first aspect of the invention.

As described herein, the insulating layer may be comprised of silicon nitride and/or aluminum nitride. Accordingly, the insulating layer does not contain silicon oxide and therefore does not contain any native surface oxide. In one embodiment of the method, the first step of providing a planar silicon substrate with an insulating layer includes heating the silicon substrate with native oxide in a reaction chamber to a temperature above 900° C. to remove the native oxide present on the silicon substrate. Heating with; and contacting the surface with hydrogen gas thereby removing the native oxide. This method is particularly advantageous because it can be carried out in-situ in the reaction chamber before the formation of the insulating layer. It is fast, reliable and effective in removing natural oxides.

In this embodiment, the hydrogen gas preferably consists of hydrogen. In other words, hydrogen is supplied only with inevitable impurities. 99.99% purity hydrogen can be easily obtained. Hydrogen can be further purified by passing it through a suitable purifier that removes trace organics, water and oxygen from the gas stream. A high purity source of hydrogen is required to ensure that there are no undesirable side reactions.

In an alternative embodiment, the first step includes treating the silicon substrate with hydrofluoric acid thereby removing native oxide from the growth surface and introducing the silicon substrate into a reaction chamber for nitride formation. This method is less desirable because silicon is reactive and precautions must then be taken before adding the substrate to the reaction chamber. However, the use of hydrofluoric acid or equivalent serves to rapidly remove oxides without requiring high temperature processing steps.

In either case, the silicon nitride and/or aluminum nitride layer can be formed using standard growth or deposition techniques.

The method includes forming a barrier layer over the insulating layer by ALD using water or ozone as a precursor and specifically as a source of oxygen atoms. The inventors have found that when using water to form a barrier layer, thinner layers, such as 1 to 50 nm, 1 to 10 nm, or 2 to 5 nm, are particularly preferred. Without wishing to be bound by theory, the inventors have found that such a thin layer significantly reduces the H ₂ pressure building ability. When heated to the temperature required for graphene growth, release of hydrogen gas resulted in blistering of the barrier layer surface. Roughening of the barrier layer damaged the quality of graphene subsequently formed on it. When using ozone as a precursor, the thickness of the barrier layer is preferably 2 to 40 nm, preferably 5 to 20 nm, due to the slightly poorer insulating properties observed when using ozone as a precursor.

Therefore, the step of forming the barrier layer is preferably performed using water as a precursor. Similarly, the wafer of the invention comprises a barrier layer that can be, or is preferably obtained, by ALD, preferably using water as a precursor.

Suitable precursors providing the necessary aluminum or hafnium atoms for alumina or hafnium oxide are well known, commercially available and are not particularly limited. Metal halides such as metal chlorides (eg, AlCl ₃ and HfCl ₄ ) may be used. Alternatively, metal amides, metal alkoxides or organometallic precursors may be used. Hafnium precursors include, for example, tetrakis(dimethylamido)hafnium(IV), tetrakis(diethylamido)hafnium(IV), hafnium(IV) tert -butoxide and dimethylbis(cyclopentadienyl)hafnium( IV). Preferably, the barrier layer is alumina, and preferably the additional precursor for ALD is trimethylaluminum, tris(dimethylamido)aluminum, aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedio) trialkyl aluminum or trialkoxide aluminum, such as aluminum tris(acetylacetonate) or aluminum tris(acetylacetonate). Equivalent precursors suitable for other barrier layers are also known.

The deposition temperature when forming the barrier layer may be any conventional temperature known in the art. Typically, deposition temperatures range from 40° C. to 300° C., and the inventors have found that temperatures above 100° C. are preferred and provide better quality barrier layers.

In another aspect of the invention, comprising providing a wafer (or a portion thereof after dicing) as described herein and forming a graphene layer on the growth side of the barrier layer by CVD at a temperature greater than 700° C. A method of doing so and a method of manufacturing a laminate are provided.

Accordingly, a laminate comprising at least a portion of a wafer as described herein and a graphene layer formed on the growth side of the barrier layer by CVD at a temperature above 700° C. is also provided.

As will be appreciated, the wafer may be diced using conventional techniques such as sawing or laser cutting to provide a plurality of diced wafers. A graphene layer can then be formed on the diced wafer by CVD as described herein to provide a laminate comprising a portion of the wafer.

Preferably, the graphene layer is formed by the CVD method described below before wafer dicing. For example, the graphene layer is formed by CVD on a wafer having a diameter greater than at least 5 cm (2 inches). The plurality of electronic devices can then be formed using standard microfabrication techniques, whereby the plurality of devices share at least a common silicon substrate. The plurality of devices can then be separated by wafer dicing to provide electronic devices each comprising a laminate containing a portion of the original wafer.

The present invention also provides an electronic device comprising a laminate as described herein. An electronic device is a device that can then be installed into an electrical or electronic circuit, typically by wire bonding to additional circuitry, or by other methods known in the art, such as soldering using "flip chip" style solder bumps. So, an electronic device is a device that is installed in an electronic circuit and operates when an electric current is provided to the device. Preferred electronic devices are sensors such as Hall-sensors, current sensors and biosensors, modulators such as electro-optical modulators, and transistors. The invention also provides for the use of the laminate for forming electronic devices. In some implementations, the silicon substrate of the wafer of the laminate can be removed to provide an electronic device without a silicon substrate. This can be achieved through grinding or etching the silicon in a process such as described in British Patent Application No. 2102218.1, the contents of which are incorporated herein by reference.

Both the laminate and the method of making the laminate require a graphene layer to be formed by CVD on the growth side of the barrier layer of the wafer, with the graphene grown by CVD at a temperature exceeding 700°C, preferably exceeding 1000°C. and the wafer is suitable for this graphene growth by CVD at these temperatures.

Preferably, the graphene is grown by CVD according to the disclosure of WO 2017/029470, the content of which is incorporated herein by reference. This publication discloses a method of producing graphene; Primarily, they rely on heating a substrate (e.g., a wafer as described herein) held within a reaction chamber to a temperature that is within the decomposition range of the carbon-based precursor for graphene growth, with the precursor reacting in the gas phase. To establish a sufficiently steep thermal gradient extending away from the substrate surface toward the point where the precursor enters the reaction chamber such that the fraction is low enough to form graphene from the carbon released from the decomposed precursor, a relatively cold inlet is used. The precursor is introduced into the reaction chamber through. Preferably, the device comprises a showerhead with a plurality of precursor entry points or inlets, the separation from the substrate surface can vary and is preferably less than 100 mm.

The formation of graphene is synonymous with the synthesis, fabrication, production and growth of graphene. Graphene is a very well-known two-dimensional material that refers to an allotrope of carbon containing a single layer of carbon atoms in a hexagonal lattice. As used herein, graphene refers to one or more layers of graphene. Accordingly, some aspects of the invention involve the formation of single-layer graphene as well as multilayer graphene (which may be referred to as graphene layer structures). Preferably, graphene refers to a graphene layer structure having 1 to 10 monolayers of graphene. In many subsequent applications for laminates, a single layer of graphene on a wafer is particularly desirable. Therefore, the formed graphene is preferably single-layer graphene. Nevertheless, for other applications multilayer graphene is preferred, and two or three layers of graphene may be preferred.

The method of making the laminate includes forming graphene by CVD, which takes place in a CVD reaction chamber. This step of forming graphene will typically involve introducing gaseous precursors and/or precursors suspended in gases into a CVD reaction chamber. CVD generally refers to a variety of chemical vapor deposition techniques, each involving vacuum deposition to produce thin-film materials, such as two-dimensional crystalline materials such as graphene. The volatile precursor, either in the gas phase or suspended in a gas, decomposes to liberate the species needed to form the desired material, carbon in the case of graphene. As will be appreciated, the wafers are equally, preferably, suitable for the growth of uniform graphene according to the preferred CVD methods described herein.

Preferably, the method includes forming graphene by thermal CVD such that decomposition is a result of heating the precursor. Preferably, the CVD reaction chamber used is a cold wall reaction chamber where the heater coupled to the substrate is the only heat source for the chamber.

In a particularly preferred embodiment, the CVD reaction chamber includes a closed coupled showerhead having a plurality of precursor entry points or an array of precursor entry points. Such CVD devices comprising closed coupled showerheads may be known for use in MOCVD processes. Accordingly, the method may alternatively be referred to as being carried out using a MOCVD reactor comprising a closed coupled showerhead. In either case, the showerhead is preferably configured to provide a minimum separation of less than 100 mm, more preferably less than 25 mm, and even more preferably less than 10 mm between the surface of the wafer and the plurality of precursor entry points. As understood, constant separation means that the minimum separation between the surface of the wafer and each precursor entry point is substantially the same. Minimum separation refers to the minimum separation between the precursor entry point and the wafer surface. Accordingly, this embodiment includes a “vertical” arrangement in which the plane containing the precursor entry point is substantially parallel to the plane of the wafer surface, i.e., the growth plane of the barrier layer.

The point of precursor entry into the reaction chamber is preferably cooled. The inlet, or showerhead, when used, is preferably actively cooled by an external coolant, such as water, to maintain a relatively cool temperature of the precursor entry points as they pass through the plurality of precursor entry points and enter the reaction chamber. The temperature of the precursor is lower than 100°C, preferably lower than 50°C.

Preferably, the combination of cooling the precursor entry points combined with heating the wafer to a temperature exceeding 700° C. with a sufficiently small separation between the wafer surface and the plurality of precursor entry points and the extent of decomposition of the precursors results in the substrate surface extends from the precursor entry point to create a sufficiently steep thermal gradient to enable graphene formation at the substrate surface. As disclosed in WO 2017/029470, very steep thermal gradients can be used to facilitate the formation of high quality and uniform graphene, preferably directly on non-metallic substrates across the entire surface of the substrate. Wafers of the present invention may have a diameter of at least 5 cm (2 inches), 15 cm (6 inches), or 30 cm (12 inches). Particularly suitable devices for the methods described herein include Aixtron® Close-Coupled Showerhead® reactors and Veeco® TurboDisk reactors.

Consequently, in a particularly preferred embodiment where the formation of graphene comprises using a method as disclosed in WO 2017/029470, the formation of graphene is:

Providing a wafer comprising a barrier layer having a growth surface on a heated susceptor in a closed coupled reactor chamber, wherein in use the inlets are distributed throughout the wafer and having a plurality of cooled inlets arranged to have separation);

Cooling the inlet to below 100°C;

Introducing a vapor phase precursor and/or a precursor suspended in a gas into the CVD reaction chamber through an inlet to decompose the precursor and form graphene on the growth side of the barrier layer of the wafer; and

Heating the susceptor to a temperature of at least 50° C. above the decomposition temperature of the precursor, thereby providing a thermal gradient between the inlet and the growth surface sufficiently steep to allow the formation of graphene from the carbon released from the decomposed precursor. Includes,

The constant separation is less than 100 mm, preferably less than 25 mm and even more preferably less than 10 mm.

In a preferred embodiment of the invention, the precursor is introduced into the CVD reaction chamber as a mixture with a carrier gas. Carrier gases are well known in the art and may also be referred to as diluent gases or diluents. Carrier gases typically include inert gases such as inert gases and, in the case of graphene growth, hydrogen gas. Accordingly, the carrier gas is preferably one or more of hydrogen (H ₂ ), nitrogen (N ₂ ), helium (He), and argon (Ar). More preferably, the carrier gas is one of nitrogen, helium and argon or the carrier gas is a mixture of hydrogen and one of nitrogen, helium and argon.

In another aspect of the invention, a wafer is provided for uniform CVD growth of graphene at temperatures above 700° C., the wafer comprising:

planar silicon substrate,

an insulating layer provided across the silicon substrate; and

comprising, in order, a barrier layer provided throughout the insulating layer,

The barrier layer is an alumina and/or hafnium oxide layer, has a constant thickness of 20 nm or less, and provides a growth surface for uniform CVD growth of graphene.

Likewise, in another aspect of the invention, a method is provided for making wafers for uniform CVD growth of graphene at temperatures above 700° C., comprising:

providing a planar silicon substrate having an insulating layer provided across its surface;

forming a barrier layer over the insulating layer by ALD using water or ozone as a precursor,

The barrier layer is a layer of alumina and/or hafnium oxide, has a constant thickness of less than 20 nm, and provides a growth surface for uniform CVD growth of graphene at temperatures above 700° C.; and a method of making a laminate, comprising providing at least a portion of a wafer and forming a graphene layer on the growth side of the barrier layer by CVD at a temperature above 700° C. with the laminate,

The invention will now be further described with reference to the following non-limiting drawings.
Figure 1 is a plot of resistance (Ω) versus bias (V) for comparative laminates.
Figure 2 is a plot of resistance (Ω) versus bias (V) for a laminate according to the present invention.
Figure 3a is an AFM image of graphene grown by a direct comparison method on a silicon nitride surface.
Figure 3b is an AFM image of graphene grown by a direct comparison method on a silicon oxide surface.
Figure 4 is an AFM image of graphene grown according to an example.
Figure 5 is an AFM image of graphene grown according to an example.
Figure 1 is a plot of data obtained from measuring the resistance between graphene and the silicon substrate of a comparison wafer, where graphene was CVD grown at a growth temperature above 1300°C on a 200 nm thick insulating Si ₃ N ₄ layer on the silicon substrate. It was grown using .
Figure 2 is a plot of data obtained from measuring the resistance between the graphene and silicon substrate of the wafer as described herein. The wafer included an insulating Si ₃ N ₄ layer on the same silicon substrate as the comparative example, and further included a 5 nm AlO _x barrier layer formed by ALD using water as a precursor. Graphene was grown on the growth side of the AlO _x barrier layer using CVD at equivalent growth temperatures above 1300°C. Figure 2 shows that the presence ^of _a 5 _{nm AlO} It shows.
Figure 3a is an AFM image showing the morphology of graphene grown directly on the surface of silicon nitride. Figure 3b is an AFM image showing the morphology of graphene grown directly on the surface of silicon oxide. Figure 4 is an AFM image showing the improved morphology of graphene grown according to the method of the invention, particularly on thin (<5 nm) alumina layers on silicon nitride. Figure 5 is an AFM image showing the improved morphology of graphene grown according to the method of the invention, particularly on thin (<5 nm) alumina layers on aluminum nitride.
Example
A silicon wafer with a pre-grown silicon nitride or aluminum nitride coating is placed into an ALD chamber at a deposition temperature of 150° C. under a vacuum of approximately 220 mTorr (about 27 Pa) with a nitrogen gas flow of 27 sccm to equalize the chamber temperature and pressure. It not only retains within the chamber but also desorbs any moisture from the sample surface. Al ₂ O ₃ is then introduced into the deposition chamber using nitrogen as both carrier and purge gas, trimethyl aluminum (TMAl) and deionized water (DI H ₂ O) or ozone (O ₃ ) as metal organic and oxidant precursors, respectively. ) was deposited using. Precursors are pulsed into the chamber at a 3:2 ratio, using a pulse time of 0.6 seconds and a purge time of 20 and 18 or 25 seconds for TMAl and DI H ₂ O or O ₃ respectively. The film is deposited at 150° C. in a varying number of cycles (10 to 1000 cycles) depending on the desired film thickness.
The ALD capped wafer is placed on a silicon carbide coated graphite susceptor within a MOCVD reactor chamber. The reactor chamber itself is protected by an inert atmosphere within a glove box. The reactor is then sealed and purged under a flow of nitrogen, argon or hydrogen gas at a rate of 10,000 to 60,000 sccm. The susceptor is rotated at a speed of 40 to 60 rpm. The pressure in the reactor chamber is reduced to 30 to 100 mbar. Optical probes are used to monitor wafer reflectivity and temperature during growth, while the wafers are still in their unheated state and they are rotated under the probe to establish a baseline signal. The wafer is then heated using a resistive heater coil positioned below the susceptor to a set point of 1000 to 1500° C. at a rate of 0.1 to 3.0 K/s. After the wafer is optionally baked under a flow of hydrogen gas for 10 to 60 minutes, the ambient gas is converted to nitrogen or argon and the pressure is reduced to 30 to 50 mbar. After the wafer is annealed at the growth temperature and pressure for a period of 5 to 10 minutes, the hydrocarbon precursor is introduced into the chamber. It is transferred from its liquid state in a bubbler by passing a carrier gas (nitrogen, argon or hydrogen) through the liquid, which is maintained at constant temperature and pressure. The vapor enters the gas mixing manifold and through the showerhead into the reactor chamber through a number of small inlets, commonly referred to in the art as plenum/plena, ensuring uniform vapor distribution and growth across the surface of the wafer. Proceed with The wafer is exposed to hydrocarbon vapor under constant flow, pressure and temperature for a duration of 1,800 to 10,800 seconds, at which point the precursor supply valve is closed. The wafer is then cooled under a continuous flow of nitrogen, argon or hydrogen gas at a rate of 0.1 to 4 K/min. Once the wafer temperature reaches below 200°C, the chamber is pumped to vacuum and purged with an inert gas. Stop rotation and turn off heater. The reactor chamber is opened, and once the heater temperature reaches below 150° C., the graphene coated wafer is removed from the susceptor.
The formed graphene was then characterized using standard techniques including Raman spectroscopy and atomic force microscopy. Figures 3a and 3b show the morphology of graphene grown directly on silicon nitride and silicon oxide surfaces, respectively. In contrast, Figures 4 and 5 show the morphology of graphene grown on thin (<5 nm) alumina layers on silicon nitride or aluminum nitride, respectively, depending on the example. Rather than growing as separate strands or flakes of graphene, it grows as a continuous single layer, making it useful for applications in electronic devices. Crucially, the alumina barrier maintains the insulating behavior of the underlying dielectric, allowing the graphene to be gated through electric field effects. In the absence of an alumina barrier, graphene growth degrades the insulating dielectric and creates electrical contact between the underlying graphene layer and the silicon wafer.
As used herein, the singular forms include plural references unless the context clearly dictates otherwise. The use of the term “comprising” is intended to be construed as including such features but not excluding other features, and is also intended to include the option of features being necessarily limited to those described. That is, unless the context clearly states otherwise. The term also refers to "consisting essentially of" (which is intended to mean that certain additional components may be present so long as they do not materially affect the essential characteristics of the feature described) and "consisting of" (which consists of Expressed as a percentage, it includes the limitation that no other characteristics can be included so that when added up to 100%, taking into account unavoidable impurities.
It will be understood that although the terms “first”, “second”, etc. may be used herein to describe various elements, layers and/or portions, the elements, layers and/or portions should not be limited by these terms. will be. These terms are used to distinguish one element, layer, or portion from another element, or from an additional, element, layer, or portion. The term “on” will be understood to mean “directly on” such that there is no intervening layer between one material that is said to be “on” another material. Other element(s) may be referred to herein as "below", "below", "lower", "above", etc. for ease of description and to describe the relationship of one element or feature to the feature(s). Spatially relative terms such as “top” and the like may be used herein. It will be understood that spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. For example, if a wafer or device as described herein is turned over, an element described as “below” or “below” another element or feature will be oriented “above” another element or feature. Accordingly, the exemplary term “below” can include both up and down orientations. The wafer or device may be otherwise oriented and the spatially relative descriptors used herein are interpreted accordingly.
The foregoing detailed description has been provided by way of illustration and example, and is not intended to limit the scope of the appended claims. Many modifications of the presently preferred embodiments illustrated herein will be apparent to those skilled in the art and are within the scope of the appended claims and their equivalents.

Claims (12)

A wafer for uniform CVD growth of graphene at a temperature exceeding 700° C., the wafer comprising, in order:
planar silicon substrate,
an insulating layer provided across the silicon substrate; and
comprising, in order, a barrier layer provided throughout the insulating layer,
The insulating layer is a silicon nitride and/or aluminum nitride layer,
The barrier layer has a constant thickness of 50 nm or less and provides a growth surface for uniform CVD growth of graphene. The wafer according to claim 1, wherein the barrier layer is an alumina, yttria, zirconia and/or YSZ layer, preferably alumina. 3. Wafer according to claim 1 or 2, wherein the insulating layer has a constant thickness of 10 nm to 100 μm, preferably 50 nm to 10 μm. 4. The wafer according to any one of claims 1 to 3, wherein the barrier layer has a constant thickness of 1 to 10 nm, preferably 1 to 5 nm. 5. The wafer according to any one of claims 1 to 4, wherein the barrier layer is obtainable by ALD using water or ozone as a precursor. A laminate comprising at least a portion of the wafer according to any one of claims 1 to 5 and a graphene layer formed on the growth side of the barrier layer by CVD at a temperature above 700°C. An electronic device comprising the laminate of claim 6. A method of manufacturing a wafer for the CVD growth of uniform graphene at a temperature exceeding 700° C., comprising:
providing a planar silicon substrate having an insulating layer provided across its surface;
forming a barrier layer over the insulating layer by ALD using water or ozone as a precursor,
The insulating layer is a silicon nitride and/or aluminum nitride layer,
The method of claim 1 , wherein the barrier layer has a constant thickness of less than 50 nm and provides a growth surface for the CVD growth of uniform graphene at a temperature above 700°C. 9. The method of claim 8, wherein the barrier layer is an alumina, yttria, zirconia and/or YSZ layer. The method of claim 9, wherein the barrier layer is alumina, and the additional precursor for ALD is trialkyl aluminum or trialkoxide aluminum, preferably trimethylaluminum, tris(dimethylamido)aluminum, aluminum tris(2,2,6, 6-tetramethyl-3,5-heptandionate) or aluminum tris(acetylacetonate). 11. The method according to any one of claims 8 to 10, wherein the wafer is according to any one of claims 1 to 5. As a method of manufacturing a laminate,
providing said wafer according to any one of claims 1 to 5, or obtained by said method according to any one of claims 8 to 11, and
A method comprising forming a graphene layer on the growth side of the barrier layer by CVD at a temperature greater than 700°C.

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