GB2605167A - A wafer for the CVD growth of uniform graphene and method of manufacture therof - Google Patents

Abstract

A method for the manufacture of a wafer comprises providing a planar silicon substrate having an insulating layer provided across a surface thereof and forming a barrier layer across the insulating layer by atomic layer deposition (ALD) using water or ozone as a precursor, wherein the barrier layer is an alumina and/or hafnium oxide layer and has a constant thickness of 20 nm or less. A method for the manufacture of a laminate comprises forming a graphene layer on the barrier layer by chemical vapour deposition (CVD) at a temperature in excess of 700oC. An electronic device comprising the laminate is preferably a Hall sensor, a current sensor, a biosensor, an electro-optic modulator or a transistor.

Description

A wafer for the CVD growth of uniform graphene and method of manufacture thereof The present invention provides a wafer for the CVD growth of graphene. More particularly, the present invention provides a wafer that is suitable for growing uniform graphene at a temperature in excess of 700°C. The present invention also relates to a laminate comprising said wafer and a graphene layer formed thereon, in particular having been formed by CVD at a temperature in excess of 700°C. The present invention further provides methods for the manufacture of said wafer and said laminate.

Two-dimensional materials, of which graphene is one of the most prominent, are currently the focus of intense research. Graphene in particular has been shown, both theoretically and in recent years practically, to demonstrate extraordinary properties. The electronic properties of graphene are especially remarkable and have enabled the production of electronic devices which are orders of magnitude improved over non-graphene based devices. However, there remains a need in the art for wafers, also known as substrates, which facilitate the production of high-quality, uniform graphene. In particular, there remains a need for wafers in the microelectronics industry which are suitable for use in well-established semiconductor fabrication plants which may be used directly to grow graphene and then to manufacture graphene-based electronic devices on an industrial scale.

Semiconductor fabrications plants (also known as "fabs") are factories wherein devices such as integrated circuits are manufactured. The cost of constructing and equipping a fab is typically many billions of dollars. In 2020, one fab was reported to have cost over $17 billion. Each fab is kitted out for specific manufacturing methods and has very little scope for the introduction of new technologies or methodologies. Typically, during the historical development of silicon based devices, new fabs have been constructed with each technological development to enable use of such new technology.

Globally, fabs are therefore primarily constructed for the purpose of manufacturing electronics from silicon wafers It is known in the art that graphene may be synthesised. manufactured, formed, directly on non-metallic surfaces of substrates. These include silicon and sapphire along with other more exotic surfaces such as III-V semiconductors. The present inventors have found that the most effective method for manufacturing high-quality graphene, especially directly on such non-metallic surfaces, is that disclosed in WO 2017/029470. The method of WO 2017/029470 is ideally performed using an MOCVD reactor. Whilst MOCVD stands for metal organic chemical vapour deposition due to its origins for the purposes of manufacturing semiconductor materials such as AIN and GaN from metal organic precursors such as AlMe3 (TMAI) and GaMe3 (TMGa). such apparatus and reactors are well known and understood to those skilled in the art as being suitable for use with non-metal organic precursors. MOCVD may be used synonymously with metal organic vapour phase epitaxy (MOVPE).

Whilst there is a need to use silicon wafers in order to meet the strict requirements of pre-existing semiconductor fabrication plants, there is at the same time a need to grow graphene, an excellent conductor, directly on insulating surfaces for many electronic devices. It is known in the art that silicon wafers may be provided with insulating surfaces, for example, silicon having silicon oxide or silicon nitride surfaces (i.e. Si/Si02 or Si/SiN. wafers are well-known).

The inventors have sought to bridge the gap between the need for a silicon based wafer and an insulating surface for graphene growth to facilitate the adoption of graphene into industrial electronic device production, particularly in commercial fabs, and have as a result developed both improved wafers and methods for the manufacture of such wafers. The present invention therefore overcomes, or at least substantially reduces, the various problems associated with the prior art or at least provides a commercially useful alternative.

Accordingly, in a first aspect there is provided wafer for the CVD growth of uniform graphene at a temperature in excess of 700°C, the wafer comprising in order: a planar silicon substrate, an insulating layer provided across the silicon substrate, and a barrier layer provided across the insulating layer, wherein the barrier layer is an alumina and/or hafnium oxide layer, has a constant thickness of 20 nm or less and provides a growth surface for the CVD growth of uniform graphene.

The present disclosure will now be described further. In the following passages, different aspects/embodiments of the disclosure are defined in more detail. Each aspect/embodiment so defined may be combined with any other aspect/embodiment or aspects/embodiments unless clearly indicated to the contrary. In particular, any feature indicated as being preferred or advantageous may be combined with any other feature or features indicated as being preferred or advantageous.

The present invention relates to a wafer. A wafer is a standard term in the art and is equivalent to a substrate. In this context, the wafer comprises multiple distinct layers (i.e. a silicon layer, insulating layer and barrier layer). Wafers are used for the fabrication and manufacture of electronic devices.

Specifically, the wafer of the present invention is based on silicon such that the wafer is suitable for use in pre-existing fabs. In other words, the wafer of the present invention comprises a silicon substrate. The silicon substrate is planar being of substantially constant thickness and consisting of a single layer of elemental silicon. The silicon may however be doped, as is well-known in the art, with small amounts of other elements such as boron, nitrogen and phosphorus. When doped, the semiconductor substrate may be either p-type or n-type doped. Preferably, the doped semiconductor substrate has a dopant concentration of greater than 10'5 cm-3, more preferably greater than 1016 cm-3 and/or less than 1020 cm, preferably less than 10'9 cm-3. A most preferred range is from 1016 cm-3 to 1018cm-3.

The wafer is suitable for the growth of uniform graphene by CVD at a temperature in excess of 700°C. Typically, graphene is grown at temperatures in excess of 700°C when using CVD in order to achieve high quality and uniformity hence the need for a wafer suitable for such subsequent processing.

The inventors found that when using known hybrid wafers suitable for fabs such as Si/SiO2, the conditions used to grow graphene on the insulating surface, in particular the high temperatures in excess of 700°C, resulted in damage of the insulating layer thereby reducing its function as an insulator. This effect is naturally more pronounced at the preferred higher growth temperatures such that the wafer of the present invention is preferably suitable for use at higher temperatures of greater than 800°C, greater than 900°C and even more preferably greater than 1000°C, such as greater than 1100°C.

The wafer of the present invention has addressed this issue through the presence of both an insulating and barrier layer as described herein. Specifically, the wafer comprises a planar silicon substrate wherein an insulating layer is provided across the silicon substrate. Additionally, a barrier layer is provided across the insulating layer such that the wafer comprises these three layers in a specific order whereby the insulating layer is sandwiched between the planar silicon substrate and barrier layer whereupon graphene may be directly grown by CVD on the barrier layer. As a result, there are no intervening layers between those layers of the wafer or laminate as described herein.

The insulating layer may consist of any electrically Insulating material. Accordingly, the conductivity of the insulating layer is less than that of silicon which is a semiconductor. For example, the conductivity of the insulator may be less than 10-6 S/cm, preferably less than 10-6 S/cm. Alternatively, this may be measured with respect to the materials band gap; silicon has a band gap of about 1.1 eV to about 1.6 eV whereas that of an insulator is much greater, typically greater than 3 eV, preferably greater than 4 eV.

Preferably, the insulating layer is silicon oxide and/or silicon nitride since silicon wafers having silicon oxide or silicon nitride are well-known and commercially available. Preferably the insulating layer does not comprise alumina or hafnium oxide. Equally, an insulating layer such as silicon oxide or silicon nitride may be formed across a silicon substrate surface using conventional techniques. A combination of silicon oxide and silicon nitride may be preferable for certain embodiments, for example in silicon photonics for the production of electro-optic modulators wherein the silicon nitride forms a waveguide within the silicon oxide. The thickness of the insulating layer is not particularly limited and a vast range of thicknesses, in for example Si/Si02 and Si/SiNx wafers, are available. The thickness may preferably be from 10 nm to 100 pm, such as from 50 nm to 10 pm. More preferably, the thickness is from 50 to 500 nm and in some embodiments, may be from 100 to 200 nm.

The wafer further comprises a barrier layer provided across the insulating layer: the barrier layer is that of the wafer which provides a growth surface suitable for the CVD growth of uniform graphene. As will be appreciated, the opposite surface of the barrier layer is that in direct contact with and across the surface of the insulating layer below. Specifically, the barrier layer is an alumina layer and/or a hafnium oxide layer. These materials may be referred to as A1203 or Hf02, respectively, but it should be appreciated that the exact stoichiometry may vary within normal bounds. Preferably the materials are A1203 or Hf02. Furthermore, the barrier layer is relatively thin, at least with regards to the thickness of a standard silicon substrate, and has a constant thickness of 20 nm or less. As described herein, the thickness of the barrier layer may be at least 1 nm, or at least 2 nm. In some embodiments, the thickness of the barrier layer may therefore be from 1 to 10 nm, and preferably from 1 to 5 nm, from 2 to 10 nm or even from 2 to 5 nm.

In an alternative aspect, the barrier layer may be one or more of any of the metal oxides MgA1204, MgO, ZnO, 0a203, Ti02, SrTiO3, LaA103, Ta205, LiNb03, Y203, Y-stabilised Zr02 (YSZ), Zr02, Y3A15012 ('(AG), and/or metal nitrides AIN, h-BN, GaN, and/or SiC and/or CaF2. In these instances, all passages of the description herein of the barrier layer which refer to alumina and/or hafnium oxide should be construed as applying equally to a barrier layer formed from any these further materials and may in some embodiments be combined with alumina and/or hafnium oxide.

Preferably, the barrier layer consists of alumina or hafnium oxide. However, in some embodiments, the barrier layer may preferably consist of alumina and hafnium oxide, preferably wherein the barrier layer consists of one or more layers of alumina and one or more layers of hafnium oxide (provided the total thickness of the barrier layer is a constant thickness of less than 20 nm as described herein. Accordingly, the barrier layer may be an A1203-Hf02 nanolaminate.

Without wishing to be bound by theory, the inventors believe that when growing graphene at temperatures in excess of 700°C, such as greater than 1000°C, the insulating layer can be damaged. Typically, graphene is grown using a hydrocarbon precursor, or at least an organic compound comprising carbon and hydrogen and/or with a carrier gas comprising hydrogen. The presence of hydrogen and radical hydrocarbon species in the reaction chamber during graphene growth may etch the insulating layer which has been found to reduce the function of the insulating layer as an effective insulator. Etching creates channels which can then become filled with conductive carbon during graphene growth providing a pathway for current to leak to the underlying silicon. The inventors have found that a barrier layer of alumina or hafnium oxide on the surface of the insulating layer can protect the insulation properties, which is particularly surprisingly given its small thickness.

The inventors also investigated whether a barrier layer could be provided directly on a silicon substrate. However, the inventors found that a lattice mismatch between silicon and either of alumina or hafnium oxide are a likely cause for defects/dislocations at the interface which may then spread through the alumina or hafnium oxide layer, again providing a pathway within which conductive carbon may be filled during graphene growth thereby failing to provide graphene on an effective insulator.

Alumina and hafnium oxide are common materials for the formation of dielectric layers in electronic device fabrication. Such layers are ubiquitous in electronic devices and are known to be suitable materials to deposit on graphene, such as in the formation of a graphene transistor or as a protective layer in for example, a graphene Hall-sensor. Alumina and hafnium oxide can be grown using ALD (atomic layer deposition). ALD is technique known in the art and comprises the reaction of at least two appropriate precursors in a sequential, self-limiting manner. Repeated cycles of the separate precursors allow the growth of a thin barrier layer due to the monolayer-by-monolayer growth mechanism which makes ALD particularly advantageous.

Despite the benefits afforded by ALD, the inventors found that thicker barrier layers, such as those greater than 20 nm, gave poor quality graphene. This was itself surprising since at least sapphire substrates (A1203) have been used by the inventors in a significant portion of their previous work to provide a non-metallic surface suitable for the growth of exceptionally high quality graphene. The thicker barrier layers were found to have a surface roughness greater than that of thinner barrier layers which then propagated through as defects in any graphene which was subsequently formed thereon. The inventors were surprised to find that a barrier layer as thin as less than 20 nm was sufficient to protect the insulative properties of the insulating layer and further was essential to facilitate the growth of graphene thereon at temperatures in excess of 700°C.

Without wishing to be bound by theory, the inventors believe that by reducing the thickness of the barrier layer grown by ALD, the roughness arising from adjacent crystals of the polycrystalline alumina or hafnium oxide was reduced due to a reduction in the variation between different crystal sizes during growth of the barrier layer.

Accordingly, in a second aspect of the present invention, there is provided a method for the manufacture of a wafer for the CVD growth of uniform graphene at a temperature in excess of 700°C.

the method comprising: providing a planar silicon substrate having an insulating layer provided across a surface thereof, forming a barrier layer across the insulating layer by ALD using water or ozone as a precursor, wherein the barrier layer is an alumina and/or hafnium oxide layer, has a constant thickness of 20 nm or less and provides a growth surface for the CVD growth of uniform graphene at a temperature in excess of 700°C.

Preferably, the method is for the manufacture of a wafer according to the first aspect of the invention.

The method involves forming a barrier layer across the insulating layer by ALD using water or ozone as a precursor, specifically as the source of oxygen atoms. The inventors found that when using water to form the barrier layer, thinner layers were particularly preferable, such as 1 to 10 nm, or 2 to 5 nm.

Without wishing to be bound by theory, the inventors found that such thin layers have significantly reduced capability of retaining excess water. Upon heating to the temperatures required for graphene growth, evaporation of water retained in thicker layers resulted in blistering of the barrier layer surface. The roughening of the barrier layer impaired the quality of the graphene subsequently formed thereon. When using ozone as a precursor, the thickness of the barrier layer is preferably from 2 to 20 nm, preferably from 5 to 10 nm due to the slightly poorer insulative properties observed when using ozone as a precursor.

Accordingly, the step of forming a barrier layer is preferably performed using water as a precursor. Similarly, the wafer of the present invention preferably comprises a barrier layer which is obtainable, preferably obtained, by ALD using water as a precursor.

Suitable precursors which provide the required aluminium or hafnium atoms are well-known, commercially available and not particularly limited. Metal halides such as metal chlorides (e.g. AlC13 and HfC14) may be used. Alternatively, metal amides, metal oxides or organometallic precursors may be used. Hafnium precursors include, for example, tetrakis(dimethylamido)hafnium(IV), tetrakis(diethylamido)hafnium(IV), hafnium(1V) tert-butoxide and dimethylbis(cyclopentadienyl)hafnium(IV). Preferably, the barrier layer is alumina and preferably a further precursor for the ALD is a trialkyl aluminium or trialkoxide aluminium, such as trimethylaluminium, tris(dimethylamido)aluminium, aluminium tris(2,2,6,6-tetramethyl- 3,5-heptanedionate) or aluminium tris(acetylacetonate).

The deposition temperature when forming the alumina and/or hafnium oxide barrier may be any conventional temperature known in the art. Typically the deposition temperature is from 40°C to 300°C, and the inventors have found that temperatures above 100°C are preferable and afford better quality barrier layers.

In another aspect of the present invention, there is provided a method for the manufacture of a laminate, the method comprising providing a wafer described herein and forming a graphene layer on the growth surface of the barrier layer by CVD at a temperature in excess of 700°C.

Thus, there is also provided a laminate comprising a wafer as described herein and a graphene layer formed on the growth surface of the barrier layer by CVD at a temperature in excess of 700°C.

The present invention also provides an electronic device comprising a laminate as described herein. An electronic device is one which may then be installed into an electrical or electronic circuit, typically by wire bonding to further circuitry or by other methods known in the art such as soldering using "flip chip" style solder bumps. Thus an electronic device is a functioning device when installed in an electronic circuit and current is provided to the device. Preferred electronic devices are sensors such as Hall-sensors, current sensors and biosensors, modulators such as electro-optic modulators, and transistors. The present invention also provides the use of a laminate to form an electronic device. In some embodiments, the silicon substrate of the wafer of the laminate may be removed to afford an electronic device having no silicon substrate. This may be achieved through grinding or etching of the silicon in a process as described in UK Patent Application No. 2102218.1 (the contents of which is incorporated herein by reference).

The laminate and method for the manufacture of a laminate both require a graphene layer having been formed by CVD on the growth surface of the barrier layer of the wafer, wherein the graphene is grown by CVD at temperatures in excess of 700°C, preferably in excess of 1000°C, the wafer being suitable for such graphene growth by CVD at such temperatures.

Preferably, the graphene is grown by CVD in accordance with the disclosure of WO 2017/029470 (the contents of which is incorporated herein by reference). This publication discloses methods for manufacturing graphene; principally these rely on heating a substrate (such as a wafer as described herein) held within a reaction chamber to a temperature that is within a decomposition range of a carbon based precursor for graphene growth, introducing the precursor into the reaction chamber through a relatively cool inlet so as to establish a sufficiently steep thermal gradient that extends away from the substrate surface towards the point at which the precursor enters the reactions chamber such that the fraction of precursor that reacts in the gas phase is low enough to allow the formation of graphene from carbon released from the decomposed precursor. Preferably the apparatus comprises a showerhead having a plurality of precursor entry points or inlets, the separation of which from the substrate surface may be varied and is preferably less than 100 mm.

Forming graphene is synonymous with synthesising, manufacturing, producing and growing graphene. Graphene is a very well-known two-dimensional material referring to an allotrope of carbon comprising a single layer of carbon atoms in a hexagonal lattice. Graphene, as used herein, refers to one or more layers of graphene. Accordingly, some aspects of the present invention involve the formation of a monolayer of graphene as well as multilayer graphene (which may be termed a graphene layer structure). Preferably, graphene refers to a graphene layer structure having from 1 to monolayers of graphene. In many subsequent applications for a laminate, a monolayer of graphene on a wafer is particularly preferred. Accordingly, the graphene formed is preferably monolayer graphene. Nevertheless, multilayer graphene is preferable for other applications and 2 or 3 layers of graphene may be preferred.

The method for the manufacture of a laminate comprises forming graphene by CVD which will take place in a CVD reaction chamber. This step of forming graphene will typically comprise introducing a precursor in a gas phase and/or suspended in a gas into the CVD reaction chamber. CVD refers generally to a range of chemical vapour deposition techniques, each of which involve vacuum deposition to produce thin film materials such as two-dimensional crystalline materials like graphene. Volatile precursors, those in the gas phase or suspended in a gas, are decomposed to liberate the necessary species to form the desired material, carbon in the case of graphene. As will be appreciated, the wafer is, equally, preferably suitable for the growth of uniform graphene in accordance with the preferable CVD methods described herein.

Preferably, the method involves forming graphene by thermal CVD such that decomposition is a result of heating the precursor. Preferably, the CVD reaction chamber used is a cold-walled reaction chamber wherein a heater coupled to the substrate is the only source of heat to the chamber.

In a particularly preferred embodiment, the CVD reaction chamber comprises a close-coupled showerhead having a plurality, or an array, of precursor entry points. Such CVD apparatus comprising a close-coupled showerhead may be known for use in MOCVD processes. Accordingly, the method may alternatively be said to be performed using an MOCVD reactor comprising a close-coupled showerhead. In either case, the showerhead is preferably configured to provide a minimum separation of less than 100 mm, more preferably less than 25 mm, even more preferably less than 10 mm, between the surface of the wafer and the plurality of precursor entry points. As will be appreciated, by a constant separation it is meant that the minimum separation between the surface of the wafer and each precursor entry point is substantially the same. The minimum separation refers to the smallest separation between a precursor entry point and the wafer surface. Accordingly, such an embodiment involves a "vertical" arrangement whereby the plane containing the precursor entry points is substantially parallel to the plane of the wafer surface, i.e. the growth surface of the barrier layer.

The precursor entry points into the reaction chamber are preferably cooled. The inlets, or when used, the showerhead, are preferably actively cooled by an external coolant, for example water, so as to maintain a relatively cool temperature of the precursor entry points such that the temperature of the precursor as it passes through the plurality of precursor entry points and into the reaction chamber is less than 100°C, preferably less than 50°C.

Preferably, a combination of a sufficiently small separation between the wafer surface and the plurality of precursor entry points and the cooling of the precursor entry points, coupled with the heating of the wafer to with a decomposition range of the precursor and in excess of 700°C, generates a sufficiently steep thermal gradient extending from the substrate surface to the precursor entry points to allow graphene formation on the substrate surface. As disclosed in WO 2017/029470, very steep thermal gradients may be used to facilitate the formation of high-quality and uniform graphene directly on non-metallic substrates, preferably across the entire surface of the substrate. The wafer of the present invention may have a diameter of at least 5 cm (2 inches), at least 15 cm (6 inches) or at least 30 cm (12 inches). Particularly suitable apparatus for the method described herein include an Aixtron® Close-Coupled Showerhead® reactor and a Veeco® TurboDisk reactor.

Consequently, in a particularly preferred embodiment wherein the formation of graphene involves using a method as disclosed in WO 2017/029470, the formation of graphene comprises: providing the wafer comprising a barrier layer having a growth surface on a heated susceptor in a close-coupled reaction chamber, the close-coupled reaction chamber having a plurality of cooled inlets arranged so that, in use, the inlets are distributed across the wafer and have constant separation from the wafer; cooling the inlets to less than 100°C; introducing a precursor in a gas phase and/or suspended in a gas through the inlets and into the CVD reaction chamber to thereby decompose the precursor and form graphene on the growth surface of the barrier layer of the wafer; and heating the susceptor to a temperature of at least 50°C in excess of a decomposition temperature of the precursor, to provide a thermal gradient between the growth surface and inlets that is sufficiently steep to allow the formation of graphene from carbon released from the decomposed precursor; wherein the constant separation is less than 100 mm, preferably less than 25 mm, even more preferably less than 10 mm.

In a preferred embodiment of the present invention, the precursor is introduced into the CVD reaction chamber as a mixture with a carrier gas. Carrier gases are well known in the art and may also be referred to as a dilution gas or a diluent. Carrier gases typically include inert gases such as noble gases, and in the case of graphene growth, hydrogen gas. Accordingly, the carrier gas is preferably one or more of hydrogen (H2). nitrogen (N2), helium (He). and argon (Ar). More preferably the carrier gas is one of nitrogen, helium and argon or the carrier gas is a mixture of hydrogen and one of nitrogen, helium and argon.

Figures The present invention will now be described further with reference to the following non-limiting Figures, in which: Figure 1 is a plot of resistance (0) against bias (V) for a comparative laminate.

Figure 2 is a plot of resistance (0) against bias (V) for a laminate in accordance with the present invention.

Figure 3A is an AFM image of graphene grown by a comparative method, direct onto a silicon nitride surface.

Figure 3B is an AFM image of graphene grown by a comparative method, direct onto a silicon oxide surface.

Figure 4 is an AFM image of graphene grown in accordance with the Example.

Figure 1 is a plot of the data obtained from measuring the resistance between the graphene and the silicon substrate of a comparative wafer wherein the graphene was grown using CVD at a growth temperature in excess of 1300°C on a 200 nm thick insulating Si3N14 layer of silicon substrate.

Figure 2 is a plot of the data obtained from measuring the resistance between the graphene and the silicon substrate of a wafer as described herein. The wafer comprises an insulating Si31\14 layer on a silicon substrate, equivalent to that of the comparative example and further comprises a 5 nm AlOx barrier layer which had been formed by ALD using water as a precursor. The graphene was grown on the growth surface of the Ala( barrier layer using CVD at an equivalent growth temperature in excess of 1300°C. Figure 2 demonstrates that the presence of a 5 nm AlOx barrier layer in a laminate affords an average 105 improvement in resistance across a bias of from -3 V to +3 V as a result of the protection of the insulating Si3N4 layer during the process of graphene growth by CVD.

Figure 3A is an AFM image which demonstrates the morphology of graphene grown directly onto a silicon nitride surface. Figure 3B is an AFM image is an AFM image which demonstrates the morphology of graphene grown directly onto a silicon oxide surface. Figure 4 is an AFM image which demonstrates the improved morphology of graphene grown in accordance with the method of the present invention, specifically grown onto a thin (< 5 nm) alumina layer on silicon nitride.

Examples

The silicon wafer with a pre-grown silicon oxide or silicon nitride coating is placed into an ALD chamber and held in the chamber at the deposition temperature of 150°C under a vacuum of approximately 220 mTorr (about 27 Pa) with a nitrogen gas flow of 27 scorn to equilibrate the chamber temperature and pressure, as well as desorb any moisture from the sample surface. A1203 is then deposited using trimethyl aluminium (TMAI) and either deionised water (DI H20) or ozone (03) as the metalorganic and oxidant precursor, respectively. which are introduced into the deposition chamber using nitrogen as both the carrier and purge gas. The precursors are pulsed into the chamber in a 3:2 ratio, with pulse times of 0.6 seconds and purge times of 20 and 18 or 25 seconds for TMAI and DI H20 or 03, respectively. Films are deposited at 150°C with varying numbers of cycles (between 10 and 200 cycles) depending on the desired film thickness.

The ALD-capped wafers are positioned upon a silicon carbide-coated graphite susceptor within an MOCVD reactor chamber. The reactor chamber itself is protected in an inert atmosphere within a glovebox. The reactor is then sealed closed and purged under a flow of nitrogen, argon or hydrogen gas at a rate of 10,000 to 60,000 sccm. The susceptor is rotated at a rate of 40 to 60 rpm. The pressure within the reactor chamber is reduced to 30 to 100 mbar. An optical probe is used to monitor the wafer reflectivity and temperature during growth -with the wafers still in their unheated state, they are rotated under the probe in order to establish a baseline signal. The wafers are then heated using resistive heater coils positioned beneath the susceptor to a setpoint of from 1000 to 1500°C at a rate of 0.1 to 3.0 'Qs. The wafers are optionally baked under flow of hydrogen gas for from 10 to 60 min, after which the ambient gas is switched to nitrogen or argon and the pressure is reduced to 30 to 50 mbar. The wafer is annealed at the growth temperature and pressure for a period of from 5 to 10 min, after which a hydrocarbon precursor is admitted to the chamber. This is transported from its liquid state in a bubbler by passing a carrier gas (nitrogen, argon or hydrogen) through the liquid which is held under constant temperature and pressure. The vapour enters a gas mixing manifold and proceeds to the reactor chamber through a showerhead via a multitude of small inlets commonly referred to in the art as plenums/plena, which guarantees uniform vapour distribution and growth across the surface of the wafers. The wafers are exposed to the hydrocarbon vapour under constant flow, pressure and temperature for a duration of 1,800 to 10,800 s at which point the precursor supply valve is shut off. The wafers are then cooled under continuing flow of nitrogen, argon or hydrogen gas at a rate of from 0.1 to 4 K/min. Once the wafer temperature reaches below 200°C, the chamber is pumped to vacuum and purged with inert gas. The rotation is stopped and the heaters are shut off.

The reactor chamber is opened and the graphene-coated wafers are removed from the susceptor once the heater temperature reaches below 150°C.

The graphene formed was then characterised using standard techniques including Raman spectroscopy and atomic force microscopy. Figures 3A and 3B show the morphology of graphene grown direct onto silicon nitride and silicon oxide surfaces, respectively. In contrast, Figure 4 shows the morphology of graphene grown in accordance with the Example onto a thin (< 5 nm) alumina layer on silicon nitride. Rather than growing as discrete strands or flakes of graphene, it grows as a continuous single layer, making it useful for application in electronic devices. Crucially, the alumina barrier also retains the insulating behaviour of the dielectric beneath, allowing the graphene to be gated via a field-effect. In the absence of the alumina barrier, the graphene growth degrades the insulating dielectric, and creates electrical contact between the graphene layer and the silicon wafer beneath.

As used herein, the singular form of "a", "an" and "the" include plural references unless the context clearly dictates otherwise. The use of the term "comprising" is intended to be interpreted as including such features but not excluding other features and is also intended to include the option of the features necessarily being limited to those described. In other words, the term also includes the limitations of "consisting essentially of" (intended to mean that specific further components can be present provided they do not materially affect the essential characteristic of the described feature) and "consisting of" (intended to mean that no other feature may be included such that if the components were expressed as percentages by their proportions, these would add up to 100%, whilst accounting for any unavoidable impurities), unless the context clearly dictates otherwise.

It will be understood that, although the terms "first", "second", etc. may be used herein to describe various elements, layers and/or portions, the elements, layers and/or portions should not be limited by these terms. These terms are only used to distinguish one element, layer or portion from another, or a further, element, layer or portion. It will be understood that the term "on" is intended to mean "directly on" such that there are no intervening layers between one material being said to be "on" another material. Spatially relative terms, such as "below", "beneath", "lower", "above", "upper and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s). It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a wafer or device as described herein is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the example term "belowt can encompass both an orientation of above and below. The wafer or device may be otherwise oriented and the spatially relative descriptors used herein interpreted accordingly.

The foregoing detailed description has been provided by way of explanation and illustration, and is not intended to limit the scope of the appended claims. Many variations of the presently preferred embodiments illustrated herein will be apparent to one of ordinary skill in the art, and remain within the scope of the appended claims and their equivalents.

Claims (11)

1. Claims: 1. A wafer for the CVD growth of uniform graphene at a temperature in excess of 700°C, the wafer comprising in order: a planar silicon substrate, an insulating layer provided across the silicon substrate, and a barrier layer provided across the insulating layer, wherein the barrier layer is an alumina and/or hafnium oxide layer, has a constant thickness of 20 nm or less and provides a growth surface for the CVD growth of uniform graphene.
2. 2. The wafer according to claim 1, wherein the insulating layer is a silicon nitride and/or silicon oxide layer.
3. 3. The wafer according to claim 1 or claim 2, wherein the insulating layer has a constant thickness of from 10 nm to 100 pm, preferably from 50 nm to 10 pm.
4. 4. The wafer according to any preceding claim, wherein the barrier layer has a constant thickness of from 1 to 10 nm, preferably from 1 to 5 nm.
5. 5. The wafer according to any preceding claim, wherein the barrier layer is obtainable by ALD using water or ozone as a precursor.
6. 6. A laminate comprising the wafer according to any of the preceding claims and a graphene layer formed on the growth surface of the barrier layer by CVD at a temperature in excess of 700°C.
7. 7. An electronic device comprising the laminate of claim 6.
8. 8. A method for the manufacture of a wafer for the CVD growth of uniform graphene at a temperature in excess of 700°C, the method comprising: providing a planar silicon substrate having an insulating layer provided across a surface thereof, forming a barrier layer across the insulating layer by ALD using water or ozone as a precursor, wherein the barrier layer is an alumina and/or hafnium oxide layer, has a constant thickness of 20 nm or less and provides a growth surface for the CVD growth of uniform graphene at a temperature in excess of 700°C.
9. 9. The method according to claim 8, wherein the barrier layer is alumina and a further precursor for the ALD is a trialkyl aluminium or trialkoxide aluminium, preferably trimethylaluminium, tris(dimethylamido)aluminium, aluminium tris(2,2,6,6-tetramethy1-3.5-heptanedionate) or aluminium tris(acetylacetonate).
10. 10. The method according to claim 8 or claim 9, wherein the wafer is according to any of claims 1 to 5.
11. 11. A method for the manufacture of a laminate, the method comprising: providing the wafer according to any of claims 1 to 5, or obtained by the method of any of claims 8 to 10, and forming a graphene layer on the growth surface of the barrier layer by CVD at a temperature in excess of 700°C.