KR20230146068A - Wide bandgap semiconductor device with sensor element - Google Patents

Abstract

Shielding technologies are used to provide embedded sensor elements, such as temperature sensing elements, on wide bandgap power semiconductor devices. The semiconductor device may include a drift layer and an embedded sensor element. The drift layer may be a wide bandgap semiconductor material. A shielding structure is provided below the embedded sensor element in the drift layer. Embedded sensor elements may be provided between contacts in electrical contact with the shield well. The distance between contacts can be minimized. Noise reduction wells may be provided between the contacts to further isolate the embedded sensor element from parasitic signals.

Description

Wide bandgap semiconductor device with sensor element

Related Applications

This application claims priority to U.S. Patent Application No. 17/201,468, filed March 15, 2021.

Areas of Disclosure

This disclosure relates to semiconductor devices, and more particularly to wide bandgap semiconductor devices including sensor elements.

Wide bandgap semiconductor devices are often used for power applications where the semiconductor device handles high voltages and/or currents. It is often desirable to monitor one or more operating conditions of these wide bandgap power semiconductor devices, such as temperature, current, etc., in order to adjust one or more control signals provided thereto. For example, if the temperature of the device rises above a threshold, it may be desirable to adjust the switching speed of the device or turn it off to avoid damage to the device. Although embedded sensor elements that are monolithically integrated on the device's die are preferred, integrating sensor elements into wide bandgap power semiconductor devices presents several technological challenges that have not yet been overcome. do. Therefore, current solutions rely on individual sensor elements placed in close proximity to the semiconductor die they are measuring. This results in both reduced accuracy and increased area. Accordingly, there is a need for wide bandgap power semiconductor devices with one or more embedded sensor elements.

In one embodiment, the semiconductor device includes a drift layer and an embedded sensor element. The drift layer includes a wide bandgap semiconductor material. By including a sensor element embedded on a wide bandgap semiconductor device, accurate measurement of one or more operating parameters can be achieved in a compact solution.

In one embodiment, the embedded sensor element is a temperature sensing element, such as a diode. The semiconductor device may further include an insulating layer between the embedded sensor element and the drift layer. To provide additional shielding, a shielding well with a doping type opposite to that of the drift layer may be provided below the embedded sensor element in the drift layer. The shielding well can provide additional isolation for the embedded sensor element from parasitic signals. Additionally, an embedded sensor element can be provided between the first and second contacts, both of which are in electrical contact with the shield well and coupled to a fixed potential, such as ground. Coupling the shielding well to a fixed potential can provide additional isolation for the embedded sensor element from parasitic signals. The first contact and the second contact may be electrically coupled to the shielding well through a first contact well and a second contact well, respectively, each of these contact wells having the same doping type as the shielding well and a higher doping than the shielding well. It has a doping concentration. The shielding well may further be provided with a noise reduction well. The noise reduction well may have a doping type opposite to that of the shielding well. The noise reduction well can reduce the resistance at the surface of the drift layer beneath the embedded sensor element, thereby providing additional isolation of the embedded sensor element from parasitic signals. The first and second contacts may also be in electrical contact with the noise reduction well. In another embodiment, a functional layer and an additional insulating layer are provided between the embedded sensor element and the drift layer. The functional layer and additional insulating layer can provide additional isolation for the embedded sensor element from parasitic signals. The distance between the first and second contact wells can be minimized to further improve the isolation of the embedded sensor element from parasitic signals. In various embodiments, the distance between the first contact well and the second contact well is less than 200 μm, less than 100 μm, less than 50 μm, and less than 25 μm.

In one embodiment, a method for manufacturing a semiconductor device includes providing a drift layer and providing an embedded sensor element. The drift layer may include a wide bandgap semiconductor material. By including a sensor element embedded on a wide bandgap semiconductor device, accurate measurement of one or more operating parameters can be achieved in a compact solution.

In one embodiment, the embedded sensor element is a temperature sensing element, such as a diode. The method may further include providing an insulating layer between the embedded sensor element and the drift layer. To provide additional shielding, a shielding well with a doping type opposite to that of the drift layer may be provided below the embedded sensor element in the drift layer. A shielding well can provide additional isolation for the embedded sensor element from parasitic signals. Additionally, an embedded sensor element may be provided between the first and second contacts, both of which are in electrical contact with the shield well and coupled to a fixed potential, such as ground. Coupling the shielding well to a fixed potential can provide additional isolation for the embedded sensor element from parasitic signals. The first contact and the second contact may be electrically coupled to the shielding well through the first and second contact wells, respectively, each of these contact wells having the same doping type as the shielding well and a higher doping concentration than the shielding well. . The shielding well may further be provided with a noise reduction well. The noise reduction well may have a doping type opposite to that of the shielding well. The noise reduction well can reduce the resistance at the surface of the drift layer beneath the embedded sensor element, thereby providing additional isolation of the embedded sensor element from parasitic signals. The first and second contacts may also be in electrical contact with the noise reduction well. In another embodiment, a functional layer and an additional insulating layer are provided between the embedded sensor element and the drift layer. The functional layer and additional insulating layer can provide additional isolation for the embedded sensor element from parasitic signals. The distance between the first and second contact wells can be minimized to further improve the isolation of the embedded sensor element from parasitic signals. In various embodiments, the distance between the first contact well and the second contact well is less than 200 μm, less than 100 μm, less than 50 μm, and less than 25 μm.

In other aspects, any of the foregoing aspects individually or together, and/or various separate aspects and features as described herein may be combined for additional advantage. Any of the various features and elements disclosed herein may be combined with one or more other disclosed features and elements unless otherwise indicated herein.

Those skilled in the art will understand the scope of the disclosure and realize further aspects thereof after reading the following detailed description of preferred embodiments in conjunction with the accompanying drawings.

The accompanying drawings, which are incorporated into and form a part of this specification, illustrate various aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.
1 is a cross-sectional view of a semiconductor die according to one embodiment of the present disclosure.
2 is a cross-sectional view of a semiconductor die according to one embodiment of the present disclosure.
3 is a cross-sectional view of a semiconductor die according to one embodiment of the present disclosure.
4 is a cross-sectional view of a semiconductor die according to one embodiment of the present disclosure.
5 is a cross-sectional view of a semiconductor die according to one embodiment of the present disclosure.
6 is a top view of an embedded sensor element according to one embodiment of the present disclosure.
7 is a top view of an embedded sensor element according to one embodiment of the present disclosure.
8 is a top view of an embedded sensor element according to one embodiment of the present disclosure.
9 is a top view of a portion of a shielding structure for an embedded sensor element according to one embodiment of the present disclosure.
Figure 10 is a top view of a portion of a shielding structure for an embedded sensor element according to one embodiment of the present disclosure.
11A is a cross-sectional view of a functional component according to one embodiment of the present disclosure.
11B is a top view of a functional component according to one embodiment of the present disclosure.
12 is a flow diagram illustrating a method for manufacturing a semiconductor die, according to one embodiment of the present disclosure.
Figure 13 is a cross-sectional view of an embedded sensor element according to one embodiment of the present disclosure.
14 is a top view of a transistor semiconductor die according to one embodiment of the present disclosure.
15 is a top view of a transistor semiconductor die according to one embodiment of the present disclosure.
16 is a top view of a transistor semiconductor die according to one embodiment of the present disclosure.
17 is a top view of a transistor semiconductor die according to one embodiment of the present disclosure.
18 is a cross-sectional view of a transistor semiconductor die according to one embodiment of the present disclosure.
19 is a cross-sectional view of a transistor semiconductor die according to one embodiment of the present disclosure.
20A-20C are graphs illustrating the performance of transistor semiconductor die according to various embodiments of the present disclosure.
21 is a top view of a transistor semiconductor die according to one embodiment of the present disclosure.
22 is a top view of a transistor semiconductor die according to one embodiment of the present disclosure.
23 is a top view of a transistor semiconductor die according to one embodiment of the present disclosure.
Figure 24 is a top view of a transistor semiconductor die according to one embodiment of the present disclosure.
Figure 25 is a top view of a transistor semiconductor die according to one embodiment of the present disclosure.
Figure 26 is a cross-sectional view of a transistor semiconductor die according to one embodiment of the present disclosure.
Figure 27 is a cross-sectional view of a transistor semiconductor die according to one embodiment of the present disclosure.
Figure 28 is a cross-sectional view of a transistor semiconductor die according to one embodiment of the present disclosure.

The embodiments disclosed below present information necessary to enable a person skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawings, a person skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not specifically addressed herein. It should be understood that these concepts and applications are within the scope of this disclosure and the appended claims.

Although the terms first, second, etc. may be used herein to describe various elements, it will be understood that such elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of the present disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

When an element, such as a layer, region, or substrate, is said to be "on" or extending "onto" another element, it may be directly on or extending directly onto the other element, or may have intervening elements. You will also understand that it can exist. In contrast, when an element is said to be “directly on” or extend “directly onto” another element, no intervening elements are present. Likewise, when an element, such as a layer, region, or substrate, is said to be "over" or extend "over" another element, it means that it is directly over or extends directly over the other element. It will be understood that or intervening elements may also be present. In contrast, when an element is said to be “directly on” or “extending directly over” another element, no intervening elements are present. It will also be understood that when an element is said to be “connected” or “coupled” to another element, it may be directly connected or coupled to the other element or there may be intervening elements. In contrast, when an element is said to be "directly connected" or "directly coupled" to another element, no intervening elements are present.

Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” are used in the drawings. It may be used herein to describe the relationship of one element, layer, or area as shown to another element, layer, or area. It will be understood that these terms and the preceding terms are intended to encompass different orientations of the device in addition to the orientation shown in the figures.

The terminology used herein is for the purpose of describing specific embodiments only and is not intended to limit the disclosure. As used herein, the singular forms “a”, “an”, and “the” are intended to include the plural forms as well, unless the context clearly dictates otherwise. The terms “comprises,” “comprising,” “includes,” and/or “including,” when used herein, refer to the described features, integers, etc. , steps, operations, elements, and/or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It will be understood as

Unless otherwise defined, all terms (including technical and scientific terms) used in this specification have the same meaning as commonly understood by a person skilled in the art to which this disclosure pertains. Terms used in this specification should be interpreted to have meanings consistent with their meanings in the context of this specification and related technology, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such in this specification. You will understand more.

Embodiments are described herein with reference to schematic illustrations of embodiments of the present disclosure. Accordingly, the actual dimensions of the layers and elements may differ, and variations from the shapes of the examples are expected, for example, as a result of manufacturing techniques and/or tolerances. For example, areas illustrated or described as square or rectangular may have rounded or curved features, and areas shown as straight lines may have some irregularities. Accordingly, the areas illustrated in the drawings are schematic, and their shapes are not intended to illustrate the exact shape of an area of the device, nor are they intended to limit the scope of the disclosure. Additionally, the sizes of structures or regions may be exaggerated relative to other structures or regions for illustrative purposes and, accordingly, are provided to illustrate general structures of the subject matter and may be drawn to scale or Maybe not. Common elements between the drawings may be shown herein with common element numbers and may not be subsequently redescribed.

1 shows a cross-sectional view of a semiconductor die 10 according to one embodiment of the present disclosure. Semiconductor die 10 includes a substrate 12, a drift layer 14 on substrate 12, and an insulating layer 16 on drift layer 14. The semiconductor die 10 has an active area 18 provided with one or more implanted areas to form a functional semiconductor device, and an edge termination area surrounding the active area 18. termination region) (20). Somewhere within the edge termination area 20, an embedded sensor element 22 is provided. In some embodiments, embedded sensor element 22 is on insulating layer 16 and thus insulating layer 16 is between embedded sensor element 22 and drift layer 14.

As described above, one or more implanted regions are provided in active region 18 to form a functional semiconductor device. In one embodiment, the functional semiconductor device is a switching power semiconductor device. For example, functional semiconductor devices include metal-oxide-semiconductor field-effect transistors (MOSFETs), especially vertical MOSFETs, bipolar junction transistors (BJTs), and isolated It may be an insulated gate bipolar transistor (IGBT), a junction field-effect transistor (JFET), a gate-controlled thyristor (GTO), etc. Additionally, the functional semiconductor device may be in any suitable topology, such as planar, vertical, and trench devices. Accordingly, the substrate 12 and/or drift layer 14 includes wide bandgap materials such as silicon carbide, gallium nitride, gallium oxide, and zinc oxide. This may be because these materials may be advantageous in devices intended to handle high voltages and/or currents. As mentioned above, sensor elements integrated within wide bandgap power semiconductor devices present several technical challenges. In particular, wide bandgap materials have significantly higher sheet resistance than their narrow bandgap counterparts. This high resistance, combined with the high voltages and currents handled by the power devices, causes large parasitic signals that interfere with the operation of the embedded sensor elements. For narrow bandgap semiconductor devices, such as silicon devices, the sensor elements can in many cases be integrated directly within the drift layer, or otherwise provided with minimal shielding from parasitic signals, while these same devices They will not function when embedded within a wide bandgap power semiconductor device.

Another obstacle to implementing embedded sensor elements in wide bandgap power semiconductor devices is cost. Manufacturing for narrow bandgap power semiconductor devices, such as silicon devices, is inexpensive, and the extra process steps add little extra cost, but for wide bandgap power semiconductor devices, each extra process step costs a significant amount of money. Add costs. Therefore, it is desirable to implement embedded sensor elements using as few additional manufacturing steps as possible.

As defined herein, a power semiconductor device is a semiconductor device with an avalanche breakdown voltage of 50V or greater. As discussed above, the high voltages and currents handled by these devices can generate parasitic signals that present challenges to the implementation of embedded sensor elements. The relatively high sheet resistance of wide bandgap semiconductor materials further complicates the implementation of embedded sensor elements.

One way to isolate the embedded sensor element 22 is to provide an insulating layer 16 between the embedded sensor element 22 and the drift layer 14. In one embodiment, insulating layer 14 is an oxide layer, such as a field oxide layer. For example, the insulating layer 14 may comprise one or more layers of Al ₂ O ₃ and SiO ₂ individually or alternatingly and/or one or more layers of Si ₃ N ₄ and SiO ₂ individually or alternatingly. It can be included. Accordingly, the insulating layer 14 may already exist on the semiconductor die 10. For example, insulating layer 14 may form a gate oxide in some regions of semiconductor die 10 and a field oxide in other regions of semiconductor die 10. Accordingly, the insulating layer 14 is already available without additional manufacturing steps. Additionally, the embedded sensor element 22 may be provided in an already existing polysilicon layer to create a functional semiconductor device on the semiconductor die 10. For example, the polysilicon layer may form a gate electrode and/or gate contact in some portions of semiconductor die 10. Accordingly, the layer used to provide the embedded sensor element 22 is already available without additional manufacturing steps other than reworking the mask used to deposit the layer. To create the functionality of the embedded sensor element 22 (e.g. to create a diode, lumped resistor, etc.) on that part of the polysilicon layer that provides the embedded sensor element 22. More than one implant may be required, details of which are discussed below. These extra manufacturing steps are the minimum number necessary to provide embedded sensor element 22, thereby minimizing the cost of embedded sensor element 22.

The polysilicon layer used to provide the gate electrode and/or contact and sensor elements 22 may be a doped polysilicon layer provided through any suitable process. In some embodiments, the polysilicon layer is provided through an epitaxial growth process in which dopants are provided in air to create the desired doping profile. In other embodiments, the polysilicon layer can be deposited and then doped as desired through an implantation process. As discussed above, ion implantation may be the preferred approach when providing sensor element 22 because it may require separately doped regions to provide a diode or other sensing device. Ion implantation can also provide other benefits, such as improving the uniformity of the sheet resistance of the polysilicon layer by 5-10% in some embodiments and by 10-20% in other embodiments. This is due to the use of heavy dopant ions, such as boron-diflouride (BF2), which can break down the crystal structure of the polysilicon layer into smaller crystal sizes.

Although the insulating layer 16 may provide some degree of isolation for the embedded sensor element 22, more isolation may be desirable in some scenarios. Accordingly, Figure 2 shows a cross-sectional view of the semiconductor die 10 showing additional details of the embedded sensor element 22. For illustration purposes, MOSFET cell 24 is shown adjacent to embedded sensor element 22. However, as discussed above, this is by way of example only, and any number of functional semiconductor devices, such as BJTs, IGBTs, and thyristors, may be provided in place of or in addition to MOSFET cell 24.

MOSFET cell 24 includes a pair of junction implants 26 separated by a junction field effect transistor (JFET) region 28. Each of the junction implants 26 includes a deep well region 30, a source region 32, and a body region 34. Gate oxide 36, which is part of insulating layer 16, is over JFET region 28 and a portion of each of junction implants 26 on drift layer 14, as shown. Source contact 38 is over a portion of each of the junction implants 26 on drift layer 14, as also shown. Gate contact 40 is on gate oxide 36. Drain contact 42 is on substrate 12 opposite drift layer 14. As shown, MOSFET cell 24 is an n-type device, with a substrate 12, drift layer 14, deep well regions 30, source regions 32, and body regions 34. , and JFET regions 28 are labeled with their doping types and relative doping concentrations to each other (“+” indicates a higher doping level compared to other regions). However, the principles of this disclosure apply equally to p-type devices in which all doping types shown are inverted. Those skilled in the art will recognize MOSFET cell 24 as a vertical MOSFET, particularly a double diffusion MOSFET (DMOS). Additionally, those skilled in the art will appreciate that MOSFET cells 24 are provided throughout active region 18 and are interconnected to provide a MOSFET with a number of desired characteristics, such as a desired on-state resistance and a desired blocking voltage. You will see that it is just one of many cells that are connected. The examples described throughout this application show a MOSFET cell 24 along with details of an embedded sensor element 22, but the embedded sensor element 22 may also be a BJT cell, IGBT cell, JFET cell, GTO cell. It may be provided together with etc. Additionally, the embedded sensor element 22 could also be provided with a planar or trench device, rather than the vertical device shown.

Looking at the details of embedded sensor element 22, embedded sensor element 22 may include one or more layers on field oxide 44 that are part of insulating layer 16 on drift layer 14. In particular, the embedded sensor element 22 may include a functional sensor layer 52 and a sensor contact layer 54 . Notably, functional sensor layer 52 is part of a polysilicon layer that is also used to provide gate contact 40. That is, gate contact 40 and functional sensor layer 52 are formed from the same layer (eg, patterned using a mask). As mentioned above, this saves manufacturing steps and thus allows the implementation of the embedded sensor element 22 with minimal additional costs. As shown in Figure 2, field oxide 44 is much thicker than gate oxide 36 due to their different functions. While gate oxide 36 acts as a dielectric to provide gate capacitance, field oxide 44 is used to provide electrical isolation and shielding for various portions of semiconductor die 10.

Below the sensor element 22 embedded in the drift layer 14, a shielding well 46 is provided. Drift layer 14 is an n-type layer, while shielding well 46 is a p-type region. More generally, shield well 46 has a doping type opposite to that of drift layer 14. Shielding well 46 may in some embodiments be an implanted area in drift layer 14, but may generally be provided by any suitable means. The shield well 46 forms a P-N junction with the drift layer 14 to block DC voltages at the surface of the drift layer 14 below the sensor element 22 in which the shield well is embedded. In shield well 46, a first contact well 48A and a second contact well 48B are provided. First contact well 48A and second contact well 48B are p-type regions with a higher doping concentration than shield well 46. First contact well 48A and second contact well 48B may be implanted regions in drift layer 14, but may also be provided by any suitable means. The contact wells 48 are electrically coupled to the shield well 46 such that the first contact 50A and the second contact 50B are electrically coupled to the shield well 46 via the first contact well 48A and the second contact well 48B, respectively. An ohmic connection to the shield well 46 is provided for first contact 50A and second contact 50B. To further shield the embedded sensor element 22 from parasitic voltages and currents, first contact 50A and second contact 50B are coupled to a fixed potential, such as ground. In other embodiments, first contact 50A and second contact 50B are coupled to source contacts 38 of MOSFET cell 24 or otherwise connected to a specific functional semiconductor device on semiconductor die 10. part can be connected. Coupling first contact 50A and second contact 50B to a fixed potential or to a specific portion of a functional semiconductor device on semiconductor die 10 may cause transient signals in drift layer 14 (e.g. For example, AC signals) can reduce parasitic currents in the shield well 46. This is important because the shielding well 46 has a finite resistance and therefore any parasitic currents in the shielding well 46 will create a voltage at the surface of the drift layer 14 beneath the embedded sensor element 22. . These voltages may be capacitively coupled to the embedded sensor element 22 via the field oxide 44, which will interfere with its operation. In various embodiments, first contact 50A and second contact 50B, as well as source contact 38 and drain contact 42, may include any suitable ohmic metal, such as aluminum, titanium, and titanium nitride. You can. Although not shown, a metal contact layer may also be bonded to gate contact 40 to form a gate contact pad. This additional metal contact layer may also include any suitable ohmic metal such as aluminum, titanium and titanium nitride.

Those skilled in the art will know that wide bandgap semiconductor materials have much higher resistivity than their narrow bandgap counterparts. This is generally beneficial for power devices because it allows the power devices to support higher voltages without breakdown, but it is difficult to implement for embedded sensors due to their tendency to generate large parasitic signals that interfere with their operation. It presents unique technical challenges. As shown in Figure 2, there is a distance D between the first contact well 48A and the second contact well 48B. An embedded sensor element 22 is provided within this distance D between the first contact well 48A and the second contact well 48B. A first contact well ( It is desirable to minimize the distance D between 48A) and the second contact well 48B. The resistance of the shielding well 46 at the midpoint between the first contact well 48A and the second contact well 48B is proportional to the distance D between the first contact well 48A and the second contact well 48B. do. By minimizing the distance D, resistance can also be minimized. In one embodiment, the distance D between first contact well 48A and second contact well 48B is less than 200 μm. In other embodiments, the distance D between first contact well 48A and second contact well 48B is as low as less than 100 μm, less than 50 μm, less than 25 μm, and 5 μm. The smaller the distance between first contact well 48A and second contact well 48B, the lower the resistance through shielding well 46. This results in lower interference in the embedded sensor element 22 due to the reduction of parasitic voltages within the shield well 46.

Minimizing the distance D between the first contact well 48A and the second contact well 48B means that the embedded sensor element 22 is generally in and/or out of the page as shown in FIG. 2 . Or it means that it will be provided as a long thin strip extending outwards. Embedded sensor element 22 may be any type of sensing element, such as a diode, resistor, etc., that can provide voltage and/or current proportional to the measurement of interest. For example, a diode may be provided by implanting an n-type region and/or a p-type region in the functional sensor layer 52, which is the same polysilicon layer used for the gate contact 40 as discussed above. . In some embodiments, the polysilicon layer may already be doped in one way or the other (e.g. as a p-type layer) and thus only have one implant (e.g. forming an n-type region). injection is required to do so. The diode can provide a forward voltage drop that is proportional to temperature, thereby allowing an external sensing circuit to measure the temperature of semiconductor die 10. Exemplary details of the embedded sensor element 22 are provided below.

To further reduce parasitic signals coupled into the embedded sensor element 22, the shielding well 46 may be provided with a noise reduction well 56, as shown in Figure 3. Noise reduction well 56 has an opposite doping type to shielding well 46 and is connected to first contact 50A and second contact 50B through first contact well 48A and second contact well 48B, respectively. makes electrical contact with In the example shown in Figure 3, noise reduction well 56 is an n-type region. Noise reduction well 56 may be an implanted area in drift layer 14, but may also be provided by any suitable means. Those skilled in the art will appreciate that n-type wide bandgap semiconductor materials often have resistances that are up to three orders of magnitude lower than their p-type counterparts. By providing a noise reduction well 56, the resistance at the surface of the drift layer 14 below the embedded sensor element 22 can be further reduced, which in turn causes parasitic signals to couple to the embedded sensor element 22. can be reduced.

As discussed above, functional sensor layer 52 is part of a polysilicon layer that also provides gate contact 40. This may save manufacturing steps, but it may also prevent the layer from being metallized or silicided, since doing so would not allow the functional sensor layer 52 to provide a sensing element. This is because metallization or silicidation are generally blanket processes that affect the entire polysilicon layer. Metallization or silicidation of the polysilicon layer providing the gate contact may be desirable because it can reduce the resistance and thus improve the distribution of gate signals throughout the semiconductor die 10, thereby improving switching speeds and other This is because performance characteristics can be improved. Additionally, additional isolation may be required between the embedded sensor element 22 and the drift layer 14, also by the shielding well 46 and the noise reduction well 56. Accordingly, Figure 4 shows an embedded sensor element 22 with additional isolation according to one embodiment of the present disclosure. The semiconductor die 10 shown in FIG. 4 is similar to that of FIG. 2 except that there is an additional insulating layer 58 and an additional functional layer 60 between the embedded sensor element 22 and the drift layer 14. It is substantially the same as shown in . In this embodiment, the functional sensor layer 52 is not part of the same layer used to form gate contact 40, but rather a “second-level layer” in addition to that used to form gate contact 40. “It’s a polysilicon layer. Additional functional layer 60 as shown in FIG. 4 is part of the same layer used to form gate contact 40, which may be a polysilicon layer in various embodiments as described above. Additional functionality to provide embedded sensor element 22 such that insulating layer 16, additional functional layer 60, and additional insulating layer 58 are between embedded sensor element 22 and drift layer 14. Two additional layers are provided above layer 60, namely an additional insulating layer 58 and a functional sensor layer 52. The additional two layers provide increased shielding of the embedded sensor element 22 while adding only two additional layers as needed. Additional insulating layer 58 may include any suitable insulating material, such as SiO ₂ . The functional sensor layer 52 may be a second-level polysilicon layer, provided in a similar manner to the first polysilicon layer providing the gate contact 40 and additional functional layer 60 as described above. The second-level polysilicon layer adds additional manufacturing steps to create the semiconductor die 10, but can provide advantages such as allowing the first polysilicon layer to be metallized or silicided, as described above. As discussed, the performance of semiconductor die 10 can be improved.

To provide even more shielding, a noise reduction well 56 may be added to the semiconductor die 10 shown in FIG. 4. One such embodiment is shown in Figure 5. As discussed above, noise reduction well 56 can further reduce parasitic voltages at the surface of drift layer 14 beneath embedded sensor element 22 by reducing the resistance in this region. Accordingly, interference with the embedded sensor element 22 can be reduced even further. Although not shown in FIGS. 4 or 5 , in embodiments in which the additional functional layer 60 is partially or fully metallized and/or silicided, the contacts 50 are electrically coupled to the additional functional layer 60 . can be combined This may provide additional isolation for the embedded sensor element 22.

In the above-described embodiments, the substrate 12 may be an n-type layer with a thickness between 0.2 μm and 10.0 μm and a doping concentration between 1×10 ¹⁷ cm ⁻³ and 5×10 ²¹ cm ⁻³ . Drift layer 14 may be an n-type layer with a thickness between 1.0 μm and 20.0 μm and a doping concentration between 1×10 ¹⁵ cm ⁻³ and 1×10 ¹⁷ cm ⁻³ . Shielding well 46 may be a p-type region with a thickness between 0.1 μm and 3.0 μm and a doping concentration between 1×10 ¹⁷ cm ⁻³ and 5×10 ²¹ cm ⁻³ . In various embodiments, the thickness of shielding well 46 may be provided in any subrange between 0.1 μm and 3.0 μm, or at any discrete point within the range. For example, the thickness of the shielding well 46 may be between 0.1 μm and 2.5 μm, between 0.1 μm and 2.0 μm, between 0.1 μm and 1.5 μm, between 0.1 μm and 1.0 μm, between 0.1 and 0.5 μm, between 0.5 and 3.0 μm. Between, between 1.0μm and 3.0μm, between 1.5μm and 3.0μm, between 2.0μm and 3.0μm, between 2.5μm and 3.0μm, between 0.5μm and 2.5μm, between 1.0μm and 2.0μm, between 1.5μm and 2.0μm It may be, etc. Additionally, the doping concentration of shielding well 46 may be provided in any subrange between 1×10 ¹⁷ cm ⁻³ and 5×10 ²¹ cm ⁻³ , or at any discrete point within the range. For example, the doping concentration of shielding well 46 is between 5×10 ¹⁷ cm ^-3 and 5×10 ²¹ cm ^-3 , between 1×10 ¹⁸ cm ^-3 and 5×10 ²¹ cm ^-3 , and 5×10 Between ¹⁸ cm ^-3 and 5×10 ²¹ cm ^-3 , between 1×10 ¹⁹ cm ^-3 and 5×10 ²¹ cm ^-3 , between 5×10 ¹⁹ cm ^-3 and 5×10 ²¹ cm ^-3 , 1× Between 10 ²⁰ cm ^-3 and 5×10 ²¹ cm ^-3 , between 5×10 ²⁰ cm ^-3 and 5×10 ²¹ cm ^-3 , between 1×10 ²¹ cm ^-3 and 5×10 ²¹ cm ^-3 , 1 Between ×10 ¹⁷ cm ^-3 and 1×10 ²¹ cm ^-3 , between 1×10 ¹⁷ cm ^-3 and 5×10 ²⁰ cm ^-3 , between 1×10 ¹⁷ cm ^-3 and 1×10 ²⁰ cm ^-3 , Between 1×10 ¹⁷ cm ^-3 and 5×10 ¹⁹ cm ^-3 , between 1×10 ¹⁷ cm ^-3 and 1×10 ¹⁹ cm ^-3 , between 1×10 ¹⁷ cm ^-3 and 5×10 ¹⁸ cm ^-3 , between 1×10 ¹⁷ cm ^-3 and 1×10 ¹⁸ cm ^-3 , between 1×10 ¹⁷ cm ^-3 and 5×10 ¹⁷ cm ^-3 , between 5×10 ¹⁷ cm ^-3 and 1×10 ²¹ cm ^-3 between 1 × 10 ¹⁸ cm ^-3 and 5 × 10 ²⁰ cm ^-3 , between 5 × 10 ¹⁸ cm ^-3 and 1 × 10 ²⁰ cm ^-3 , and between 1 × 10 ¹⁹ cm ^-3 and 5 × 10 ¹⁹ cm It can be between ^-3 . Each of the contact wells 48 may be a p-type region with a thickness between 0.1 μm and 2.5 μm and a doping concentration between 1×10 ¹⁷ cm ⁻³ and 5×10 ²¹ cm ⁻³ . In various embodiments, the thickness of contact wells 48 may be provided within any subrange between 0.1 μm and 2.5 μm, or at any discrete point within the range. For example, the thickness of the contact wells 48 may be between 0.5 μm and 2.5 μm, between 1.0 μm and 2.5 μm, between 1.5 μm and 2.5 μm, between 2.0 μm and 2.5 μm, between 0.1 μm and 2.0 μm, between 0.1 μm and It may be between 1.5 μm, between 0.1 μm and 1.0 μm, between 0.1 μm and 0.5 μm, between 0.5 μm and 2.0 μm, and between 1.0 μm and 1.5 μm. Additionally, the doping concentration of the contact wells 48 may be provided in any subrange between 1×10 ¹⁷ cm ⁻³ and 5×10 ²¹ cm ⁻³ , or at any discrete point within the range. For example, the doping concentration of contact wells 48 is between 5×10 ¹⁷ cm ⁻³ and 5×10 ²¹ cm ⁻³ , between 1×10 ¹⁸ cm ⁻³ and 5×10 ²¹ cm ⁻³ , and 5×10 Between ¹⁸ cm ^-3 and 5×10 ²¹ cm ^-3 , between 1×10 ¹⁹ cm ^-3 and 5×10 ²¹ cm ^-3 , between 5×10 ¹⁹ cm ^-3 and 5×10 ²¹ cm ^-3 , 1× Between 10 ²⁰ cm ^-3 and 5×10 ²¹ cm ^-3 , between 5×10 ²⁰ cm ^-3 and 5×10 ²¹ cm ^-3 , between 1×10 ²¹ cm ^-3 and 5×10 ²¹ cm ^-3 , 1 Between ×10 ¹⁷ cm ^-3 and 1×10 ²¹ cm ^-3 , between 1×10 ¹⁷ cm ^-3 and 5×10 ²⁰ cm ^-3 , between 1×10 ¹⁷ cm ^-3 and 1×10 ²⁰ cm ^-3 , Between 1×10 ¹⁷ cm ^-3 and 5×10 ¹⁹ cm ^-3 , between 1×10 ¹⁷ cm ^-3 and 1×10 ¹⁹ cm ^-3 , between 1×10 ¹⁷ cm ^-3 and 5×10 ¹⁸ cm ^-3 , between 1×10 ¹⁷ cm ^-3 and 1×10 ¹⁸ cm ^-3 , between 1×10 ¹⁷ cm ^-3 and 5×10 ¹⁷ cm ^-3 , between 5×10 ¹⁷ cm ^-3 and 1×10 ²¹ cm ^-3 between 1 × 10 ¹⁸ cm ^-3 and 5 × 10 ²⁰ cm ^-3 , between 5 × 10 ¹⁸ cm ^-3 and 1 × 10 ²⁰ cm ^-3 , and between 1 × 10 ¹⁹ cm ^-3 and 5 × 10 ¹⁹ cm It can be between ^-3 . Noise reduction well 56 may be an n-type region with a thickness between 0.1 μm and 2.5 μm and a doping concentration between 1×10 ¹⁷ cm ⁻³ and 5× ^{10 21} cm ⁻³ . In various embodiments, the thickness of noise reduction well 56 may be provided within any subrange between 0.1 μm and 2.5 μm, or at any discrete point within the range. For example, the thickness of the noise reduction well 56 may be between 0.5 μm and 2.5 μm, between 1.0 μm and 2.5 μm, between 1.5 μm and 2.5 μm, between 2.0 μm and 2.5 μm, between 0.1 μm and 2.0 μm, and between 0.1 μm. It may be between and 1.5μm, between 0.1μm and 1.0μm, between 0.1μm and 0.5μm, between 0.5μm and 2.0μm, and between 1.0μm and 1.5μm. Additionally, the doping concentration of noise reduction well 56 may be provided in any subrange between 1×10 ¹⁷ cm ⁻³ and 5×10 ²¹ cm ⁻³ , or at any discrete point within the range. For example, the doping concentration in noise reduction well 56 is between 5×10 ¹⁷ cm ^-3 and 5·10 ²¹ cm ^-3 , between 1×10 ¹⁸ cm ^-3 and 5×10 21 cm -3 , and 5×10 ²¹ cm ^-3 . Between 10 ¹⁸ cm ^-3 and 5×10 ²¹ cm ^-3 , between 1×10 ¹⁹ cm ^-3 and 5×10 ²¹ cm ^-3 , between 5×10 ¹⁹ cm ^-3 and 5×10 ²¹ cm ^-3 , 1 Between ×10 ²⁰ cm ^-3 and 5×10 ²¹ cm ^-3 , between 5×10 ²⁰ cm ^-3 and 5×10 ²¹ cm ^-3 , between 1×10 ²¹ cm ^-3 and 5×10 ²¹ cm ^-3 , Between 1×10 ¹⁷ cm ^-3 and 1×10 ²¹ cm ^-3 , between 1×10 ¹⁷ cm ^-3 and 5×10 ²⁰ cm ^-3 , between 1×10 ¹⁷ cm ^-3 and 1×10 ²⁰ cm ^-3 , between 1×10 ¹⁷ cm ^-3 and 5×10 ¹⁹ cm ^-3 , between 1×10 ¹⁷ cm ^-3 and 1×10 ¹⁹ cm ^-3 , between 1×10 ¹⁷ cm ^-3 and 5×10 ¹⁸ cm ^-3 between 1×10 ¹⁷ cm ^-3 and 1×10 ¹⁸ cm ^-3 between 1×10 ¹⁷ cm ^-3 and 5×10 ¹⁷ cm ^-3 between 5×10 ¹⁷ cm ^-3 and 1×10 ²¹ cm ^{-3 3} , between 1×10 ¹⁸ cm ^-3 and 5×10 ²⁰ cm ^-3 , between 5×10 ¹⁸ cm ^-3 and 1×10 ²⁰ cm ^-3 , and between 1×10 ¹⁹ cm ^-3 and 5×10 ¹⁹ It may be between cm ^-3 .

The improvements discussed above include separating the embedded sensor element 22 from the drift layer 14 with an insulating layer 16, providing a shielding well 46, and minimizing the distance between contact wells 48. and providing a noise reduction well 56, providing an additional insulating layer 58, and providing an additional functional layer 60, alone or in combination, provide an embedded sensor element from the drift layer 14. The isolation of (22) can be significantly improved. In particular, the improvements discussed herein can provide greater than 50V DC isolation from high power portions of the semiconductor die 10, such as its source and drain. In various embodiments, the improvements discussed herein can provide DC isolation of greater than 75V and greater than 100V. In general, the improvements discussed herein make it possible to include embedded sensor elements on wide bandgap power semiconductor die because, without such isolation means, such embedded sensor elements would be subject to interference that would destroy their functionality. Because you will receive.

As discussed above, embedded sensor element 22 may be any suitable sensing element. In one embodiment, embedded sensor element 22 is a temperature sensing element. In particular, the embedded sensor element 22 may be a diode that provides a forward voltage drop proportional to temperature. Accordingly, Figure 6 shows a top view of an embedded sensor element 22 according to one embodiment of the present disclosure. For context, first contact 50A and second contact 50B are also shown. The embedded sensor element 22 includes an anode contact 62 and a cathode contact 64. Anode contact 62 is in electrical contact with p-type region 66 in functional sensor layer 52. Cathode contact 64 is in electrical contact with n-type region 68 in functional sensor layer 52. The p-type region 66 and/or n-type region 68 may be provided through an implantation process of the functional sensor layer 52 according to well-known processes. As shown, p-type region 66 and n-type region 68 may be separated by a region of material. These material regions may be intrinsic (undoped) or doped in a different manner than p-type region 66 and n-type region 68.

In some scenarios, it may be desirable to provide multiple diodes in series to tailor the forward voltage for a particular sensing circuit. Accordingly, Figure 7 shows a top view of an embedded sensor element 22 according to a further embodiment of the present disclosure. The embedded sensor element 22 shown in Figure 7 is substantially the same as that shown in Figure 6 except that it includes two diodes instead of one. The functional sensor layer 52 is separated into two distinct parts, each of which is used to form an individual diode. These diodes are bonded together through a metal layer as shown. Although only two diodes are shown, those skilled in the art will understand that embedded sensor element 22 may include any number of individual elements, including diodes, without departing from the principles of the present disclosure. will be.

8 shows a top view of an embedded sensor element 22 according to a further embodiment of the present disclosure. The embedded sensor element 22 shown in Figure 8 is similar to that of Figure 7, except that the p-type region 66 and n-type region 68 can be overlapped to reduce the area required for each diode. Substantially similar to what is shown. Those skilled in the art will understand that diodes can be formed using any number of layout techniques, all of which are contemplated herein.

In some embodiments, noise reduction well 56 is a blanket area underneath the entirety of embedded sensor element 22. However, this may present parasitic N-P-N transistors which can be problematic in some situations. Accordingly, noise reduction well 56 may be patterned in some embodiments as shown in FIGS. 9 and 10. 9 and 10 show top views of the noise reduction well 56 without embedded sensor elements 22 or insulating layer 16 to avoid obscuring the drawing. In Figure 9, the noise reduction wells 56 are provided in a first wide grid pattern, while in Figure 10 the noise reduction wells 56 are provided in a tight grid pattern. In particular, these are merely example patterns, and those skilled in the art will readily appreciate that any suitable pattern may be used for the noise reduction well 56 without departing from the principles of the present disclosure.

Returning to the embodiment discussed above with respect to FIGS. 4 and 5 , providing an embedded sensor element 22 on a second-level polysilicon layer may include the inclusion of other functional components in addition to the embedded sensor element 22. Implementation may be permitted. For example, a lumped resistor that can be used as a gate resistor for a MOSFET can be implemented in the second polysilicon layer with an embedded sensor element 22. Accordingly, Figure 11A shows a cross-sectional view of lumped resistor 70 according to one embodiment of the present disclosure. A lumped resistor 70 is provided in the same functional layer 52 as the functional sensor layer 52 discussed above. Specifically, lumped resistor 70 is provided through a doped portion of polysilicon having a first resistor contact 72A and a second resistor contact 72B, as shown in the plan view of the lumped resistor in FIG. 11B. do. Lumped resistor 70 may be coupled to gate contact 40 of MOSFET cell 24 to provide an on-chip gate resistor. In some embodiments, one of the resistor contacts 72 may provide a gate contact pad. In such a case, only one of the resistor contacts 72 may be provided and lumped resistor 70 may be coupled internally to the gate contact. However, in other embodiments, one of the resistor contacts 72 may be a gate contact pad, and the other may be used to measure the resistance of lumped resistor 70 during manufacturing to ensure that the desired resistance is achieved. It can be exposed to allow it. As discussed above, the functional sensor layer 52 may be a polysilicon layer that is doped during growth (in-situ) or later doped through an implantation process, such as ion implantation, to provide the desired resistance. Although lumped resistor 70 is shown as a simple rectangle in FIGS. 11A and 11B, lumped resistor 70 may be provided in any number of shapes. For example, the portion of functional sensor layer 52 that forms lumped resistor 70 may be provided as circular, polygonal, or any other shape. Providing lumped resistor 70 in this manner can improve performance when lumped resistor 70 is used as a gate resistor by improving current distribution and/or reducing parasitic signals. Those skilled in the art will appreciate that, in addition to resistors, other functional components can also be implemented in the second-level polysilicon layer.

Although not shown in the figures above, various metal contacts such as source contact 38, drain contact 42, contacts 50 and resistor contacts 72 are provided directly on the area to which they are electrically coupled. It may not work. Rather, any number of passivation or encapsulation layers may separate these contacts from the areas of the semiconductor die 10 they contact, and connections between them may be provided with vias through these layers. .

12 is a flow diagram illustrating a method for manufacturing a semiconductor die including an embedded sensor element, according to one embodiment of the present disclosure. First, a drift layer is provided on the substrate (step 100). The drift layer includes a wide bandgap semiconductor material. Providing a drift layer may include growing the drift layer according to any suitable semiconductor growth processes. One or more implants are provided in the drift layer to provide a shielding structure for embedded sensor elements as well as functional semiconductor devices such as MOSFETs, BJTs, IGBTs, or thyristors (step 102). The shielding structure for the embedded sensor element may include one or more of the shielding wells, contact wells, and noise reduction wells discussed above. Implanted areas may be provided by any suitable implantation process. An insulating layer is provided on the drift layer (step 104). The insulating layer may provide a gate oxide and a field oxide in different portions of the semiconductor die and thus may be provided with different thicknesses in the different portions. Gate contact and functional sensor layers are provided on the insulating layer (step 106). The gate contact and functional sensor layer may be a polysilicon layer provided by any suitable deposition process. The polysilicon layer can be deposited and patterned to create the gate contact and functional sensor layer. In some embodiments, the gate contact and functional sensor layer are not provided simultaneously. Instead, a gate contact and an additional polysilicon layer are provided together, an additional insulating layer is provided on the additional polysilicon layer, and a functional sensor layer is provided on the additional insulating layer. The results of this approach are shown in Figures 4 and 5 above. Next, one or more implanted regions are provided in the functional sensor layer to provide embedded sensor elements (step 108). For example, a p-type region and/or an n-type region may be provided to form a diode used as a temperature sensor. Finally, a metal layer is provided, at least a portion of which is used to provide electrical contacts to the shielding structure and embedded sensor element (step 110). In some embodiments, multiple metal layers may be provided, with passivation or intermetallic dielectric layers provided in between.

13 shows a cross-sectional view of an embedded sensor element 22 according to one embodiment of the present disclosure. The embedded sensor element 22 has a cross-sectional view perpendicular to that shown in FIG. 2 (i.e., across the embedded sensor element 22 to the ground with reference to FIG. 2 ) and has a pair of sensor contact pads 74 ) is substantially similar to that shown in Figure 2, except that is shown. Those skilled in the art will appreciate that in order to make electrical connection with a portion of a semiconductor die, a contact pad must be provided with certain minimum dimensions. Minimum dimensions may be based on the minimum size at which the desired electrical connection, such as one or more wirebonds, can be achieved within specific process constraints. Since the sensor contact layer 54 shown in FIG. 2 may be coplanar with one or more other metal features (e.g., source contact 38, contacts 50, gate metal layer, etc.), The area available for contact pads within this layer may be limited such that the contact pads do not overlap and therefore make electrical contact with these features. Accordingly, Figure 13 shows contacts 50 implemented in a first metal layer 76A and sensor contact pads 74 implemented in one or more additional metal layers 76B. An intermetallic dielectric layer 78 is provided over the first metal layer 76A and provides a surface on which sensor contact pads 74 may be provided. In particular, when sensor contact pads 74 are provided on intermetallic dielectric layer 78, they may overlap contacts 50 in the underlying first metal layer 76, thereby providing contact pads. There is a lot more space to do it. By moving the sensor contact pads 74 onto an additional metal layer, the area available for the sensor contact pads 74 is increased. This may provide more reliable contact with the embedded sensor element 22 and thus may improve performance in some embodiments.

To further illustrate aspects of the disclosure in which one or more additional metal layers are used to provide space for contact pads, FIG. 14 shows a top view of a transistor semiconductor die 210 according to one embodiment of the disclosure. It shows. For purposes of illustration, transistor semiconductor die 210 is a vertical metal-oxide-semiconductor electric field-comprising a passivation layer 212 with openings for a gate contact pad 214 and a plurality of source contact pads 216. It is an effect transistor (MOSFET) device. Transistor semiconductor die 210 is a vertical power device with a drain contact pad (not shown) located on the back side of the device. Gate contact pad 214 and source contact pads 216 may serve as surfaces for coupling transistor semiconductor die 210 to external circuitry. Accordingly, the gate contact pad 214 and source contact pads 216 may have a minimum size so that they can be reliably connected. In one embodiment, the minimum size of each of gate contact pad 214 and source contact pads 216 is 0.4 mm ² . In various embodiments, the minimum size of gate contact pad 214 and source contact pads 216, respectively, is 0.5 mm ² , 0.6 mm ² , 0.7 mm ² , 0.8 mm ² , 0.9 mm ² and a maximum of 1.0 mm ² . You can.

Figure 15 shows a top view of the transistor semiconductor die 210 with the passivation layer 212 removed. Below the passivation layer 212 is a gate metal layer 218, a gate via bar 220 coupled to the gate metal layer 218, and a source metal layer 222. As discussed in more detail below, gate metal layer 218, gate via bar 220, and source metal layer 222 are provided by the same metallization layer, and thus source metal layer 222 is as shown. As shown, an opening 224 should be included to accommodate the entire area of the gate metal layer 218 and gate via bar 220. Figure 15 also shows device region 226 and edge termination region 228 of transistor semiconductor die 210. As discussed above, device region 226 is a section of transistor semiconductor die 210 that includes one or more implants that are electrically coupled to one or more electrodes to provide selective current conduction and voltage blocking capabilities of the device. It's an area. Edge termination region 228 is provided to reduce the concentration of electric fields at the edges of transistor semiconductor die 210 and thus prevent breakdown at low reverse voltages.

FIG. 16 shows a top view of transistor semiconductor die 210 with gate metal layer 218, gate via bar 220, source metal layer 222, and a number of other layers (described below) removed. Below these layers are a number of source regions 230 separated by a number of gate regions 232. The source regions 230 may have a doping type and/or doping concentration that is different from the doping type and/or doping concentration of the drift layer in which they are located (e.g., via a separate epitaxy process from the drift layer or by implantation of the drift layer). and/or doping concentration, while the gate regions 232 may be provided as regions where the doping type and/or doping concentration of the drift layer remains relatively unchanged or varies by a different amount. As shown in FIG. 16, the gate areas 232 are provided as stripes, but the gate areas 232 may similarly be provided as a grid as shown in FIG. 17. To provide the primary function of transistor semiconductor die 210, gate contact pad 214 must be in electrical contact with gate regions 232, while source contact pads 216 are in electrical contact with source regions 230. There must be electrical contact.

Figure 18 shows a cross-sectional view of a portion of a transistor semiconductor die 210 according to one embodiment of the present disclosure. Transistor semiconductor die 210 includes a substrate 234 and a drift layer 236 above substrate 234. Multiple implants 238 at the surface of drift layer 236 provide source regions 230, while multiple non-implanted regions between implants 238 provide gate regions 232. to provide. A plurality of gate electrodes 240 are provided on the gate regions 232, such that each of the gate electrodes 240 is positioned between the implants 238 on either side of the gate region 32 on which they are provided. It continues. Each of the gate electrodes 240 is separated from the surface of the drift layer 236 by an oxide layer 242 . A plurality of source electrodes 244 are provided on the source regions 230 such that each of the source electrodes 244 is in contact with a different one of the implants 238 . Gate metal layer 218 is drifted such that gate metal layer 218 is separated from the surface of drift layer 236 by oxide layer 242 and coupled to each of the gate electrodes 240 on a plane not shown in FIG. 18. Provided on the surface of layer 236. To keep the gate electrodes 240 electrically isolated from the source electrodes 244, a dielectric layer 246 is provided over the gate electrodes 240. Source electrodes 244 are exposed at the surface of dielectric layer 246. A source metal layer 222 is provided on the dielectric layer 246 to contact the source electrodes 244. A drain metal layer 248 is provided on the substrate 234 opposite the drift layer 236.

15 and 18, the source metal layer 222 and gate metal layer 218 are the device of transistor semiconductor die 210 in a single metallization step (i.e., as a single appropriately patterned metal layer). Provided within area 226. This means that the source metal layer 222 and gate metal layer 218 are provided on the same surface/plane of the transistor semiconductor die 210. Accordingly, source metal layer 222 cannot overlap gate metal layer 218 and must instead include an opening to gate metal layer 218 . Due to constraints on the size of the gate metal layer 218 (e.g., minimum contact pad size for wire bonding), the coverage of the source metal layer 222 is therefore limited to the device region 226 of the transistor semiconductor die 210. ) is limited within. As shown in FIG. 18 , the region beneath the source metal layer 222 is an active region where current is transferred from the source metal layer 222 to the drain metal layer 248 by the drift layer 236 . The area beneath the gate metal layer 218 is an inactive region because current cannot be transmitted beneath the gate metal layer 218 by the drift layer 236. Accordingly, the total active area of device region 226 and thus the total current carrying capacity of transistor semiconductor die 210 may be limited for a given size of die.

Accordingly, Figure 19 shows a cross-sectional view of a transistor semiconductor die 210 according to a further embodiment of the present disclosure. The transistor semiconductor die 210 shown in Figure 19 is substantially similar to that shown in Figure 18, but further includes an additional dielectric layer 250 over the dielectric layer 246. Specifically, gate electrodes 240 and source electrodes 244 are provided on the surface of the drift layer 236, and the dielectric layer 246 allows the gate electrodes 240 to conduct electrical energy from the source electrodes 244. and are provided over the gate electrodes 240 and source electrodes 244 such that the source electrodes 244 are exposed at the surface of the dielectric layer 246, and the source metal layer 222 is on the dielectric layer 246. An additional dielectric layer 250 is provided over the dielectric layer 246 and the source metal layer 222, and a gate metal layer 218 is provided over the additional dielectric layer 250. Gate metal layer 218 is connected to gate electrodes 240 by one or more vias 252 running through dielectric layer 246 and an additional dielectric layer 250 (connected on a plane not shown in FIG. 19). are electrically coupled. As illustrated, providing additional dielectric layer 250 allows at least a portion of gate metal layer 218 to overlap source metal layer 222. One or more vias 252 are very small compared to the total area of gate metal layer 218. Accordingly, only a very small opening in the source metal layer 222 is required, thus increasing the overall area covered by the source metal layer 222. As discussed above, because the area beneath source metal layer 222 is the active area of transistor semiconductor die 210, this effectively increases the overall active area and thus the current carrying capacity of the transistor semiconductor die. In fact, the total inactive area of device region 226 of transistor semiconductor die 210 may be less than the total area of gate metal layer 218 and, in some embodiments, less than the total area of gate contact pad 214. And this has never been achievable before.

Increasing the active area of the transistor semiconductor die 210 allows for an increase in current carrying capacity for a given size. Alternatively, increasing the active area of transistor semiconductor die 210 allows reduction in size of the die without sacrificing current carrying capacity. This ultimately allows additional chips to be provided for a given wafer when manufacturing the transistor semiconductor die 210. Although the examples discussed herein primarily relate to transistor semiconductor die 210 providing MOSFET devices, the principles described herein also apply to field effect transistor (FET) devices, bipolar junction transistor (BJT) devices, and insulated gate devices. The same applies to transistor semiconductor die 210 providing bipolar transistor (IGBT) devices, or any other type of vertical transistor device with two or more top-level contacts. With this in mind, gate contact pad 214 may be generally referred to as a first contact pad, source contact pads 216 may be generally referred to as a second contact pad, and source metal layer 222 may be generally referred to as a first metallization layer, gate metal layer 218 may be generally referred to as a second metallization layer, and source regions 230 may be generally referred to as a first set of regions. and the gate regions may be generally referred to as a second set of regions.

In one embodiment, substrate 234 and drift layer 236 are silicon carbide. Using silicon carbide for substrate 234 and drift layer 236 can significantly increase the performance of transistor semiconductor die 210 compared to using conventional material systems such as silicon. Although not shown, implants 238 may include several different implanted regions therein as needed to provide selective current conduction and voltage blocking capabilities of transistor semiconductor die 210. Dielectric layer 246 and additional dielectric layer 250 may include one or more layers of Al ₂ O ₃ and SiO ₂ , for example, in an alternating manner. In other embodiments, dielectric layer 246 and additional dielectric layer 250 may include one or more layers of Si ₃ N ₄ and SiO ₂ , for example, in an alternating manner. In general, dielectric layer 246 and additional dielectric layer 250 may include any suitable dielectric materials (e.g., those with a wide bandgap (>˜5 eV) and a relatively low dielectric constant). Dielectric layer 246 and additional dielectric layer 250 may include the same or different materials. Additional passivation layers, including Si ₃ N ₄ , Al ₂ O ₃ , AlN, SiO ₂ , or any other suitable materials, may be added to the dielectric layer 246 and additional dielectric layers as needed to avoid interactions between the materials. It can be interleaved with (250). Passivation layer 212 may include Si ₃ N ₄ , Al ₂ O ₃ , AlN, SiO ₂ , or any other suitable materials in various embodiments.

FIG. 20A is a graph showing improvements in current carrying capacity for a transistor semiconductor die 210 due to movement of gate metal layer 218 over source metal layer 222. The solid line illustrates the relationship between the size and current carrying capacity of the transistor semiconductor die 210 without improvements to the layout of the contact pads as shown in FIG. 18. The dashed line illustrates the same relationship between the current carrying capacity of the transistor semiconductor die 210 with the improvements discussed above with respect to FIG. 19. The graph assumes a constant rated blocking voltage (e.g., 1200V). As shown, improvements in the current carrying capacity of transistor semiconductor die 210 are realized regardless of die size. As discussed above, this is due to an increase in the active area of device area 226.

FIG. 20B is a graph further showing improvements in current carrying capacity for transistor semiconductor die 210 due to movement of gate metal layer 218 over source metal layer 222. The graph illustrates the relationship between the current rating of the transistor semiconductor die 210 and the percentage increase in current carrying capacity (compared to a transistor semiconductor die without improvements such as shown in FIG. 18). As illustrated, the percentage by which the current capability of transistor semiconductor die 210 is increased is inversely related to the current rating of transistor semiconductor die 210. This is because as the current rating of the transistor semiconductor die 210 increases, its overall size also increases. Accordingly, the active area recovered as a result of movement of the gate metal layer 218 over the source metal layer 222 constitutes a smaller percentage of the total active area of the device, thereby resulting in the current seen by utilizing these improvements. Reduces the percentage increase in carrying capacity. Figure 20B shows that the greatest improvements in device performance due to the improvements discussed herein are seen at lower current ratings.

FIG. 20C is a graph further showing improvements in current carrying capacity for transistor semiconductor die 210 due to movement of gate metal layer 218 over source metal layer 222. The graph illustrates the relationship between the percentage increase in current carrying capacity (compared to a transistor semiconductor die without improvements such as shown in FIG. 18) and the voltage rating of the transistor semiconductor die 210. As illustrated, the percentage of current capability of transistor semiconductor die 210 increases in a positive relationship with the voltage rating of transistor semiconductor die 210. The depicted graph assumes a constant size of the transistor semiconductor die 210. The relationship between the percentage increase in current carrying capacity and the voltage rating is due to the fact that as the voltage rating of the transistor semiconductor die 210 increases, the size of the edge termination region 228 also increases. Accordingly, the size of the device area 226 is reduced such that the recovered active area as a result of movement of the gate metal layer 218 over the source metal layer 222 constitutes a greater percentage of the total active area of the device; increases the percentage increase in current carrying capacity seen with the use of these improvements. Figure 20C shows that the greatest improvements in device performance for a given chip size are seen at higher voltage ratings.

21 shows a top view of a transistor semiconductor die 210 according to one embodiment of the present disclosure. Specifically, FIG. 21 shows transistor semiconductor die 210 with gate metal layer 218 and additional dielectric layer 250 removed. Underneath the additional dielectric layer 250, the source metal layer 222 is exposed. Gate via bar 220 is still present in the embodiment shown in Figure 21. The first dashed box 254 illustrates the area over which the gate metal layer 218 is provided. This area may correspond to the boundaries of gate contact pad 214 or may extend beyond the boundaries of gate contact pad 214. That is, the entirety of the gate metal layer 218 may be exposed through the passivation layer 212, such as the gate contact pad 214, or only a portion of the gate metal layer 218 may be exposed through the passivation layer 212. It may be covered by a passivation layer 212 to form a gate contact pad 214. As shown, a portion of the gate metal layer 218 overlies the gate via bar 220 and thus prevents the gate contact pad 214 from contacting the gate electrodes 240 coupled to the gate via bar 220. Allowed. Second dashed box 256A and third dashed box 256B illustrate the area of source contact pads 216 . The gate via bar 220 is still located on the surface of the drift layer 236, and therefore the source metal layer 222 is still required to have an opening 258 sized to receive the gate via bar 220. . However, the overall size of the gate via bar 220 is much smaller than that of a conventional gate contact pad. Accordingly, the size of the active area within the device region 226 of the transistor semiconductor die 210 can be significantly increased.

Figure 22 shows a top view of a transistor semiconductor die 210 according to a further embodiment of the present disclosure. Specifically, FIG. 22 shows transistor semiconductor die 210 with gate metal layer 218 and additional dielectric layer 250 removed. Underneath the additional dielectric layer 250, the source metal layer 222 is exposed. Gate via bar 220 is removed in the embodiment shown in Figure 22 and replaced with a number of gate contact vias 260, which extend through dielectric layer 246 and additional dielectric layer 250 to form one or more lower Contacting the gate electrode 240, they are coupled together on the surface of the drift layer 236 (e.g., in a grid configuration as shown above). The first dashed box 254 illustrates the area over which the gate metal layer 218 is provided. As shown, a portion of gate metal layer 218 overlaps gate contact vias 260 to connect gate contact pad 214 to gate electrodes 240 . Second dashed box 256A and third dashed box 256B illustrate the area of source contact pads 216 . Gate contact vias 260 may have a much smaller area than gate via bar 220 . Accordingly, the total size of the openings 258 in the source metal layer 222 to accommodate the connections from the gate contact pad 214 to the gate electrodes 240 can be made much smaller, thereby reducing the transistor semiconductor die. The active area within the device area 226 of 210 may be further increased.

As the size of the connection between the gate contact pad 214 and the lower gate electrodes 240 decreases, the gate resistance of the transistor semiconductor die 210 may increase. Accordingly, the size and shape of the gate contact pad 214, the gate metal layer 218, and the number and placement of the gate contact vias 260 are consistent with the values of FIGS. 23 and 23 while minimizing the gate resistance of the transistor semiconductor die 210. It may be arranged to maximize the active portion of device area 226 as shown at 24. 23 and 24 , first dashed box 254 represents the placement of gate metal layer 218 over gate contact vias 260 . Gate contact pad 214 may correspond to all or a subset of gate metal layer 218 as discussed above. The second dashed box 256A and the third dashed box 256B once again represent the area of the source contact pads 216. In FIG. 23 , fourth dashed box 256C and fifth dashed box 256D represent additional areas of source contact pads 216 that can be provided.

In addition to maximizing the active portion of device region 226 of transistor semiconductor die 210, additional dielectric layer 250 may also be used to provide additional features. Accordingly, Figure 25 shows a top view of a transistor semiconductor die 210 according to one embodiment of the present disclosure. Specifically, Figure 25 shows the transistor semiconductor die 210 with the passivation layer 212 removed. Below the passivation layer 212 is an additional dielectric layer 250 with gate contact pad 214 and source contact pads 216 exposed. In addition to these contact pads, a number of sensor contact pads 262 are provided on the additional dielectric layer 250. Sensor contact pads 262 are coupled to sensor 264, such as embedded sensor element 22 discussed above. Sensor 264 may be any type of sensor (eg, a temperature sensor, a strain sensor, or a current sensor). Sensor 264 may also be located on the surface of additional dielectric layer 250, on dielectric layer 246, on drift layer 236, or even in a stack of layers, such as in drift layer 236. It may be located further down. If sensor 264 is located in drift layer 236, it may damage the entire active area of device area 226. However, the sensor 264 will typically be very small compared to the size of the device area 226, so having the sensor in the drift layer 236 may only result in a small reduction in the active area of the device area 226. Typically, sensor contact pads 262 will be much larger than sensor 264 itself, and because sensor contact pads 262 may be located over source metal layer 222, the activity of device area 226 The area will be minimally affected by the introduction of one or more sensors into the transistor semiconductor die 210. Sensor contact pads 262 may be formed by the same metallization layer (ie, in the same metallization step) as gate metal layer 218 in some embodiments.

Figure 26 shows a cross-sectional view of a transistor semiconductor die 210 according to one embodiment of the present disclosure. The transistor semiconductor die 210 shown in Figure 26 is substantially similar to that shown in Figure 19, except that the sensor contact pad 262 is shown on the surface of an additional dielectric layer 250. Sensor 264 may be located behind sensor contact pad 262 on additional dielectric layer 250, so sensor 264 is not shown in FIG. 26.

Figure 27 shows a cross-sectional view of a transistor semiconductor die 210 according to a further embodiment of the present disclosure. The transistor semiconductor die 210 shown in FIG. 27 is similar to that of FIG. 26 except that the sensor contact pad 262 is coupled to the sensor 264 located in the drift layer 236 by a sensor contact via 266. It is substantially similar to that shown in . Sensor 264 may include one or more implanted regions in drift layer 236, such that sensor 264 may be any type of semiconductor device. Sensor 264 may be used to measure temperature, strain, current, voltage, or any other desired parameter. As discussed above, sensor contact pad 262 generally requires a greater amount of area to implement than sensor 264 and sensor contact via 266. Providing a sensor contact pad 262 on the additional dielectric layer 250 such that the sensor contact pad 262 at least partially overlaps the source metal layer 222 thus allows the sensor 264 in the transistor semiconductor die 210 reduces the impact of providing on the active area of its device area 226. Although sensor 264 is shown in drift layer 236, sensor 264 may be located anywhere above or below drift layer 236, and may include any number of vias and They can be joined using intervening metal layers.

Figure 28 shows a cross-sectional view of a transistor semiconductor die 210 according to a further embodiment of the present disclosure. Transistor semiconductor die 210 has a first intervening layer 268A between dielectric layer 246 and additional dielectric layer 250 and a second intervening layer 268B between additional dielectric layer 250 and gate metal layer 218. ) is substantially similar to that shown in Figure 19, except that it further includes. First intervening layer 268A and second intervening layer 268B may reduce chemical interactions between dielectric layer 246, additional dielectric layer 250, gate metal layer 218, and source metal layer 222. You can. This is important because the additional dielectric layer 250 may require densification anneal for good dielectric properties. First intervening layer 268A and second intervening layer 268B may include Si ₃ N ₄ , Al ₂ O ₃ , AlN, SiO ₂ , various layers of the same, or any other suitable materials. As discussed above, dielectric layer 246 and additional dielectric layer 250 may include SiO ₂ or any other suitable materials. As shown, second intervening layer 268B may be provided after openings for one or more vias 252 are made. Accordingly, second intervening layer 268B is configured to reduce chemical interactions between the metal of one or more vias 252, dielectric layer 246, and additional dielectric layer 250. One or more vias 252 may be provided along the edges. One or more vias 252 may include a single conductive metal that is the same or different from the gate metal layer 218, or a different metal as needed to form a chemical or diffusion barrier layer along the walls of one or more vias 252. may contain a stack of .

Figure 28 also shows the passivation layer 212 over the gate metal layer 218. The passivation layer 212 may protect the transistor semiconductor die 210 from the surrounding environment. Passivation layer 212 may include Si ₂ N ₄ , Al ₂ O ₃ , SiO ₂ , alternating layers of the same, or any other suitable materials.

Transistor semiconductor die 210 may be a power semiconductor die configured to conduct at least 0.5 A in a forward conduction mode of operation and to block at least 100 V in a blocking mode of operation. In various embodiments, the transistor semiconductor die 210 is capable of generating a current of at least 1.0 A, at least 2.0 A, at least 3.0 A, at least 4.0 A, at least 5.0 A, at least 6.0 A, at least 7.0 A, at least 8.0 A, It can be configured to conduct at least 9.0A, and at least 10.0A. The transistor semiconductor die 210 may be configured to block at least 250V, at least 500V, at least 750V, at least 1kV, at least 1.5kV, and at least 2.0kV in a blocking operation mode. The same parameters apply to semiconductor die 10 discussed above.

It is contemplated that any of the foregoing aspects, and/or various separate aspects and features as described herein, may be combined for additional advantage. Any of the various embodiments as disclosed herein may be combined with one or more other disclosed embodiments unless otherwise indicated herein.

Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the following claims.

Claims (58)

As a semiconductor device,
● A drift layer comprising a wide bandgap semiconductor material; and
● A semiconductor device containing an embedded sensor element. According to paragraph 1,
A semiconductor device, wherein the built-in sensor element is a temperature sensing element. According to paragraph 2,
The semiconductor device further comprising an insulating layer between the drift layer and the embedded sensor element. According to paragraph 3,
The semiconductor device further comprising a shielding well between the drift layer and the embedded sensor element, the shielding well having a doping type opposite to that of the drift layer. According to paragraph 4,
The semiconductor device of claim 1, wherein the shield well is an implanted region in the drift layer. According to clause 5,
● A first contact in electrical contact with the shield well; and
● A second contact in electrical contact with the shielding well, wherein the embedded sensor element is between the first contact and the second contact. According to clause 6,
● First contact well - where:
● The first contact well is the implanted area in the shield well;
● the first contact well has the same doping type as the shielding well and a doping concentration greater than that of the shielding well;
● the first contact is in electrical contact with the shielding well through the first contact well; and
● Second contact well - where:
● the second contact well is the implanted area in the shield well;
● the second contact well has the same doping type as the shielding well and a doping concentration greater than that of the shielding well;
● The second contact is in electrical contact with the shielding well through the second contact well. According to clause 6,
wherein the first contact and the second contact are electrically coupled to a fixed potential. According to clause 6,
A semiconductor device wherein the distance between the first contact and the second contact is 200 μm or less. According to clause 9,
The semiconductor device, wherein the distance between the first contact and the second contact is 100 μm or less. According to clause 10,
The semiconductor device, wherein the distance between the first contact and the second contact is 50 μm or less. According to clause 11,
The semiconductor device of claim 1, wherein the distance between the first contact and the second contact is at least 5 μm. According to clause 6,
further comprising a noise reduction well;
● the noise reduction well has a doping type opposite to that of the shielding well;
● the noise reduction well is separated from the drift layer by at least a portion of the noise reduction well;
● The semiconductor device, wherein the first contact and the second contact are in electrical contact with the noise reduction well. According to paragraph 4,
further comprising an additional functional layer and an additional insulating layer between the drift layer and the embedded sensor element, the insulating layer being on the drift layer, the additional functional layer being on the insulating layer, and the additional insulating layer is on the additional functional layer, and the embedded sensor element is on the additional insulating layer. According to clause 14,
The semiconductor device of claim 1, wherein the additional functional layer comprises polysilicon. According to clause 14,
The semiconductor device of claim 1, wherein the additional functional layer comprises polysilicon, one of at least partially metallized and at least partially silicided. According to clause 14,
The semiconductor device further comprising a lumped resistor element on the additional insulating layer. According to clause 17,
● The semiconductor device includes an active region;
● the active region includes one or more implanted regions configured to provide a metal-oxide-semiconductor field-effect transistor (MOSFET);
● A semiconductor device, wherein the lumped resistor element is coupled to the gate of the MOSFET. According to clause 14,
further comprising a noise reduction well;
● the noise reduction well has a doping type opposite to that of the shielding well;
● the noise reduction well is separated from the drift layer by at least a portion of the noise reduction well;
● The semiconductor device, wherein the first contact and the second contact are in electrical contact with the noise reduction well. According to paragraph 3,
A semiconductor device further comprising an active region, the active region comprising one or more implanted regions configured to provide a switching power semiconductor device. According to clause 20,
The switching power semiconductor device is a metal-oxide-semiconductor field-effect transistor (MOSFET). According to clause 21,
A semiconductor device, wherein the MOSFET is a vertical MOSFET. According to clause 20,
The switching power semiconductor device is one of a bipolar junction transistor (BJT), an insulated gate bipolar transistor (IGBT), and a thyristor. According to clause 20,
A semiconductor device, wherein the wide bandgap semiconductor material comprises silicon carbide. According to clause 20,
A semiconductor device, wherein the wide bandgap semiconductor material includes one of gallium nitride, gallium oxide, and zinc oxide. In clause 7,
● Intermetallic dielectric layer;
● A sensor contact pad on the intermetallic dielectric layer, wherein the sensor contact pad at least partially overlaps one of the first contact and the second contact, the sensor contact pad being connected to the first contact by a portion of the intermetallic dielectric layer. electrically isolated from the first contact and the second contact; and
● A via through the intermetallic dielectric, the via electrically coupling the sensor contact pad to the embedded sensor element. According to paragraph 3,
A semiconductor device, wherein the embedded sensor element is a diode. As a method for manufacturing a semiconductor device,
● Providing a drift layer comprising a wide bandgap semiconductor material; and
● A method, comprising providing an embedded sensor element. According to clause 28,
The method of claim 1, wherein the embedded sensor element is a temperature sensing element. According to clause 29,
The method further comprising providing an insulating layer between the drift layer and the embedded sensor element. According to clause 29,
The method further comprising providing a shielding well between the drift layer and the embedded sensor element, the shielding well having a doping type opposite to that of the drift layer. According to clause 31,
The method of claim 1, wherein providing the shielding well includes injecting the shielding well into the drift layer. According to clause 32,
● Providing a first contact in electrical contact with the shield well; and
● Providing a second contact in electrical contact with the shielding well, wherein the embedded temperature sensing element is between the first contact and the second contact. According to clause 33,
● Providing a first contact well, wherein:
● The first contact well is the implanted area in the shield well;
● the first contact well has the same doping type as the shielding well and a doping concentration greater than that of the shielding well;
● the first contact is in electrical contact with the shielding well through the first contact well; and
● Providing a second contact well, wherein:
● the second contact well is the implanted area in the shield well;
● the second contact well has a doping concentration equal to that of the shielding well and a doping concentration greater than that of the shielding well;
● The second contact is in electrical contact with the shielding well through the second contact well. According to clause 33,
wherein the first contact and the second contact are electrically coupled to a fixed potential. According to clause 33,
The method of claim 1 , wherein the first contact and the second contact are provided such that the distance between the first contact and the second contact is less than 200 μm. According to clause 36,
The method of claim 1 , wherein the first contact and the second contact are provided such that the distance between the first contact and the second contact is less than 100 μm. According to clause 37,
The method of claim 1, wherein the first contact and the second contact are provided such that the distance between the first contact and the second contact is less than 50 μm. According to clause 38,
The method wherein the first contact and the second contact are provided such that the distance between the first contact and the second contact is at least 5 μm. According to clause 33,
further comprising providing a noise reduction well,
● the noise reduction well has a doping type opposite to that of the shielding well;
● the noise reduction well is separated from the drift layer by at least a portion of the noise reduction well;
● The first contact and the second contact are in electrical contact with the noise reduction well. According to clause 40,
providing an additional functional layer and an additional insulating layer between the drift layer and the embedded sensor element, wherein the insulating layer is on the drift layer and the additional functional layer is on the insulating layer; The method of claim 1, wherein the additional insulating layer is on the additional functional layer, and the embedded sensor element is on the additional insulating layer. According to clause 41,
The method of claim 1, wherein the additional functional layer comprises polysilicon. According to clause 41,
The method of claim 1, wherein the additional functional layer comprises polysilicon, one of at least partially metallized and at least partially silicided. According to clause 41,
The method further comprising providing a lumped resistor element on the additional insulating layer. According to clause 44,
Providing one or more implanted regions in an active region such that the one or more implanted regions provide a metal-oxide-semiconductor field-effect transistor (MOSFET), wherein the lumped resistor element is coupled to the gate of the MOSFET. A method further comprising: According to clause 41,
further comprising providing a noise reduction well,
● the noise reduction well has a doping type opposite to that of the shielding well;
● the noise reduction well is separated from the drift layer by at least a portion of the noise reduction well;
● The first contact and the second contact are in electrical contact with the noise reduction well. According to clause 29,
The method further comprising providing one or more implanted regions in the active region of the drift layer such that the one or more implanted regions are configured to provide a switching power semiconductor device. According to clause 47,
The method of claim 1, wherein the switching power semiconductor device is a metal-oxide-semiconductor field-effect transistor (MOSFET). According to clause 48,
The method of claim 1, wherein the MOSFET is a vertical MOSFET. According to clause 47,
The method of claim 1, wherein the switching power semiconductor device is one of a bipolar junction transistor (BJT), an insulated gate bipolar transistor (IGBT), and a thyristor. According to clause 47,
The method of claim 1, wherein the wide bandgap semiconductor material comprises silicon carbide. According to clause 47,
The method of claim 1, wherein the wide bandgap semiconductor material includes one of gallium nitride, gallium oxide, and zinc oxide. According to clause 29,
The method of claim 1, wherein the embedded sensor element is a diode. As a semiconductor device,
● Substrate;
● A drift layer on the substrate;
● an insulating layer on the drift layer;
● A first functional layer on the insulating layer;
● an additional insulating layer on the first functional layer; and
● A semiconductor device comprising a lumped resistor element on the additional insulating layer. According to clause 54,
The semiconductor device of claim 1, wherein the first functional layer comprises polysilicon. According to clause 55,
The semiconductor device of claim 1, wherein the first functional layer comprises polysilicon, one of partially metallized and partially silicided. According to clause 56,
The semiconductor device includes an active region comprising one or more implanted regions in the drift layer, the one or more implanted regions configured to provide a metal-oxide-semiconductor field-effect transistor (MOSFET), the lumped region A semiconductor device wherein a resistor element is coupled to the gate of the MOSFET. According to clause 57,
The semiconductor device of claim 1, wherein the first functional layer provides a gate electrode of the MOSFET.

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