JP2024510130A - Wide bandgap semiconductor device with sensor element - Google Patents

Abstract

Shielding techniques are used to provide embedded sensor elements, such as temperature sensing elements, on wide bandgap power semiconductor devices. The semiconductor device may include a drift layer and an embedded sensor element. The drift layer may be a wide bandgap semiconductor material. A shielding structure is provided in the drift layer below the embedded sensor element. An embedded sensor element may be provided between the contacts in electrical contact with the shielding well. The distance between contact points can be minimized. A noise reduction well can be provided between the contacts to further isolate the embedded sensor element from parasitic signals.

Description

This application claims priority to U.S. Patent Application No. 17/201,468, filed March 15, 2021.

TECHNICAL FIELD This disclosure relates to semiconductor devices, and particularly to wide bandgap semiconductor devices including sensor elements.

Wide bandgap semiconductor devices are often used in power applications where the semiconductor devices handle high voltages and/or currents. These wide bandgap power semiconductor devices desirably monitor one or more operating conditions such as temperature, current, etc. in order to adjust one or more control signals sent to them. There are many cases. For example, if the temperature of the device rises above a threshold, it may be desirable to adjust the switching speed of the device or power down the device to avoid damage to the device. Although embedded sensor elements integrated into the die of the device are preferred, incorporating sensor elements into wide bandgap power semiconductor devices presents several technical challenges that must be overcome. Current solutions therefore rely on individual sensor elements placed in close proximity to the semiconductor die being measured. This results in both decreased accuracy and increased area. Therefore, there is a need for wide bandgap power semiconductor devices with one or more embedded sensor elements.

In one example, a semiconductor device includes a drift layer and an embedded sensor element. The drift layer includes a wide bandgap semiconductor material. By including embedded sensor elements on wide bandgap semiconductor devices, accurate measurement of one or more operating parameters can be achieved with a compact solution.

In one embodiment, the embedded sensor element is a temperature sensing element such as a diode. The semiconductor device may further include an insulating layer between the embedded sensor element and the drift layer. To provide further shielding, a shielding well with a doping type opposite to that of the drift layer may be provided below the embedded sensor element in the drift layer. A shielding well can further isolate the embedded sensor element from parasitic signals. Additionally, an embedded sensor element may be provided between the first contact and the second contact, both of which are in electrical contact with the shielding well and coupled to a fixed potential, such as ground. Coupling the shielding well to a fixed potential further isolates the embedded sensor element from parasitic signals. The first contact and the second contact are electrically connected to the shield well through the first contact well and the second contact well, respectively, each having the same doping type as the shield well and a higher doping concentration than the shield well. may be combined with The shielding well may further include a noise reduction well. The noise reduction well may have a doping type that is opposite to that of the shielding well. The noise reduction well reduces the resistance at the surface of the drift layer below the embedded sensor element, thereby further isolating the embedded sensor element from parasitic signals. The first contact and the second contact may be in electrical contact with the noise reduction well. In yet another embodiment, a functional layer and an additional insulating layer are provided between the embedded sensor element and the drift layer. Functional layers and additional insulation layers can further isolate the embedded sensor element from parasitic signals. To further improve isolation of the embedded sensor element from parasitic signals, the distance between the first contact well and the second contact well may be minimized. In various examples, the distance between the first contact well and the second contact well is less than 200 μm, less than 100 μm, less than 50 μm, and less than 25 μm.

In one example, a method of manufacturing a semiconductor device includes providing a drift layer and providing an embedded sensor element. The drift layer may include a wide bandgap semiconductor material. By including embedded sensor elements on wide bandgap semiconductor devices, accurate measurement of one or more operating parameters can be achieved with a compact solution.

In one embodiment, the embedded sensor element is a temperature sensing element such as a diode. The method may further include providing an insulating layer between the embedded sensor element and the drift layer. For further shielding, a shielding well with a doping type opposite to that of the drift layer may be provided below the embedded sensor element in the drift layer. A shielding well can further isolate the embedded sensor element from parasitic signals. Additionally, an embedded sensor element may be provided between the first contact and the second contact, both of which are in electrical contact with the shielding well and coupled to a fixed potential, such as ground. Coupling the shielding well to a fixed potential further isolates the embedded sensor element from parasitic signals. The first contact and the second contact are electrically connected to the shield well through the first contact well and the second contact well, respectively, each having the same doping type as the shield well and a higher doping concentration than the shield well. may be combined with The shielding well may further include a noise reduction well. The noise reduction well may have a doping type that is opposite to that of the shielding well. The noise reduction well reduces the resistance at the surface of the drift layer below the embedded sensor element, thereby further isolating the embedded sensor element from parasitic signals. The first contact and the second contact may be in electrical contact with the noise reduction well. In yet another embodiment, a functional layer and an additional insulating layer are provided between the embedded sensor element and the drift layer. Functional layers and additional insulation layers can further isolate the embedded sensor element from parasitic signals. To further improve isolation of the embedded sensor element from parasitic signals, the distance between the first contact well and the second contact well may be minimized. In various examples, the distance between the first contact well and the second contact well is less than 200 μm, less than 100 μm, less than 50 μm, and less than 25 μm.

In other aspects, any of the aforementioned aspects, individually or together, and/or the various separate aspects and features described herein may be combined for further advantage. Any of the various features and elements as disclosed herein may be combined with one or more other disclosed features and elements unless indicated to the contrary herein.

Those skilled in the art will understand the scope of the present disclosure and will realize additional aspects thereof after reading the following detailed description of the preferred embodiment in conjunction with the accompanying drawings.

The accompanying drawings, which are incorporated in and form a part of this specification, illustrate certain aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

1 is a cross-sectional view of a semiconductor die according to one embodiment of the present disclosure. FIG. 1 is a cross-sectional view of a semiconductor die according to one embodiment of the present disclosure. FIG. 1 is a cross-sectional view of a semiconductor die according to one embodiment of the present disclosure. FIG. 1 is a cross-sectional view of a semiconductor die according to one embodiment of the present disclosure. FIG. 1 is a cross-sectional view of a semiconductor die according to one embodiment of the present disclosure. FIG. 1 is a top-down view of an embedded sensor element according to one embodiment of the present disclosure; FIG. 1 is a top-down view of an embedded sensor element according to one embodiment of the present disclosure; FIG. 1 is a top-down view of an embedded sensor element according to one embodiment of the present disclosure; FIG. FIG. 3 is a top down view of a portion of a shielding structure for an embedded sensor element according to one embodiment of the present disclosure. FIG. 3 is a top down view of a portion of a shielding structure for an embedded sensor element according to one embodiment of the present disclosure. FIG. 2 is a cross-sectional view of a functional component according to one embodiment of the present disclosure. 2 is a top-down view of functional components according to one embodiment of the present disclosure; FIG. FIG. 2 is a flow diagram illustrating a method of manufacturing a semiconductor die according to one embodiment of the present disclosure. 1 is a cross-sectional view of an implantable sensor element according to one embodiment of the present disclosure. FIG. 1 is a top-down view of a transistor semiconductor die according to one embodiment of the present disclosure; FIG. 1 is a top-down view of a transistor semiconductor die according to one embodiment of the present disclosure; FIG. 1 is a top-down view of a transistor semiconductor die according to one embodiment of the present disclosure; FIG. 1 is a top-down view of a transistor semiconductor die according to one embodiment of the present disclosure; FIG. 1 is a cross-sectional view of a transistor semiconductor die according to one embodiment of the present disclosure. FIG. 1 is a cross-sectional view of a transistor semiconductor die according to one embodiment of the present disclosure. FIG. 3 is a graph illustrating the performance of transistor semiconductor die according to various embodiments of the present disclosure. 3 is a graph illustrating the performance of transistor semiconductor die according to various embodiments of the present disclosure. 3 is a graph illustrating the performance of transistor semiconductor die according to various embodiments of the present disclosure. 1 is a top-down view of a transistor semiconductor die according to one embodiment of the present disclosure; FIG. 1 is a top-down view of a transistor semiconductor die according to one embodiment of the present disclosure; FIG. 1 is a top-down view of a transistor semiconductor die according to one embodiment of the present disclosure; FIG. 1 is a top-down view of a transistor semiconductor die according to one embodiment of the present disclosure; FIG. 1 is a top-down view of a transistor semiconductor die according to one embodiment of the present disclosure; FIG. 1 is a cross-sectional view of a transistor semiconductor die according to one embodiment of the present disclosure. FIG. 1 is a cross-sectional view of a transistor semiconductor die according to one embodiment of the present disclosure. FIG. 1 is a cross-sectional view of a transistor semiconductor die according to one embodiment of the present disclosure. FIG.

The embodiments described below represent the information necessary to enable one skilled in the art to practice the embodiments and illustrate the best mode of carrying out the embodiments. Upon reading the following description in light of the accompanying drawings, those skilled in the art will understand the concepts of this disclosure and will recognize applications of these concepts not specifically addressed herein. It is to be understood that these concepts and applications are within the scope of this disclosure and the appended claims.

Although the terms first, second, etc. are used herein to describe various elements, it is understood that these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element can be referred to as a second element, and similarly, a second element can be referred to as a first element without departing from the scope of this disclosure. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

When an element, such as a layer, region, or substrate, is referred to as being "on" or extending "over" another element, it can be said to be "on" or extend "over" another element. , or intervening elements may be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. Similarly, when an element, such as a layer, region, or substrate, is referred to as being "on" or extending "over" another element, it is referring to being directly on or directly over the other element. It is understood that the device may extend over a length of 100 m or more, or that there may be intervening elements. In contrast, when an element is referred to as being "directly on" or extending "directly over" another element, there are no intervening elements present. It is also understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be intervening elements. In contrast, when an element is referred to as "directly connected" or "directly coupled" to another element, there are no intervening elements present.

Relative terms such as "lower" or "above" or "above" or "below" or "horizontal" or "vertical" refer to the relationship between one element, layer or region of another as illustrated in the figure. may be used herein to describe a relationship to a , layer, or region. It is understood that these terms and the terms discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. As used herein, the terms "comprising", "comprising", "comprising" and/or "comprising" refer to the described feature, integer, step, act, element and/or component. It is further understood that specifying the presence of does not exclude the presence or addition of one or more other features, integers, steps, acts, elements, components and/or groups thereof.

Unless defined otherwise, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Terms used herein should be interpreted to have meanings consistent with their meanings in the context of this specification and related art, and unless explicitly defined herein, idealized It is further understood that the terms and conditions are not to be construed in a formal or overly formal sense.

Embodiments are described herein with reference to schematic illustrations of embodiments of the disclosure. As such, the actual dimensions of the layers and elements may vary, and variations from the illustrated shapes are anticipated, eg, as a result of manufacturing techniques and/or tolerances. For example, areas illustrated or described as squares or rectangles may have rounded or curved features, and areas illustrated as straight lines may have some irregularity. As such, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shapes of the regions of the device and are not intended to limit the scope of the disclosure. do not have. Additionally, the sizes of structures or regions may be exaggerated relative to other structures or regions for illustrative purposes and are provided to illustrate the overall structure of the subject matter and are not drawn to scale. However, it does not have to be depicted. Common elements between figures may be designated herein with a common element number and may not be re-described subsequently.

FIG. 1 illustrates a cross-sectional view of a semiconductor die 10 according to one embodiment of the present disclosure. Semiconductor die 10 includes a substrate 12, a drift layer 14 on substrate 12, and an insulating layer 16 on drift layer 14. Semiconductor die 10 includes an active area 18 in which one or more implant regions are provided to form a functional semiconductor device, and an edge termination region 20 surrounding active area 18 . Somewhere within the edge termination region 20 an embedded sensor element 22 is provided. In some embodiments, embedded sensor element 22 is on insulating layer 16 such that insulating layer 16 is between embedded sensor element 22 and drift layer 14 .

As discussed above, one or more implant regions are provided in active area 18 to form a functional semiconductor device. In one embodiment, the functional semiconductor device is a switching power semiconductor device. For example, functional semiconductor devices include metal-oxide-semiconductor field-effect transistors (MOSFETs), especially vertical MOSFETs, and bipolar junction transistors (BJTs). ), insulated gate bipolar Transistor (IGBT: insulated gate bipolar transistor), junction field-effect transistor (JFET: junction field-effect transistor), gate-controlled thyristor (GTO: gate-controlled thyristor) r) etc. Additionally, functional semiconductor devices may be of any suitable topology, such as planar, vertical, and trench devices. Accordingly, the substrate 12 and/or the drift layer 14 may be made of a wide range of materials such as silicon carbide, gallium nitride, gallium oxide, and zinc oxide, which can be useful in devices intended to handle high voltages and/or currents. - May contain bandgap material. As discussed above, sensor elements incorporated into wide bandgap power semiconductor devices present several technical challenges. In particular, wide bandgap materials have significantly higher sheet resistance than their narrow bandgap counterparts. This high resistance, combined with the high voltages and currents handled by the power device, creates large parasitic signals that interfere with the operation of the embedded sensor element. For narrow bandgap semiconductor devices such as silicon devices, sensor elements are often integrated directly into the drift layer, which can minimize shielding from otherwise parasitic signals; The same device has no functionality when embedded in a wide bandgap power semiconductor device.

Another obstacle in implementing embedded sensor elements in wide bandgap power semiconductor devices is cost. While the fabrication of narrow bandgap power semiconductor devices, such as silicon devices, is inexpensive and the extra processing steps add little extra cost, each extra processing step of wide bandgap power semiconductor devices adds significant Add costs. Therefore, it is desirable to implement embedded sensor elements using as few additional manufacturing steps as possible.

As defined herein, a power semiconductor device is a semiconductor device that has an avalanche breakdown voltage of 50V or greater. As discussed above, the high voltages and currents handled by these devices can create parasitic signals that present challenges to the implementation of embedded sensor elements. The relatively high sheet resistance of wide bandgap semiconductor materials further complicates the implementation of embedded sensor elements.

One way to separate the embedded sensor element 22 is to provide an insulating layer 16 between the embedded sensor element 22 and the drift layer 14. In one embodiment, insulating layer 14 is an oxide layer, such as a field oxide layer. For example, insulating layer 14 may include one or more layers of Al ₂ O ₃ and SiO ₂ , separately or alternately, and/or one or more layers of Si ₃ N ₄ and SiO ₂ , separately or alternately. Alternatively, they may be included alternately. Thus, insulating layer 14 may already be present on semiconductor die 10 . For example, insulating layer 14 may form a gate oxide in some areas of semiconductor die 10 and a field oxide in other areas of semiconductor die 10. The insulating layer 14 is therefore already available without additional manufacturing steps. Additionally, embedded sensor elements 22 may be provided in an already existing polysilicon layer to create a functional semiconductor device on semiconductor die 10. For example, the polysilicon layer may form gate electrodes and/or gate contacts in some portions of semiconductor die 10. The layers used to provide the embedded sensor element 22 are therefore already available without additional manufacturing steps, except for reworking the mask used to deposit the layers. To create the functionality of the embedded sensor element 22, one or more implants are required (e.g., to create a diode, lumped resistor, etc.) in the portion of the polysilicon layer that forms the embedded sensor element 22. There are cases, the details of which are discussed below. These extra manufacturing steps are the minimum number required to provide the implantable sensor element 22, thereby minimizing the cost of the implantable sensor element 22.

The polysilicon layer used to provide the gate electrode and/or contact and sensor element 22 may be a doped polysilicon layer provided via any suitable process. In some embodiments, the polysilicon layer is provided via an epitaxial growth process in which dopants are provided in air to create the desired doping profile. In other embodiments, the polysilicon layer may be deposited and then optionally doped via an implant step. As discussed above, ion implantation may be the preferred approach when providing the sensor element 22 since it requires a separately doped area to provide the diode or other sensing device. Ion implantation can also provide other benefits, such as improving the sheet resistance uniformity of the polysilicon layer by 5-10% in some embodiments and 10-20% in other embodiments. This is due to the use of heavy dopant ions, such as boron difluoride (BF2), which can break down the crystal structure of the polysilicon layer into smaller crystal sizes.

Although the insulating layer 16 isolates the embedded sensor elements 22 to some extent, more isolation may be desirable in some scenarios. Accordingly, FIG. 2 depicts a cross-sectional view of semiconductor die 10 showing additional details of embedded sensor element 22. FIG. For purposes of illustration, a MOSFET cell 24 is shown adjacent to the embedded sensor element 22. However, as discussed above, this is exemplary only and any number of functional semiconductor devices may be provided instead of or in addition to MOSFET cells 24, such as BJTs, IGBTs, and thyristors.

MOSFET cell 24 includes a pair of junction implants 26 separated by a junction field effect transistor (JFET) region 28 . Each one of junction implants 26 includes a deep well region 30, a source region 32, and a body region 34. Gate oxide 36, which is part of insulating layer 16, overlies drift layer 14 over a portion of each one of junction implant 26 and JFET region 28, as shown. There is also a source contact 38 on drift layer 14 over each one portion of junction implant 26 as shown. A gate contact 40 is on the gate oxide 36 . There is a drain contact 42 on the opposite side of the substrate 12 from the drift layer 14. As shown, MOSFET cell 24 is an n-type device in which substrate 12, drift layer 14, deep well region 30, source region 32, body region 34, and JFET region 28 have different doping types and They are labeled with relative doping concentrations ('+' indicates higher doping levels relative to other regions). However, the principles of this disclosure apply equally to p-type devices in which all of the doping types shown are reversed. Those skilled in the art will recognize MOSFET cell 24 as a vertical MOSFET, specifically a double-diffused MOSFET (DMOS). Additionally, those skilled in the art will appreciate that the MOSFET cells 24 are provided throughout the active area 18 with a number of cells interconnected to provide the MOSFET with some desired properties, such as a desired on-state resistance and a desired blocking voltage. Understand that it is only one of the Although the examples described throughout this application show MOSFET cells 24 with details of embedded sensor elements 22, embedded sensor elements 22 can also be provided alongside BJT cells, IGBT cells, JFET cells, GTO cells, etc. . Additionally, the embedded sensor element 22 may be provided alongside a planar or trench device, rather than a vertical device as shown.

Turning to the details of the embedded sensor element 22, the embedded sensor element 22 may include one or more layers on a field oxide layer 44 that is part of the insulating layer 16 on the drift layer 14. In particular, embedded sensor element 22 may include a functional sensor layer 52 and a sensor contact layer 54. Note that the functional sensor layer 52 is part of the polysilicon layer that is also used to provide the gate contact 40. In other words, gate contact 40 and functional sensor layer 52 are formed from the same layer (eg, patterned using a mask). As discussed above, this reduces manufacturing steps and thus allows implementation of embedded sensor elements 22 with minimal additional cost. As shown in FIG. 2, field oxide 44 is much thicker than gate oxide 36 because of their different functions. Gate oxide 36 acts as a dielectric to provide gate capacitance, while field oxide 44 is used to provide electrical isolation and shielding for various portions of semiconductor die 10.

A shielding well 46 is provided below the embedded sensor element 22 in the drift layer 14 . Drift layer 14 is an n-type layer, while shielding well 46 is a p-type region. More generally, shielding well 46 has a doping type that is opposite to that of drift layer 14. Shield well 46 may be an implanted region in drift layer 14 in some embodiments, but may generally be provided by any suitable means. The shield well 46 forms a PN junction with the drift layer 14 such that the shield well blocks DC voltages at the surface of the drift layer 14 beneath the embedded sensor element 22 . In the shield well 46, a first contact well 48A and a second contact well 48B are provided. First contact well 48A and second contact well 48B are p-type regions with a higher doping concentration than shield well 46. First contact well 48A and second contact well 48B may be implanted regions in drift layer 14, but may be provided by any suitable means. Contact well 48 is ohmically connected to shield well 46 for first contact 50A and second contact 50B such that first contact 50A and second contact 50B are connected to first contact well 48A and second contact 50B. They are electrically coupled to the shield wells 46 via second contact wells 48B, respectively. To further shield the embedded sensor element 22 from parasitic voltages and currents, the first contact 50A and the second contact 50B are coupled to a fixed potential, such as ground. In other embodiments, the first contact 50A and the second contact 50B may be coupled to the source contact 38 of the MOSFET cell 24 or otherwise to a particular portion of a functional semiconductor device on the semiconductor die 10. may be connected to. By coupling first contact 50A and second contact 50B to a fixed potential on semiconductor die 10 or to a specific portion of a functional semiconductor device, transient signals (e.g., alternating current signals) in drift layer 14 can cause Parasitic current can be reduced. This is important because the shield well 46 has a finite resistance, so any parasitic current in the shield well 46 will generate a voltage at the surface of the drift layer 14 below the embedded sensor element 22. These voltages may be capacitively coupled into the embedded sensor element 22 through the field oxide 44, which interferes with its operation. In various embodiments, first contact 50A and second contact 50B and source contact 38 and drain contact 42 may include any suitable ohmic metal, such as aluminum, titanium, and titanium nitride. Although not shown, a metal contact layer may be coupled to gate contact 40 to form a gate contact pad. This additional metal contact layer may also include any suitable ohmic metal such as aluminum, titanium, and titanium nitride.

Those skilled in the art will appreciate that wide bandgap semiconductor materials have significantly higher resistance than their narrow bandgap counterparts. While this is overall beneficial for power devices as they can support higher voltages without breakdown, it also makes embedded sensors less susceptible to embedded sensors due to their tendency to generate large parasitic signals that interfere with their operation. Presents unique technical challenges to implementation. As shown in FIG. 2, there is a distance D between the first contact well 48A and the second contact well 48B. The embedded sensor element 22 is provided within this distance D between the first contact well 48A and the second contact well 48B. In order to minimize the resistance across the area of the shielding well 46, to reduce parasitic currents that may otherwise induce voltages that interfere with the operation of the embedded sensor element 22, as discussed above. It is desirable to minimize the distance D between the first contact well 48A and the second contact well 48B. The resistance of the shield well 46 at the midpoint between the first contact well 48A and the second contact well 48B is proportional to the distance D between the first contact well 48A and the second contact well 48B. . By minimizing the distance D, the resistance can also be minimized. In one embodiment, the distance D between the first contact well 48A and the second contact well 48B is less than 200 μm. In other embodiments, the distance D between the first contact well 48A and the second contact well 48B is less than 100 μm, less than 50 μm, less than 25 μm, and a minimum of 5 μm. The smaller the distance between the first contact well 48A and the second contact well 48B, the lower the resistance through the shield well 46. This results in lower interference at the embedded sensor element 22 due to the reduction of parasitic voltages within the shielding well 46.

Minimizing the distance D between the first contact well 48A and the second contact well 48B allows the embedded sensor element 22 to generally be inserted into the page and/or as shown in FIG. Means provided as an elongated strip extending outside the page. The embedded sensor element 22 may be any type of sensing element, such as a diode, a resistor, etc., and can provide a voltage and/or current that is proportional to the measurement of interest. For example, a diode may be provided by implanting an n-type region and/or a p-type region into functional sensor layer 52, which is similar to that used for gate contact 40, as discussed above. It is the same polysilicon layer. In some embodiments, the polysilicon layer may already be doped in some way (e.g., as a p-type layer) and thus only one implant is needed (e.g., to form an n-type region). injection). The diode may have a forward voltage drop that is proportional to temperature, allowing external sensing circuitry to measure the temperature of semiconductor die 10. Exemplary details of the embedded sensor element 22 are described below.

To further reduce parasitic signals coupled into the embedded sensor element 22, a noise reduction well 56 may be provided in the shield well 46, as shown in FIG. The noise reduction well 56 has a doping type that is opposite to that of the shield well 46 and has a doping type that is opposite to that of the shield well 46 and is provided through the first contact 50A and the second contact 50B and the first contact well 48A and the second contact well 48B, respectively. , in electrical contact. In the example shown in FIG. 3, noise reduction well 56 is an n-type region. Noise reduction well 56 may be an implanted region in drift layer 14, but may be provided by any suitable means. Those skilled in the art will appreciate that n-type wide bandgap semiconductor materials often have resistances up to three orders of magnitude lower than their p-type counterparts. By providing the noise reduction well 56, the resistance at the surface of the drift layer 14 below the embedded sensor element 22 can be further reduced, which in turn can reduce parasitic signals coupled into the embedded sensor element 22.

As discussed above, functional sensor layer 52 is part of the polysilicon layer that also forms gate contact 40. While this can reduce manufacturing steps, it is a blanket process in which the metallization or silicide effect globally affects the entire polysilicon layer, since the functional sensor layer 52 cannot constitute a sensing element. It is also possible to prevent the layer from becoming metallized or silicified. Metallization or silicidation of the polysilicon layer forming the gate contact may be desirable, since it can reduce resistance and thus improve the distribution of the gate signal across the semiconductor die 10 to improve switching speed and other performance characteristics. There is. Further, even with the use of shielding wells 46 and noise reduction wells 56, additional isolation between embedded sensor element 22 and drift layer 14 may be desired. Accordingly, FIG. 4 illustrates a further separate implanted sensor element 22 according to one embodiment of the present disclosure. The semiconductor die 10 shown in FIG. 4 is substantially the same as that shown in FIG. 2, except that there is an additional insulating layer 58 and an additional functional layer 60 between the embedded sensor element 22 and the drift layer 14. It's the same. In this example, functional sensor layer 52 is not part of the same layer used to form gate contact 40, but is added to that used to form gate contact 40. This is a "second level" polysilicon layer. The additional functional layer 60 as shown in FIG. 4 is part of the same layer used to form the gate contact 40, which in various embodiments as discussed above is It may also be a silicon layer. Two additional layers, namely an additional insulating layer 58 and a functional sensor layer 52, are provided over the additional functional layer 60, and the insulating layer 16, the additional functional layer 60, and the additional insulating layer 58 are embedded. Embedded sensor element 22 is configured to be between sensor element 22 and drift layer 14 . The two additional layers further provide shielding of the embedded sensor element 22 while adding only two additional necessary layers. Additional insulating layer 58 may include any suitable insulating material, such as _SiO2 . Functional sensor layer 52 may be a second level polysilicon layer, which is provided similarly to the first polysilicon layer forming gate contact 40 and additional functional layer 60, as described above. It will be done. The second level polysilicon layer provides advantages such as allowing the first polysilicon layer to be metallized or silicided, while adding an additional manufacturing step to make the semiconductor die 10. can improve the performance of semiconductor die 10, as described above.

To provide even more shielding, a noise reduction well 56 may be added to the semiconductor die 10 shown in FIG. 4. Such an embodiment is shown in FIG. As discussed above, noise reduction well 56 can further reduce parasitic voltages at the surface of drift layer 14 below embedded sensor element 22 by reducing the resistance in this area. Therefore, interference with the embedded sensor element 22 can be further reduced. Although not shown in FIGS. 4 or 5, in embodiments where additional functional layer 60 is partially or fully metallized and/or silicided, contact 50 may be electrically connected to additional functional layer 60. May be combined. This allows the embedded sensor element 22 to be further separated.

In the embodiment described above, the substrate 12 is an n-type layer with a thickness between 0.2 μm and 10.0 μm and a doping concentration between 1×10 ¹⁷ cm ⁻³ and 5×10 ²¹ cm ⁻³ . It's okay. Drift layer 14 may be an n-type layer with a thickness between 1.0 μm and 20.0 μm and a doping concentration between 1×10 ¹⁵ cm ⁻³ and 1×10 ¹⁷ cm ⁻³ . The shielding well 46 may be a p-type region with a thickness between 0.1 μm and 3.0 μm and a doping concentration between 1×10 ¹⁷ cm ⁻³ and 5×10 ²¹ cm ⁻³ . In various embodiments, the thickness of the shielding well 46 may be provided at any subrange between 0.1 μm and 3.0 μm, or at any discrete point within the range. For example, the thickness of the shielding well 46 may be between 0.1 μm and 2.5 μm, between 0.1 μm and 2.0 μm, between 0.1 μm and 1.5 μm, between 0.1 μm and 1.0 μm, Between 0.1 and 0.5 μm, between 0.5 and 3.0 μm, between 1.0 μm and 3.0 μm, between 1.5 μm and 3.0 μm, between 2.0 μm and 3.0 μm, It may be between 2.5 μm and 3.0 μm, between 0.5 μm and 2.5 μm, between 1.0 μm and 2.0 μm, between 1.5 μm and 2.0 μm, etc. Furthermore, the doping concentration of the shielding well 46 may be provided at any subrange between 1×10 ¹⁷ cm ⁻³ and 5×10 ²¹ cm ⁻³ or at any discrete point within the range. For example, the doping concentration of the shielding well 46 is between 5×10 ¹⁷ cm ⁻³ and 5×10 ²¹ cm ⁻³ , between 1×10 ¹⁸ cm ⁻³ and 5×10 ²¹ cm ⁻³ , and 5×10 ¹⁸ cm ⁻³ to 5×10 ²¹ cm ⁻³ , 1×10 ¹⁹ cm ⁻³ to 5×10 ²¹ cm ⁻³ , 5×10 ¹⁹ cm ⁻³ to 5×10 ²¹ cm ⁻³ , between 1×10 ²⁰ cm ⁻³ and 5×10 ²¹ cm ⁻³ , between 5×10 ²⁰ cm ⁻³ and 5×10 ²¹ cm ⁻³ , and between 1×10 ²¹ cm ⁻³ and 5×10 ²¹ cm ⁻ between ³ , between 1×10 ¹⁷ cm ⁻³ and 1×10 ²¹ cm ⁻³ , between 1×10 ¹⁷ cm ⁻³ and 5×10 ²⁰ cm ⁻³ , and between 1×10 ¹⁷ cm ⁻³ and 1× between 10 ²⁰ cm ^-3 , between 1 x 10 ¹⁷ cm ^-3 and 5 x 10 ¹⁹ cm ^-3 , between 1 x 10 17 cm ^-3 and 1 x ^{10 19 cm -3} , and 1 x 10 ¹⁷ cm ^- between ³ and 5×10 ¹⁸ cm ⁻³ , between 1×10 ¹⁷ cm ⁻³ and 1×10 ¹⁸ cm ⁻³ , between 1×10 ¹⁷ cm ⁻³ and 5×10 ¹⁷ cm ⁻³ , and 5× between 10 ¹⁷ cm ^-3 and 1 × 10 ²¹ cm ^-3 , between 1 × 10 ¹⁸ cm ^-3 and 5 × 10 ²⁰ cm ^-3 , and between 5 × 10 ¹⁸ cm ^-3 and 1 × 10 ²⁰ cm ^-3 and between 1×10 ¹⁹ cm ⁻³ and 5×10 ¹⁹ cm ⁻³ . Each one of the contact wells 48 is a p-type region having a thickness between 0.1 μm and 2.5 μm and a doping concentration between 1×10 ¹⁷ cm ⁻³ and 5×10 ²¹ cm ⁻³ . Good too. In various embodiments, the thickness of contact well 48 may be provided within any subrange between 0.1 μm and 2.5 μm, or at any discrete point within the range. For example, the thickness of the contact well 48 may be between 0.5 μm and 2.5 μm, between 1.0 μm and 2.5 μm, between 1.5 μm and 2.5 μm, between 2.0 μm and 2.5 μm, Between 0.1 μm and 2.0 μm, between 0.1 μm and 1.5 μm, between 0.1 μm and 1.0 μm, between 0.1 μm and 0.5 μm, between 0.5 μm and 2.0 μm, and may be between 1.0 μm and 1.5 μm. Additionally, the doping concentration of contact well 48 may be provided at any subrange between 1×10 ¹⁷ cm ⁻³ and 5×10 ²¹ cm ⁻³ or any discrete point within the range. For example, the doping concentration of the contact well 48 is between 5×10 ¹⁷ cm ⁻³ and 5×10 ²¹ cm ⁻³ , between 1×10 ¹⁸ cm ⁻³ and 5×10 ²¹ cm ⁻³ , and 5×10 ¹⁸ cm ⁻³ to 5×10 ²¹ cm ⁻³ , 1×10 ¹⁹ cm ⁻³ to 5×10 ²¹ cm ⁻³ , 5×10 ¹⁹ cm ⁻³ to 5×10 ²¹ cm ⁻³ , 1× between 10 ²⁰ cm ⁻³ and 5×10 ²¹ cm ⁻³ , between 5×10 ²⁰ cm ⁻³ and 5×10 ²¹ cm ⁻³ , and between 1×10 ²¹ cm ⁻³ and 5×10 ²¹ cm ⁻³ between 1×10 ¹⁷ cm ⁻³ and 1×10 ²¹ cm ⁻³ , between 1×10 ¹⁷ cm ⁻³ and 5×10 ²⁰ cm ⁻³ , and between 1×10 ¹⁷ cm ⁻³ and 1×10 ²⁰ cm ⁻³ , between 1×10 ¹⁷ cm ⁻³ and 5×10 ¹⁹ cm ⁻³ , between 1×10 ¹⁷ cm ⁻³ and 1×10 ¹⁹ cm ⁻³ , from 1×10 ¹⁷ cm ⁻³ between 5×10 ¹⁸ cm ⁻³ , between 1×10 ¹⁷ cm ⁻³ and 1×10 ¹⁸ cm ⁻³ , between 1×10 ¹⁷ cm ⁻³ and 5×10 ¹⁷ cm ⁻³ , and 5×10 ¹⁷ between ¹ ×10 ²¹ cm ^{−3 and 1×10 21 cm −3} , between 1×10 ¹⁸ cm ⁻³ and 5×10 ²⁰ cm ⁻³ , between 5×10 ¹⁸ cm ⁻³ and 1×10 ²⁰ cm ⁻³ , and may be between 1×10 ¹⁹ cm ⁻³ and 5×10 ¹⁹ cm ⁻³ . The noise reduction well 56 may be an n-type region having a thickness between 0.1 μm and 2.5 μm and a doping concentration between 1×10 ¹⁷ cm ⁻³ and 5×10 ²¹ cm ⁻³ . In various embodiments, the thickness of the noise reduction well 56 may be provided within any subrange between 0.1 μm and 2.5 μm, or at any discrete point within the range. For example, the thickness of the noise reduction well 56 may be between 0.5 μm and 2.5 μm, between 1.0 μm and 2.5 μm, between 1.5 μm and 2.5 μm, and between 2.0 μm and 2.5 μm. , between 0.1 μm and 2.0 μm, between 0.1 μm and 1.5 μm, between 0.1 μm and 1.0 μm, between 0.1 μm and 0.5 μm, between 0.5 μm and 2.0 μm , and between 1.0 μm and 1.5 μm. Further, the doping concentration of the noise reduction well 56 may be provided at any subrange between 1×10 ¹⁷ cm ⁻³ and 5×10 ²¹ cm ⁻³ or any discrete point within the range. For example, the doping concentration of the noise reduction well 56 may be between 5×10 ¹⁷ cm ⁻³ and 5×10 ²¹ cm ⁻³ , between 1×10 ¹⁸ cm ⁻³ and 5×10 ²¹ cm −3 , and between 5×10 18 cm ⁻³ and 5×10 21 cm −3 between ¹⁸ cm ⁻³ and 5×10 ²¹ cm ⁻³ , between 1×10 ¹⁹ cm ⁻³ and 5×10 ²¹ cm ⁻³ , and between 5×10 ¹⁹ cm ⁻³ and 5×10 ²¹ cm ⁻³ , between 1×10 ²⁰ cm ⁻³ and 5×10 ²¹ cm ⁻³ , between 5×10 ²⁰ cm ⁻³ and 5×10 ²¹ cm ⁻³ , and between 1×10 ²¹ cm ⁻³ and 5×10 ²¹ cm between ^-3 , between 1×10 ¹⁷ cm ⁻³ and 1×10 ²¹ cm ⁻³ , between 1×10 ¹⁷ cm ⁻³ and 5×10 ²⁰ cm ⁻³ , and between 1×10 ¹⁷ cm ⁻³ and 1 between ×10 ²⁰ cm ^-3 , between 1 × 10 ¹⁷ cm ^-3 and 5 × 10 ¹⁹ cm ^-3 , between 1 × 10 ¹⁷ cm -3 and 1 × 10 ¹⁹ cm ^-3 , ^and 1 × 10 ¹⁷ cm between ^-3 and 5×10 ¹⁸ cm ⁻³ , between 1×10 ¹⁷ cm ⁻³ and 1×10 ¹⁸ cm ⁻³ , between 1×10 17 cm ⁻³ and 5× ^{10 17 cm −3} , 5 between ×10 ¹⁷ cm ^-3 and 1 × 10 ²¹ cm ^-3 , between 1 × 10 ¹⁸ cm ^-3 and 5 × 10 ²⁰ cm ^-3 , and between 5 × 10 ¹⁸ cm ^-3 and 1 × 10 ²⁰ cm ^-3 and between 1×10 ¹⁹ cm ⁻³ and 5×10 ¹⁹ cm ⁻³ .

The improvements discussed above, i.e., separating the embedded sensor element 22 from the drift layer 14 by an insulating layer 16, providing a shielding well 46, minimizing the distance between contact wells 48, and providing a noise reduction well 56. , providing an additional insulating layer 58 , and providing an additional functional layer 60 , either alone or in combination, can significantly improve the isolation of the embedded sensor element 22 from the drift layer 14 . In particular, the improvements discussed herein allow greater than 50V DC isolation from high power portions of semiconductor die 10, such as its source and drain. In various embodiments, the improvements discussed herein are capable of greater than 75V and greater than 100V DC isolation. In general, the improvements discussed herein enable the inclusion of embedded sensor elements on wide bandgap power semiconductor die, and without these isolation measures, such embedded sensor elements would destroy their functionality. subject to such interference.

As discussed above, embedded sensor element 22 may be any suitable sensing element. In one embodiment, embedded sensor element 22 is a temperature sensing element. In particular, the embedded sensor element 22 may be a diode that exhibits a forward voltage drop proportional to temperature. Accordingly, FIG. 6 depicts a top down view of an implantable sensor element 22 according to one embodiment of the present disclosure. To illustrate, a first contact 50A and a second contact 50B are also shown. Embedded sensor element 22 includes an anode contact 62 and a cathode contact 64. Anode contact 62 is in electrical contact with p-type region 66 in functional sensor layer 52 . Cathode contact 64 is in electrical contact with n-type region 68 in functional sensor layer 52 . P-type region 66 and/or n-type region 68 may be provided via an implantation process of functional sensor layer 52 according to well-known processes. As shown, p-type region 66 and n-type region 68 may be separated by a region of material. This material region may be intrinsic (undoped) or doped in a different manner than p-type region 66 and n-type region 68.

In some scenarios, it may be desirable to have several diodes in series to match the forward voltage to a particular sensing circuit. Accordingly, FIG. 7 shows a top down view of an implantable sensor element 22 according to additional embodiments of the present disclosure. The embedded sensor element 22 shown in FIG. 7 is substantially the same as that shown in FIG. 6, except that it includes two diodes instead of one. Functional sensor layer 52 is separated into two separate parts, each used to form a discrete diode. These diodes are coupled through metal layers as shown. Although only two diodes are shown, those skilled in the art will appreciate that embedded sensor element 22 may include any number of discrete elements, including diodes, without departing from the principles of this disclosure.

FIG. 8 shows a top down view of an embedded sensor element 22 according to an additional embodiment of the present disclosure. Embedded sensor element 22 shown in FIG. 8 is substantially similar to that shown in FIG. 7, except that p-type region 66 and n-type region 68 are nested, so that each diode The required area can be reduced. Those skilled in the art will appreciate that the diodes can be formed using any number of layout techniques, all of which are contemplated herein.

In some embodiments, noise reduction well 56 is a blanket region below the entirety of embedded sensor element 22 . However, this provides a parasitic NPN transistor, which can cause problems in some situations. Accordingly, noise reduction well 56 may be patterned in some embodiments as shown in FIGS. 9 and 10. 9 and 10 show top down views of noise reduction well 56 and do not show embedded sensor element 22 or insulating layer 16 to avoid obscuring the drawings. In FIG. 9, noise reduction wells 56 are provided in a first wide grid pattern, while in FIG. 10, noise reduction wells 56 are provided in a tight grid pattern. It should be noted that these are only exemplary patterns, and those skilled in the art will readily understand that any suitable pattern can be used for the noise reduction wells 56 without departing from the principles of this disclosure.

Returning to the embodiment discussed above with respect to FIGS. 4 and 5, providing the embedded sensor element 22 on the second level polysilicon layer facilitates the implementation of other functional components in addition to the embedded sensor element 22. can be made possible. For example, a lumped resistor, which can be used as a gate resistor for a MOSFET, can be implemented in the second polysilicon layer with embedded sensor element 22. FIG. 11A thus shows a cross-sectional view of lumped resistor 70 according to one embodiment of the present disclosure. Lumped resistor 70 is provided in functional layer 52, which is the same as functional sensor layer 52 discussed above. Specifically, lumped resistor 70 is connected through a doped portion of polysilicon having a first resistive contact 72A and a second resistive contact 72B, as shown in the top down view of the lumped resistor in FIG. 11B. It will be established. Lumped resistor 70 may be coupled to gate contact 40 of MOSFET cell 24 to provide an on-chip gate resistor. In some embodiments, one of the resistive contacts 72 may provide a gate contact pad. In such a case, only one of the resistive contacts 72 may be provided, and the lumped resistor 70 may be internally coupled to the gate contact. However, in other embodiments, one of the resistive contacts 72 may be a gate contact pad and the other resistive resistor 70 may have a resistance of lumped resistor 70 during manufacturing to ensure the desired resistance is achieved. May be exposed so as to be measurable. As discussed above, functional sensor layer 52 is a polysilicon layer that is doped during growth (in-situ) or later via an implantation process, such as ion implantation, to obtain the desired resistance. There may be. Although lumped resistor 70 is shown as a simple rectangle in FIGS. 11A and 11B, lumped resistor 70 may be provided in any number of shapes. For example, the portion of functional sensor layer 52 forming lumped resistor 70 may be provided in a circular shape, a polygonal shape, or any other shape. Providing lumped resistor 70 in this manner allows lumped resistor 70 to improve performance when used as a gate resistor by improving current distribution and/or reducing parasitic signals. Those skilled in the art will understand that in addition to resistors, other functional components may also be implemented in the second level polysilicon layer.

Although not shown in the above figures, various metal contacts such as source contact 38, drain contact 42, contact 50, and resistive contact 72 may be provided even if they are not directly provided in the area to which they are electrically coupled. good. Rather, any number of passivation or encapsulation layers may separate these contacts from the areas of semiconductor die 10 that they contact, and connections between them may include vias through these layers. good.

FIG. 12 is a flow diagram illustrating a method of manufacturing a semiconductor die including an embedded sensor element according to one embodiment of the present disclosure. First, a drift layer is provided on a substrate (step 100). The drift layer includes a wide bandgap semiconductor material. Providing the drift layer may include growing the drift layer by any suitable semiconductor growth process. The drift layer is provided with one or more implants (step 102) to provide a shielding structure for functional semiconductor devices such as MOSFETs, BJTs, IGBTs, or thyristors, as well as embedded sensor elements. Shielding structures for embedded sensor elements may include one or more of the shielding wells, contact wells, and noise reduction wells discussed above. The implanted region may be provided by any suitable implantation process. An insulating layer is provided on the drift layer (step 104). The insulating layer may be provided with a gate oxide and a field oxide in different parts of the semiconductor die, and thus with different thicknesses in different parts thereof. A gate contact and a functional sensor layer are provided on the insulating layer (step 106). The gate contact and functional sensor layer may be a polysilicon layer provided by any suitable deposition process. A polysilicon layer may be deposited and patterned to create gate contacts and functional sensor layers. In some embodiments, the gate contact and functional sensor layer are not provided at the same time. Alternatively, the gate contact and the additional polysilicon layer are provided together, an additional insulating layer is provided on the additional polysilicon layer, and a functional sensor layer is provided on the additional insulating layer. The results of this approach are shown in FIGS. 4 and 5 above. One or more implant regions are then provided in the functional sensor layer to provide an embedded sensor element (step 108). For example, a p-type region and/or an n-type region may be provided to form a diode, which is used as a temperature sensor. Finally, a metal layer is provided, at least a portion of which is used to provide electrical contacts to the shielding structure and the embedded sensor element (step 110). In some embodiments, multiple metal layers may be provided, with a passivation or intermetal dielectric layer provided therebetween.

FIG. 13 illustrates a cross-sectional view of an implantable sensor element 22 according to one embodiment of the present disclosure. Embedded sensor element 22 is shown in FIG. 2 except that the cross-sectional view is perpendicular to that shown in FIG. A pair of sensor contact pads 74 are shown, substantially similar to those shown in FIG. Those skilled in the art will appreciate that in order to make an electrical connection with a portion of a semiconductor die, contact pads must be provided having certain minimum dimensions. The minimum dimensions may be based on the smallest size that a desired electrical connection, such as one or more wire bonds, can be achieved within certain process limits. The sensor contact layer 54 shown in FIG. 2 may be coplanar with one or more other metal features (e.g., source contact 38, contact 50, gate metal layer, etc.) so that The area available for the contact pads may be limited so that the contact pads do not overlap and therefore make electrical contact with these features. Accordingly, FIG. 13 shows contacts 50 mounted on first metal layer 76A and sensor contact pads 74 mounted on one or more additional metal layers 76B. An intermetal dielectric layer 78 is provided over the first metal layer 76A and provides a surface on which sensor contact pads 74 may be provided. Note that when the sensor contact pads 74 are provided on the intermetal dielectric layer 78, the contact pads can overlap the contacts 50 in the first metal layer 76 below, so there is more room for providing the contact pads. be. By moving sensor contact pads 74 onto an additional metal layer, the area available for sensor contact pads 74 is increased. This may provide more reliable contact with the implanted sensor element 22 and thus improve performance in some embodiments.

To further illustrate aspects of the present disclosure in which one or more additional metal layers are used to provide space for contact pads, FIG. 14 shows a diagram of a transistor semiconductor die 210 according to one embodiment of the present disclosure. A top view is shown. For illustrative purposes, transistor semiconductor die 210 is a vertical metal oxide semiconductor field effect transistor (MOSFET) that includes a passivation layer 212 with openings for a gate contact pad 214 and several source contact pads 216. It is a device. Transistor semiconductor die 210 is a vertical power device with a drain contact pad (not shown) located on the back side of the device. Gate contact pad 214 and source contact pad 216 may be provided as surfaces for coupling transistor semiconductor die 210 to external circuitry. Accordingly, gate contact pad 214 and source contact pad 216 may have a minimum size to ensure that they can connect. In one embodiment, the minimum size of each one of gate contact pad 214 and source contact pad 216 is 0.4 mm ² . In various embodiments, the minimum size of each one of gate contact pad 214 and source contact pad 216 is 0.5 mm ² , 0.6 mm ² , 0.7 mm ² , 0.8 mm ² , 0.9 mm ² , and may be up to 1.0 ^mm2 .

FIG. 15 shows a top view of transistor semiconductor die 210 with passivation layer 212 removed. Beneath the passivation layer 212 is a gate metal layer 218, a gate via bar 220 coupled to the gate metal layer 218, and a source metal layer 222. As discussed in more detail below, gate metal layer 218, gate via bar 220, and source metal layer 222 are provided by the same metallization layer; therefore, source metal layer 222, as shown, An opening 224 must be included to accommodate the entire area of gate metal layer 218 and gate via bar 220. FIG. 15 also shows device region 226 and edge termination region 228 of transistor semiconductor die 210. As discussed above, device region 226 includes one or more implants electrically coupled to one or more electrodes to provide selective current conduction and voltage blocking capabilities of the device. The region of the transistor semiconductor die 210 that includes the transistor semiconductor die 210 . Edge termination region 228 is provided to reduce electric field concentration at the edge of transistor semiconductor die 210, thus preventing breakdown at low reverse voltages.

FIG. 16 shows a top down view of transistor semiconductor die 210 with gate metal layer 218, gate via bars 220, source metal layer 222, and several other layers (discussed below) removed. Beneath these layers are several source regions 230 separated by several gate regions 232. Source regions 230 may be provided as regions having a doping type and/or doping concentration different from that of the drift layer in which they are located (e.g., a separate epitaxy step from the drift layer). on the other hand, the gate region 232 may be provided as a region in which the doping type and/or doping concentration of the drift layer is relatively unchanged or varied by different amounts. . Although the gate regions 232 are provided as stripes as shown in FIG. 16, the gate regions 232 may similarly be provided in a grid as illustrated in FIG. To provide the primary functionality of transistor semiconductor die 210, gate contact pad 214 must be in electrical contact with gate region 232, while source contact pad 216 must be in electrical contact with source region 230. It won't happen.

FIG. 18 illustrates a cross-sectional view of a portion of a transistor semiconductor die 210 according to one embodiment of the present disclosure. Transistor semiconductor die 210 includes a substrate 234 and a drift layer 236 above substrate 234. Some implants 238 at the surface of drift layer 236 provide source regions 230, while some non-implant regions between implants 238 provide gate regions 232. A number of gate electrodes 240 are provided on the gate region 232 such that each one of the gate electrodes 240 passes between the implants 238 on either side of the gate region 32 on which they are provided. Each one of gate electrodes 240 is separated from the surface of drift layer 236 by an oxide layer 242 . A number of source electrodes 244 are provided on the source region 230 such that each one of the source electrodes 244 is in contact with a different one of the implants 238. Gate metal layer 218 is separated from the surface of drift layer 236 by oxide layer 242 and coupled to a respective one of gate electrodes 240 in a plane not shown in FIG. It is provided on the surface of the drift layer 236. A dielectric layer 246 is provided over gate electrode 240 to keep gate electrode 240 electrically isolated from source electrode 244 . Source electrode 244 is exposed on the surface of dielectric layer 246. A source metal layer 222 is provided on dielectric layer 246 in contact with source electrode 244 . A drain metal layer 248 is provided on the opposite side of the substrate 234 from the drift layer 236.

As shown in FIGS. 15 and 18, source metal layer 222 and gate metal layer 218 are formed within device region 226 of transistor semiconductor die 210 in a single metallization step (i.e., a single, appropriately patterned metal layer). (as a metal layer). This means that source metal layer 222 and gate metal layer 218 are provided on the same surface/plane of transistor semiconductor die 210. Therefore, source metal layer 222 cannot overlap gate metal layer 218 and must instead include an opening for gate metal layer 218. Due to constraints on the size of gate metal layer 218 (e.g., minimum contact pad size for wire bonding), coverage of source metal layer 222 is therefore limited within device area 226 of transistor semiconductor die 210. . As shown in FIG. 18, the area below the source metal layer 222 is an active area that conducts current from the source metal layer 222 to the drain metal layer 248 by the drift layer 236. The area below the gate metal layer 218 is an inactive area because the drift layer 236 below the gate metal layer 218 does not allow current to flow. Accordingly, the total active area of device region 226, and thus the total current carrying capacity of transistor semiconductor die 210, may be limited for a given size of the die.

Accordingly, FIG. 19 depicts a cross-sectional view of a transistor semiconductor die 210 according to additional embodiments of the present disclosure. The transistor semiconductor die 210 shown in FIG. 19 is substantially similar to that shown in FIG. 18, but further includes an additional dielectric layer 250 over the dielectric layer 246. Specifically, gate electrode 240 and source electrode 244 are provided on the surface of drift layer 236 , and dielectric layer 246 is arranged such that gate electrode 240 is electrically isolated from source electrode 244 and source electrode 244 is electrically isolated from dielectric layer 246 . A source metal layer 222 is provided over the dielectric layer 246 and an additional dielectric layer 250 is provided over the gate electrode 240 and the source electrode 244 so as to be exposed at the surface. A gate metal layer 218 is provided above an additional dielectric layer 250 . Gate metal layer 218 is electrically coupled to gate electrode 240 by one or more vias 252 through dielectric layer 246 and an additional dielectric layer 250 (connected in a plane not shown in FIG. 19). Ru. As illustrated, the additional dielectric layer 250 can cause at least a portion of the gate metal layer 218 to overlap the source metal layer 222. One or more vias 252 are very small compared to the total area of gate metal layer 218. Therefore, only a very small opening in the source metal layer 222 is required, and the total area covered by the source metal layer 222 is thereby increased. As discussed above, since the area below the source metal layer 222 is the active area of the transistor semiconductor die 210, this effectively increases the total active area and thus the current carrying capacity of the transistor semiconductor die. In practice, the total inactive area of device region 226 of transistor semiconductor die 210 is less than the total area of gate metal layer 218, and in some embodiments less than the total area of gate contact pads 214, which was previously could not be achieved.

Increasing the active area of transistor semiconductor die 210 allows for increased current carrying capacity for a given size. Alternatively, increasing the active area of transistor semiconductor die 210 allows die size to be reduced without sacrificing current carrying capacity. This allows additional chips to be provided for a given wafer in turn when fabricating transistor semiconductor die 210. Although the examples discussed herein primarily relate to transistor semiconductor die 210 that constitutes a MOSFET device, the principles described herein are applicable to field effect transistor (FET) devices, bipolar junction transistor (BJT) devices, insulated gate - Applies equally to transistor semiconductor die 210 constituting a bipolar transistor (IGBT) device, or any other type of vertical transistor device with two or more top-level contacts. With this in mind, gate contact pads 214 may be referred to collectively as first contact pads, source contact pads 216 may be referred to collectively as second contact pads, and source metal layer 222 may be referred to as first contact pads. The gate metal layer 218 may be referred to collectively as a second metallization layer, the source region 230 may be referred to collectively as a first set of regions, and the gate region may be referred to as a first set of regions. This may be collectively referred to as a set of second areas.

In one embodiment, substrate 234 and drift layer 236 are silicon carbide. Using silicon carbide for substrate 234 and drift layer 236 can significantly increase the performance of transistor semiconductor die 210 compared to using conventional material systems such as silicon. Although not shown, implant 238 may optionally include several different implant regions therein to provide selective current conduction and voltage blocking capabilities of transistor semiconductor die 210. Dielectric layer 246 and additional dielectric layer 250 may include one or more layers of Al ₂ O ₃ and SiO ₂ , for example, alternating. In other examples, dielectric layer 246 and additional dielectric layer 250 may include one or more layers of Si ₃ N ₄ and SiO ₂ , eg, alternating. In general, dielectric layer 246 and additional dielectric layer 250 may include any suitable dielectric material, such as one with a wide bandgap (>~5 eV) and a relatively low dielectric constant. Dielectric layer 246 and additional dielectric layer 250 may include the same or different materials. An additional passivation layer, including Si ₃ N ₄ , Al ₂ O ₃ , AlN, SiO ₂ or any other suitable material, may optionally be added to the dielectric layer 246 to avoid interaction between the materials. and additional dielectric layers 250 may be alternated. Passivation layer 212 may include Si ₃ N ₄ , Al ₂ O ₃ , AlN, SiO ₂ or any other suitable material in various embodiments.

FIG. 20A is a graph illustrating the improvement in current carrying capacity to transistor semiconductor die 210 due to movement of gate metal layer 218 over source metal layer 222. The solid line illustrates the relationship between current carrying capacity and size of transistor semiconductor die 210 without modification of the contact pad layout, as shown in FIG. The dashed line illustrates the same relationship between the current carrying capacity of transistor semiconductor die 210 with the improvements discussed above with respect to FIG. This graph assumes a constant rated blocking voltage (eg, 1200V). As illustrated, the improvement in current carrying capacity of transistor semiconductor die 210 is realized regardless of die size. As discussed above, this is due to the increased active area of device region 226.

FIG. 20B is a graph further illustrating the improvement in current carrying capacity to the transistor semiconductor die 210 due to movement of the gate metal layer 218 over the source metal layer 222. The graph illustrates the relationship between the percentage increase in current carrying capacity (compared to a transistor semiconductor die without improvements as illustrated in FIG. 18) and the current rating of the transistor semiconductor die 210. As illustrated, the rate at which the current carrying capacity of transistor semiconductor die 210 increases has an inverse relationship to the current rating of transistor semiconductor die 210. This is because as the current rating of transistor semiconductor die 210 increases, its overall size also increases. Therefore, the active area reclaimed as a result of the movement of gate metal layer 218 above source metal layer 222 accounts for a smaller percentage of the total active area of the device, thereby reducing the current carrying capacity seen with the use of these improvements. Reduce the rate of increase in. FIG. 20B illustrates that the greatest improvement in device performance with the improvements discussed herein is seen at lower current ratings.

FIG. 20C is a graph further illustrating the improvement in current carrying capacity to transistor semiconductor die 210 due to movement of gate metal layer 218 over source metal layer 222. The graph shows the percentage increase in current carrying capacity (compared to a transistor semiconductor die without improvements as illustrated in FIG. 18) versus the voltage rating of the transistor semiconductor die 210. As illustrated, the rate at which the current carrying capacity of the transistor semiconductor die 210 increases is positively related to the voltage rating of the transistor semiconductor die 210. The illustrated graph assumes a constant size of transistor semiconductor die 210. The relationship between percentage increase in current carrying capacity and voltage rating is due to the fact that as the voltage rating of transistor semiconductor die 210 increases, the size of edge termination region 228 also increases. Accordingly, the size of device region 226 is reduced such that the active area reclaimed as a result of movement of gate metal layer 218 over source metal layer 222 accounts for a greater proportion of the total active area of the device, thereby The use of these improvements further increases the percentage increase in current carrying capacity seen. FIG. 20C illustrates that the greatest improvement in device performance for a given chip size is seen at higher voltage ratings.

FIG. 21 shows a top down view of a transistor semiconductor die 210 according to one embodiment of the present disclosure. Specifically, FIG. 21 shows transistor semiconductor die 210 with gate metal layer 218 and additional dielectric layer 250 removed. Underneath the additional dielectric layer 250, a source metal layer 222 is exposed. Gate via bar 220 is still present in the embodiment shown in FIG. A first dashed box 254 illustrates the area over which the gate metal layer 218 is provided. This area may correspond to the boundaries of gate contact pads 214 or may extend beyond the boundaries of gate contact pads 214. In other words, the entire gate metal layer 218 may be exposed through the passivation layer 212, such as the gate contact pad 214, and a portion of the gate metal layer 218 may be exposed through the passivation layer 212, such as the gate contact pad 214. 214 may be covered by a passivation layer 212. As shown, a portion of gate metal layer 218 covers gate via bar 220 such that gate contact pad 214 can contact gate electrode 240 that is coupled to gate via bar 220. can. Second dashed box 256A and third dashed box 256B illustrate the area of source contact pad 216. Gate via bar 220 is still located on the surface of drift layer 236, so source metal layer 222 is still required to have opening 258 sized to accommodate gate via bar 220. However, the overall size of gate via bar 220 is much smaller than that of a conventional gate contact pad. Accordingly, the size of the active area within device region 226 of transistor semiconductor die 210 can be significantly increased.

FIG. 22 shows a top down view of a transistor semiconductor die 210 according to additional embodiments of the present disclosure. Specifically, FIG. 22 shows transistor semiconductor die 210 with gate metal layer 218 and additional dielectric layer 250 removed. Underneath the additional dielectric layer 250, a source metal layer 222 is exposed. Gate via bars 220 are removed in the embodiment shown in FIG. Replaced by gate contact vias 260, these are then coupled together on the surface of drift layer 236 (eg, in a lattice configuration as shown above). A first dashed box 254 illustrates the area over which the gate metal layer 218 is provided. As shown, a portion of gate metal layer 218 covers gate contact via 260, thereby connecting gate contact pad 214 to gate electrode 240. Second dashed box 256A and third dashed box 256B illustrate the area of source contact pad 216. Gate contact via 260 may have an even smaller area than gate via bar 220. Therefore, the total size of the opening 258 in the source metal layer 222 that accommodates the connection from the gate contact pad 214 to the gate electrode 240 can be further reduced, thereby allowing active The area can be made even larger.

As the size of the connection between gate contact pad 214 and underlying gate electrode 240 decreases, the gate resistance of transistor semiconductor die 210 may increase. Accordingly, the size and shape of gate contact pad 214, gate metal layer 218, and number and placement of gate contact vias 260 can be adjusted while simultaneously maximizing the active portion of device area 226, as illustrated in FIGS. 23 and 24. The transistor semiconductor die 210 can be arranged to minimize gate resistance. In FIGS. 23 and 24, first dashed box 254 represents the placement of gate metal layer 218 over gate contact via 260. In FIGS. Gate contact pad 214 may correspond to all or a subset of gate metal layer 218, as discussed above. Second dashed box 256A and third dashed box 256B again represent the area of source contact pad 216. In FIG. 23, fourth dashed box 256C and fifth dashed box 256D represent additional areas of source contact pads 216 that may be provided.

In addition to maximizing the active portion of device area 226 of transistor semiconductor die 210, additional dielectric layers 250 may also be used to provide additional features. Accordingly, FIG. 25 depicts a top down view of a transistor semiconductor die 210 according to one embodiment of the present disclosure. Specifically, FIG. 25 shows transistor semiconductor die 210 with passivation layer 212 removed. Beneath the passivation layer 212 is an additional dielectric layer 250 through which the gate contact pad 214 and source contact pad 216 are exposed. In addition to these contact pads, several sensor contact pads 262 are provided on the additional dielectric layer 250. Sensor contact pad 262 is coupled to a sensor 264, such as the embedded sensor element 22 described above. Sensor 264 may be any type of sensor (eg, a temperature sensor, a strain sensor, or a current sensor). Sensor 264 may also be located on the surface of additional dielectric layer 250 or further down the layer stack, such as on dielectric layer 246, on drift layer 236, or within drift layer 236. If sensor 264 is located in drift layer 236, it may compromise the total active area of device region 226. However, the sensor 264 is overall very small compared to the size of the device region 226, so having the sensor in the drift layer 236 may result in only a slight reduction in the active area of the device region 226. be. Overall, the sensor contact pad 262 is much larger than the sensor 264 itself, and because the sensor contact pad 262 can be located above the source metal layer 222, the active area of the device region 226 is much larger than the sensor 264 itself. The impact of introducing one or more sensors within is minimal. Sensor contact pad 262 may be formed by the same metallization layer (ie, in the same metallization step) as gate metal layer 218 in some examples.

FIG. 26 illustrates a cross-sectional view of a transistor semiconductor die 210 according to one embodiment of the present disclosure. The transistor semiconductor die 210 shown in FIG. 26 is substantially similar to that shown in FIG. 19, except that sensor contact pads 262 are shown on the surface of the additional dielectric layer 250. Although sensor 264 is not shown in FIG. 26, sensor 264 may be located behind sensor contact pads 262 on additional dielectric layer 250.

FIG. 27 shows a cross-sectional view of a transistor semiconductor die 210 according to additional embodiments of the present disclosure. The transistor semiconductor die 210 shown in FIG. 27 is substantially similar to that shown in FIG. are doing. Sensor 264 may include one or more implanted regions in drift layer 236 such that sensor 264 can be any type of semiconductor device. Sensor 264 may be used to measure temperature, strain, current, voltage, or any other desired parameter. As discussed above, sensor contact pads 262 require a larger overall area to implement than sensors 264 and sensor contact vias 266. Sensor 264 is attached to transistor semiconductor die 210 over the active area of device region 226 by providing sensor contact pad 262 on additional dielectric layer 250 such that sensor contact pad 262 at least partially overlaps source metal layer 222. Reduce the impact of providing Although a sensor 264 is shown in drift layer 236, sensor 264 may be located anywhere above or below drift layer 236 and may include any number of vias and intervening metal layers without departing from the principles of this disclosure. May be combined using

FIG. 28 shows a cross-sectional view of a transistor semiconductor die 210 according to additional embodiments of the present disclosure. Transistor semiconductor die 210 further includes a first intervening layer 268A between dielectric layer 246 and additional dielectric layer 250 and a second intervening layer 268B between additional dielectric layer 250 and gate metal layer 218. It is substantially similar to that shown in FIG. 19, except that. First intervening layer 268A and second intervening layer 268B can reduce chemical interactions between dielectric layer 246, additional dielectric layer 250, gate metal layer 218, and source metal layer 222. This is important because the additional dielectric layer 250 may require a densification anneal for good dielectric properties. The first intervening layer 268A and the second intervening layer 268B may include various layers of Si ₃ N ₄ , Al ₂ O ₃ , AlN, SiO ₂ , the same, or any other suitable material. As discussed above, dielectric layer 246 and additional dielectric layer 250 may include SiO ₂ or any other suitable material. As shown, second intervening layer 268B may be provided after the openings for one or more vias 252 are created. Accordingly, the second intervening layer 268B is configured such that the second intervening layer 268B reduces chemical interactions between the metals of the one or more vias 252, the dielectric layer 246, and the additional dielectric layer 250. One or more vias 252 may be provided along the edges. One or more vias 252 may include a single conductive metal, the same or different than gate metal layer 218, or form a chemical or diffusion barrier layer along the walls of one or more vias 252. Stacks of different metals may be included as needed to achieve this.

FIG. 28 also shows a passivation layer 212 over the gate metal layer 218. Passivation layer 212 can protect transistor semiconductor die 210 from the surrounding environment. Passivation layer 212 may include alternating layers of Si ₂ N ₄ , Al ₂ O ₃ , SiO ₂ , the same, or any other suitable material.

Transistor semiconductor die 210 may be a power semiconductor die configured to conduct at least 0.5A in a forward conducting mode of operation and blocking at least 100V in a blocking mode of operation. In various embodiments, the transistor semiconductor die 210 has a current of at least 1.0 A, at least 2.0 A, at least 3.0 A, at least 4.0 A, at least 5.0 A, at least 6.0 A, at least It may be configured to conduct 7.0A, at least 8.0A, at least 9.0A, and at least 10.0A. Transistor semiconductor die 210 may be configured to block at least 250V, at least 500V, at least 750V, at least 1 kV, at least 1.5 kV, and at least 2.0 kV in the blocking mode of operation. The same parameters apply to semiconductor die 10 discussed above.

It is contemplated that any of the foregoing aspects and/or the various separate aspects and features as described herein may be combined for further advantages. Any of the various embodiments as disclosed herein may be combined with one or more other disclosed embodiments unless indicated to the contrary herein.

Those skilled in the art will recognize improvements and modifications to the preferred embodiments of this disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.

Claims (58)

A semiconductor device comprising: a drift layer comprising a wide bandgap semiconductor material; and an embedded sensor element. 2. The semiconductor device of claim 1, wherein the embedded sensor element is a temperature sensing element. 3. The semiconductor device of claim 2, further comprising an insulating layer between the drift layer and the embedded sensor element. 4. The semiconductor device of claim 3, further comprising a shielding well between the drift layer and the embedded sensor element, the shielding well having a doping type that is opposite to a doping type of the drift layer. 5. The semiconductor device of claim 4, wherein the shielding well is an implant region in the drift layer. further comprising: a first contact in electrical contact with the shield well; and a second contact in electrical contact with the shield well, the embedded sensor element being in contact with the first contact and the second contact. 6. The semiconductor device according to claim 5, wherein the semiconductor device is between a contact point of the semiconductor device. a first contact well,
the first contact well is an implant region in the shield well;
the first contact well has the same doping type as the shield well and has a doping concentration greater than the doping concentration of the shield well;
The first contact is in electrical contact with the shield well through the first contact well, and the first contact well and the second contact well,
the second contact well is an implant region in the shield well;
the second contact well has the same doping type as the shield well and has a doping concentration greater than the doping concentration of the shield well;
7. The semiconductor device of claim 6, wherein the second contact further comprises a second contact well in electrical contact with the shield well via the second contact well. 7. The semiconductor device of claim 6, wherein the first contact and the second contact are electrically coupled to a fixed potential. 7. The semiconductor device according to claim 6, wherein a distance between the first contact and the second contact is 200 μm or less. 10. The semiconductor device of claim 9, wherein the distance between the first contact and the second contact is 100 μm or less. 11. The semiconductor device of claim 10, wherein the distance between the first contact and the second contact is 50 μm or less. 12. The semiconductor device of claim 11, wherein the distance between the first contact and the second contact is at least 5 μm. Additionally equipped with a noise reduction well,
the noise reduction well has a doping type that is opposite to the doping type of the shielding well;
the noise reduction well is separated from the drift layer by at least a portion of the noise reduction well;
7. The semiconductor device of claim 6, wherein the first contact and second contact are in electrical contact with the noise reduction well. further comprising an additional functional layer and an additional insulating layer between the drift layer and the embedded sensor element, the insulating layer being on the drift layer, the additional functional layer being on the insulating layer, and the 5. The semiconductor device of claim 4, wherein an additional insulating layer is on the additional functional layer and the embedded sensor element is on the additional insulating layer. 15. The semiconductor device of claim 14, wherein the additional functional layer comprises polysilicon. 15. The semiconductor device of claim 14, wherein the additional functional layer comprises polysilicon that is one of at least partially metallized and at least partially silicided. 15. The semiconductor device of claim 14, further comprising a lumped resistance element on the additional insulating layer. The semiconductor device includes an active area;
the active area includes one or more implant regions configured to provide a metal oxide semiconductor field effect transistor (MOSFET);
18. The semiconductor device of claim 17, wherein the lumped resistance element is coupled to a gate of the MOSFET. Additionally equipped with a noise reduction well,
the noise reduction well has a doping type that is opposite to the doping type of the shielding well;
the noise reduction well is separated from the drift layer by at least a portion of the noise reduction well;
15. The semiconductor device of claim 14, wherein the first contact and the second contact are in electrical contact with the noise reduction well. 4. The semiconductor device of claim 3, further comprising an active area, the active area including one or more implant regions configured to provide a switching power semiconductor device. 21. The semiconductor device of claim 20, wherein the switching power semiconductor device is a metal oxide semiconductor field effect transistor (MOSFET). 22. The semiconductor device of claim 21, wherein the MOSFET is a vertical MOSFET. 21. The semiconductor device of claim 20, wherein the switching power semiconductor device is one of a bipolar junction transistor (BJT), an insulated gate bipolar transistor (IGBT), and a thyristor. 21. The semiconductor device of claim 20, wherein the wide bandgap semiconductor material comprises silicon carbide. 21. The semiconductor device of claim 20, wherein the wide bandgap semiconductor material includes one of gallium nitride, gallium oxide, and zinc oxide. intermetal dielectric layer,
the sensor contact pad on the intermetal dielectric layer such that the sensor contact pad at least partially overlaps one of the first contact and the second contact; the sensor contact pad electrically isolated from the first contact and the second contact by a portion; and the intermetal dielectric layer such that a via electrically couples the sensor contact pad to the embedded sensor element. 8. The semiconductor device of claim 7, further comprising: the via extending through the via. 4. The semiconductor device of claim 3, wherein the embedded sensor element is a diode. a drift layer is provided, the drift layer comprising a wide bandgap semiconductor material;
A method of manufacturing a semiconductor device comprising providing an embedded sensor element. 29. The method of claim 28, wherein the embedded sensor element is a temperature sensing element. 30. The method of claim 29, further comprising providing an insulating layer between the drift layer and the embedded sensor element. 30. The method of claim 29, further comprising providing a shielding well between the drift layer and the embedded sensor element, the shielding well having a doping type that is opposite to a doping type of the drift layer. 32. The method of claim 31, wherein providing the shield well includes implanting the shield well into the drift layer. providing a first contact in electrical contact with the shielding well;
33. The method of claim 32, further comprising providing a second contact in electrical contact with the shielding well such that the embedded temperature sensing element is between the first contact and the second contact. Method described. a first contact well,
the first contact well is an implant region in the shield well;
the first contact well has the same doping type as the shield well and has a doping concentration greater than the doping concentration of the shield well;
the first contact is in electrical contact with the shield well through the first contact well;
a second contact well,
the second contact well is an implant region in the shield well;
the second contact well has the same doping concentration as the shield well and has a doping concentration greater than the doping concentration of the shield well;
34. The method of claim 33, further comprising providing the second contact well, wherein the second contact is in electrical contact with the shield well through the second contact well. 34. The method of claim 33, wherein the first contact and the second contact are electrically coupled to a fixed potential. 34. The method of claim 33, wherein the first contact and the second contact are provided such that the distance between the first contact and the second contact is less than 200 [mu]m. 37. The method of claim 36, wherein the first contact and the second contact are provided such that the distance between the first contact and the second contact is less than 100 μm. 38. The method of claim 37, wherein the first contact and the second contact are provided such that the distance between the first contact and the second contact is less than 50 μm. 39. The method of claim 38, wherein the first contact and the second contact are provided such that the distance between the first contact and the second contact is at least 5 μm. further comprising providing a noise reduction well;
the noise reduction well has a doping type that is opposite to the doping type of the shielding well;
the noise reduction well is separated from the drift layer by at least a portion of the noise reduction well;
34. The method of claim 33, wherein the first contact and second contact are in electrical contact with the noise reduction well. further comprising providing an additional functional layer and an additional insulating layer between the drift layer and the embedded sensor element, the insulating layer being on the drift layer, and the additional functional layer being on the insulating layer. 41. The method of claim 40, wherein the additional insulating layer is on the additional functional layer and the embedded sensor element is on the additional insulating layer. 42. The method of claim 41, wherein the additional functional layer comprises polysilicon. 42. The method of claim 41, wherein the additional functional layer comprises polysilicon that is one of at least partially metallized and at least partially silicided. 42. The method of claim 41, further comprising providing a lumped resistive element on the additional insulating layer. further comprising providing the active area with the one or more implant regions such that the one or more implant regions provide a metal oxide semiconductor field effect transistor (MOSFET), wherein the lumped resistance element is a metal oxide semiconductor field effect transistor (MOSFET). 45. The method of claim 44, wherein the method is coupled to a gate. further comprising providing a noise reduction well;
the noise reduction well has a doping type that is opposite to the doping type of the shielding well;
the noise reduction well is separated from the drift layer by at least a portion of the noise reduction well;
42. The method of claim 41, wherein the first contact and the second contact are in electrical contact with the noise reduction well. 30. The method of claim 29, further comprising providing the one or more implant regions in an active area of the drift layer such that the one or more implant regions are configured to provide a switching power semiconductor device. the method of. 48. The method of claim 47, wherein the switching power semiconductor device is a metal oxide semiconductor field effect transistor (MOSFET). 49. The method of claim 48, wherein the MOSFET is a vertical MOSFET. 48. The method of claim 47, wherein the switching power semiconductor device is one of a bipolar junction transistor (BJT), an insulated gate bipolar transistor (IGBT), and a thyristor. 48. The method of claim 47, wherein the wide bandgap semiconductor material comprises silicon carbide. 48. The method of claim 47, wherein the wide bandgap semiconductor material includes one of gallium nitride, gallium oxide, and zinc oxide. 30. The method of claim 29, wherein the embedded sensor element is a diode. substrate,
a drift layer on the substrate;
an insulating layer on the drift layer;
a first functional layer on the insulating layer;
A semiconductor device comprising: an additional insulating layer on the first functional layer; and a lumped resistance element on the additional insulating layer. 55. The semiconductor device of claim 54, wherein the first functional layer comprises polysilicon. 56. The semiconductor device of claim 55, wherein the first functional layer comprises polysilicon that is one of partially metallized and partially silicided. The semiconductor device includes an active area including one or more implant regions in the drift layer, the one or more implant regions configured to provide a metal oxide semiconductor field effect transistor (MOSFET); 57. The semiconductor device of claim 56, wherein the lumped resistance element is coupled to a gate of the MOSFET. 58. The semiconductor device of claim 57, wherein the first functional layer provides a gate electrode of the MOSFET.