KR20230139792A - Methods and apparatus to reduce error in operational amplifiers - Google Patents

Abstract

The exemplary device couples the first switch input to the first switch output and the second switch input to the second switch output based on the control signal in the first state; a switch circuit configured to connect the first switch input to the second switch output and the second switch input to the first switch output based on the control signal in the second state; In response to the control signal, generate a first voltage based on the gain and connections in the first state; In response to the control signal, the operational amplifier is configured to generate a second voltage based on the gain and connections in the second state; and an analog-to-digital converter (ADC) configured to convert the first voltage and the second voltage to digital values based on multiplication of the input voltage and the gain.

Description

Method and apparatus for reducing errors in operational amplifiers {METHODS AND APPARATUS TO REDUCE ERROR IN OPERATIONAL AMPLIFIERS}

Cross-reference to related applications

This patent application claims the benefit and priority of Indian Provisional Patent Application No. 202241017794, filed on March 28, 2022, the entire contents of which are incorporated herein by reference.

technology field

This description relates generally to operational amplifiers (op amps), and more specifically to methods and devices for reducing errors in operational amplifiers.

Operational amplifiers are often used in analog circuits to generate an output voltage that is amplified relative to the input voltage. In some examples, the ratio of the output voltage of an operational amplifier to the input voltage of the operational amplifier is referred to as the gain of the operational amplifier. In some configurations, such as a negative feedback loop, the gain of the operational amplifier can be configured by external components.

For methods and apparatuses for reducing error in operational amplifiers, an example device includes, in a first state, based on a control signal, a first switch input to a first switch output and a second switch input to a second switch input. Connect to the switch output; a switch circuit configured to connect the first switch input to the second switch output and the second switch input to the first switch output based on the control signal in the second state; In response to the control signal, generate a first voltage based on the gain and connections in the first state; an operational amplifier configured to generate a second voltage based on the gain and connections in the second state, in response to the control signal; and an analog-to-digital converter (ADC) configured to convert the first voltage and the second voltage to digital values based on multiplication of the input voltage and the gain.

1 is an exemplary block diagram of a computer system.
Figure 2 shows example block diagrams of the example offset controller circuit of Figure 1;
FIG. 3 is an exemplary circuit diagram of the switch circuit and operational amplifier of FIG. 1.
FIG. 4 is an example block diagram of the analog-to-digital converter (ADC) circuit of FIG. 1.
Figure 5 shows a timing diagram illustrating the compute output signal, chop control signal, and ADC output signal of Figure 1, as well as the ADC start of conversion (SOC) signal and sample output signal of Figure 4.
FIG. 6 is histograms illustrating errors in the offset controller circuit of FIG. 1.
Identical reference numerals or different reference designators are used in the drawings to indicate identical or similar (functionally and/or structurally) features.

The drawings are not necessarily drawn to scale. Generally, like reference numerals in the drawing(s) and this description refer to identical or similar parts. Although the drawings show areas with clean lines and boundaries, some or all of these lines and/or boundaries may be idealized. In practice, boundaries and/or lines may be non-observable, blended and/or irregular.

Operational amplifiers are used in a variety of applications including signal processing, sensing, and control systems. In many applications, an operational amplifier is used as the initial calculation in the system, using the output of the operational amplifier to perform further calculations. In these applications, the performance of the operational amplifier can have a significant impact on the performance of the overall system. Accordingly, electronics manufacturers can continuously attempt to improve the performance and accuracy of operational amplifiers.

One way to characterize the performance of an op amp is its offset voltage. Offset voltage refers to the error in which the voltage produced by an operational amplifier is different from the expected voltage. For example, an operational amplifier with a gain of 10 can output 10.2 millivolts (mV) in response to a 1 mV signal, where 0.2 mV is due to the offset voltage. Offset voltage can occur due to differences between the voltages received at the input stages of transistors within an operational amplifier. Additionally, the magnitude of the offset voltage is affected by the temperature of the operational amplifier. Temperature drift, a metric that quantifies how much the offset voltage changes in response to changes in temperature, can also be used to characterize the performance of an operational amplifier.

In some examples, electronics manufacturers may use chopping techniques to mitigate offset voltage. When using the chopping technique, the output of the operational amplifier can be characterized as a square wave alternating between the maximum of G x (input voltage + offset voltage) and the minimum of G x (input voltage - offset voltage), where G is the operational amplifier refers to the benefits of Previous solutions using chopping techniques can mitigate the offset voltage by averaging the maximum and minimum voltages and implementing a frequency filter to eliminate offset voltage swings. However, previous solutions using chopping may require additional space in the integrated circuit to implement both the operational amplifier and frequency filter, increasing manufacturing costs.

Example methods, systems, and devices described herein describe an example operational amplifier implemented on an integrated circuit (such as a microprocessor) that includes an example analog-to-digital converter (ADC). Advantageously, offset swings resulting from using chopping techniques are eliminated when the exemplary ADC samples the output of the operational amplifier. As a result, examples herein illustrate techniques for removing offset voltage without the use of circuitry external to the microprocessor, such as a frequency filter. Additionally, the exemplary operational amplifier alternates between G x (input voltage plus offset voltage) and G x (input voltage minus offset voltage) at a rate determined by the example ADC. As a result, the example operational amplifier may exhibit lower offset voltage and lower temperature drift than previous solutions.

1 is an example block diagram of an example computer system 100. The example computer system 100 includes an example voltage source 102, an example input voltage 104, an example offset controller circuit 105, an example ADC output signal 120, an example memory 122, and Includes an example processor circuit 124. The example offset controller circuit 105 includes an example switch circuit 106A, an example offset voltage 108, an example operational amplifier 110, an example op amp output signal (OPAOUT) 112, and an example voltage divider. (114), an exemplary ADC (116), and an exemplary chop control signal (118).

Exemplary voltage source 102 generates input voltage 104. Exemplary voltage source 102 may be implemented as any type of device and may generate input voltage 104 for any purpose. For example, voltage source 102 may be a sensor circuit that generates input voltage 104 to perform a measurement. In another example, voltage source 102 may be a transceiver circuit that generates input voltage 104 in response to receiving data over a transmission medium (e.g., cell network, cable, etc.). In some examples, input voltage 104 may vary over time.

The exemplary offset controller circuit 105 receives input voltage 104 from voltage source 102 and generates digital values (i.e., '0' and '1' bits) representing the input voltage. The digital values may be referred to as example ADC output signal 120. The components within the example offset controller circuit 105 may be implemented together on an integrated circuit. In some examples, one or more of example voltage source 102, example memory 122, and example processor circuit 124 may be implemented on the same integrated circuit as example offset controller circuit 105. In other examples, one or more of example voltage source 102, example memory 122, and example processor circuit 124 may be implemented separately from example offset controller circuit 105.

Within example offset controller circuit 105, example switch circuit 106A includes a plurality of switches. The exemplary switch circuit 106A has two inputs and two outputs. Exemplary switch circuit 106A transitions between a first state and a second state based on chop control signal 118. In the first state, a first input in each of the example switch circuits 106A is connected to a first output and a second input is connected to a second output. In the second state, the first input in the example switch circuit 106A is connected to the second output and the second input is connected to the first output. Exemplary switch circuit 106A is further discussed with respect to FIG. 2 .

Within the example offset controller circuit 105, the example offset voltage 108 is a representation of the internal error in the operational amplifier 110. In the illustrative example of FIG. 1 , the exemplary offset voltage 108 is an external product from operational amplifier 110 to provide a visual indication of error, as well as to allow operational amplifier 110 to be functionally described as an ideal operational amplifier. It is expressed as An ideal op amp is a virtual model of an operational amplifier that has infinite input impedance, no output impedance, and produces no errors. The exemplary offset voltage 108 can be any value. In some examples, the example offset voltage 108 may change over time due to changes in ambient temperature.

Within the example offset controller circuit 105, the example operational amplifier 110 receives a differential input in the form of two input voltages from the switch circuit 106A. The exemplary operational amplifier 110 generates an op amp output signal 112, which is an output voltage amplified with respect to the input voltage between the differential pair of inputs. The gain of the operational amplifier 110 may be any value. In the examples used herein, the gain of operational amplifier 110 can be generalized as a variable G. Exemplary operational amplifier 110 is represented in FIG. 1 as an ideal operational amplifier. The actual implementation of example operational amplifier 110 is further discussed with respect to FIG. 3 .

Within the example offset controller circuit 105, the example voltage divider 114 is implemented by two or more resistors in series coupled to the op amp output signal 112 at a first node and coupled to ground at a second node. do. The exemplary voltage divider 114 also includes one or more intermediate nodes between the resistors connected in series. Each intermediate node represents an intermediate voltage that is less than the op amp output signal 112 but greater than ground (e.g., 0 volts (V)). The voltage at any intermediate node within voltage divider 114 is It can be explained as, where is the voltage from the op amp output signal 112, is the total resistance between the middle node and the first node, is the total resistance between the intermediate node and ground. In Figure 1, the manufacturer has one of the intermediate nodes The values of the resistors in the exemplary voltage divider 114 may be determined in advance to have a voltage of . This node is connected to the second input of switch circuit 106A. The values of the resistors used for voltage divider 114 values may be predetermined by the manufacturer and may be based on the gain G.

Within the exemplary offset controller circuit 105, an exemplary ADC 116 converts the op amp output signal 112, which is an analog voltage, to digital bits. The exemplary ADC 116 generates an ADC output signal 120 that includes a high supply voltage for logic '1' bits and a low supply voltage for logic '0' bits. The exemplary ADC 116 also generates a chop control signal 118. Exemplary chop control signals 118 are further discussed in connection with FIGS. 2 and 4 .

Exemplary memory 122 stores digital bits encoded in ADC output signal 120. Exemplary memory 122 may be implemented as any type of memory. For example, example memory 122 may be volatile memory or non-volatile memory. Volatile memory may be implemented by synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), RAMBUS® dynamic random access memory (RDRAM®), and/or any other type of RAM device. Non-volatile memory may be implemented by flash memory and/or any other desired type of memory device.

Exemplary processor circuit 124 may obtain digital bits from memory 122 and perform operations based on the digital bits. For example, digital bits may represent sensor readings, and processor circuitry 124 may perform operations by presenting the readings to a user on a display. In another example, the digital bits represent a message from an external device, and processor circuit 124 can perform operations by sending a response message to the external device. The example processor circuit 124 may be implemented by any type of processor device. Examples of processor devices include programmable microprocessors, field programmable gate arrays (FPGAs) capable of instantiating instructions, central processor units (CPUs), graphics processor units (GPUs), and digital signal processors (DSPs). , or microcontrollers, and integrated circuits such as application specific integrated circuits (ASICs).

Advantageously, the components of the example offset controller circuit 105 may be implemented together on a single integrated circuit, such as a microprocessor. Because ADCs are common components used in a variety of applications, manufacturers can design microprocessors to include an ADC by default. Accordingly, using the example ADC 116 to correct the offset voltage generated in the op amp output signal 112 does not require additional die space on the integrated circuit like the frequency filter of previous solutions.

The exemplary switch circuit 106A changes between a first state and a second state based on the chop control signal 118. In doing so, the example computer system 100 allows the op amp output signal 112 to and Implement a chopping technique that alternates between As used above and herein, refers to an exemplary input voltage 104, refers to an example offset voltage 108. Advantageously, the use of the exemplary ADC 116 to not only correct the offset voltage, but also determine when the op amp output signal 112 changes values via the chop control signal 118, provides better results than previous solutions. Resulting in smaller offset voltage and temperature drifts.

FIG. 2 shows example block diagrams of the example offset controller circuit 105 of FIG. 1 . Figure 2 includes example configurations 202 and 204. Example configurations 202 and 204 illustrate example switch circuit 106A in two different states. 2, offset voltage 108 is illustrated external to example operational amplifier 110, which is represented as an ideal operational amplifier.

Switch circuit 106A includes two inputs. In the example switch circuit 106A, a first input is connected to input voltage 104 and a second input is connected to the middle node of voltage divider 114. Switch circuit 106A additionally includes two outputs. In example configurations 202, 204, switch circuit 106A may be implemented by four single pole single throw (SPST) switches, which in turn may utilize transistors or other suitable switching circuit elements. It can be implemented using In these examples, within switch circuit 106A, a first SPST switch connects a first input to a first output, a second SPST switch connects a first input to a second output, and a third SPST switch connects a first input to a first output. Two inputs connect to the first output, and a fourth SPST switch connects the second input to the second output. In other examples, different numbers of different switches may be used to implement switch circuit 106A. For example, two single pole double throw (SPDT) switches may be implemented, where a given SPDT switch connects one of its inputs to both the first and second outputs.

Example configuration 202 shows example switch circuit 106A in a first state. In the first state, switch circuit 106A couples input voltage 104 to a first output and op amp output signal 112 to a second output. The first output of switch circuit 106A is then connected in series to an external representation of offset voltage 108. Accordingly, the voltage experienced by the positive input terminal of example operational amplifier 110 in example configuration 202 is am. Additionally, the characteristic of ideal op amps is that the output voltage increases until the voltage difference between the input terminals is 0V, thus increasing the feedback input. Accordingly, the voltage experienced by the negative input terminal of the example operational amplifier 110 in the example configuration 202 in the steady state is also am. These voltages are then amplified by G within the exemplary operational amplifier 110. Accordingly, when switch circuit 106A is in the first state, op amp output signal 112 is am.

Example configuration 204 shows example switch circuit 106A in a second state. In the second state, switch circuit 106A couples input voltage 104 directly to the negative terminal of operational amplifier 110 through a second output. Additionally, because the exemplary operational amplifier 110 is represented as an ideal operational amplifier, both terminals of the exemplary operational amplifier 110 must experience the input voltage 104. However, the positive input terminal of operational amplifier 110 is still connected in series with offset voltage 108. Accordingly, the voltage experienced by the positive input terminal is the sum of the offset voltage 108 and the voltage at the first output of switch circuit 106A. Therefore, for the positive terminal of operational amplifier 110 to experience input voltage 104, the voltage at the first output of switch circuit 106A is It must be. In the example configuration 204, the first output of the switch circuit 106A is connected in series to a second input of the switch circuit 106A, which in turn is connected in series to the output of the example voltage divider 114. Connected. The exemplary voltage divider 114 is designed to output a voltage with an amplitude less than the exemplary op amp output signal 112. Specifically, the output of the example voltage divider 114 has an amplitude that is reduced by a factor of G compared to the example op amp output signal 112. Accordingly, the voltage at the first output of switch circuit 106A is When switch circuit 106A is in the second state, exemplary op amp output signal 112 is am.

2 illustrates how example switch circuit 106A is used to alternate the value of op amp output signal 112 within example offset controller circuit 105. For example, when chop control signal 118 indicates that switch circuit 106A should be in a first state, example offset controller circuit 105 may It operates in the example configuration 202 so that: In addition, when chop control signal 118 indicates that switch circuit 106A should be in the second state, example offset controller circuit 105 It operates in the example configuration 204 so that: Advantageously, the exemplary chop control signal 118 is generated by the exemplary ADC 116. As a result, the frequency at which the chop control signal 118 transitions between two values of the op amp output signal 112 is the frequency at which the exemplary ADC 116 converts the analog voltage to a digital value. is synchronous with the sampling rate. Synchronous implementation of the example chop control signal 118 through the example ADC 116 can reduce the magnitude of the offset voltage and temperature drift of the example operational amplifier 110 compared to previous solutions.

FIG. 3 is a circuit diagram of switch circuit 106A and exemplary operational amplifier 110 of FIG. 1 . 3 includes a switch circuit 106A, an exemplary operational amplifier 110, and an exemplary voltage divider 114. The exemplary operational amplifier 110 includes exemplary Positive Metal Oxide Semiconductor (PMOS) transistors 302, 304, 306, 308, 310, 312, 314, and exemplary Negative Metal Oxide Semiconductor (NMOS) transistors 316, 318. , 320, 322), and exemplary switch circuits 106B, 106C.

Exemplary PMOS transistors 302, 304, and 306 are configured to form the input stage of an operational amplifier. In the input stage, the current flowing through the drain gate of PMOS transistors 302 and 304 is proportional to the input voltage 104 and the voltage provided by voltage divider 114. The two voltages provided by switch circuit 106A are ideally equal in magnitude, but in practice may be different. The difference in magnitude between the voltages measured at 302 and 304 is the offset voltage 108.

Exemplary PMOS transistors 308, 310, 312, 314 and exemplary NMOS transistors 316, 318, 320, 322 collectively form a folded cascode amplifier. The gain of operational amplifier 110, which is a measure of the amplification of the voltage between NMOS transistors 318 and 322, is based on the transconductance of the transistors in the folded cascode amplifier.

In fact, the example operational amplifier 110 may include three example switch circuit 106A, 106B, and 106C implementations as described in FIG. 3 . Example switch circuits 106B and 106C may be implemented in a similar manner as example switch circuit 106A previously described. That is, the example switch circuits 106B and 106C each have two inputs and two outputs. Exemplary switch circuits 106B and 106C each transition between a first state and a second state based on chop control signal 118. Additionally, the exemplary switch circuits 106A, 106B, and 106C may be configured such that, at any point in time, all three switch circuits 106A, 106B, and 106C are in a first state or all are in a second state. Exemplary switch circuits 106B and 106C may each be implemented by four SPST switches, which in turn may be implemented using transistors or other suitable switching circuit elements. The exemplary switch circuits 106B and 106C are not required in FIGS. 1-2 to illustrate the exemplary operational amplifier 110 as an ideal operational amplifier; however, in reality, the exemplary operational amplifier 110 may have an exemplary chop control signal ( 118) in the first state based on and in the second state It may include example switch circuits 106A, 106B, and 106C, respectively, to output .

The exemplary switch circuit 106B has two inputs and two outputs. The two inputs of the example switch circuit 106B are coupled to the drain gates of the example PMOS transistors 308 and 310. The two outputs of the example switch circuit 106B are coupled to the source gates of the example PMOS transistors 312 and 314. When the example switch circuit 106B is in the first state, the drain gate of the example PMOS transistor 308 is coupled to the source gate of the example PMOS transistor 312 and the drain gate of the example PMOS transistor 310 is coupled to the source gate of the example PMOS transistor 310. is coupled to the source gate of the example PMOS transistor 314. When the example switch circuit 106B is in the second state, the drain gate of the example PMOS transistor 308 is coupled to the source gate of the example PMOS transistor 314 and the drain gate of the example PMOS transistor 310 is coupled to the source gate of the example PMOS transistor 314. is coupled to the source gate of the example PMOS transistor 312.

The example switch circuit 106C has two inputs and two outputs. The two inputs of the example switch circuit 106C are coupled to the source gates of the example NMOS transistors 316 and 318. The two outputs of the example switch circuit 106C are coupled to the drain gates of the example NMOS transistors 320 and 322. When the example switch circuit 106C is in the first state, the source gate of the example NMOS transistor 316 is coupled to the drain gate of the example NMOS transistor 320 and the source gate of the example NMOS transistor 318 is coupled to the drain gate of the example NMOS transistor 318. is coupled to the source gate of the example NMOS transistor 322. When the example switch circuit 106C is in the second state, the source gate of the example NMOS transistor 316 is coupled to the drain gate of the example NMOS transistor 322 and the source gate of the example NMOS transistor 318 is coupled to the drain gate of the example NMOS transistor 318. is coupled to the source gate of the exemplary NMOS transistor 320.

3 illustrates how an operational amplifier 110 can be designed at the transistor level to amplify the input voltage 104 and implement a chopping technique. Advantageously, operational amplifier 110 includes switch circuits 106B and 106C controlled by exemplary ADC 116 via chop control signal 118. As a result, the exemplary ADC 116 can generate digital bits that do not represent the offset voltage 108, eliminating the need for additional die space to remove the offset voltage with circuitry such as a frequency filter. Additionally, because the chop control signal 118 removes the offset by allowing the output of the operational amplifier to be sampled and averaged, the use of the exemplary ADC 116 to remove the offset voltage 108 reduces the magnitude of the offset voltage. reduce. Additionally, because the example ADC 116 is capable of performing chopping techniques at multiple temperatures, the temperature drift of the example operational amplifier 110 may be lower than previous solutions.

FIG. 4 is an example block diagram of the analog-to-digital converter (ADC) circuit of FIG. 1. The example ADC 116 includes an example chop controller circuit 402, an example sample and hold circuit 404, an example average circuit 406, and an example converter circuit 408. 4 also shows an example op amp output signal 112, an example chop control signal 118, an example ADC output signal 120, an example ADC SOC signal 410, and an example sample output signal 412. Includes.

Exemplary chop controller circuit 402 implements chopping techniques in accordance with the teachings of this disclosure. For example, the example chop controller circuit 402 receives the example ADC SOC signal 410 from the example sample and hold circuit 404 and synchronously generates the example chop control signal 118. The example chop controller circuit 402 also uses a chop control signal 118 to indicate when the switches should be in a first state and when the switches should be in a second state, as previously described in FIG. 2 . to exemplary switch circuits 106A, 106B, and 106C. The exemplary chop control signal 118 and exemplary ADC SOC signal 410 are further discussed with respect to FIG. 5 . The example chop controller circuit 402 further provides instructions to the example averager circuit 406 to indicate when the average voltage should be calculated.

The exemplary sample and hold circuit 404 receives the op amp output signal 112 generated by the exemplary operational amplifier 110. Using a clock circuit, the exemplary sample and hold circuit 404 records the voltage from the op amp output signal 112 and outputs the recorded voltage for an amount of time. In some examples, the recorded voltage may be referred to as a sample or conversion. The example sample and hold circuit 404 transmits the ADC SOC signal 410 to indicate when a new conversion has begun. Similarly, the amount of time the example sample and hold circuit 404 outputs a given written voltage may be referred to as the hold time. The exemplary sample and hold circuit 404 provides a sample output signal 412, which is the recorded voltage, to the exemplary averager circuit 406. An exemplary op amp output signal 112 is further discussed with respect to FIG. 5 .

The exemplary averager circuit 406 receives multiple voltages within the exemplary sample output signal 412 over time. For example, the example averager circuit 406 may receive a first written voltage for a first hold time, then receive a second written voltage for a second hold time, and so forth. Upon receiving instructions from the example chop controller circuit 402, the example averager circuit 406 calculates the average of the two previously recorded voltages within the example sample output signal 412. The exemplary averager circuit 406 provides the calculated average voltage to the converter circuit 408.

Exemplary converter circuit 408 converts the calculated average voltage to a digital value. A digital value can contain any number of bits. The example converter circuit 408 may generate digital values using any analog-to-digital conversion technique. For example, the example converter circuit 408 may implement a lookup table that describes which corresponding digital bits should be generated for any calculated average voltage within a range of values. In such examples, the lookup table may be pre-programmed within the converter circuit 408 or may be provided to the example converter circuit 408 by the processor circuit 124. The digital values generated by the example converter circuit 408 are referred to as example ADC output signal 120.

Advantageously, the exemplary ADC 116 includes an exemplary chop control signal 118, an ADC SOC signal 410, and an exemplary chop controller circuit 402 to synchronize when the averager circuit 406 calculates the average. do. The example chop controller circuit 402 has one of the voltages used as an input to the averager circuit 406. is the same as , and the other voltage used as the input to the averager circuit 406 is This allows the ADC 116 to remove the offset by ensuring that is equal to . As a result, the digital bits generated by the converter circuit 408 are Based on the calculated average voltage of Additionally, use of the example ADC circuit 116 to remove offset reduces the implementation area compared to previous solutions that required an external filter to achieve the same.

5 shows an example op amp output signal 112, an example chop control signal 118, an example ADC SOC signal 410, an example sample output signal 412, and an example ADC output signal 120. An exemplary timing diagram 502 is shown.

The example timing diagram 502 shows how the op amp output signal 112 changes over time. Ideally, the op amp output signal 112 is It can be expressed as a square wave oscillating in the surroundings. When the example switch circuits 106A, 106B, and 106C are in the first state, the example op amp output signal 112 is as shown in FIG. The voltage described as bigger than It's in the bolt. Similarly, when the example switch circuits 106A, 106B, and 106C are in the second state, the example op amp output signal 112 is as in FIG. The voltage described as lesser It's in the bolt.

An ideal square wave contains instantaneous transitions between voltages. In fact, the example operational amplifier 110 is as shown in FIG. 5 class It may require a certain amount of time to transition between them. In some examples, example operational amplifier 110 may additionally or alternatively use a target voltage ( or ) may overshoot or undershoot, and may require a certain amount of time to return to the target voltage. In some examples, the amount of time required for the example operational amplifier 110 to return to the target voltage after a transition occurs is referred to as settle time.

The exemplary timing diagram 502 shows the above-described signal over 2.5 cycles of the chopping frequency. During one cycle of the chopping frequency, the op amp output signal 112 is and Transition once between Additionally, during one period of the chopping frequency, the exemplary ADC 116 generates one digital value.

Exemplary chop control signals 118 include high and low supply voltages. When the example chop control signal 118 indicates a low supply voltage, the example switch circuits 106A, 106B, and 106C are in the first state as described above. Similarly, when the example chop control signal indicates a high supply voltage, the example switch circuits 106A, 106B, 106C are in the second state as described above.

Example ADC SOC signal 410 illustrates when example sample and hold circuit 404 samples op amp output signal 112. The example sample and hold circuit 404 begins sampling the example op amp output signal 112 when the ADC SOC signal 410 transitions from a low to a high supply voltage. Similarly, the example sample and hold circuit 404 terminates the sample when the ADC SOC signal 410 transitions from a high to a low supply voltage. The exemplary ADC SOC signal 410 is generated by an exemplary chop controller circuit 402.

Example sample output signal 412 represents the voltages that the ADC records during each sample. While the exemplary input voltage 104 may vary over time, the exemplary chop control signal 118 may be configured to provide an exemplary chop control signal 118 such that the voltage recorded during any ADC sample period can be represented by one of two values. Synchronize the control signal 118 and the exemplary ADC SOC signal 410. Specifically, Samples labeled are voltage refers to Samples labeled are voltage refers to For one period of the chopping frequency, the exemplary sample output signal 412 is One sample labeled with and Contains one sample labeled . To filter the offset voltage, the example converter circuit 408 generates digital bits based on the average of the voltages recorded during one period of the chopping frequency (i.e., the voltages from two consecutive samples). Specifically,

and here is the analog voltage generated by the averager circuit 406 and provided to the converter circuit 408.

Exemplary ADC output signal outputs 120 include one new digital value for each period of the chopping frequency. In the example timing diagram of FIG. 5, the example ADC output signal 120 is converted to Includes an example digital value 504 generated based on the first value of . After two additional samples of the example op amp output signal 112, the example converter circuit 408 Generates an example digital value 506 based on the second value of . Exemplary digital values 504, 506 may include any amount of data. For example, example digital values 504, 506 may include one or more bits, bytes, words, etc. of data.

Advantageously, the chop control signal 118 (indicating the value of the op amp output signal 112) is connected to the ADC SOC signal 410, which is transmitted from the sample and hold circuit 404 to the exemplary chop controller circuit 402. It is based on Accordingly, the exemplary ADC 116 determines that after a transition in the chop control signal 118 occurs, subsequent samples of the op amp output signal 112 have sufficient time for the op amp output signal 112 to stabilize. The chop control signal 118 and the ADC SOC signal 410 are generated synchronously in the sense that they do not start until . Specifically, the op amp output signal 112 is the instantaneous voltage of the op amp output signal 112 and the desired target voltage ( or ) can be considered stable when the difference between them is below the error threshold. In doing so, code 1 and code 2 of the example sample output signal 412 correspond to the desired target of the op amp output signal 112 rather than the overshoot or undershoot voltage that the example operational amplifier 110 generates during the settling time. Based on voltage.

FIG. 6 includes histograms illustrating the error of the operational amplifier of FIG. 1. Figure 6 includes example histograms 602 and 604.

Example histogram 602 illustrates the offset of example operational amplifier 110 across multiple simulations of example computer system 100 operation. In some examples, the offset of the example operational amplifier 110 may be calculated as the difference between the expected output voltage of the operational amplifier 110 and the measured voltage of the operational amplifier output signal 112. In other examples, the offset of the example operational amplifier 110 may be calculated as the difference between the measured voltage of the ADC output signal 120 and the expected output voltage of the ADC 116.

The x-axis of the example histogram 602 represents the offset in volts, and the y-axis of the example histogram 602 represents the number of simulations in which the offset was calculated between two specific voltages (i.e., in a specific bin of the histogram). indicates the number of simulations it belongs to. The example histogram 602 shows that, across all example simulations, the example operational amplifier 110 exhibited an offset with a magnitude of less than 202 microvolts (μV).

Example histogram 602 illustrates temperature drift of example operational amplifier 110 over multiple simulations of example computer system 100 operation. To calculate a single temperature drift value, the example computer system 100 is simulated multiple times to operate at multiple ambient temperatures, and an offset is calculated for each unique temperature simulation. The temperature drift is then It can be explained as, where is the temperature drift, is the highest recorded offset voltage, is the lowest recorded offset voltage, is the maximum operating temperature, is the minimum operating temperature.

The x-axis of the example histogram 604 represents the temperature drift in microvolts per degree Celsius (μV/°C), and the y-axis of the example histogram 604 represents the number of simulations in which the temperature drift was calculated between two specific values. (i.e., the number of simulations belonging to a specific bin of the histogram). The example histogram 604 shows that, across all example simulations, the example operational amplifier 110 exhibited a temperature drift with a magnitude of 1.18 μV/°C or less.

In this description, the term “and/or” (when used in conjunction with A, B and/or C) refers to (a) A alone; (b) B alone; (c) C alone; (d) A and B; (e) A and C; (f) B and C; and (g) any combination or subset of A, B, C, such as A, B, and C. Additionally, as used herein, the phrase “at least one of A or B” (or “at least one of A and B”) refers to (a) at least one of A; (b) at least one B; and (c) at least one A and at least one B.

Exemplary methods, devices, and articles of manufacture described herein improve the performance of operational amplifiers and reduce the amount of die space required to remove errors from the operational amplifier. The output of exemplary operational amplifier 110 is provided directly to exemplary ADC 116 to remove offset. Both the exemplary operational amplifier 110 and the exemplary ADC 116 are implemented on the same integrated circuit, eliminating the need to use additional die space on a separate circuit to eliminate offset. Additionally, the exemplary ADC 116 controls both when the output of the operational amplifier is changed and when the output of the operational amplifier is sampled to form a digital value. As a result, the offset and temperature drift of the example operational amplifier 110 may be of lower magnitude than previous solutions.

The term “couple” is used throughout the specification. This term may cover connections, communications, or signal paths that enable functional relationships consistent with this description. For example, if device A provides a signal to control device B to perform an action, in a first example device A is coupled to device B, or in a second example intervening component C establishes a functional relationship between device A and device B. Without substantially changing, device A is coupled to device B through intervening component C, and device B is controlled by device A through control signals provided by device A.

A device that is “configured” to perform a task or function may be configured (e.g., programmed and/or hardwired) at the time of manufacture by the manufacturer to perform the function and/or may be configured to perform the function and/or other additional or alternative functions. It may be configurable (or reconfigurable) by the user after manufacturing to perform various functions. Configuration may be accomplished through firmware and/or software programming of the device, configuration and/or layout of the device's hardware components and interconnections, or a combination thereof.

As used herein, the terms “terminal,” “node,” “interconnection,” “pin,” and “lead” are used interchangeably. It is used. Unless specifically stated to the contrary, these terms are generally used to mean an interconnection or termination point between device elements, circuit elements, integrated circuits, devices or other electronic or semiconductor components.

A circuit or device described herein as including certain components may instead be adapted to be combined with such components to form the described circuit or device. For example, one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and/or inductors), and/or one or more sources (e.g., voltage and/or current sources). A structure described as a device may instead include only semiconductor elements within a single physical device (e.g., a semiconductor die and/or integrated circuit (IC) package) and may not be accessible to, for example, end users and/or third parties. It can be adapted to be coupled to at least some of the passive elements and/or sources to form the described structure at the time of manufacture or after manufacture.

Although the use of specific transistors is described herein, other transistors (or equivalent devices) may be used instead. For example, a p-type metal-oxide-silicon FET (“MOSFET”) can be used in place of an n-type MOSFET with little or no changes to the circuit. Additionally, other types of transistors (eg, bipolar junction transistors (BJTs)) may be used.

Circuits described herein are reconfigurable to include replaced components to provide functionality that is at least partially similar to functionality available prior to component replacement. Components shown as resistors, unless otherwise noted, generally represent any one or more elements combined in series and/or parallel to provide the amount of impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors each coupled in parallel between identical nodes. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors coupled in series between the same two nodes, each as a single resistor or capacitor.

The use of the phrase "ground" in the foregoing description refers to chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground ( common ground), and/or any other type of ground connection applicable or suitable to the teachings of this description. Unless otherwise stated, “about,” “approximately,” or “substantially” preceding a value means +/-10 percent of the stated value.

Modifications to the described embodiments are possible, and other embodiments are possible, within the scope of the claims.

Claims (20)

As a device,
Switch circuit - The switch circuit is,
a first switch input coupled to an input voltage;
a first switch output coupled to the positive input terminal of the operational amplifier;
a second switch input coupled to the output of the operational amplifier; and
a second switch output coupled to a negative input terminal of the operational amplifier; The switch circuit is,
Based on a control signal in a first state, connect the first switch input to the first switch output and the second switch input to the second switch output;
configured to connect the first switch input to the second switch output and the second switch input to the first switch output based on the control signal in a second state; The operational amplifier is,
In response to the control signal, generate a first voltage based on a gain and the switch circuit in the first state;
configured to, in response to the control signal, generate a second voltage based on the gain and the switch circuit in the second state; and
A device comprising an analog-to-digital converter (ADC) configured to convert the first and second voltages to digital values based on the multiplication of the input voltage and the gain. According to paragraph 1,
the control signal corresponds to either the first state or the second state at a given time,
wherein the switch circuit is further configured to determine whether to connect inputs to outputs in the first state or the second state based on the control signal. The method of claim 2, wherein the operational amplifier is:
generate the first voltage in response to determining that the control signal corresponds to the first state;
The device further configured to generate the second voltage in response to determining that the control signal corresponds to the second state. 3. The device of claim 2, wherein the control signal alternates between a first correspondence to the first state and a second correspondence to the second state at a frequency determined by the ADC. According to paragraph 4,
The first voltage is the first operational amplifier voltage,
The second voltage is the second operational amplifier voltage,
The ADC additionally,
providing the control signal in response to the first state for an amount of time;
generate a first written voltage of the output of the operational amplifier during the amount of time, wherein the difference between the first written voltage and the first operational amplifier voltage satisfies a threshold;
providing a chop control signal in response to the second state after the amount of time;
wait until the difference between the output of the operational amplifier and the second operational amplifier voltage satisfies the threshold;
After waiting, the device generates a second written voltage of the output of the operational amplifier. The device of claim 1, wherein the switch circuit, the operational amplifier, and the ADC are implemented together on an integrated circuit. According to paragraph 1,
The switch circuit is a first switch circuit;
The operational amplifier further includes a second switch circuit;
the second switch circuit forms first connections in the first state based on the control signal;
and the second switch circuit forms a second connection in the second state based on the control signal. As a device,
Switch circuit - The switch circuit is,
a first switch input coupled to an input voltage;
a first switch output coupled to the positive input terminal of the operational amplifier;
a second switch input coupled to the output of the operational amplifier; and
a second switch output coupled to a negative input terminal of the operational amplifier; The switch circuit is,
Based on a control signal in a first state, connect the first switch input to the first switch output and the second switch input to the second switch output;
configured to connect the first switch input to the second switch output and the second switch input to the first switch output based on the control signal in a second state;
The operational amplifier is,
In response to the control signal, generate a first voltage based on a gain and the switch circuit in the first state;
configured to, in response to the control signal, generate a second voltage based on the gain and the switch circuit in the second state;
An analog-to-digital converter (ADC) having an input coupled to the operational amplifier and an output coupled to a memory, the ADC comprising:
convert the first voltage and the second voltage into digital values based on the multiplication of the input voltage and the gain;
configured to store the digital value in the memory; and
A device comprising a processor circuit having an input coupled to the memory, the processor circuit configured to perform an action based on the digital value. 9. The device of claim 8, wherein the control signal alternates between a first correspondence to the first state and a second correspondence to the second state at a frequency determined by the ADC. According to clause 9,
The conversion of the first voltage and the second voltage into a digital value is a first conversion;
the ADC is further configured to perform multiple conversions of the first voltage and the second voltage into multiple digital values;
The device of claim 1, wherein the rate at which the ADC alternates between the first correspondence and the second correspondence is based on the rate of conversion of the output of the operational amplifier. According to clause 8,
The first voltage is the first operational amplifier voltage,
The second voltage is the second operational amplifier voltage,
The ADC additionally,
providing the control signal in response to the first state for an amount of time;
generate a first written voltage of the output of the operational amplifier during the amount of time, wherein the difference between the first written voltage and the first operational amplifier voltage satisfies a threshold;
provide the control signal in response to the second state after the amount of time;
wait until the difference between the output of the operational amplifier and the second operational amplifier voltage satisfies the threshold;
After waiting, the device generates a second written voltage of the output of the operational amplifier. 9. The device of claim 8, wherein the switch circuit, the operational amplifier, the ADC, the memory, and the processor circuit are implemented together in a microprocessor. The method of claim 8, wherein to convert the first voltage and the second voltage into digital values, the ADC,
sample the output of the operational amplifier during a first period during which the operational amplifier generates the first voltage;
sample the output of the operational amplifier during a second period during which the operational amplifier generates the second voltage;
The device further configured to calculate the digital value based on an average of the samples from the first period and the samples from the second period. As a method,
coupling the first switch input to an input voltage;
coupling the first switch output to a positive input terminal of an operational amplifier;
coupling a second switch input to the output of the operational amplifier;
coupling a second switch output to a negative input terminal of the operational amplifier;
connecting the first switch input to the first switch output and the second switch input to the second switch output with a switch circuit based on a control signal in a first state;
connecting, with the switch circuit, the first switch input to the second switch output and the second switch input to the first switch output in a second state based on the control signal;
generating, with an operational amplifier, in response to a chop control signal, a first voltage based on the gain and the connections in the first state;
generating, with the operational amplifier, in response to the chop control signal, a second voltage based on the gain and the connections in the second state; and
Converting, with an analog-to-digital converter (ADC), the first voltage and the second voltage to digital values based on the multiplication of the input voltage and the gain. 15. The method of claim 14, further comprising generating, with the ADC, the control signal to alternate between a first correspondence to the first state and a second correspondence to the second state. According to clause 15,
The conversion of the first voltage and the second voltage into a digital value is a first conversion;
The method further includes performing, with the ADC, multiple conversions of the first voltage and the second voltage to multiple digital values;
The rate at which the ADC alternates between the first correspondence and the second correspondence is based on the rate of conversion of the output of the operational amplifier. According to clause 14,
The first voltage is the first operational amplifier voltage,
The second voltage is the second operational amplifier voltage,
The above method is,
providing, with the ADC, the chop control signal corresponding to the first state for an amount of time;
generating, with the ADC, a first written voltage of the output of the operational amplifier for the amount of time, wherein a difference between the first written voltage and the first operational amplifier voltage satisfies a threshold;
providing, with the ADC, the chop control signal correspondingly after the amount of time;
waiting until the difference between the output of the operational amplifier and the voltage of the second operational amplifier satisfies the threshold; and
After waiting, the method further comprising generating, with the ADC, a second written voltage of the output of the operational amplifier. 15. The method of claim 14, further comprising implementing the switch circuit, the operational amplifier, and the ADC together on an integrated circuit. The method of claim 14, wherein converting the first voltage and the second voltage into digital values comprises:
sampling, with the ADC, the output of the operational amplifier during a first period during which the operational amplifier generates the first voltage;
sampling the output of the operational amplifier during a second period during which the operational amplifier generates the second voltage; and
The method further comprising calculating the digital value based on an average of the samples from the first period and the samples from the second period. According to clause 14,
The switch circuit is a first switch circuit;
The above method is,
implementing a second switch circuit within the operational amplifier;
connecting second switch circuit inputs to second switch circuit outputs in the first state based on the control signal; and
The method further comprising connecting second switch circuit inputs to second switch circuit outputs in the second state based on the control signal.

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