KR20230137802A - Exposure device and method for making wiring pattern - Google Patents

Abstract

[Problem] In a semiconductor package manufacturing process, etc., patterning of wiring is performed to suppress throughput degradation.
[Solution] In the FO-WLP exposure process, the amount of positional deviation between the semiconductor chips (SC) placed on the temporary substrate (B) with respect to the reference position is measured. In accordance with the formation position correction of the in-area wiring pattern AD, the formation position correction and scaling correction for the out-of-area wiring pattern BD are performed, and an arc-shaped supplementary wiring pattern CD is generated. Then, the corrected intra-area wiring pattern (AD), out-of-region wiring pattern (BD), and the generated arc-shaped supplementary wiring pattern (CD) are synthesized as raster data.

Description

Exposure device and wiring pattern creation method {EXPOSURE DEVICE AND METHOD FOR MAKING WIRING PATTERN}

The present invention relates to the patterning of wires in the manufacturing process of a semiconductor package, and in particular, to the patterning of wires in a technology for packaging semiconductors at the wafer level (Wafer-Level-Package, hereinafter 'WLP'). .

In WLP, electronic components such as semiconductor chips (hereinafter also referred to as "IC" or "die") and passive components are placed on a temporary support substrate, sealed with resin, and then placed on an RDL. (Re Distribution Layer) Perform wiring. After that, a semiconductor package is obtained by dicing (this process is called Mold-first (Chip-first) type WLP).

For example, within the range of the chip size, FI (Fan-In)-WLP, which wires the I/O terminal of the die to the placement location of the BGA (Ball Grid Array) that can be mounted on the motherboard, simulated the surrounding die with resin. FO (Fan-Out)-WLP, which extends to RDL wiring, is known. In FO-WLP, by packaging multiple semiconductor chips (Multi Chip FO-WLP), it is possible to realize a SiP (System in Package) that integrates and modularizes various electronic devices such as semiconductor chips and passive components.

In the mold-first type WLP, random positional deviations occur in individual semiconductor chips, etc., with respect to the positions on the reference design. Therefore, it is necessary to correct wiring pattern data created in CAD/CAM format according to positional deviation.

For example, a wiring pattern for connecting external electrodes to a misaligned semiconductor chip is obtained based on a netlist included in the design information, and wiring pattern data is generated (see Patent Document 1). Additionally, the wiring pattern determined for the area (zone) determined according to the semiconductor chip size, etc. is reconverted (resampled) (see Patent Document 2).

Patent Document 1: Japanese Patent No. 5779145 Patent Document 2: Japanese Patent No. 5767255

The positional deviation of each semiconductor chip needs to be measured by camera photography performed before exposure. Therefore, redesigning the wiring pattern after measurement takes time. In particular, as the demand for SiP by multilayering of substrates and FO-WLP increases, data correction processing of wiring patterns requires a large amount of time, affecting throughput.

Therefore, in semiconductor package manufacturing processes, etc., patterning of wiring that can suppress throughput degradation is required.

The exposure apparatus of the present invention can realize patterning of wiring such as RDL wiring in a semiconductor package manufacturing process such as WLP. For example, it can be applied to SiP exposure processes using FI-WLP, FO-WLP, multi-chip FO-WLP, etc. As for patterning the RDL wiring, it is also possible to pattern the wiring for a single-layer or multi-layer RDL.

The exposure apparatus of the present invention is designed to be connected to a wiring pattern within a region formed in a wiring region of a size larger than the die (semiconductor chip) or the die disposed on a support substrate, and to be connected to the wiring pattern within the region by design, and adjacent to the die. Wiring patterning can be performed based on the wiring pattern outside the area connecting the die or electronic component. The wiring pattern is created in advance as vector data in, for example, CAD/CAM format and input into the exposure apparatus.

The support substrate may be configured as a temporary substrate, and its shape is not limited, such as wafer-shaped (here, spherical panels are also included), as long as the dies can be arranged. For example, it is possible to configure a pseudo wafer in which a die is sealed with a mold as a temporary support substrate. In addition, as a wiring area larger than the die size, it is possible to define it as a spherical area scaled (enlarged) to match the spherical shape of the die, or it is also possible to set it as an area of a shape other than that. , any configuration of the area including the die may be sufficient. Electronic components include external electrodes, passive components, etc., and can be defined as elements that can be electrically connected to a die.

The intra-region wiring pattern includes, for example, RDL wiring for an area expanded by resin or the like in FO-WLP, RDL wiring in FI-WLP, etc. The out-of-area wiring pattern, for example, in the case of FO-WLP, includes a wiring pattern that connects the in-area wiring pattern formed in the extended region in each neighboring die. Additionally, a wiring pattern that connects a wiring pattern within the area formed in the expanded region to an electronic component such as an external electrode is also included. Meanwhile, as a wiring pattern, either a single wiring pattern or a pattern consisting of multiple wiring lines can be configured. For example, in the case of FO-WLP, as a wiring pattern connecting adjacent dies, an intra-region wiring pattern and an out-of-region wiring pattern can be configured as a wiring group in which a plurality of wirings are arranged.

The exposure apparatus of the present invention is equipped with an exposure data generation unit that converts the wiring pattern within the region and the wiring pattern outside the region into raster data and generates exposure data. The exposure data may be configured as data capable of driving the optical modulation element of the exposure apparatus. For example, in the case of an exposure device equipped with an optical modulation element array such as a DMD, it is possible to generate exposure data that controls ON/OFF of an optical modulation element such as a micromirror. The exposure data generation unit can convert the overall pattern data including the wiring pattern within the region and the wiring pattern outside the region with other patterns (other wiring patterns, patterns other than wiring, etc.) into raster data and generate it as exposure data. . Alternatively, the exposure data generation unit may distinguish the in-area wiring pattern and the out-of-area wiring pattern from other patterns and generate exposure data by raster conversion, while including the in-area wiring pattern in other patterns and out-of-area wiring patterns. It is also possible to convert patterns into raster data as separate data.

Additionally, the exposure apparatus of the present invention is equipped with a position deviation measurement unit that measures the position deviation of the die with respect to the reference position. As for the reference position, for example, it is possible to set a representative position (eg, center position) of the die determined by design as the reference position. The measurement unit can, for example, measure the degree of position deviation (position deviation amount). As the amount of positional deviation, it is possible to measure the difference between the coordinates measured when the support substrate is installed on a stage and the designed coordinates, and it is also possible to measure the rotational difference with respect to the center position of the die as the positional deviation.

In the present invention, the exposure data generation unit corrects the formation position of the intra-region wiring pattern according to the positional deviation of the die, and creates a supplementary wiring pattern that connects the in-region wiring pattern and the out-of-region wiring pattern whose ends are separated from each other. Create. For the out-of-area wiring pattern, the formation position, wiring shape, etc. may be corrected according to the positional deviation of the die, or the formation position may not be corrected. It is possible to determine the shape, length, line width, etc. of the supplementary wiring pattern according to the corrected formation position of the wiring pattern within the area.

The exposure data generation unit can be configured as a circuit including, for example, a raster conversion circuit, and may also include a circuit that performs a position deviation correction process, a circuit that performs a data synthesis process, etc. Additionally, the exposure data generation unit is not limited to specifications and aspects such as hardware, software, and firmware. There are various methods for generating and processing intra-area wiring patterns, out-of-area wiring patterns, and supplementary wiring patterns. For example, the exposure data generation unit separately converts the wiring pattern within the area and the wiring pattern outside the area with the formation position corrected from CAD/CAM format data (vector data) into raster data, while converting the supplementary wiring pattern into raster data. It is possible to create it as data. Alternatively, the supplementary wiring pattern may be generated as vector data and converted to raster data.

Correction of the formation position of the intra-region wiring pattern, conversion of the corrected intra-region wiring pattern and out-of-region wiring pattern into raster data, and generation of a supplementary wiring pattern may be performed according to the measurement of the positional deviation of the die. Additionally, the raster data conversion process for the wiring pattern within the area can be done in advance by creating standard exposure raster data before starting exposure and performing raster conversion with correction processing. For example, the exposure data generation unit is capable of determining a block containing a wiring pattern within a region and creating raster data for exposure in a regular form based on the positional coordinate data of the input block.

Raster conversion processing can be similarly performed on out-of-area wiring patterns. For example, the exposure data generation unit may perform pattern formation position correction and scaling correction for the out-of-area wiring pattern according to the in-area wiring pattern whose formation position has been corrected. The scaling correction here includes scaling (reduction or enlargement) along the longitudinal direction of the wiring. Then, the exposure device performs an exposure operation based on exposure data that synthesizes the in-region wiring pattern, the out-of-region wiring pattern, and the supplementary wiring pattern according to the generation of the supplementary wiring pattern.

The wiring width and shape of the supplementary wiring pattern vary. For example, the exposure data generation unit can form an arc-shaped pattern as a supplementary wiring pattern. The arc-shaped pattern here includes not only arcs with a strictly constant radius of curvature, but also patterns that are generally arc-shaped. For example, when the wiring pattern within the area and the wiring pattern outside the area are composed of a wiring group in which a plurality of wirings are lined up, and when considering that the wiring width, wiring spacing, and overall wiring width are maintained without change as a whole, exposure The data generation unit may generate an arc-shaped pattern.

The exposure data generation unit can generate an arc-shaped supplementary wiring pattern by extracting a part of the circular pattern. For example, it is possible to store the data of the original pattern in memory at a timing such as when a lot is changed, and the exposure data generation unit can generate an arc-shaped supplementary wiring pattern from the original pattern through masking processing. do. For example, as a wiring pattern connecting adjacent dies, when the intra-region wiring pattern and the out-of-region wiring pattern are composed of a wiring group in which a plurality of wirings are lined up, the wiring width and the inter-wiring spacing are set to the intra-region wiring pattern. It is possible to create a concentric circular wiring pattern in advance, such as an out-of-area wiring pattern, and store it in memory before starting exposure.

A method for creating a wiring pattern, which is another aspect of the present invention, includes a wiring pattern within a region formed in a wiring region of a size larger than the die or the die disposed on a support substrate, and a wiring pattern within the region being connected by design, Out-of-area wiring patterns connecting the die and neighboring dies or electronic components are converted into raster data, exposure data is generated, the positional deviation of the die relative to the reference position is measured, and the in-area wiring pattern is determined according to the die positional deviation. By correcting the formation position, a supplementary wiring pattern is created that connects the in-region wiring pattern and the out-of-region wiring pattern whose ends are separated from each other. The positional deviation of the die with respect to the reference position can be measured with an exposure device. Additionally, the supplementary wiring pattern can be created as vector data or raster data. For example, in the exposure process in FO (Fan-Out)-WLP (Wafer-Level Package), an exposure operation is performed by an exposure device based on a wiring pattern created by the wiring pattern creation method of the present invention. It is possible. Regarding conversion to raster data and generation of exposure data, it is possible to apply various data processing techniques as described above.

According to the present invention, in a semiconductor package manufacturing process or the like, it is possible to perform patterning of wiring that can suppress a decrease in throughput.

[Figure 1] A block diagram of the exposure apparatus according to this embodiment.
[FIG. 2] A diagram showing a part of a semiconductor chip mounted on a support substrate (temporary substrate) in a mold-first type FO-WLP.
[Figure 3] A diagram showing the formation of a wiring pattern based on the positional deviation of the semiconductor chip.
[FIG. 4] A diagram showing the flow of data processing of a wiring pattern involving alignment adjustment in the exposure process at the wafer level.
[FIG. 5] A diagram showing an in-area wiring pattern, an out-of-area wiring pattern, a supplementary wiring pattern, and a template pattern.
[FIG. 6] A diagram showing the pattern formation position of the wiring pattern within a region on the substrate.
[FIG. 7] A diagram showing part of a method for generating a supplementary wiring pattern (CD).
[FIG. 8] A diagram showing part of a method for generating a supplementary wiring pattern (CD).
[FIG. 9] A diagram showing correction of the pattern formation position and scaling correction for the out-of-area wiring pattern BD.
[FIG. 10] A diagram showing a wiring pattern that combines an in-area wiring pattern, an out-of-area wiring pattern, and a supplemental wiring pattern.

Below, embodiments of the present invention will be described with reference to the drawings.

1 is a block diagram of an exposure apparatus according to this embodiment.

The exposure apparatus 10 can form a circuit pattern by irradiating light to the substrate B, and is configured here as a maskless exposure apparatus equipped with a plurality of exposure heads 15 (in FIG. 1 , only one exposure head is shown). The substrate B is mounted on the drawing table 12 and can be moved in the main scanning direction (X direction) and the sub-scanning direction (Y direction) by the table driving mechanism 13. do. On the drawing table 12, an X-Y coordinate system is defined.

The exposure head 15 is equipped with a digital micro-mirror device (DMD) 16, an illumination optical system, and an imaging optical system (not shown). Light emitted from a light source 20 (laser, discharge lamp, etc.) provided in the exposure apparatus 10 is guided to the DMD 16 through an illumination optical system.

The DMD (16) is an optical modulation element array in which tiny spherical micromirrors (here, several micrometers to tens of micrometers) are arranged two-dimensionally in a matrix shape, and each micromirror is , depending on the exposure data, either a first posture (ON state) that reflects the beam from the light source 20 in the direction of the substrate B, or a second posture (OFF state) that reflects the beam in a direction outside the exposure surface. The position is selectively determined.

The spherical projection area (hereinafter referred to as 'exposure area') defined when all micromirrors are in the ON state is accompanied by movement along the main scanning direction (X direction) of the drawing table 12, The substrate (B) is moved relative to each other. However, here, the exposure head 15 is installed so that the exposure area is inclined by a predetermined micro angle with respect to the main scanning direction (X direction).

The light reflected by the micromirror in the ON state is patterned light according to the relative position of the exposure area on the substrate B, and is imaged on the exposure surface of the substrate B. By carrying out an exposure operation in which pattern light is projected while the drawing table 12 moves at a constant speed, drawing on the entire substrate B is performed. Here, multiple exposure (overlap exposure) is performed at a predetermined pitch.

The controller 30, which is connected to an external workstation or server (not shown), controls the operation of the exposure apparatus 10 and outputs control signals to each circuit, such as the light source driver 21. The program that controls the operation of the exposure apparatus 10 is stored in advance in ROM (not shown) in the controller 30. Drawing data (pattern data) input to the exposure apparatus 10 from a workstation or the like is vector data (coordinate data) configured in CAD/CAM format, and is input to the vector data processing circuit 31.

In the exposure apparatus 10, raster data (hereinafter referred to as 'standardized raster data for exposure') is created for some standard patterns in response to the drawing data input to the vector data processing circuit 31, and stored in memory before starting exposure. It is stored in (39). Other drawing data (vector data) is converted to raster data by the raster conversion circuit 26 and then sent to the synthesis circuit 40.

The correction circuit 33 is a raster data conversion processing circuit targeting standardized pattern data that needs to be converted to raster data after alignment adjustment, and is a raster data conversion circuit based on the standardized raster data for exposure stored in the memory 39. Data is output to the synthesis circuit 40. As will be described later, the mask processing circuit 34 performs mask processing on the template data stored in the memory 41, and then converts the raster data (hereinafter referred to as 'supplementary raster data') into the synthesis circuit 40. Output as

The synthesis circuit 40 combines the raster data output from the correction circuit 33 with the raster data output from the raster conversion circuit 26, and synthesizes supplementary raster data output from the mask processing circuit 34. . Standard raster data and supplementary raster data are synthesized according to the position of the exposure area during the exposure operation. The DMD drive circuit 35 controls the drive of the DMD 16 based on exposure data obtained by synthesis, and multiple exposure operations are performed accordingly.

The camera 38 is installed to capture images of the substrate B installed on the drawing table 12, and is used when adjusting alignment. Exposure control, such as image magnification, AF processing, and aperture adjustment, in the camera 38 is performed by the camera control unit 36. The measurement circuit 37 detects the positions of feature points such as alignment marks based on image data captured by the camera 38. The controller 30 performs alignment adjustment for the drawing data based on the amount of positional deviation that is the difference between the position of the detected feature point and the design reference position.

FIG. 2 is a diagram showing a portion of a semiconductor chip mounted on a support substrate (temporary substrate) B in the mold-first type FO-WLP. In FIG. 2, the arrangement of the semiconductor chips SC (here, four) on the design is shown in comparison with the semiconductor chips SC placed on the support substrate B in a resin-embedded state.

In FO-WLP, a wiring area (D) larger than the chip size of the semiconductor chip (SC) is defined, and a chip area (hereinafter referred to as 'expansion') is pseudo-expanded by resin around the semiconductor chip (SC). For (MD) (referred to as 'region'), it is possible to form a wiring pattern that connects to the chip terminal. Accordingly, it becomes possible to realize a pitch similar to the I/O terminal pitch of the BGA even for a miniaturized semiconductor chip (SC). In addition, high-density wiring patterns that are not limited by wiring design rules can be formed between semiconductor chips (SC), and a more compact SiP can be realized by mounting multichips.

The semiconductor chip (SC) has an individual random positional deviation amount with respect to the design reference position due to the malleability of the resin. Therefore, if the design wiring pattern data for the resin portion M is not corrected, a non-connected state or a short-circuit state occurs between adjacent semiconductor chips SC. Therefore, alignment adjustment is performed before exposure operation to correct drawing data.

Figure 3 is a diagram showing the formation of a wiring pattern based on the positional deviation of the semiconductor chip. In this embodiment, in the RDL wiring at the wafer level in the FO-WLP process, the wiring pattern connecting adjacent semiconductor chips is a wiring pattern (fan) formed within the semiconductor chip SC and the expansion area MD. It is also called an out wiring pattern. A wiring pattern formed outside the wiring area (D) (hereinafter referred to as 'in-area wiring pattern') (AD) and a wiring pattern (hereinafter referred to as 'out-of-area wiring pattern') (BD). Divide into two groups.

Regarding the interconnection pattern AD within the extended area MD, the pattern formation position is corrected according to the positional deviation of the semiconductor chip SC (see symbol P'). Then, for the out-of-area wiring pattern BD, the formation position etc. are corrected based on the corrected formation position of the in-area wiring pattern AD (see symbol P").

In addition, a wiring pattern (hereinafter referred to as 'supplemental wiring pattern') connecting the ends of the in-area wiring pattern (AD) and the out-of-area wiring pattern (BD) whose ends are spaced apart from each other due to formation position correction (CD) ) is created and reinforced. The synthesis of such wiring patterns is also performed for connections between semiconductor chips and electronic components such as external electrodes and passive components. Hereinafter, this will be described in detail using FIGS. 4 to 10.

FIG. 4 is a diagram showing the flow of data processing of a wiring pattern involving alignment adjustment in an exposure process at the wafer level. FIG. 5 is a diagram showing an intra-area wiring pattern (AD), an out-of-region wiring pattern (BD), a supplementary wiring pattern (CD), and a template pattern (C0). Below, for ease of explanation, data processing of wiring patterns that connect specific semiconductor chips will be mainly described.

When drawing data of CAD/CAM format data is input to the exposure apparatus 10 from a workstation or the like, the data of the in-area wiring pattern (AD) and the data of the out-of-area wiring pattern (BD) are specified and extracted ( S101). The area wiring pattern (AD) is design data and consists of a group of wires extending from a terminal and lined up in parallel at equal intervals, and the line width (W) of each wire and the distance interval (pitch) (M) between neighboring wires are the same. do. Here, it is configured as five wiring patterns.

The out-of-area wiring pattern (BD) is design data that has the same line width (W), interconnection distance spacing (M), overall wiring width (L), and the same number of lines (5) as the in-area wiring pattern (AD). It is composed of several wiring groups. In the design, the in-area wiring pattern (AD) and out-of-area wiring pattern (BD) are configured as a group of wirings that extend in a straight line beyond the wiring area (D) defined in FO-WLP (see FIG. 3).

Here, blocks BL1 and BL2 are defined that surround the in-area wiring pattern AD and the out-of-area wiring pattern BD, respectively. The drawing data of the entire substrate input to the exposure apparatus 10 in the exposure process includes pattern data of the block BL1 surrounding the intra-region wiring pattern AD. On the other hand, the pattern data of the block BL2 surrounding the out-of-area wiring pattern BD is input separately from the drawing data. Additionally, coordinate data of blocks BL1 and BL2 (here, position coordinate data of block end points) is input separately.

Meanwhile, in the memory 41 of the exposure apparatus 10, the template pattern C0, which serves as a prototype for forming the above-described supplementary wiring pattern (see FIG. 3), is stored and registered as raster data. The template pattern C0 is composed of five concentric wiring patterns in accordance with the number of wirings (5) of the in-area wiring pattern AD and the out-of-region wiring pattern BD.

The overall wiring width (l), each wiring width (w), and wiring distance interval (m) of the template pattern (C0) are determined for the wiring pattern within the area (AD) and the wiring pattern outside the region (BD). It is the same as the width (L), each wiring width (W), and the wiring distance interval (M). The data of the template pattern C0 is input to and stored in the exposure apparatus 10 for each lot, for example.

FIG. 5 shows a mask pattern (MD) for generating a supplementary wiring pattern (CD) by extracting a part of the template pattern (C0). The mask pattern (MD) has a size that covers the entire template pattern (C0) when the center (D) is aligned with the center (C) of the template pattern (C0), and is surrounded by a predetermined angle α from the center (D). It is configured as raster data that masks areas (MA) other than the area, that is, invalidates the data.

In the exposure apparatus 10, alignment measurement by camera scanning is performed in parallel with the data processing for the input drawing data described above. Accordingly, the amount of positional deviation of each semiconductor chip on the substrate B with respect to the reference position (on the design) is measured (S102).

As a method of calculating the amount of positional deviation, for example, it is possible to extract terminals (connection pads) of a semiconductor chip as feature points through image processing and perform template matching. Alternatively, it is okay to measure the alignment mark installed on the semiconductor chip. The positional deviation amount of the semiconductor chip is obtained as the deviation amount with respect to the reference position in the main scanning direction (X direction) and the sub-scanning direction (Y direction), and the rotational deviation amount (angle θ) with respect to the chip center position.

FIG. 6 is a diagram showing the pattern formation position of the wiring pattern AD within a region on the substrate B. As shown in FIG. 6, the pattern formation position of the wiring pattern AD within the area is corrected based on the detected positional deviation amount of each semiconductor chip SC. Since the semiconductor chip (SC) itself is not deformed, when the boundary line (D'L) of the wiring region (D) is defined on the substrate (B), the wiring pattern ( Processing to correct the positions and rotation angles of X and Y is performed so that the wiring group (AD) remains vertical (S103).

Here, the pattern data of the block BL1 surrounding the wiring pattern AD in the area is treated as a regular pattern used for repeated exposure, and is corrected based on the amount of positional deviation of each semiconductor chip SC described above. The standardized raster data for exposure is output to the synthesis circuit 40.

However, between the out-of-area wiring pattern BD included in the block BL2 and the in-area wiring pattern AD included in the block BL1, the line width W, the overall wiring width L, The wiring distance spacing (M) is the same. In addition, the overall wiring width (l), each wiring width (w), and the wiring distance interval (m) of the template pattern (C0) are also shown as the overall wiring width (L), each wiring width (W), and the wiring distance interval ( Same as M).

Therefore, by extracting part of the template pattern C0 shown in FIG. 5, an arc-shaped supplementary wiring pattern CD (see FIG. 3) is generated, and the wiring pattern BD outside the area of the block BL2 is created. The formation position is corrected, and scaling is corrected along the longitudinal direction. Accordingly, a wiring pattern is formed to connect semiconductor chips each having a positional deviation.

First, a method for generating a supplementary wiring pattern (CD) will be explained using FIGS. 7 to 8. When the end points of the connection block B1 of one semiconductor chip (SC) are set to A1 and B1, and the end points of the connection block B1 of the neighboring semiconductor chip are set to A2 and B2, the distance interval between the block end points is the shortest. Find 2 points. In Figure 7, the shortcomings A1 and A2 are specified as the shortcomings that create the shortest distance interval K. These shortcomings A1 and A2 are used as placement reference points.

In addition, a circle (circular arc) (CA) centered on the midpoint (A0) of the placement reference points (A1, A2) and a circle (circular arc) passing through the block endpoints B1 and B2, respectively, centered on the placement reference points (A1, A2). )(CB1, CB2) are defined, and the intersection points (C1, C2) are obtained. A rectangular region G defined by connecting the block end point A1, the intersection point C1, the block end point A2, and the intersection point C2 is given as an area for forming the out-of-area wiring pattern BD. The rectangular region G is an area that touches each wiring region of a neighboring semiconductor chip at one point.

FIG. 8 shows a diagram in which the template pattern C0 and mask data MD are overlapped with the arrangement reference points A1 and A2. When the center (D) of the mask data (MD) is overlapped with the block edge (A1), the straight line (G1) connecting the block edge (A1) and the block edge (B1) and the intersection point (C1) with the block edge (A1) are drawn. The area MA other than the area MG of the included angle α, surrounded by the connecting straight line G2, is defined as the masking area MA.

Then, by performing masking processing, a supplementary wiring pattern CD that enters the area MG of the included angle α is generated (S104). Specifically, the data in the area MA of the template pattern C0, which is raster data, is invalidated, and the raster data of the supplementary wiring pattern CD is output to the synthesis circuit 40.

The supplementary wiring pattern CD is formed at a position continuously connected to the corrected formation position of the intra-region wiring pattern AD. The radial distance interval (t) to the innermost wiring of the template pattern (C0) (see FIG. 5) is such that the connection from the intra-area wiring pattern (AD) to the supplementary wiring pattern (CD) is a straight line to a circle. It is decided that there will be a positive connection.

As for the other semiconductor chip SC side, the supplementary wiring pattern CD is extracted by performing similar masking processing using the block end point A2 as an arrangement reference point. The shape of the supplementary wiring pattern CD depends on the range of the unmasked area MG, that is, the position of the arrangement reference positions A1 and A2.

FIG. 9 is a diagram showing correction of the pattern formation position and scaling correction for the out-of-area wiring pattern BD. The formation position of the pattern data of the block BL2 (see FIG. 5) according to the rectangular area G defined by connecting the block edge A1, the intersection point C1, the block edge A2, and the intersection point C2. is corrected, and scaling correction is performed (S105).

Specifically, the pattern formation position is rotated so that the two end points b1 and b3 of the block BL2 shown in FIG. 5 coincide with the end points A1 and A2 of the blocks BL1 and BL1'. , perform scaling correction to change the block length (E) to E'. This correction process is performed with vector data. Correction for the above-described in-area wiring pattern (AD), out-of-area wiring pattern (BD), and generation of the supplementary wiring pattern (CD) are performed for each wiring pattern that connects semiconductor chips.

The in-area wiring pattern (AD) and out-of-area wiring pattern (BD) are converted into raster data through respective correction processes, and are synthesized into the drawing data of the entire substrate converted into raster data. Then, the raster data of the supplementary wiring pattern generated by the masking process is synthesized into the drawing data (S106). An exposure operation is performed using exposure data obtained by data synthesis (S107).

FIG. 10 is a diagram showing a wiring pattern that is a combination of an intra-area wiring pattern (AD), an out-of-region wiring pattern (BD), and a supplemental wiring pattern (CD). As shown in FIG. 10, a wiring pattern DD is formed across neighboring semiconductor chips SC in which the line width W, the overall wiring width L, and the wiring distance interval M do not change.

In this way, according to this embodiment, in the FO-WLP exposure process, the amount of positional deviation between the semiconductor chips SC placed on the temporary substrate B with respect to the reference position is measured. Based on the input drawing data, the wiring pattern (AD) in the area of the fan-out wiring formed in the extended area (MD) around the chip among the wiring area (D) larger than the chip size and the wiring area (D) It is classified as a wiring pattern (BD) outside the area formed on the resin between the regions.

In accordance with the formation position correction of the in-area wiring pattern AD, the formation position correction and scaling correction for the out-of-area wiring pattern BD are performed, and an arc-shaped supplementary wiring pattern CD is generated. Then, the corrected intra-area wiring pattern (AD), out-of-region wiring pattern (BD), and the generated arc-shaped supplementary wiring pattern (CD) are synthesized as raster data.

In this embodiment, correction of the RDL wiring pattern is performed according to a series of exposure processes, such as conversion processing from the input of drawing data as vector data to raster data, and exposure operation. Since the wiring pattern is not redesigned in vector data, the effect on throughput can be suppressed.

In particular, by creating an arc-shaped supplementary wiring pattern (CD), it is possible to continuously connect the in-area wiring pattern (AD) and the out-of-area wiring pattern (BD), which had become separate due to correction of the pattern formation position. In particular, since the line width (W), overall wiring width (L), and wiring distance interval (M) are connected between the two chips without changing, changes in electrical characteristics such as changes in impedance can be suppressed.

Since the supplementary wiring pattern (CD) is created based on the concentric template pattern (C0), an appropriate supplementary wiring pattern (CD) can be created for the semiconductor chips (SC) with different positional deviation amounts. Additionally, in the FO-WLP exposure process, the wiring pattern that connects semiconductor chips usually becomes a wiring group with a plurality of wiring patterns lined up, but both ends of the wiring can be smoothly connected and reinforced only by masking. Additionally, since the masking process itself has a fast processing speed, it does not significantly reduce throughput.

It may be possible to create a supplementary wiring pattern other than an arc shape. Supplementary wiring patterns of various shapes can be prepared and stored in advance, and a supplementary wiring pattern of an appropriate shape can be applied to connect the ends of the wiring that have become separated. It is okay to do so. Additionally, for the out-of-area wiring pattern BD, it is acceptable to perform only scaling correction without rotating the formation position. It can be applied not only to the exposure process of FO-WLP but also to the exposure process of FI-WLP. In addition, the above-described exposure process may be applied to an exposure device by laser scanning.

10: Exposure device
26: Raster conversion circuit
33: correction circuit
37: Measurement circuit
38: Camera
40: synthesis circuit
AD: Wiring pattern within area
BD: Out-of-zone wiring pattern
CD: Supplementary wiring pattern

Claims (9)

A wiring pattern within a region formed in a wiring region of a size larger than that of the die placed on a support substrate or the die, and a region connected by design to the wiring pattern within the region and connected to a die or electronic component adjacent to the die. An exposure data generation unit that converts an external wiring pattern into raster data and generates exposure data,
Position deviation measurement unit that measures the position deviation of the die with respect to the reference position
Equipped with
The exposure data generation unit generates a supplementary wiring pattern connecting an in-region wiring pattern and an out-of-region wiring pattern whose ends are spaced apart by correcting the formation position of the in-region wiring pattern according to the positional deviation of the die, and ,
An exposure apparatus characterized in that an exposure operation is performed based on exposure data combining an in-region wiring pattern, an out-of-region wiring pattern, and a supplementary wiring pattern. According to paragraph 1,
The exposure data generation unit,
An exposure device characterized by generating an arc-shaped pattern as a supplementary wiring pattern. According to paragraph 2,
The exposure data generation unit,
An exposure apparatus characterized by generating an arc-shaped supplementary wiring pattern by extracting part of a circular pattern. According to paragraph 3,
The exposure data generation unit,
An exposure apparatus characterized by generating an arc-shaped supplementary wiring pattern through masking processing. According to paragraph 4,
The exposure data generation unit,
An exposure apparatus characterized by performing correction and scaling correction of a pattern formation position for an out-of-area wiring pattern according to an in-area wiring pattern whose formation position has been corrected. According to any one of claims 1 to 5,
An exposure apparatus characterized in that the in-region wiring pattern and the out-of-region wiring pattern are configured as a wiring group in which a plurality of wirings are lined up. According to paragraph 1,
An exposure device characterized by being used in the exposure process in a Fan-Out (FO)-WLP (Wafer-Level Package). A wiring pattern within a region formed in a wiring region of a size larger than that of the die placed on a support substrate or the die, and a region connected by design to the wiring pattern within the region and connected to a die or electronic component adjacent to the die. Convert external wiring patterns into raster data and generate exposure data,
Measure the positional deviation of the die with respect to the reference position,
By correcting the formation position of the intra-region wiring pattern according to the positional deviation of the die, creating a supplementary wiring pattern that connects the in-region wiring pattern and the out-of-region wiring pattern whose ends are separated from each other.
A method of creating a wiring pattern characterized by: An exposure apparatus characterized in that, in an exposure process in a Fan-Out (FO)-WLP (Wafer-Level Package), an exposure operation is performed using a wiring pattern created based on the wiring pattern creation method described in claim 8. .

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