KR20230130938A - Apparatus and method for estimating timing error of frequency hopping - Google Patents

Abstract

시간 동안 수신 신호 샘플이 있을 때, 0~

까지 신호를 필터링하고, 0~

까지 신호를 필터링하며,

~

까지 신호를 필터링하는 n개의 필터로 구성되는 필터부와, 각 필터를 통해 M만큼 필터링된 각 신호를 샘플별로 제곱하고 하나의 값으로 더한 뒤 제곱하여 신호 전력을 검파하는 n개의 Mth 파워 검파기로 구성되는 파워 검파부와, 제 2 Mth 파워 검파기의 출력과 제 3 Mth 파워 검파기의 출력을 더한 값을 들어오는 값을 나누어 주는 n개의 정규화기로 구성되는 정규화부와, K홉만큼 상기 각 정규화기의 값을 더해 주는 n개의 K홉 덧셈기로 구성되는 덧셈부와, 상기 각 K홉 덧셈기의 출력값을 이용하여 홉 타이밍 오차(동기 오차)를 계산하는 미세 동기 오차 계산부를 포함할 수 있다.The frequency hopping timing error estimation device according to the present invention includes a reverse hopping unit that converts the frequency hopping phase-modulated received signal to baseband by inversely jumping the frequency according to the timing, and I/Q the converted baseband received signal. A demodulator that converts the signal into a complex signal (I+Qj), and the converted complex signal

When there are received signal samples during the time, 0~

Filter the signal from 0 to

Filters the signal to

~

It consists of a filter unit consisting of n filters that filter signals up to n, and n Mth power detectors that detect the signal power by squaring each signal filtered by M through each filter for each sample, adding them to one value, and then squaring them. a power detector, a normalizer consisting of n normalizers that divide the incoming value by adding the output of the 2nd Mth power detector and the output of the 3rd Mth power detector, and the value of each normalizer by K hops It may include an addition unit composed of n K-hop adders that add, and a fine synchronization error calculation unit that calculates a hop timing error (synchronization error) using the output value of each K-hop adder.

Description

Frequency hopping timing error estimation device and method {APPARATUS AND METHOD FOR ESTIMATING TIMING ERROR OF FREQUENCY HOPPING}

The present invention relates to a technique for estimating the timing error of frequency hopping. More specifically, the present invention relates to a technique for estimating the timing error of frequency hopping, and more specifically, by applying an Mth power algorithm suitable for a phase modulation (M-PSK) communication system to gather the symbols of the signal in one place and hop to the frequency. It relates to a frequency hopping timing error estimation device and method that can easily estimate the timing error of .

The basic configuration of the phase modulation (M-PSK) communication system, as shown in Figure 1 as an example, generates a complex signal using an I/Q modulator with a local oscillator with a phase difference of 90 degrees, and is a frequency hopping communication system. performs communication by periodically changing a random frequency.

Due to this frequency hopping, the timing of frequency changes must be synchronized during reception. Here, timing synchronization is divided into coarse timing synchronization and fine timing synchronization.

The present invention relates to a timing error estimator required for fine timing synchronization that can be synchronized to a communication level at the 0.5 hop level.

The conventional timing error estimator receives the received signal, passes it through a reverse hop, and then through an envelope detector. An I/Q demodulator is located within the envelope detector, and the received signal is accumulated over the hop time and then squared to calculate the power per hop section. It's a method.

However, at this time, a problem occurs in the case of a phase modulation communication system. In other words, in the case of a phase modulated signal, unlike other modulation methods, only the phase is modulated, so the signal passing through the I/Q demodulator has a phase difference of 180 degrees for each symbol during BPSK (no noise condition).

At this time, when all signals within the hop timing are added, the sum of the signals is close to 0. Therefore, since the output of each envelope detector (e.g., envelope detector 3) is close to 0, a problem arises in which the fine synchronization error calculation role of calculating fine synchronization according to the power of each envelope detector cannot be performed.

Korean Patent No. 10-2189047 (Announcement Date: 2020. 12. 09.) Korean Patent No. 10-1914282 (Announcement Date: 2018. 11. 01.)

The present invention provides a frequency hopping timing error estimation device and method that can easily estimate the frequency hopping timing error by gathering the symbols of the signal in one place by applying an Mth power algorithm suitable for a phase modulation communication system. I want to do it.

The problems to be solved by the present invention are not limited to those mentioned above, and other problems to be solved that are not mentioned can be clearly understood by those skilled in the art from the description below. will be.

시간 동안 수신 신호 샘플이 있을 때, 0~

까지 신호를 필터링하고, 0~

까지 신호를 필터링하며,

~

까지 신호를 필터링하는 n개의 필터로 구성되는 필터부와, 각 필터를 통해 M만큼 필터링된 각 신호를 샘플별로 제곱하고 하나의 값으로 더한 뒤 제곱하여 신호 전력을 검파하는 n개의 Mth 파워 검파기로 구성되는 파워 검파부와, 제 2 Mth 파워 검파기의 출력과 제 3 Mth 파워 검파기의 출력을 더한 값을 들어오는 값을 나누어 주는 n개의 정규화기로 구성되는 정규화부와, K홉만큼 상기 각 정규화기의 값을 더해 주는 n개의 K홉 덧셈기로 구성되는 덧셈부와, 상기 각 K홉 덧셈기의 출력값을 이용하여 홉 타이밍 오차(동기 오차)를 계산하는 미세 동기 오차 계산부를 포함하는 주파수 도약 타이밍 오차 추정 장치를 제공할 수 있다.According to one aspect, the present invention includes a reverse hopping unit that converts a frequency-hopping phase-modulated received signal into a baseband by inversely jumping the frequency according to the timing, and converts the converted baseband received signal into an I/Q signal. A demodulator that converts the complex signal (I+Qj) into a complex signal (I+Qj), and the converted complex signal

When there are received signal samples during the time, 0~

Filter the signal from 0 to

Filters the signal to

~

It consists of a filter unit consisting of n filters that filter signals up to n, and n Mth power detectors that detect the signal power by squaring each signal filtered by M through each filter for each sample, adding them to one value, and then squaring them. a power detector, a normalizer consisting of n normalizers that divide the incoming value by adding the output of the 2nd Mth power detector and the output of the 3rd Mth power detector, and the value of each normalizer by K hops To provide a frequency hopping timing error estimation device including an adder consisting of n K-hop adders that add, and a fine synchronization error calculation unit that calculates the hop timing error (synchronization error) using the output value of each K-hop adder. You can.

Each of the K-hop adders of the present invention can initialize the value after K hops.

Frequency hopping timing error estimation device.

The fine synchronization error calculation unit of the present invention can calculate V1 and V2 using the following formula.

는 제 1 K홉 덧셈기의 출력을, 상기

는 제 2 K홉 덧셈기의 출력을, 상기

는 제 3 K홉 덧셈기의 출력을 각각 나타냄)(remind

is the output of the first Khop adder,

is the output of the second Khop adder,

represents the output of the 3rd K-hop adder, respectively)

)를 다음의 수식과 같이 계산할 수 있다.Using the calculated V1 and V2, the hop timing error (

) can be calculated using the following formula.

,

일 경우,

=0.5홉

,

In case,

=0.5 hops

일 경우,

홉

In case,

hop

일 경우,

홉

In case,

hop

,

일 경우,

=-0.5홉

,

In case,

=-0.5 hops

시간 동안 수신 신호 샘플이 있을 때, 0~

까지 신호를 필터링하고, 0~

까지 신호를 필터링하며,

~

까지 신호를 필터링하는 단계와, M만큼 필터링된 각 신호를 샘플별로 제곱하고 하나의 값으로 더한 뒤 제곱하여 신호 전력을 검파하는 단계와, 제 2 Mth 파워 검파기의 출력과 제 3 Mth 파워 검파기의 출력을 더한 값을 들어오는 값을 나누어 정규화시키는 단계와, K홉만큼 정규화된 각 값을 덧셈해 주는 단계와, 각 K홉 덧셈의 출력값을 이용하여 홉 타이밍 오차(동기 오차)를 계산하는 단계를 포함하는 주파수 도약 타이밍 오차 추정 방법을 제공할 수 있다.According to another aspect, the present invention includes the steps of converting a frequency-hopping phase-modulated received signal into a baseband by inversely jumping the frequency according to the timing, and converting the converted baseband received signal into an I/Q signal. A step of converting into a complex signal (I+Qj), and the converted complex signal is

When there are received signal samples during the time, 0~

Filter the signal from 0 to

Filters the signal to

~

A step of filtering the signal up to, squaring each signal filtered by M for each sample, adding them as one value, and then squaring them to detect the signal power, the output of the second Mth power detector and the output of the third Mth power detector A step of normalizing the added value by dividing the incoming value, adding each normalized value by K hops, and calculating the hop timing error (synchronization error) using the output value of each K hop addition. A method for estimating frequency hopping timing error can be provided.

시간 동안 수신 신호 샘플이 있을 때, 0~

까지 신호를 필터링하고, 0~

까지 신호를 필터링하며,

~

까지 신호를 필터링하는 단계와, M만큼 필터링된 각 신호를 샘플별로 제곱하고 하나의 값으로 더한 뒤 제곱하여 신호 전력을 검파하는 단계와, 제 2 Mth 파워 검파기의 출력과 제 3 Mth 파워 검파기의 출력을 더한 값을 들어오는 값을 나누어 정규화시키는 단계와, K홉만큼 정규화된 각 값을 덧셈해 주는 단계와, 각 K홉 덧셈의 출력값을 이용하여 홉 타이밍 오차(동기 오차)를 계산하는 단계를 포함하는 동작을 상기 프로세서가 수행하도록 하기 위한 명령어를 포함하는 컴퓨터 판독 가능한 기록매체를 제공할 수 있다.According to another aspect, the present invention is a computer-readable recording medium storing a computer program, wherein, when executed by a processor, the computer program jumps the frequency of a phase-modulated received signal that jumps in reverse in accordance with the timing. converting the received baseband signal into an I/Q signal and converting it into a complex signal (I+Qj), and converting the received signal of the baseband into a complex signal (I+Qj).

When there are received signal samples during the time, 0~

Filter the signal from 0 to

Filters the signal to

~

A step of filtering the signal up to, squaring each signal filtered by M for each sample, adding them as one value, and then squaring them to detect the signal power, the output of the second Mth power detector and the output of the third Mth power detector A step of normalizing the added value by dividing the incoming value, adding each normalized value by K hops, and calculating the hop timing error (synchronization error) using the output value of each K hop addition. A computer-readable recording medium containing instructions for causing the processor to perform an operation may be provided.

시간 동안 수신 신호 샘플이 있을 때, 0~

까지 신호를 필터링하고, 0~

까지 신호를 필터링하며,

~

까지 신호를 필터링하는 단계와, M만큼 필터링된 각 신호를 샘플별로 제곱하고 하나의 값으로 더한 뒤 제곱하여 신호 전력을 검파하는 단계와, 제 2 Mth 파워 검파기의 출력과 제 3 Mth 파워 검파기의 출력을 더한 값을 들어오는 값을 나누어 정규화시키는 단계와, K홉만큼 정규화된 각 값을 덧셈해 주는 단계와, 각 K홉 덧셈의 출력값을 이용하여 홉 타이밍 오차(동기 오차)를 계산하는 단계를 포함하는 동작을 상기 프로세서가 수행하도록 하기 위한 명령어를 포함하는 컴퓨터 프로그램을 제공할 수 있다.According to another aspect, the invention is a computer program stored in a computer-readable recording medium, which, when executed by a processor, reverses the frequency of the frequency-hopping phase-modulated received signal according to the timing. A step of converting to baseband, converting the converted baseband reception signal into an I/Q signal and converting it into a complex signal (I+Qj), and the converted complex signal is

When there are received signal samples during the time, 0~

Filter the signal from 0 to

Filters the signal to

~

A step of filtering the signal up to, squaring each signal filtered by M for each sample, adding them as one value, and then squaring them to detect the signal power, the output of the second Mth power detector and the output of the third Mth power detector A step of normalizing the added value by dividing the incoming value, adding each normalized value by K hops, and calculating the hop timing error (synchronization error) using the output value of each K hop addition. A computer program including instructions for causing the processor to perform an operation may be provided.

According to an embodiment of the present invention, by applying an Mth power algorithm suitable for a phase modulation communication system, the timing error of frequency hopping can be easily estimated by gathering the symbols of the signal in one place.

According to an embodiment of the present invention, it can be applied to a phase modulation communication system using a typical IQ demodulator, and can also be implemented by applying to an FPGA having a block structure.

Figure 1 is a basic configuration diagram of a phase modulation (M-PSK) communication system.
Figure 2 is a block diagram of a frequency hopping timing error estimation device according to an embodiment of the present invention.
Figure 3 shows an example in which the signal position changes due to Mth power.
Figure 4 shows an example of an Mth power detector.
Figure 5 is a flowchart showing the main process of estimating the timing error of frequency hopping according to an embodiment of the present invention.

The advantages and features of the present invention and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and can be implemented in various forms. The present embodiments are merely provided to ensure that the disclosure of the present invention is complete and to those skilled in the art to which the present invention pertains. It is provided to fully inform the person of the scope of the invention, and the scope of the invention is only defined by the claims.

In describing the embodiments of the present invention, detailed descriptions of well-known functions or configurations will be omitted except when actually necessary. The terms described below are terms defined in consideration of functions in the embodiments of the present invention, and may vary depending on the intention or custom of the user or operator. Therefore, the definition should be made based on the contents throughout this specification.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings.

Figure 2 is a block diagram of a frequency hopping timing error estimation device according to an embodiment of the present invention.

Referring to FIG. 2, the frequency hopping timing error estimation device according to an embodiment of the present invention includes an inverse hopping unit 202, an I/Q demodulation unit 204, a filter unit 206, a power detector 208, and a normalization unit. It may include 210, an addition unit 212, and a fine synchronization error calculation unit 214.

When a phase-modulated reception signal with a frequency hopping is received, the reverse hopping unit 202 may perform functions such as converting the frequency hopping signal to baseband by inversely hopping the frequency in accordance with the timing.

The I/Q demodulator 204 may perform functions such as converting the baseband reception signal converted through the inverse jump unit 202 into an I/Q signal and converting it into a complex signal (I+Qj). For example, when a signal whose synchronization error is not adjusted passes through the demodulator 204, a complex signal sample is generated.

시간 동안 수신 신호 샘플이 있을 때, 0~

까지 신호를 필터링하고(제 1 필터, 206a), 0~

까지 신호를 필터링하며(제 2 필터, 206b),

~

까지 신호를 필터링하는(제 3 필터, 206c) 등의 기능을 수행할 수 있다.The filter unit 206 may be composed of, for example, three filters 206a, 206b, and 206c, and the complex signal generated through the I/Q demodulator 204 is

When there are received signal samples during the time, 0~

Filter the signal (first filter, 206a) from 0 to

Filtering the signal until (second filter, 206b),

~

It can perform functions such as filtering the signal (third filter, 206c).

The power detector 208 may be composed of, for example, three Mth power detectors 208a, 208b, and 208c, and samples each signal filtered by M through each filter 206a, 206b, and 206c. You can perform functions such as detecting signal power by squaring the stars, adding them to one value, and then squaring them.

That is, the sample that passes through each filter passes through each Mth power detector and outputs one power value.

If the received signal is a BPSK signal, M is 2, and as an example, as shown in Figure 3, the two points of -1 and 1 on the complex plane have the effect of converging to 1, so the noise decreases as the number of K of the K-hop adder increases. Suppression is possible.

At this time, in the Mth power detector, as shown in FIG. 4 as an example, all samples of the complex signal are squared by M, then added, and the absolute value squared is taken to obtain one power value.

The normalization unit 210 may be composed of, for example, three normalizers 210a, 210b, and 210c. As an example, the output of the second Mth power detector 208b and the output of the third Mth power detector 208c are used. Functions such as normalizing the power level can be performed by dividing the added value by the incoming value.

은 다음의 수식 1과 같이 나타난다.Output of first normalizer 210a

appears as in Equation 1 below.

[Formula 1]

는 제 1 Mth 파워 검파기(208a)의 출력을,

는 Mth 파워 검파기(208b)의 출력을,

는 Mth 파워 검파기(208c)의 출력을 각각 의미한다.In Formula 1 above,

is the output of the first Mth power detector (208a),

is the output of the Mth power detector (208b),

Means the output of the Mth power detector (208c), respectively.

For example, the value passing through the Mth power detector is normalized through a normalizer that divides it into a value normalized by the sum of Mth power #2 and Mth power #3.

The addition unit 212 may be composed of, for example, three K-hop adders 212a, 212b, and 212c, and performs functions such as adding the values of each normalizer 210a, 210b, and 210c by K hops. can do. And, after K hops, the value is initialized.

), #2(

), #3(

)의 값을 K홉 동안 누적한 후 미세 동기 오차 계산부로 전달(인가)한다.That is, the addition unit 212 is normalized #1 (

), #2(

), #3(

) is accumulated for K hops and then transmitted (applied) to the fine synchronization error calculation unit.

은 다음의 수식 2와 같이 계산될 수 있다.For example, the output of a K-hop adder

can be calculated as in Equation 2 below:

[Formula 2]

은 n번째, 정규화기 #1의 출력을 의미한다.In Equation 2 above,

means the output of the nth, normalizer #1.

The fine synchronization error calculation unit 214 may perform functions such as calculating the hop timing error (synchronization error) using the output values of each K-hop adder 212a, 212b, and 212c.

That is, the fine synchronization error calculation unit 214 can calculate V1 and V2 through Equation 3 below.

[Formula 3]

는 제 1 K홉 덧셈기의 출력을,

는 제 2 K홉 덧셈기의 출력을,

는 제 3 K홉 덧셈기의 출력을 각각 나타낸다.In Equation 3 above,

is the output of the first K-hop adder,

is the output of the second K-hop adder,

represents the output of the third K-hop adder, respectively.

)를 아래의 수식 4와 같이 계산할 수 있다.Using V1 and V2 calculated through Equation 3 above, the hop timing error (

) can be calculated as in Equation 4 below.

[Formula 4]

,

일 경우,

=0.5홉

,

In case,

=0.5 hops

일 경우,

홉

In case,

hop

일 경우,

홉

In case,

hop

,

일 경우,

=-0.5홉

,

In case,

=-0.5 hops

Figure 5 is a flowchart showing the main process of estimating the timing error of frequency hopping according to an embodiment of the present invention.

Referring to FIG. 5, when a phase-modulated reception signal with a frequency hopping is received, the reverse hopping unit 202 converts the frequency hopping signal to baseband by inversely jumping the frequency according to the timing (step 502).

The I/Q demodulator 204 converts the baseband reception signal converted through the inverse jump unit 202 into an I/Q signal and converts it into a complex signal (I+Qj) (step 504). For example, when a signal whose synchronization error is not adjusted passes through the demodulator 204, a complex signal sample is generated.

시간 동안 수신 신호 샘플이 있을 때, 0~

까지 신호를 필터링하고(제 1 필터, 206a), 0~

까지 신호를 필터링하며(제 2 필터, 206b),

~

까지 신호를 필터링(제 3 필터, 206c)한다(단계 506).In the filter unit 206, the complex signal generated through the I/Q demodulator 204 is

When there are received signal samples during the time, 0~

Filter the signal (first filter, 206a) from 0 to

Filtering the signal until (second filter, 206b),

~

The signal is filtered (third filter, 206c) until (step 506).

The power detector 208 squares each signal filtered by M through each filter 206a, 206b, and 206c for each sample, adds them to one value, and then squares them to detect signal power (step 508). That is, the sample that passes through each filter passes through each Mth power detector and outputs one power value.

The normalization unit 210 normalizes the power level by, for example, dividing the input value by adding the output of the second Mth power detector 208b and the output of the third Mth power detector 208c (step 510).

The addition unit 212 may be composed of, for example, three K-hop adders 212a, 212b, and 212c, and performs functions such as adding the values of each normalizer 210a, 210b, and 210c by K hops. can do. And, after K hops, the value is initialized.

), #2(

), #3(

)의 값을 K홉 동안 누적(덧셈)한 후 미세 동기 오차 계산부로 전달한다(단계 512).In the addition unit 212, normalized #1 (

), #2(

), #3(

) is accumulated (added) for K hops and then transmitted to the fine synchronization error calculation unit (step 512).

The fine synchronization error calculation unit 214 calculates the hop timing error (synchronization error) using the output values of each K-hop adder 212a, 212b, and 212c (step 514).

Meanwhile, combinations of each block in the attached block diagram and each step in the flow diagram may be performed by computer program instructions. Since these computer program instructions can be mounted on the processor of a general-purpose computer, special-purpose computer, or other programmable data processing equipment, the instructions performed through the processor of the computer or other programmable data processing equipment are shown in each block of the block diagram or flow diagram. Each step creates the means to perform the functions described.

These computer program instructions may also be stored in computer-usable or computer-readable memory, etc., that can be directed to a computer or other programmable data processing equipment to implement a function in a particular way, so that the computer-usable or computer-readable memory The instructions stored in can also produce manufactured items containing instruction means that perform the functions described in each block of the block diagram or each step of the flow diagram.

In addition, computer program instructions can be mounted on a computer or other programmable data processing equipment, so a series of operation steps are performed on the computer or other programmable data processing equipment to create a process that is executed by the computer and run on the computer or other program. Instructions that perform possible data processing equipment may also provide steps for executing functions described in each block of the block diagram and each step of the flow diagram.

Additionally, each block or each step may represent a module, segment, or portion of code that includes at least one or more executable instructions for executing specified logical function(s). Additionally, it should be noted that in some alternative embodiments it is possible for the functions mentioned in the blocks or steps to occur out of order. For example, two blocks or steps shown in succession may in fact be performed substantially simultaneously, or the blocks or steps may sometimes be performed in reverse order depending on the corresponding function.

The above description is merely an illustrative explanation of the technical idea of the present invention, and those of ordinary skill in the art to which the present invention pertains can make various substitutions, modifications, changes, etc. without departing from the essential characteristics of the present invention. It will be easy to see that this is possible. In other words, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but rather to explain it, and the scope of the technical idea of the present invention is not limited by these embodiments.

Therefore, the scope of protection of the present invention should be interpreted in accordance with the claims described below, and all technical ideas within the equivalent scope should be interpreted as being included in the scope of rights of the present invention.

202: Weight Jump Department
204: I/Q demodulation unit
206: filter unit
208: Power detection unit
210: Normalization unit
212: addition part
214: Fine synchronization error calculation unit

Claims (6)

A reverse jump unit that converts the frequency-hopping phase-modulated reception signal to baseband by jumping the frequency backwards according to the timing,
A demodulator for converting the converted baseband reception signal into an I/Q signal and converting it into a complex signal (I+Qj);
The converted complex signal is

When there are received signal samples during the time, 0~

Filter the signal from 0 to

Filters the signal to

~

A filter unit consisting of n filters that filter signals up to
A power detector consisting of n Mth power detectors that detect the signal power by squaring each signal filtered by M through each filter for each sample, adding them to one value, and then squaring them;
a normalization unit consisting of n normalizers that divide the incoming value by adding the output of the second Mth power detector and the output of the third Mth power detector;
An adder consisting of n K-hop adders that add the values of each normalizer by K hops,
A fine synchronization error calculation unit that calculates the hop timing error (synchronization error) using the output value of each K-hop adder.
Frequency hopping timing error estimation device. According to claim 1,
Each of the K-hop adders is:
Initializing the value after K hops
Frequency hopping timing error estimation device. According to claim 1,
The fine synchronization error calculation unit,
Calculate V1 and V2 using the following formulas,

(remind

is the output of the first Khop adder,

is the output of the second Khop adder,

represents the output of the 3rd K-hop adder, respectively)
Using the calculated V1 and V2, the hop timing error (

) is calculated using the following formula:

,

In case,

=0.5 hops

In case,

hop

In case,

hop

,

In case,

=-0.5 hops Converting the frequency-hopping phase-modulated received signal to baseband by inversely jumping the frequency according to the timing;
Converting the converted baseband received signal into an I/Q signal and converting it into a complex signal (I+Qj);
The converted complex signal is

When there are received signal samples during the time, 0~

Filter the signal from 0 to

Filters the signal to

~

A step of filtering the signal to
Detecting the signal power by squaring each signal filtered by M for each sample, adding them to one value, and then squaring them;
Normalizing the output of the second Mth power detector and the output of the third Mth power detector by dividing the incoming value;
A step of adding each value normalized by K hops,
Including calculating the hop timing error (synchronization error) using the output value of each K-hop addition.
Frequency hopping timing error estimation method. A computer-readable recording medium storing a computer program,
When the computer program is executed by a processor,
Converting the frequency-hopping phase-modulated received signal to baseband by inversely jumping the frequency according to the timing;
Converting the converted baseband received signal into an I/Q signal and converting it into a complex signal (I+Qj);
The converted complex signal is

When there are received signal samples during the time, 0~

Filter the signal from 0 to

Filters the signal to

~

A step of filtering the signal to
Detecting the signal power by squaring each signal filtered by M for each sample, adding them to one value, and then squaring them;
Normalizing the output of the second Mth power detector and the output of the third Mth power detector by dividing the incoming value;
A step of adding each value normalized by K hops,
Comprising instructions for causing the processor to perform an operation comprising calculating a hop timing error (synchronization error) using the output value of each K-hop addition,
A computer-readable recording medium. A computer program stored on a computer-readable recording medium,
When the computer program is executed by a processor,
Converting the frequency-hopping phase-modulated received signal to baseband by inversely jumping the frequency according to the timing;
Converting the converted baseband received signal into an I/Q signal and converting it into a complex signal (I+Qj);
The converted complex signal is

When there are received signal samples during the time, 0~

Filter the signal from 0 to

Filters the signal to

~

A step of filtering the signal to
Detecting the signal power by squaring each signal filtered by M for each sample, adding them to one value, and then squaring them;
Normalizing the output of the second Mth power detector and the output of the third Mth power detector by dividing the incoming value;
A step of adding each value normalized by K hops,
Comprising instructions for causing the processor to perform an operation comprising calculating a hop timing error (synchronization error) using the output value of each K-hop addition,
computer program.

Images