KR20230128932A - Semiconductor devices - Google Patents

Abstract

A semiconductor device according to an embodiment of the present invention includes: a substrate including an active region extending in a first direction; a gate electrode extending in a second direction crossing the active region on the substrate; , a plurality of channel layers disposed spaced apart from each other along a third direction perpendicular to the upper surface of the substrate and disposed to be surrounded by the gate electrode, disposed between the plurality of channel layers and the gate electrode, and a ferroelectric material A plurality of dielectric layers including a ferroelectric material or an anti-ferroelectric material, and recess regions in which the active region is recessed at both sides of the gate electrode, and the plurality of channel layers and It includes contact source/drain regions, and the plurality of dielectric layers have different coercive voltages.

Description

Semiconductor device {SEMICONDUCTOR DEVICES}

The present invention relates to semiconductor devices.

Ferroelectrics are materials having ferroelectricity that maintain spontaneous polarization by aligning electric dipole moments even when an external electric field is not applied. Research is being conducted to apply these ferroelectric properties to memory devices of semiconductor devices.

One of the technical problems to be achieved by the present invention is to provide a semiconductor device with improved integration and electrical characteristics.

A semiconductor device according to example embodiments includes a substrate including an active region extending in a first direction, a gate electrode extending in a second direction crossing the active region on the substrate, and a substrate on the active region. A plurality of channel layers arranged to be spaced apart from each other along a third direction perpendicular to the top surface and surrounded by the gate electrode, and disposed between the plurality of channel layers and the gate electrode and made of a ferroelectric material Alternatively, a plurality of dielectric layers including an anti-ferroelectric material, and a source / disposed in recess regions in which the active region is recessed at both sides of the gate electrode and in contact with the plurality of channel layers / Including drain regions, the plurality of dielectric layers may have different coercive voltages.

A semiconductor device according to example embodiments includes a substrate including an active region extending in a first direction, a gate electrode extending in a second direction crossing the active region on the substrate, and a substrate on the active region. First to third channel layers spaced apart from each other in a third direction perpendicular to the top surface and sequentially disposed from the active region, surrounded by the gate electrode, and surrounding the first to third channel layers, First to third dielectric layers sequentially disposed along the third direction from the active region and including a ferroelectric material or an antiferroelectric material, and recess regions in which the active region is recessed at both sides of the gate electrode and includes source/drain regions in contact with the first to third channel layers, and the first to third dielectric layers may have different thicknesses.

A semiconductor device according to example embodiments includes a memory cell array in which a plurality of memory elements are disposed, and a peripheral circuit area including peripheral circuits for controlling the memory cell array, each of the plurality of memory elements , an active region extending in a first direction, a gate electrode extending in a second direction crossing the active region, and disposed spaced apart from each other along a third direction perpendicular to the top surface of the active region on the active region, wherein the a plurality of channel layers disposed to be surrounded by a gate electrode, and a plurality of dielectric layers disposed between the plurality of channel layers and the gate electrode and including a ferroelectric material or an antiferroelectric material, each of the plurality of In the memory elements of , the number of the plurality of channel layers is N (N is a natural number greater than or equal to 2), and each of the plurality of memory elements may store data of N bits or less.

In the MBCFET structure, a semiconductor device with improved degree of integration and improved electrical characteristics can be provided by allowing the dielectric layers to have different coherent voltages.

The various beneficial advantages and effects of the present invention are not limited to the above, and will be more easily understood in the process of describing specific embodiments of the present invention.

1 is a plan view illustrating a semiconductor device according to example embodiments.
2 is a cross-sectional view illustrating a semiconductor device according to example embodiments.
3A to 3C are partial enlarged views of a semiconductor device according to example embodiments.
4 illustrates a hysteresis curve of a ferroelectric material constituting a semiconductor device according to example embodiments.
5 is a block diagram illustrating a semiconductor device according to example embodiments.
6 to 7B are diagrams for describing an operation of a semiconductor device according to example embodiments.
8 is a diagram for describing an operation of a semiconductor device according to example embodiments.
9 is a cross-sectional view illustrating a semiconductor device according to example embodiments. 9 shows a cross section corresponding to FIG. 2 .
10 is a cross-sectional view illustrating a semiconductor device according to example embodiments.
11A and 11B are cross-sectional views illustrating a semiconductor device according to example embodiments.
12A and 12B are cross-sectional views illustrating a semiconductor device according to example embodiments.
13A to 13E are views illustrating a process sequence to describe a method of manufacturing a semiconductor device according to example embodiments.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described as follows. Hereinafter, terms such as 'upper', 'top', 'top', 'bottom', 'bottom', 'bottom', and 'side' are indicated by reference numerals and are based on drawings, except where otherwise indicated. It can be understood as referring to.

1 is a plan view illustrating a semiconductor device according to example embodiments.

2 is a cross-sectional view illustrating a semiconductor device according to example embodiments. FIG. 2 illustrates cross-sections of the semiconductor device of FIG. 1 taken along cutting lines II' and II-II'. For convenience of description, only some components of the semiconductor device are illustrated in FIG. 1 .

Referring to FIGS. 1 and 2 , the semiconductor device 100 includes a substrate 101 including an active region 105 and first to third channel layers disposed vertically spaced apart from each other on the active region 105 . A channel structure 140 including fields 141 , 142 , and 143 , a gate structure GS extending to cross the active region 105 and including a gate electrode 175 , and a source contacting the channel structure 140 . /drain regions 150 and contact plugs 180 connected to the source/drain regions 150 . The semiconductor device 100 may further include an element isolation layer 110 , internal spacer layers 130 , and an interlayer insulating layer 190 . The gate structure GS may include dielectric layers 160 including a ferroelectric material or an antiferroelectric material, gate spacer layers 172 , and a gate electrode 175 .

In the semiconductor device 100, the active region 105 has a fin shape, and the gate electrode 175 is between the active region 105 and the channel structure 140, and the first through first through It may be disposed between the third channel layers 141 , 142 , and 143 and on the channel structure 140 . Accordingly, the semiconductor device 100 may include a multi bridge channel FET (MBCFET ^TM ) structure transistor, which is a gate-all-around type field effect transistor.

The substrate 101 may have an upper surface extending in the x and y directions. The substrate 101 may include a semiconductor material, such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI compound semiconductor. For example, the group IV semiconductor may include silicon, germanium, or silicon-germanium. The substrate 101 may be provided as a bulk wafer, an epitaxial layer, a Silicon On Insulator (SOI) layer, or a Semiconductor On Insulator (SeOI) layer.

The substrate 101 may include an active region 105 disposed thereon. The active region 105 is defined by the device isolation layer 110 within the substrate 101 and may be disposed to extend in a first direction, for example, an x direction. However, depending on the description method, it may also be possible to describe the active region 105 as a separate configuration from the substrate 101 . The active region 105 may have a structure protruding upward. The active region 105 may be made of a part of the substrate 101 or may include an epitaxial layer grown from the substrate 101 . However, at both sides of the gate structure GS, the active region 105 is partially recessed to form recess regions, and source/drain regions 150 may be disposed in the recess regions. In example embodiments, the active region 105 may or may not include a well region containing impurities.

The device isolation layer 110 may define an active region 105 in the substrate 101 . The device isolation layer 110 may be formed by, for example, a shallow trench isolation (STI) process. The device isolation layer 110 may expose an upper surface of the active region 105 or partially expose an upper surface of the active region 105 . In example embodiments, the device isolation layer 110 may have a curved top surface so as to have a higher level closer to the active region 105 . The device isolation layer 110 may be made of an insulating material. The device isolation layer 110 may include, for example, oxide, nitride, or a combination thereof.

The channel structure 140 may be disposed on the active region 105 in regions where the active region 105 intersects the gate structure GS. The channel structure 140 may include first to third channel layers 141 , 142 , and 143 that are two or more channel layers spaced apart from each other in the z direction. However, the number and shape of channel layers constituting one channel structure 140 may be variously changed in embodiments. The channel structure 140 may be connected to the source/drain regions 150 . The channel structure 140 may have a width equal to or smaller than that of the active region 105 in the y direction, and may have a width equal to or similar to that of the gate structure GS in the x direction. In some embodiments, the channel structure 140 may have a reduced width such that side surfaces are located under the gate structure GS in the x direction.

The channel structure 140 may be formed of a semiconductor material, and may include, for example, at least one of a group ₃ semiconductor material, an oxide semiconductor material, and a two-dimensional transition metal chalcogen compound semiconductor material. In some embodiments, the channel structure 140 may include an impurity region located in a region adjacent to the source/drain regions 150 .

The Group ₃ semiconductor may be, for example, at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge), and may have a single crystal, polycrystalline, or amorphous structure. For example, in the semiconductor device 100, the dielectric layers 160 include a ferromagnetic material or an antiferromagnetic material, so that leakage current characteristics are secured and the channel structure 140 may have a polycrystalline or amorphous structure instead of a single crystal.

The oxide semiconductor material may be an oxide containing at least one of indium (In), zinc (Zn), and gallium (Ga). The oxide semiconductor material may be, for example, zinc tin oxide (ZTO), indium zinc oxide (IZO), ZnO, indium gallium zinc oxide (IGZO), indium gallium silicon oxide (IGSO), indium oxide (InO), or tin oxide. (SnO), Titanium Oxide (TiO), Zinc Oxynitride (ZnON), Magnesium Zinc Oxide (MgZnO), Indium Zinc Oxide (InZnO), Indium Gallium Zinc Oxide (InGaZnO), Zirconium Indium Zinc Oxide (ZrInZnO), Hafnium Indium Zinc Oxide (HfInZnO), Tin Indium Zinc Oxide (SnInZnO), Aluminum Tin Indium Zinc Oxide (AlSnInZnO), Silicon Indium Zinc Oxide (SiInZnO), Zinc Tin Oxide (ZnSnO), Aluminum Zinc Tin Oxide (AlZnSnO), Gallium Zinc Tin Oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO), and indium gallium silicon oxide (InGaSiO).

The two-dimensional transition metal chalcogen compound semiconductor material may have a two-dimensional layered structure, and may include, for example, at least one of MoS ₂ , MoSe ₂ , WS ₂ , and WSe ₂ .

The gate structure GS may be disposed to cross the active region 105 and the channel structure 140 and extend in the second direction, for example, the y direction. A channel region of a memory device may be formed in the channel structure 140 crossing the gate electrode 175 of the gate structure GS. The gate structure GS includes a gate electrode 175, dielectric layers 160 between the gate electrode 175 and the channel structure 140, and gate spacer layers 172 on side surfaces of the gate electrode 175. can do. In some embodiments, the gate structure GS may further include a capping layer on a top surface of the gate electrode 175 . Alternatively, a portion of the interlayer insulating layer 190 on the gate structure GS may be referred to as a gate capping layer.

The dielectric layers 160 may be disposed between the active region 105 and the gate electrode 175 and between the channel structure 140 and the gate electrode 175, and may cover at least some of the surfaces of the gate electrode 175. It can be arranged to cover. For example, the dielectric layers 160 may be disposed to surround all surfaces except for the uppermost surface of the gate electrode 175 . The dielectric layers 160 may extend between the gate electrode 175 and the gate spacer layers 172, but are not limited thereto. The dielectric layers 160 include the first to third dielectric layers 161 , 162 , and 163 surrounding the first to third channel layers 141 , 142 , and 143 , and the first to third channel layers ( 141 , 142 , and 143 may include a lowermost fourth dielectric layer 167 spaced apart from each other.

Dielectric layers 160 may include a ferroelectric material or an antiferroelectric material. The dielectric layers 160 may include, for example, hafnium (Hf), zirconium (Zr), silicon (Si), yttrium (Y), aluminum (Al), gadolinium (Gd), strontium (Sr), lanthanum (La), It may include at least one of scandium (Sc) and oxides thereof. The dielectric layers 160 may be, for example, hafnium oxide (HfO ₂ ), zirconium oxide (ZrO ₂ ), hafnium-zirconium oxide (Hf _x Zr _1-x O ₂ , 0<x<1), and combinations thereof. It includes, as a base material, at least one material selected from the group consisting of hafnium (Hf), zirconium (Zr), silicon (Si), yttrium (Y), aluminum (Al), gadolinium (Gd), Strontium (Sr), Lanthanum (La), Scandium (Sc) Carbon (C), Germanium (Ge), Tin (Sn), Lead (Pb), Magnesium (Mg), Calcium (Ca), Barium (Ba), Titanium (Ti), and one or more dopant materials selected from the group consisting of combinations thereof may be further included. For example, dielectric layers 160 may include zirconium (Zr), silicon (Si), yttrium (Y), aluminum (Al), gadolinium (Gd), strontium (Sr), lanthanum (La), and scandium (Sc). At least one of them may include doped hafnium oxide.

The first to third dielectric layers 161, 162, and 163 may have different coherent voltages. In this embodiment, the first to third dielectric layers 161, 162, and 163 may include the same or different materials and may have different thicknesses. Even when the first to third dielectric layers 161, 162, and 163 include the same material as each other, the first to third dielectric layers 161, 162, and 163 have different thicknesses and thus have different coherent voltages. can have This will be described in more detail with reference to FIG. 4 below.

In this embodiment, the first dielectric layer 161 surrounding the first channel layer 141 has a first thickness T1, and the second dielectric layer 162 surrounding the second channel layer 142 has a first thickness T1. The third dielectric layer 163 having a second thickness T2 greater than the thickness T1 and surrounding the third channel layer 143 may have a third thickness T3 greater than the second thickness T2. . Each of the first to third thicknesses T1 , T2 , and T3 may have, for example, a range of about 1 nm to about 30 nm. For example, the first thickness T1 may have a range of about 1 nm to about 5 nm, and the third thickness T3 may have a range of about 20 nm to about 30 nm. In embodiments, the location of the dielectric layer 160 having the largest and smallest coherent voltage may be varied. For example, it may be possible for the first dielectric layer 161 to have the largest thickness or the second dielectric layer 162 to have the largest thickness.

The lowermost fourth dielectric layer 164 may have the same first thickness T1 as the adjacent first dielectric layer 161, but is not limited thereto. In the dielectric layers 160 , regions extending perpendicularly from the third dielectric layer 163 and contacting the gate spacer layers 172 may also have the same third thickness T3 as the third dielectric layer 163 . Not limited. Also, in a cross section along the x direction, regions where the dielectric layers 160 contact the internal spacer layers 130 may have the same thickness as the upper or lower dielectric layers 160 . For example, the region may have the same thickness as the upper dielectric layers 160 . In some embodiments, the region may include a region where the upper and lower dielectric layers 160 contact each other, and thus may include a region where the thickness is changed.

A first distance D1 between the fourth dielectric layer 167 and the first dielectric layer 161 may be greater than a second distance D2 between the first dielectric layer 161 and the second dielectric layer 162, and The distance D2 may be greater than the third distance D3 between the second dielectric layer 162 and the third dielectric layer 163, but is not limited thereto.

Gate spacer layers 172 may be disposed on both side surfaces of the gate electrode 175 on top of the channel structure 140 . The gate spacer layers 172 may insulate the source/drain regions 150 and the gate electrode 175 . In an embodiment, the shape of the gate spacer layers 172 may be variously changed, and in some embodiments, the gate spacer layers 172 may have a multilayer structure. The gate spacer layers 172 may be formed of at least one of oxide, nitride, and oxynitride, and in particular, may be formed of a low dielectric constant layer.

The gate electrode 175 may be disposed to fill a gap between the channel structures 140 on the active region 105 and to extend to an upper portion of the channel structure 140 . The gate electrode 175 may be spaced apart from the channel structure 140 by dielectric layers 160 . The gate electrode 175 may include a conductive material, for example, a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN), and/or aluminum (Al) or tungsten. (W), or a metal material such as molybdenum (Mo) or a semiconductor material such as doped polysilicon. In some embodiments, the gate electrode 175 may be composed of two or more multi-layers.

The source/drain regions 150 may be disposed in recess regions partially recessed from upper portions of the active regions 105 on both sides of the gate structure GS. The source/drain regions 150 may be disposed to contact side surfaces of the first to third channel layers 141 , 142 , and 143 of the channel structure 140 . The upper surfaces of the source/drain regions 150 may be located at the same or similar height as the lower surface of the uppermost gate electrode 175, and the height may be variously changed in embodiments. The source/drain regions 150 may include impurities.

The inner spacer layers 130 may be disposed parallel to the gate structure GS between the channel structures 140 . The gate electrode 175 may be stably spaced apart from the source/drain regions 150 by the internal spacer layers 130 and electrically separated from each other. The internal spacer layers 130 may have a shape in which side surfaces facing the gate structure GS are convexly rounded inward toward the gate structure GS, but are not limited thereto. The inner spacer layers 130 may be formed of oxide, nitride, and oxynitride, and particularly may be formed of a low-k film. However, in some embodiments, the inner spacer layers 130 may be omitted. In this case, the gate structure GS or the source/drain regions 150 may be disposed to extend in the x direction to fill the region where the internal spacer layers 130 are disposed.

The interlayer insulating layer 190 may be disposed to cover the source/drain regions 150 and the gate structure GS and to cover the device isolation layer 110 . The interlayer insulating layer 190 may include at least one of oxide, nitride, and oxynitride, and may include, for example, a low dielectric constant material. In some embodiments, the interlayer insulating layer 190 may include a plurality of insulating layers.

The contact plugs 180 may pass through the interlayer insulating layer 190 and be connected to the source/drain regions 150 and may apply electrical signals to the source/drain regions 150 . The contact plugs 180 may have inclined side surfaces in which the width of the lower portion is narrower than the width of the upper portion according to the aspect ratio, but is not limited thereto. The contact plugs 180 may extend from the top to, for example, below the lower surface of the third channel layer 143, but are not limited thereto. In example embodiments, the contact plugs 180 may be disposed to contact along top surfaces of the source/drain regions 150 without recessing the source/drain regions 150 . Although not shown, a contact plug may also be connected to the gate electrode 175 .

The contact plugs 180 may include a metal silicide layer positioned in an area in contact with the source/drain areas 150 and disposed on an upper surface of the metal silicide layer and sidewalls of the contact plugs 180 . A barrier layer may be further included. The barrier layer may include, for example, a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN). The contact plugs 180 may include, for example, a metal material such as aluminum (Al), tungsten (W), or molybdenum (Mo). In example embodiments, the number and arrangement of conductive layers constituting the contact plugs 180 may be variously changed.

When the semiconductor device 100 functions as a memory device, the dielectric layer 160 surrounding each of the first to third channel layers 141 , 142 , and 143 constituting the channel structure 140 has different coherent voltages. , The memory device may implement a multi-level cell (MLC) or a multi-bit cell. This will be described in more detail with reference to FIGS. 5 to 8 below.

In the description of the following embodiments, descriptions overlapping with those described above with reference to FIGS. 1 and 2 will be omitted.

3A to 3C are partial enlarged views of a semiconductor device according to example embodiments. 3A to 3C show a partial region of the dielectric layer 160 corresponding to the 'A' region of FIG. 2 .

Referring to FIG. 3A , the dielectric layer 160a may include first and second dielectric layers 160_1 and 160_2 that are alternately stacked. The first and second dielectric layers 160_1 and 160_2 may include different ferroelectric materials or antiferroelectric materials. For example, the first dielectric layers 160_1 may include hafnium oxide (HfO ₂ ), and the second dielectric layers 160_2 may include zirconium oxide (ZrO ₂ ).

In FIGS. 3A to 3C , the first and second dielectric layers 160_1 and 160_2 may be independently described without being associated with each other.

Referring to FIG. 3B , the dielectric layer 160b may include first dielectric layers 160_1 and a second dielectric layer 160_2 interposed between the first dielectric layers 160_1 . The first dielectric layers 160_1 may include a ferroelectric material or an antiferroelectric material. The second dielectric layer 160_2 may include a ferroelectric material or an antiferroelectric material, or may include a material that is not ferroelectric or antiferroelectric. For example, the first dielectric layers 160_1 may include hafnium zirconium oxide (HZO), and the second dielectric layer 160_2 may include aluminum oxide (Al ₂ O ₃ ).

Referring to FIG. 3C , the dielectric layer 160c may include a first dielectric layer 160_1 and a second dielectric layer 160_2 sequentially disposed from the channel structure 140 . The first dielectric layers 160_1 may include a material that is not ferroelectric and may include a material that is not antiferroelectric. The second dielectric layer 160_2 may include a ferroelectric material or an antiferroelectric material. For example, the first dielectric layers 160_1 may include silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), silicon oxynitride (SiON), a high-k dielectric material, or a combination thereof. can include Here, the high dielectric constant material means a dielectric material having a higher dielectric constant than silicon oxide (SiO ₂ ). The high dielectric constant material may be, for example, aluminum oxide (Al ₂ O ₃ ), tantalum oxide (Ta ₂ O ₃ ), titanium oxide (TiO ₂ ), yttrium oxide (Y ₂ O ₃ ), zirconium oxide (ZrO ₂ ) , zirconium silicon oxide (ZrSixOy), hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSixOy), lanthanum oxide (La ₂ O ₃ ), lanthanum aluminum oxide (LaAlxOy), lanthanum hafnium oxide (LaHfxOy), hafnium aluminum oxide (HfAlxOy ), praseodymium oxide (Pr ₂ O ₃ ), or a combination thereof.

As described above with reference to FIGS. 3A to 3C , each of the dielectric layers 160a, 160b, and 160c may have a single-layer structure as well as a multi-layer structure in the embodiments, and the specific structure is variously changed in the embodiments. It can be.

4 illustrates a hysteresis curve of a ferroelectric material constituting a semiconductor device according to example embodiments.

Referring to FIG. 4 , polarization does not occur unless an electric field is applied to the dielectric layer 160 (see FIG. 2 ) including a ferroelectric material. When the voltage across the dielectric layer 160 or the voltage applied to the gate electrode 175 increases in the positive (plus) direction, the polarization (or amount of charge) changes from zero to the saturation polarization point within the positive polarization region. A positive maximum (+P _Sat ) is reached. Thereafter, even if the voltage across the dielectric layer 160 drops to 0 V again, the polarization does not drop to zero and remains at the positive residual point (+P _R ), which is a remanent polarization point.

When the voltage across the dielectric layer 160 increases in a negative direction, the polarizability changes from a positive residual point (+P _R ) to a negative maximum point (-P _Sat ) in the negative polarization region. At this time, the ferroelectric material of the dielectric layer 160 is polarized in a direction opposite to the polarization direction at the positive maximum point (+P _Sat ). Thereafter, even if the voltage across the dielectric layer 160 drops to 0 V again, the polarizability does not drop to zero and remains at the negative residual point (-P _R ).

In order to change the polarization direction of the dielectric layer 160, a voltage must be applied in the opposite direction, and this voltage corresponds to the coherent voltage (+V _C , -V _C ). The coercive voltages (+V _C , -V _C ) are proportional to the thickness of the dielectric layer 160 and the coercive field (E _C ) of the material of the dielectric layer 160 . Accordingly, when the materials of the first to third dielectric layers 161, 162, and 163 constituting the dielectric layer 160 are the same, the coherent voltages (+V _C , -V _C ) may be applied to the first to third dielectric layers 161, 162, 163) may increase in proportion to the thickness. In addition, when the thicknesses of the first to third dielectric layers 161, 162, and 163 constituting the dielectric layer 160 are the same and materials are different, the core sheave voltages (+V _C , -V _C ) of each material are It can increase in proportion to the electric field.

5 is a block diagram illustrating a semiconductor device according to example embodiments.

Referring to FIG. 5 , the semiconductor device 1 may include a memory cell array 10 and a peripheral circuit area 20 .

The memory cell array 10 may include memory cells or memory elements. In the memory cell array 10 , the memory cells may be non-volatile memory cells. For example, the memory cells may have a structure described above with reference to FIGS. 1 to 3C or a structure described below with reference to FIGS. 9 to 12B .

The peripheral circuit area 20 may include peripheral circuits such as a row decoder 22 , a sense amplifier 24 , a column decoder 26 , and a control logic 28 . In the peripheral circuit area 20, the row decoder 22 may be connected to memory devices through a word line WL, and the sense amplifier 24 may be connected to memory devices through a bit line BL. The row decoder 22 may select a memory cell from which data is written or read, and the sense amplifier 24 may program data into the memory cell or read data from the memory cell through a bit line. The column decoder 26 may transfer data to be written to the sense amplifier 24 or transfer data read from the memory cell array 10 by the sense amplifier 24 to the control logic 28 . The control logic 28 may control the operation of the row decoder 22, the sense amplifier 24, and the column decoder 26.

6 to 7B are diagrams for describing an operation of a semiconductor device according to example embodiments.

First, referring to FIG. 6, the first to third dielectric layers 161, 162, and 163 of FIG. 2 are referred to as first to third ferroelectric layers FE1, FE2, and FE3, respectively, and each of the coherent voltage When is referred to as the first to third voltages (+V _C1 , +V _C2 , +V _C3 , -V _C1 , -V _C2 , -V _C3 ), the first to third ferroelectric layers FE1 , FE2 , and FE3 ) to store data in one memory cell. For example, in the embodiment illustrated in FIG. 6 , one memory cell or memory device may store 3-bit data in a triple level cell (TLC) method. In FIG. 6, (1) to (8) refer to the polarization states of the first to third ferroelectric layers FE1, FE2, and FE3, and the voltages indicated on each top are the last to implement the polarization state. Indicates the input program voltage.

Specifically, a voltage greater than or equal to a positive third voltage (+V _C3 ), for example, a first program voltage is applied to the gate electrode 165 (see FIG. 3 ), so that the first to third ferroelectric layers FE1, FE2, The memory cell may be set to the polarization state (1) by causing electric dipoles to be polarized in the first direction in all of FE3). In this specification, the magnitude of voltage is described based on an absolute value.

In the case of the polarization state (2), the second negative voltage (-V C2 ) equal to or greater than the first negative voltage (-V _C1 ) at the gate electrode 165 of the memory cell set to the polarization _state (1) It may be implemented by further applying a smaller second program voltage so that the polarization direction of the first ferroelectric layer FE1 is changed to a second direction opposite to the first direction.

When a second or third program voltage equal to or greater than or greater than the negative second voltage (-V _C2 ) and smaller than the negative third voltage (-V _C3 ) is applied to the polarization state (1) or (2), Polarization directions of the first and second ferroelectric layers FE1 and FE2 may be changed to a second direction opposite to the first direction. Accordingly, the first to third ferroelectric layers FE1, FE2, and FE3 may be in a polarization state (3). Fig. 7a thus shows a program method for implementing the polarization state (3). According to this, first, after inputting the first program voltage higher than the positive third voltage (+V _C3 ), the same as or greater than the second negative voltage (-V _C2 ) and higher than the negative third voltage (-V _C3 ). A program operation may be performed in the order of inputting a small second program voltage.

When a third program voltage equal to or higher than the positive first voltage (+V _C1 ) and smaller than the positive second voltage (+V _C2 ) is applied to the polarization state (3), the first ferroelectric layer FE1 The polarization direction may be changed from the second direction to the first direction, resulting in a polarization state (4). Figure 7b shows a program method for implementing this polarization state (4). Referring to FIG. 7B , the first program voltage equal to or greater than the third positive voltage (+V _C3 ), equal to or greater than the second negative voltage (-V _C2 ) and smaller than the third negative voltage (-V _C3 ). By sequentially inputting 2 program voltages and a third program voltage that is equal to or greater than the positive first voltage (+V _C1 ) and smaller than the positive second voltage (+V _C2 ), the first to second program voltages included in the memory cell are sequentially input. A program operation may be performed to set the polarization state of the third ferroelectric layers FE1 , FE2 , and FE3 to the polarization state (4).

Similarly, when a first program voltage equal to or higher than the negative third voltage (-V _C3 ) is applied to the gate electrode 165 , all of the first to third ferroelectric layers FE1 , FE2 , and FE3 in the second direction Polarization may occur, resulting in a polarization state (5). When a second program voltage equal to or higher than the positive first voltage (+V _C1 ) and smaller than the positive second voltage (+V _C2 ) is applied to the polarization state (5), the first ferroelectric layer FE1 The polarization direction may be changed to the first direction, resulting in a polarization state (6). In the polarization state (5) or (6), when a second or third program voltage equal to or greater than the positive second voltage (+V _C2 ) and smaller than the positive third voltage (+V _C3 ) is applied, the second or third program voltage is applied. Polarization directions of the first and second ferroelectric layers FE1 and FE2 may be changed to the first direction. The polarization state (7) can thereby be realized. When a third program voltage equal to or higher than the negative first voltage (-V _C1 ) and smaller than the negative second voltage (-V _C2 ) is applied to the polarization state (7), the first ferroelectric layer (FE1) The polarization direction may be changed from the first direction to the second direction, resulting in a polarization state (8).

The voltage applied to the gate electrode 165 may be performed and controlled by, for example, the peripheral circuit region 20 of FIG. 5 . Data may be written by sequentially inputting program voltages having different codes as described above to the memory cells implemented by the semiconductor device 100 of FIG. 2 . As described above, the program voltages for writing one data may have different sizes, and the first program voltage input first may have the largest size. However, the program operation may be completed only with a program voltage higher than the positive third voltage (+V _C3 ) or higher than the negative third voltage (-V _C3 ) according to data to be written in the memory cell.

According to this embodiment, when the number of channel layers in a memory cell is 3, and thus the number of dielectric layers is 3, 8 different polarization states can be implemented as shown in FIG. 3 bits can be stored. As such, in exemplary embodiments, when the number of channel layers of a memory cell is N (N is a natural number greater than or equal to 2), data of up to N bits may be stored in the memory cell. That is, data of N bits or less can be stored in the memory cell. Also, as described above, desired 3-bit data can be written in one memory cell by inputting program voltages having different sizes up to N times.

8 is a diagram for describing an operation of a semiconductor device according to example embodiments.

Referring to FIG. 8 , a memory device of the semiconductor device 100 (see FIG. 2 ) may be programmed to have one of first to eighth states P1 , P2 , P3 , P4 , P5 , P6 , P7 , and P8 . and the first to eighth states P1 , P2 , P3 , P4 , P5 , P6 , P7 , and P8 may correspond to different threshold voltages. The threshold voltage of the memory device in the first program state P1 may be the lowest, and the threshold voltage of the memory device in the eighth program state P8 may be the highest. In addition, the memory device may store 3-bit data including a least significant bit (LSB), a central significant bit (CSB), and a most significant bit (MSB). The first to eighth states P1, P2, P3, P4, P5, P6, P7, and P8 may be allocated to different 3-bit data.

In example embodiments, the memory device includes first to third ferroelectric layers FE1, FE2, and FE3, and the most significant bit MSB is obtained by adjusting the polarization state of the first ferroelectric layer FE1. can be programmed in Similarly, the middle bit CSB is programmed into the memory device by adjusting the polarization state of the second ferroelectric layer FE2, and the least significant bit LSB is programmed into the memory device by adjusting the polarization state of the third ferroelectric layer FE3. can be programmed

6 and 8, the first program state (P1) of polarization state (1) is assigned to data '111', and the second program state (P2) of polarization state (2) is assigned to data '110'. and the third program state (P3) of polarization state (4) is assigned to data '101', the fourth program state (P4) of polarization state (3) is assigned to data '100', and the polarization state ( 7), the fifth program state (P5) is assigned data '011', the polarization state (8), the sixth program state (P5) is assigned data '010', and the polarization state (6), the seventh program The state P7 is assigned data '001', and the polarization state 5, the eighth program state P8, can be assigned data '000'. As described above with reference to FIG. 6, in the case of data by polarization states (2) to (4) and polarization states (6) to (8) in which the program voltage is input twice or more, the first to third ferroelectric layers At least some of (FE1, FE2, and FE3) may have different polarization states, and thus at least some of bits of data programmed into the memory device may have different values.

In example embodiments, a read voltage between the maximum value of the threshold voltage distribution corresponding to the fourth program state P4 and the minimum value of the threshold voltage distribution corresponding to the fifth program state P5 is applied to the gate electrode of the memory device ( 165), it is possible to execute a first read operation for determining the most significant bit (MSB).

The read operation of the middle bit (CSB) is performed by using a read voltage between the maximum value of the threshold voltage distribution corresponding to the second program state P2 and the minimum value of the threshold voltage distribution corresponding to the third program state P3. A read operation or a second read operation using a read voltage between the maximum value of the threshold voltage distribution corresponding to the sixth program state P6 and the minimum value of the threshold voltage distribution corresponding to the seventh program state P7 there is.

The read operation of the least significant bit (LSB) is a third program using a read voltage between the maximum value of the threshold voltage distribution corresponding to the first program state P1 and the minimum value of the threshold voltage distribution corresponding to the second program state P2. Read operation, a third read operation using a read voltage between the maximum value of the threshold voltage distribution corresponding to the third program state (P3) and the minimum value of the threshold voltage distribution corresponding to the fourth program state (P4), and the fifth program state A third read operation using a read voltage between the maximum value of the threshold voltage distribution corresponding to (P5) and the minimum value of the threshold voltage distribution corresponding to the sixth program state (P6), and One of third read operations using a read voltage between the maximum value of the threshold voltage distribution and the minimum value of the threshold voltage distribution corresponding to the eighth program state P8 may be included. However, a specific operation method of the read operation is not limited thereto.

9 is a cross-sectional view illustrating a semiconductor device according to example embodiments. 9 shows a cross section corresponding to FIG. 2 .

Referring to FIG. 9 , in the semiconductor device 100a, the first to fourth dielectric layers 161a, 162a, 163a, and 167a of the dielectric layers 160a may all have the same thickness T5. However, even in this case, the first through third dielectric layers 161a, 162a, and 163a may have different core sheave voltages. To this end, the first to third dielectric layers 161a, 162a, and 163a may include ferroelectric or antiferroelectric materials having different covalent electric fields. Alternatively, even when the first to third dielectric layers 161a, 162a, and 163a include the same ferroelectric or antiferroelectric material as described above with reference to FIGS. 3A to 3C, the internal arrangement structure may be different. can

10 is a cross-sectional view illustrating a semiconductor device according to example embodiments. FIG. 10 shows a cross section corresponding to the right side of FIG. 2 .

Referring to FIG. 10 , in the semiconductor device 100b, the first to third channel layers 141b, 142b, and 143b constituting the channel structure 140b are formed in the y direction, which is the extending direction of the gate electrode 175. The first to third widths L1, L2, and L3 may be different from each other. Accordingly, in the dielectric layers 160b, the first to third dielectric layers 161b, 162b, and 163b may also have different widths. In this embodiment, the first to third dielectric layers 161b, 162b, and 163b may have different thicknesses and different widths.

The first channel layer 141b may have a first width L1, the second channel layer 142b may have a second width L2 smaller than the first width L1, and the third channel layer 142b may have a second width L2 smaller than the first width L1. (143b) may have a third width (L3) smaller than the second width (L2). The active region 105 is illustrated as having substantially the same width as the first width L1, but is not limited thereto. The first to third dielectric layers 161b, 162b, and 163b surrounding the first to third channel layers 141b, 142b, and 143b, respectively, may also have sequentially decreasing widths. The fourth dielectric layer 167b may have the same thickness as the first dielectric layer 161b, but is not limited thereto. However, in exemplary embodiments, the levels of the channel layer and the dielectric layer having the smallest width and the largest width may be variously changed. For example, in some embodiments, the third channel layer 143b may have the largest width.

Since the first to third channel layers 141b, 142b, and 143b have different widths, the device including each of the first to third channel layers 141b, 142b, and 143b may be in a turn-on state. In this case, the difference in current amount further increases according to the turned-on channel layer, so that the read operation described above with reference to FIG. 8 can be more easily performed.

11A and 11B are cross-sectional views illustrating a semiconductor device according to example embodiments. 11A and 11B each show a cross section corresponding to the right side of FIG. 2 .

Referring to FIG. 11A , the semiconductor device 100c may further include a channel separator 210 unlike the embodiment of FIG. 2 . The channel separator 210 may pass through the channel structure 140c in the z direction, which is a direction perpendicular to the upper surface of the substrate 101 , to divide the channel structure 140c and the dielectric layers 160c in the y direction. The channel separator 210 may include an insulating material.

The channel structure 140c includes the first layer 141_1 and the second layer 141_2 of the first channel layers 141_1 and 141_2 disposed on the same level, and the second channel layers disposed on the same level. It includes the first layer 142_1 and the second layer 142_2 of (142_1 and 142_2), and the first layer 143_1 and the second layer of the third channel layers 143_1 and 143_2 disposed on the same level ( 143_2) may be included. The first layers 141_1, 142_1, and 143_1 and the second layers 141_2, 142_2, and 143_2 may have different widths in the y direction. The first layers 141_1, 142_1, and 143_1 may have a fourth width L4, and the second layers 141_2, 142_2, and 143_2 may have a fifth width L5 greater than the fourth width L4. Relative sizes of the fourth width L4 and the fifth width L5 may be variously changed in embodiments. In some embodiments, the fourth width L4 and the fifth width L5 may be equal to each other.

One side surfaces of the dielectric layers 160c in the y direction may contact the channel separator 210 . In the dielectric layers 160c, the first to sixth dielectric layers 161_1, 161_2, 162_1, 162_2, 163_1, and 163_2 surrounding the six channel layers 141_1, 141_2, 142_1, 142_2, 143_1, and 143_2, respectively, are connected to each other. Different first to sixth thicknesses T1c, T2c, T3c, T4c, T5c, and T6c may be provided. Accordingly, the first to sixth dielectric layers 161_1 , 161_2 , 162_1 , 162_2 , 163_1 , and 163_2 may have different coherent voltages. In the first to sixth thicknesses T1c, T2c, T3c, T4c, T5c, and T6c, the size may sequentially increase from the first thickness T1c to the sixth thickness T6c. However, in exemplary embodiments, the order of increase and decrease and the relative thickness of the first to sixth thicknesses T1c, T2c, T3c, T4c, T5c, and T6c may be variously changed.

Referring to FIG. 11B , unlike the embodiment of FIG. 11A , the semiconductor device 100d further includes a gate separator 220 connected to the channel separator 210 and dividing the gate electrode 175 in the y direction. can include Accordingly, different electrical signals may be applied to the gate electrodes 175 divided along the y direction.

For the channel structure 140c and the dielectric layers 160c, the above description with reference to FIG. 11A may be equally applied. However, in some embodiments, unlike the embodiment of FIG. 11A , the dielectric layers surrounding the channel layers 141_1 , 141_2 , 142_1 , 142_2 , 143_1 , and 143_2 disposed on the same level are mutually related to each other. They may have the same thickness. For example, the first dielectric layer 161_1 and the second dielectric layer 161_2 have the same thickness, the third dielectric layer 162_1 and the fourth dielectric layer 162_2 have the same thickness, and the fifth dielectric layer 163_1 and the second dielectric layer 163_1 have the same thickness. Six dielectric layers 163_2 may have the same thickness. In embodiments, the first dielectric layer 161_1, the third dielectric layer 162_1, and the fifth dielectric layer 163_1 disposed to overlap in the z direction have different thicknesses, and the second dielectric layer 161_2 and the fourth dielectric layer ( 162_2) and the sixth dielectric layer 163_2 have different thicknesses, the thicknesses of the dielectric layers 160c may be variously changed.

12A and 12B are cross-sectional views illustrating a semiconductor device according to example embodiments. 12A and 12B respectively show cross sections corresponding to the right side of FIG. 2 .

Referring to FIG. 12A , in the semiconductor device 100e, the channel structure 140e includes first to fourth channel layers 141 , 142 , 143 , and 144 , and the dielectric layers 160e include first to fourth channel layers 140e. Five dielectric layers 161, 162, 163, 167, and 164 may be included. The fifth dielectric layer 164 may be disposed to surround the fourth channel layer 144 and may have a thickness T7 different from the first to third thicknesses T1 , T2 , and T3 of the third dielectric layer 163 . there is. For example, the thickness T7 of the third dielectric layer 163 may be greater than the third thickness T3, but is not limited thereto. The first to third dielectric layers 161 , 162 , and 163 and the fifth dielectric layer 164 may have different coherent voltages.

As such, in embodiments, the number of channel layers constituting the channel structure 140e may be variously changed, and accordingly, the number of dielectric layers surrounding the channel layers may also be variously changed. For example, according to the semiconductor device 100e of the present embodiment, similarly to that described above with reference to FIGS. 6 to 8 , a Quad Level Cell (QLC) may be implemented and a maximum of 4 bits may be stored.

Referring to FIG. 12B , in the semiconductor device 100f, the first to third channel layers 141f, 142f, and 143f constituting the channel structure 140f include nanowires NW having a relatively small length in the y direction. ) may be included, respectively. Accordingly, each of the first to third channel layers 141f, 142f, and 143f may include a plurality of, for example, three nanowires NW. However, the number of nanowires NW disposed on the same level and the number of nanowires NW disposed along the z direction may be variously changed in embodiments.

The dielectric layers 160f may include first to ninth dielectric layers 161_1 , 161_2 , 161_3 , 162_1 , 162_2 , 162_3 , 163_1 , 163_2 , and 163_3 surrounding each of the nanowires NW. The first to ninth dielectric layers 161_1, 161_2, 161_3, 162_1, 162_2, 162_3, 163_1, 163_2, and 163_3 may have different coherent voltages. For example, as in the present embodiment, the first to ninth dielectric layers 161_1, 161_2, 161_3, 162_1, 162_2, 162_3, 163_1, 163_2, and 163_3 may have different thicknesses.

13A to 13E are views illustrating a process sequence to describe a method of manufacturing a semiconductor device according to example embodiments. 13A to 13E describe an embodiment of a manufacturing method for manufacturing the semiconductor device of FIGS. 1 and 2 , and each shows a cross section corresponding to FIG. 2 .

Referring to FIG. 13A , an active structure including sacrificial layers 120 and first to third channel layers 141 , 142 , and 143 alternately stacked on a substrate 101 and an active region 105 . can form

The sacrificial layers 120 may be replaced with the dielectric layers 160 and the gate electrode 175 through subsequent processes, as shown in FIG. 2 . The sacrificial layers 120 may be formed of a material having etch selectivity with respect to the first to third channel layers 141 , 142 , and 143 . The first to third channel layers 141 , 142 , and 143 may include a material different from that of the sacrificial layers 120 . The sacrificial layers 120 and the first to third channel layers 141, 142, and 143 may include, for example, a semiconductor including at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge). It includes materials, but may include different materials, and may or may not include impurities. For example, the sacrificial layers 120 may include silicon germanium (SiGe), and the first to third channel layers 141 , 142 , and 143 may include silicon (Si).

The sacrificial layers 120 and the first to third channel layers 141 , 142 , and 143 may be formed by performing an epitaxial growth process on the substrate 101 . The number of layers of the channel layers 141 , 142 , and 143 alternately stacked with the sacrificial layers 120 may be variously changed in embodiments.

Next, the active structure may be formed by patterning the sacrificial layers 120 , the first to third channel layers 141 , 142 , and 143 , and an upper region of the substrate 101 . The active structure may include sacrificial layers 120 and first to third channel layers 141, 142, and 143 that are alternately stacked with each other, and a portion of the substrate 101 is removed to protrude upward. Formed active regions 105) may be further included. The active structure may be formed in a line shape extending in one direction, for example, the x direction. Depending on the aspect ratio, the side surfaces of the active structure may have an inclined shape such that the width increases while facing downward.

In the region where a portion of the substrate 101 is removed, the device isolation layer 110 may be formed by burying the insulating material and then partially removing the insulating material so that the active region 105 protrudes. A top surface of the device isolation layer 110 may be formed lower than a top surface of the active region 105 .

Referring to FIG. 13B , a sacrificial gate structure 200 and gate spacer layers 172c may be formed on the active structure.

The sacrificial gate structure 200 may be a sacrificial structure formed in a region where the dielectric layer 160 and the gate electrode 175 on the channel structure 140 are disposed through a subsequent process, as shown in FIG. 2 . The sacrificial gate structure 200 may have a line shape extending in one direction crossing the active structure. The sacrificial gate structure 200 may extend in the y direction, for example.

The sacrificial gate structure 200 may include first and second sacrificial gate layers 202 and 205 and a mask pattern layer 206 that are sequentially stacked. The first and second sacrificial gate layers 202 and 205 may be patterned using the mask pattern layer 206 . The first and second sacrificial gate layers 202 and 205 may be an insulating layer and a conductive layer, respectively, but are not limited thereto. In some embodiments, the first and second sacrificial gate layers 202 and 205 may be formed of one layer. For example, the first sacrificial gate layer 202 may include silicon oxide, and the second sacrificial gate layer 205 may include polysilicon. The mask pattern layer 206 may include silicon oxide and/or silicon nitride.

Gate spacer layers 172 may be formed on both sidewalls of the sacrificial gate structure 200 . The gate spacer layers 172 may be made of a low-k material, and may include, for example, at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

Referring to FIG. 13C , recess regions are formed by partially removing the sacrificial layers 120 and the first to third channel layers 141, 142, and 143 exposed by the sacrificial gate structure 200, and Source/drain regions 150 may be formed in the recess regions.

First, portions of the exposed sacrificial layers 120 and the first to third channel layers 141, 142, and 143 are removed by using the sacrificial gate structure 200 and the gate spacer layers 172 as a mask. Thus, the recess regions may be formed. Accordingly, the first to third channel layers 141 , 142 , and 143 may form a channel structure 140 having a limited length along the x direction.

Next, some of the sacrificial layers 120 may be removed from the side surfaces, and internal spacer layers 130 may be formed. The sacrificial layers 120 may be selectively etched with respect to the channel structure 140 by, for example, a wet etching process, and may be removed to a predetermined depth from a side surface along the x direction. The sacrificial layers 120 may have side surfaces that are concave inward due to side etching as described above. However, the specific shape of the side surfaces of the sacrificial layers 120 is not limited to that shown in FIG. 13C. The inner spacer layers 130 may be formed by filling an insulating material in a region from which the sacrificial layers 120 are removed and removing the insulating material deposited on the outside of the channel structure 140 . The inner spacer layers 130 may be formed of the same material as the gate spacer layers 172, but are not limited thereto. For example, the inner spacer layers 130 may include at least one of SiN, SiCN, SiOCN, SiBCN, and SiBN.

Next, the source/drain regions 150 may be grown and formed from side surfaces of the active regions 105 and the channel structure 140 by, for example, a selective epitaxial process. The source/drain regions 150 may include impurities by in-situ doping, and may include a plurality of layers having different doping elements and/or doping concentrations.

Referring to FIG. 13D , an upper gap region UR and lower gap regions LR may be formed by forming an interlayer insulating layer 190 and removing the sacrificial gate structure 200 and the sacrificial layers 120. there is.

The interlayer insulating layer 190 may be formed by forming an insulating film covering the sacrificial gate structure 200 and the source/drain regions 150 and performing a planarization process to expose the mask pattern layer 206 .

The sacrificial gate structure 200 may be selectively removed with respect to the gate spacer layers 172 , the interlayer insulating layer 190 , the channel structure 140 , and the internal spacer layers 130 . Next, the sacrificial layers 120 may be selectively removed from side surfaces along the y direction of the sacrificial layers 120 exposed through the upper gap region UR. In this step, since the sacrificial layers 120 include a material different from that of the channel structure 140 , they may be selectively removed with respect to the channel structure 140 by a wet etching process.

Referring to FIG. 13E , dielectric layers 160 may be formed in the upper gap region UR and the lower gap regions LR.

The dielectric layers 160 may be formed to surround the first to third channel layers 141 , 142 , and 143 with different thicknesses. For example, after forming the first and fourth dielectric layers 161 and 167 to surround the first to third channel layers 141, 142 and 143, a mask layer or a sacrificial layer is formed to form the first And it may cover the fourth dielectric layers 161 and 167 . Next, a dielectric material may be further formed in the exposed region to have a thickness of the second dielectric layer 162 , and then a mask layer or a sacrificial layer may be formed to cover the second dielectric layer 162 . Next, the first to fourth dielectric layers 161 , 162 , 163 , and 167 may be formed by further forming a dielectric material in the exposed region to have a thickness of the third dielectric layer 163 . However, a method of forming the dielectric layers 160 to have different thicknesses is not limited thereto.

Next, referring to FIG. 2 together, a gate electrode 175 may be formed to form a gate structure GS and contact plugs 180 may be formed.

The gate electrode 175 may be formed to completely fill the upper gap region UR and the lower gap regions LR. Accordingly, a gate structure GS including the gate spacer layers 172 , the dielectric layers 160 , and the gate electrode 175 may be formed.

Next, contact holes exposing the source/drain regions 150 may be formed in the interlayer insulating layer 190 , and contact plugs 180 may be formed by filling the contact holes with a conductive material. Although not shown, wiring structures connected to the contact plugs 180 may be further formed on the contact plugs 180 . As a result, the semiconductor device 100 of FIG. 2 can be manufactured.

The present invention is not limited by the above-described embodiments and accompanying drawings, but is intended to be limited by the appended claims. Therefore, various forms of substitution, modification and change will be possible by those skilled in the art within the scope of the technical spirit of the present invention described in the claims, and this also falls within the scope of the present invention. something to do.

101: substrate 105: active layer
110: device isolation layer 120: sacrificial layer
130: inner spacer layer 140: channel structure
150: source/drain region 160: dielectric layer
172: gate spacer layer 175: gate electrode
180: contact plug 190: interlayer insulating layer

Claims (10)

a substrate including an active region extending in a first direction;
a gate electrode extending in a second direction crossing the active region on the substrate;
a plurality of channel layers disposed on the active region and spaced apart from each other along a third direction perpendicular to the top surface of the substrate and surrounded by the gate electrode;
a plurality of dielectric layers disposed between the plurality of channel layers and the gate electrode and including a ferroelectric material or an anti-ferroelectric material; and
A source/drain region disposed in recess regions in which the active region is recessed at both sides of the gate electrode and in contact with the plurality of channel layers;
The semiconductor device of claim 1 , wherein the plurality of dielectric layers have different coercive voltages.
According to claim 1,
The semiconductor device of claim 1 , wherein the plurality of dielectric layers have different thicknesses.
According to claim 1,
The semiconductor device of claim 1 , wherein the plurality of dielectric layers include ferroelectric materials having different coercive fields.
According to claim 1,
The plurality of dielectric layers are composed of hafnium (Hf), zirconium (Zr), silicon (Si), yttrium (Y), aluminum (Al), gadolinium (Gd), strontium (Sr), lanthanum (La), scandium (Sc) , and at least one of oxides thereof.
According to claim 1,
Each of the plurality of dielectric layers includes first and second layers sequentially stacked from the plurality of channel layers,
The semiconductor device of claim 1 , wherein the first layer does not include a ferroelectric material, and the second layer includes a ferroelectric material.
According to claim 1,
and a channel separation portion passing through the plurality of channel layers along the third direction and dividing the plurality of channel layers into first and second layers, respectively, in the second direction.
a substrate including an active region extending in a first direction;
a gate electrode extending in a second direction crossing the active region on the substrate;
first to third channel layers spaced apart from each other in a third direction perpendicular to the top surface of the substrate, sequentially disposed from the active region, and surrounded by the gate electrode;
First to third dielectric layers surrounding the first to third channel layers and sequentially disposed along the third direction from the active region, and including a ferroelectric material or an anti-ferroelectric material. ; and
It is disposed in recess regions where the active region is recessed at both sides of the gate electrode, and includes source/drain regions in contact with the first to third channel layers,
The semiconductor device of claim 1 , wherein the first to third dielectric layers have different thicknesses.
According to claim 7,
Each of the first to third dielectric layers has a thickness in the range of 1 nm to 30 nm.
a memory cell array in which a plurality of memory elements are disposed; and
a peripheral circuit area including peripheral circuits for controlling the memory cell array;
Each of the plurality of memory elements,
an active region extending in a first direction;
a gate electrode extending in a second direction crossing the active region;
a plurality of channel layers disposed on the active region and spaced apart from each other along a third direction perpendicular to a top surface of the active region and surrounded by the gate electrode; and
a plurality of dielectric layers disposed between the plurality of channel layers and the gate electrode and including a ferroelectric material or an anti-ferroelectric material;
In each of the plurality of memory elements, the number of the plurality of channel layers is N (N is a natural number equal to or greater than 2), and each of the plurality of memory elements stores data of N bits or less.
According to claim 9,
In a program operation of writing first data into a selected memory element among the plurality of memory elements, the peripheral circuit region applies a first program voltage and a second program voltage having different codes to the gate electrode of the selected memory element. A semiconductor device that inputs sequentially.

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