KR20230127839A - Method and apparatus for synchronizing singnal of signal measuring devices - Google Patents

Abstract

A method and apparatus for synchronizing signals of signal measuring devices are disclosed. A signal synchronization method according to an embodiment of the present disclosure includes receiving a reference time and performing time synchronization with the reference time; calculating a clock frequency of a system clock based on the reference time; and generating a sampling clock using the calculated clock frequency of the system clock and a preset sampling frequency.

Description

Signal synchronization method and device of signal measuring devices {METHOD AND APPARATUS FOR SYNCHRONIZING SINGNAL OF SIGNAL MEASURING DEVICES}

The present disclosure relates to a signal synchronization method and apparatus, and more particularly, to a method and apparatus for synchronizing signals of a plurality of independent signal measurement devices.

Various signal measurement devices including smart phones and smart watches are widely used in our daily life. It is increasingly necessary to integrate and process multiple signals measured simultaneously from multiple independent devices. As a typical example, a camera and a microphone are measured in a broadcast. Due to environmental constraints and signal quality, it is necessary to measure video and audio signals from multiple independent cameras and microphones rather than from one device. Since signals measured in independent devices are not synchronized by default, additional post-processing synchronization It needs work.

The reason that signals measured from independent devices are not synchronized is because the independent devices operate with independent system clocks, so each device has a different recognition time. Even if the devices are manufactured through the same process, the frequency of the system clock is different for each device, and even if the difference in frequency is slight, it causes a very large difference when the signal measurement time becomes long. It is the same reason that an accurate digital clock cannot be driven without a periodic satellite reception time synchronization process.

An object of the present disclosure is to provide a method and apparatus for synchronizing signals of a plurality of independent signal measuring devices.

The technical problems to be achieved in the present disclosure are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the description below. You will be able to.

According to embodiments of the present disclosure, a method and apparatus for synchronizing signals of signal measurement devices are disclosed. A signal synchronization method according to an embodiment of the present disclosure includes receiving a reference time and performing time synchronization with the reference time; calculating a clock frequency of a system clock based on the reference time; and generating a sampling clock using the calculated clock frequency of the system clock and a preset sampling frequency.

Furthermore, the signal synchronization method according to an embodiment of the present disclosure may further include synchronizing a phase of the generated sampling clock at a preset phase synchronization time point.

In this case, the step of synchronizing the phase of the sampling clock may receive the phase synchronization time point from the master device providing the reference time, and synchronize the phase of the sampling clock at the received phase synchronization time point.

At this time, in the step of synchronizing the phases of the sampling clocks, the phases of the sampling clocks may be synchronized after resetting a counter generating the sampling clocks at the phase synchronization time point.

At this time, the step of performing the time synchronization may perform the time synchronization by receiving the time of the master device as the reference time from the master device.

In this case, the step of calculating the clock frequency of the system clock may include calculating the number of clocks of the system clock in the unit time based on a preset unit time, and using the calculated number of clocks to calculate the clock frequency of the system clock. can be calculated.

A signal synchronization device according to another embodiment of the present disclosure includes a communication unit; and a control unit, wherein the control unit performs time synchronization with a reference time received through the communication unit, calculates a clock frequency of a system clock based on the reference time, and matches the clock frequency of the calculated system clock in advance. It is characterized in that a sampling clock is generated using a set sampling frequency.

A signal synchronization system according to another embodiment of the present disclosure includes a master device providing a reference time; and a plurality of slave devices, wherein each of the slave devices performs time synchronization with a reference time received from the master device, calculates a clock frequency of a system clock based on the reference time, and calculates a clock frequency of a system clock based on the reference time. It is characterized in that the sampling clock is generated using the clock frequency of the clock and a preset sampling frequency.

The features briefly summarized above with respect to the disclosure are merely exemplary aspects of the detailed description of the disclosure that follows, and do not limit the scope of the disclosure.

According to the present disclosure, a method and apparatus for synchronizing signals of a plurality of independent signal measuring devices may be provided.

Effects obtainable in the present disclosure are not limited to the effects mentioned above, and other effects not mentioned may be clearly understood by those skilled in the art from the description below. will be.

1 shows an example of clock frequency synchronization and phase synchronization.
2 shows an example of signal sampling synchronization and sampling clock synchronization.
3 shows the structure of a signal synchronization system according to an embodiment of the present disclosure.
4 shows the configuration of a signal synchronizing device according to another embodiment of the present disclosure.
FIG. 5 is an exemplary diagram for explaining the operation of the signal synchronizing device of FIG. 4 .
6 is an operation flowchart of a signal synchronization method according to another embodiment of the present disclosure.
7 is a block diagram of a device to which a signal synchronization apparatus according to another embodiment of the present disclosure is applied.

Hereinafter, with reference to the accompanying drawings, embodiments of the present disclosure will be described in detail so that those skilled in the art can easily implement the present disclosure. However, this disclosure may be embodied in many different forms and is not limited to the embodiments set forth herein.

In describing the embodiments of the present disclosure, if it is determined that a detailed description of a known configuration or function may obscure the gist of the present disclosure, a detailed description thereof will be omitted. And, in the drawings, parts irrelevant to the description of the present disclosure are omitted, and similar reference numerals are attached to similar parts.

In the present disclosure, when a component is said to be "connected", "coupled" or "connected" to another component, this is not only a direct connection relationship, but also an indirect connection relationship where another component exists in the middle. may also be included. In addition, when a component "includes" or "has" another component, this means that it may further include another component without excluding other components unless otherwise stated. .

In the present disclosure, terms such as first and second are used only for the purpose of distinguishing one element from another, and do not limit the order or importance of elements unless otherwise specified. Accordingly, within the scope of the present disclosure, a first component in one embodiment may be referred to as a second component in another embodiment, and similarly, a second component in one embodiment may be referred to as a first component in another embodiment. can also be called

In the present disclosure, elements that are distinguished from each other are only for clearly describing each characteristic, and do not necessarily mean that the elements are separated. That is, a plurality of components may be integrated to form a single hardware or software unit, or a single component may be distributed to form a plurality of hardware or software units. Accordingly, even such integrated or distributed embodiments are included in the scope of the present disclosure, even if not mentioned separately.

In the present disclosure, components described in various embodiments do not necessarily mean essential components, and some may be optional components. Accordingly, an embodiment comprising a subset of elements described in one embodiment is also included in the scope of the present disclosure. In addition, embodiments including other components in addition to the components described in various embodiments are also included in the scope of the present disclosure.

In the present disclosure, expressions of positional relationships used in this specification, such as upper, lower, left, right, etc., are described for convenience of description, and when viewing the drawings shown in this specification in reverse, the positions described in the specification Relationships can also be interpreted in reverse.

In the present disclosure, "A or B", "at least one of A and B", "at least one of A or B", "A, B or C", "at least one of A, B and C", and " Each of the phrases such as “at least one of A, B, or C” may include any one of the items listed together in that phrase, or all possible combinations thereof.

Basically, the clock synchronization process may consist of frequency synchronization (a) and phase synchronization (b) as shown in FIG. 1 . You cannot control the system clock, but you can control the clock used for signal sampling. Here, signal synchronization and sampling clock synchronization are different concepts as shown in FIG. 2 .

In the signal sampling process, a low frequency sampling clock desired to be measured is created using a counter to a high frequency system clock, and the signal is sampled according to the corresponding clock. Usually, an MCU can control a precise period by incorporating a plurality of prescaler counters. For example, the ARM cortex M series generates a sampling clock according to a desired sampling frequency through a 16 bit prescaler counter and a 32 bit auto-reload counter.

Since the desired sampling frequency may be different for each signal measurement device, synchronization of a sampling clock and synchronization of signal sampling are not the same. For example, when the desired sampling frequencies of audio and video are 20,000 Hz and 60 Hz, respectively, if the actual sampling clock frequencies are 20,200 Hz and 60.6 Hz, respectively, it can be said that the clocks are not synchronized but the signal sampling is synchronized. Synchronization of signal sampling between independent devices means that the measurement point and measurement time are the same between each device.

Synchronization is becoming an important issue in various fields. In media video production, an error of several ms is not perceived by the viewer, but an error of tens to hundreds of ms is perceptible to the viewer. For multi-biometric signal measurement, for example, the p300 of brain waves and the pulse transit time for blood pressure estimation, an error of several ms does not cause a big problem in multi-biometric signal analysis, but an error of tens to hundreds of ms This can cause significant errors in signal analysis. In real applications, synchronization errors within a few milliseconds are acceptable.

Synchronization of signals measured in existing independent devices (or apparatuses) undergoes additional synchronization work by catching a slate at an edit point (measurement point and time), for example, in movies and broadcasts. Since the audio signal can be resampled through interpolation, synchronization can be performed very simply if the edit point is accurately known. At this time. Resampling is not resampling the original signal, but a process of estimating a synchronized signal. In other words, it can be seen that the accuracy of the resampled signal is degraded even by a slight difference. In addition, since additional batch processing synchronization work is required, the efficiency is lowered and utilization in real-time applications is difficult.

Various techniques for synchronizing time between devices have been proposed. Typically, in the case of the precision time protocol (IEEE 1599), it is a technology for synchronizing time between a master device and a slave device. This technology enables precise time synchronization with an error of less than ms at the time of synchronization, but cannot perform signal sampling synchronization performed for a long time.

Another prior art shared a sampling clock or trigger as a method for synchronizing sampling. This clock or trigger sharing method is difficult to apply when the desired sampling frequencies are different between devices, and it is difficult to share the exact sampling clock and trigger due to propagation delay in wired communication and latency in wireless communication. There is also a problem. Even if the trigger signal is accurate, the constant sampling clock or trigger sharing is very redundant. The problem of such inaccuracy and low efficiency increases as the communication distance increases from wired to wireless and even wirelessly.

Embodiments of the present disclosure are intended to perform signal synchronization, for example, signal sampling synchronization, of independent devices without a separate post-processing process.

In this case, the embodiments of the present disclosure may synchronize signals between a plurality of independent devices by controlling a counter that creates a sampling clock of the independent devices.

In embodiments of the present disclosure, signal sampling synchronization devices may be divided into a master device (or device) issuing a command and a plurality of slave devices performing synchronization according to a command.

Figure 3 shows the structure of a signal synchronization system according to an embodiment of the present disclosure, showing the structure for the case where the master device is not equipped with a GNSS receiver (a) and the case where the GNSS receiver is provided (b).

As shown in FIG. 3, the signal synchronization system according to an embodiment of the present disclosure includes a master device (Master) and a plurality of slave devices (Slave 1, ..., Slave N), and includes a satellite navigation system (GNSS; Global Navigation Satellite Systems) performs time synchronization and signal sampling synchronization according to whether the receiver is installed, that is, whether satellite reception time is available.

In synchronization, as shown in FIG. 3A, the master device uses the system clock time of the master device itself as the reference time of the signal synchronization system when satellite reception time cannot be used, such as when a GNSS receiver is not equipped. As shown in FIG. 3B, when a GNSS receiver is provided, the satellite reception time of the GNSS receiver can be used as the reference time of the signal synchronization system. If both the master and slave devices are equipped with GNSS receivers, the signal sampling synchronization process can be performed based on the satellite reception time of the GNSS receiver without a separate time synchronization process. perform synchronization. In this case, time synchronization may use a precision time protocol (PTP) (IEEE 1599).

That is, the time synchronization system according to an embodiment of the present disclosure may synchronize the time of each slave device with the time of the system clock of the master device in order to use the time of the system clock of the master device as a reference time. Of course, as described above, the master device may or may not have a GNSS receiver, and the system clock of the master device may be used as the reference time regardless of whether or not the GNSS receiver is used. Even if the slave device has a GNSS receiver, the slave device can use the time of the master device as a reference time through time synchronization with the system clock of the master device.

The master device in an embodiment of the present disclosure may be a device that measures a signal by synchronizing a signal with slave devices, and performs phase synchronization of the sampling clock of the slave devices with the reference time of the slave devices. It may also be a control device that provides information on synchronization timing. Of course, the master device is not limited or limited to a device that performs the above functions, and may include all types of devices applicable to the method, device, and system of the present disclosure.

Each of the slave devices (Slave 1, ..., Slave N) calculates the clock frequency of the system clock using the reference time by time synchronization with the master device, and uses the clock frequency of the calculated system clock to calculate the clock frequency of the slave devices. After generating a sampling clock of a desired sampling frequency in each, phase synchronization of the generated sampling clock may be performed at a phase synchronization time point.

Accordingly, each of the slave devices can synchronize the sampling clock with another device without a separate post-processing process by accurately generating a sampling clock of a desired sampling frequency and synchronizing the phase of the sampling clock at a phase synchronization time point.

This signal synchronization device will be described with reference to FIGS. 4 and 5 .

4 shows a configuration of a signal synchronizing device according to another embodiment of the present disclosure, and shows a configuration for a master device or a slave device. Here, it is assumed that the configuration of the signal synchronizing device of the slave device is shown.

Referring to FIG. 4 , a signal synchronization apparatus 400 according to another embodiment of the present disclosure includes a communication unit 410, a counter 420, and a control unit 430. Of course, the master device or the slave device may include not only configuration means constituting the signal synchronizing device but also all configuration means necessary for the corresponding device, for example, configuration means for a memory, an interface device, and the like.

The communication unit 410 is a configuration means for communicating with the master device, to perform time synchronization with the system clock of the master device, to receive the system clock of the master device as a reference time, and to synchronize the phase of the sampling clock. Phase synchronization timing reservation information is received. Of course, when a signal synchronization device is provided in the master device, the communication unit 410 may communicate with each slave device.

Depending on the embodiment, the communication unit 410 receives the satellite reception time of the GNSS receiver when the master device is equipped with a GNSS receiver, or receives information about the time of the system clock of the master device when the master device does not have a GNSS receiver. there is.

The counter 420 generates a sampling clock corresponding to a desired sampling frequency using the system clock of the slave device under the control of the controller 430 .

The control unit 430 performs time synchronization with the master device with the reference time received through the communication unit 410, calculates the clock frequency of the system clock based on the reference time, and sets the clock frequency of the calculated system clock in advance. By controlling the counter 420 using a desired sampling frequency, control is performed to generate a sampling clock corresponding to the desired sampling frequency.

At this time, the control unit 430 calculates the clock number of the system clock in unit time based on a preset unit time, for example, 1 second, and uses the calculated number of clocks to clearly determine the clock frequency of the system clock. can be calculated That is, the controller 430 can clearly calibrate an error in the system clock frequency that may occur depending on the product through the calculation of the clock frequency using the number of clocks of the system clock in unit time. Accordingly, the control unit 430 can remove a sampling clock error that may occur due to an error in the system clock frequency, thereby generating a sampling clock corresponding to a desired sampling frequency.

Furthermore, the control unit 430 controls to synchronize the phase of the sampling clock at the phase synchronization time point according to the phase synchronization time point reservation information received from the master device through the communication unit 410.

At this time, the controller 430 may synchronize the phase of the sampling clock with other slave devices as well as the master device by resetting the counter 420 at the phase synchronization time point and then synchronizing the phase of the sampling clock.

The operation of the signal synchronizing device 400 will be described in more detail with reference to FIG. 5 .

Figure 5 shows an exemplary diagram for explaining the operation of the signal synchronizing device of FIG. 4, Figure 5a shows an exemplary diagram for explaining a frequency synchronization process, Figure 5b is an exemplary diagram for explaining a phase synchronization process it is shown

If the signal sampling synchronization process is composed of a frequency synchronization process and a phase synchronization process, the frequency synchronization process will be described with reference to FIG. 5A as follows.

As shown in Figure 5a, the frequency synchronization process, a. Time synchronization is performed twice at two different time points, for example, a start time and an end time of a preset unit time, and b. Between the two synchronization points, the number of system clocks is calculated and the clock frequency of the actual system is calculated. That is, the control unit calculates the clock frequency of the actual system by calculating the number of system clocks within a unit time through time synchronization twice. and, c. A sampling clock corresponding to a desired sampling frequency is generated by finely adjusting the system clock counter and the sampling clock counter from the clock frequency of the system.

When both the master device and the slave device have built-in GNSS receivers, frequency synchronization can be performed using a pulse per second (PSS) signal without a separate time synchronization process. In this case, the interval between synchronization points may be a preset time, for example, 1 second. Conversely, since the system time of the master device is the basis for synchronization when there is no GNSS receiver, in the case of the master device, steps b and c, which are subsequent frequency synchronization processes, are not required, except for the time synchronization process, which is process a, above. can

The phase synchronization process will be described with reference to FIG. 5B.

As shown in Figure 5b, the phase synchronization process, i. Through communication between the master device and the slave device, the phase synchronization point is reserved. Here, for recognizing the synchronization point after reservation, the satellite reception time or the system clock of each device may be used. ii. Each device, for example, a master device and each of a plurality of slave devices may perform a phase synchronization process for a sampling clock by generating a sampling clock after resetting a counter for a sampling clock at a phase synchronization time point.

Due to transmission delay and latency of communication, since the master device cannot know when to synchronize with the slave device, individual devices proceed with their own phase synchronization process after reserving the phase synchronization point. If the phase synchronization is performed in this way, there is an advantage in that the distance between the synchronizing devices is free because it is not affected by transmission delay and latency of communication. Here, the phase synchronization process may be performed together with a signal measurement start command.

Since the sampling clock is controlled according to the synchronized reference time, synchronization is possible even if the desired sampling frequencies of the two devices are different, for example, 20,000 Hz and 60 Hz. Fine tuning of the counter can be controlled by selecting a prescaler counter and changing the value of the auto-reload register. Although the phase synchronization of the two devices has been described here, it is not limited or limited thereto, and phase synchronization of a plurality of devices, for example, slave devices or a master device and a slave device, can be performed through the above process. .

Although, with respect to the above process, it has been described as being performed in the slave device, this process may also be performed in the master device. That is, the master device does not perform a time synchronization process, but calculates the system clock frequency, uses the calculated system clock frequency to generate a sampling clock of a desired sampling frequency, and converts the generated sampling clock to the sampling clock of the slave devices. A process for phase synchronization may be performed.

As such, the phase synchronization system or device according to embodiments of the present disclosure may perform signal synchronization of independent devices, for example, signal sampling synchronization, without a separate post-processing process.

In addition, since the phase synchronization system or device according to the embodiments of the present disclosure can utilize the satellite reception time information of the GNSS receiver, synchronization of the sampling frequency is possible without communication between the master device and the slave device, a single device It can also be used for the purpose of calibration of the sampling frequency of the signal sampling synchronization (e.g., precision time protocol (IEEE 1599)), the satellite reception time of the GNSS receiver, and the phase synchronization process are all devices may not be affected by the distance between them.

Conventional signal synchronization techniques used a method of synchronizing with post-processing after measuring a signal and a method of sharing a sampling clock. However, the method of synchronizing with post-processing after measuring a signal requires an inefficient post-processing process and shares a sampling clock. This method has a problem of continuously transmitting and receiving an unstable sampling clock. In particular, in the case of the method of sharing the sampling clock, when the sampling frequencies of the signals are different, for example, when the sampling frequencies are different, such as 20,000 Hz and 60 Hz, there is a problem in that it is difficult to perform synchronization. On the other hand, the phase synchronization system or device according to the embodiments of the present disclosure enables efficient and stable signal synchronization without inefficient post-processing and unstable clock sharing by sharing time information between independent terminals or devices, and also Synchronization can be performed without any problem even when the sampling frequencies of the are different, and it has a great advantage in that it is not affected by the distance between measurement devices. The above advantages of stability and efficiency show the difference more clearly in a wireless environment, and in addition, if all devices can receive satellite GNSS, very accurate synchronization can be performed.

6 is an operation flowchart of a method for synchronizing a signal according to another embodiment of the present disclosure, and is an operation flowchart in the apparatus of FIGS. 1 to 5 . Here, an operation flowchart in the slave device will be described.

Referring to FIG. 6, a signal synchronization method according to another embodiment of the present disclosure performs time synchronization using a reference time of a master device, and a system used in the corresponding device based on the reference time by the time synchronization. The clock frequency of the clock is calculated (S610, S620).

Here, step S610 can be omitted if both the master device and the slave device have GNSS receivers, and if the master device does not have a GNSS receiver or the slave device does not have a GNSS receiver, the corresponding process will be performed. can

The reference time in step S610 may mean the time of the system clock in the master device, and may be the satellite reception time when a GNSS receiver is provided.

The step S620 calculates or detects the number of clocks of the system clock of the corresponding device through two time synchronization processes at the start and end times of a preset time unit, for example, 1 second, and the number of clocks of the system clock in unit time. The clock frequency of the system clock can be calculated using

When the clock frequency of the system clock is calculated in step S620, a sampling clock having a desired sampling frequency is generated by controlling a counter using the calculated clock frequency of the system clock and a desired sampling frequency in the slave device (S630).

When the sampling clock of the desired sampling frequency is generated by step S630, phase synchronization of the sampling clock is performed at a preset phase synchronization time point, for example, a phase synchronization time point received from the master device (S640).

Here, step S640 resets the counter at the phase synchronization time and then synchronizes the phase of the sampling clock, thereby synchronizing the phase of the sampling clock with other slave devices as well as the master device.

Even if the description is omitted in the method of FIG. 6, the method according to the embodiment of the present disclosure may include all the contents described in the apparatus and system of FIGS. 1 to 5, which will be appreciated by those skilled in the art. self-evident

7 is a block diagram of a device to which a signal synchronization apparatus according to another embodiment of the present disclosure is applied.

For example, the signal synchronizing apparatus according to another embodiment of the present disclosure of FIG. 4 may be the device 1600 of FIG. 7 . Referring to FIG. 7 , a device 1600 may include a memory 1602 , a processor 1603 , a transceiver 1604 and a peripheral device 1601 . Also, as an example, the device 1600 may further include other configurations, and is not limited to the above-described embodiment. In this case, the device 1600 may be, for example, a fixed network management device (eg, a server, a PC, etc.).

More specifically, the device 1600 of FIG. 7 may be an exemplary hardware/software architecture such as a signal measuring device, an image capturing device, a voice recording device, and the like. At this time, for example, the memory 1602 may be a non-removable memory or a removable memory. Also, as an example, the peripheral device 1601 may include a display, GPS, or other peripheral devices, and is not limited to the above-described embodiment.

Also, as an example, the above-described device 1600 may include a communication circuit like the transceiver 1604, and based on this, communication with an external device may be performed.

Also, as an example, the processor 1603 may include a general purpose processor, a digital signal processor (DSP), a DSP core, a controller, a microcontroller, application specific integrated circuits (ASICs), field programmable gate array (FPGA) circuits, any other It may be at least one or more of a tangible integrated circuit (IC) and one or more microprocessors associated with a state machine. That is, it may be a hardware/software configuration that performs a control role for controlling the device 1600 described above. Also, the processor 1603 can perform the functions of the control unit 430 of FIG. 4 by modularizing them.

At this time, the processor 1603 may execute computer executable instructions stored in the memory 1602 to perform various essential functions of the signal synchronization device. For example, the processor 1603 may control at least one of signal coding, data processing, power control, input/output processing, and communication operations. Also, the processor 1603 may control a physical layer, a MAC layer, and an application layer. Also, as an example, the processor 1603 may perform authentication and security procedures in an access layer and/or an application layer, and is not limited to the above-described embodiment.

For example, the processor 1603 may communicate with other devices through the transceiver 1604 . For example, the processor 1603 may control the signal synchronization device to communicate with other devices through a network through execution of computer executable instructions. That is, the communication performed in the present disclosure can be controlled. For example, the transceiver 1604 may transmit an RF signal through an antenna and may transmit the signal based on various communication networks.

In addition, as an example, MIMO technology, beamforming, etc. may be applied as an antenna technology, and is not limited to the above-described embodiment. In addition, the signal transmitted and received through the transceiver 1604 may be modulated and demodulated and controlled by the processor 1603, and is not limited to the above-described embodiment.

Exemplary methods of this disclosure are presented as a series of operations for clarity of explanation, but this is not intended to limit the order in which steps are performed, and each step may be performed concurrently or in a different order, if desired. In order to implement the method according to the present disclosure, other steps may be included in addition to the exemplified steps, other steps may be included except for some steps, or additional other steps may be included except for some steps.

Various embodiments of the present disclosure are intended to explain representative aspects of the present disclosure, rather than listing all possible combinations, and matters described in various embodiments may be applied independently or in combination of two or more.

In addition, various embodiments of the present disclosure may be implemented by hardware, firmware, software, or a combination thereof. For hardware implementation, one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), It may be implemented by a processor (general processor), controller, microcontroller, microprocessor, or the like.

The scope of the present disclosure is software or machine-executable instructions (eg, operating systems, applications, firmware, programs, etc.) that cause operations according to methods of various embodiments to be executed on a device or computer, and such software or It includes a non-transitory computer-readable medium in which instructions and the like are stored and executable on a device or computer.

400 Signal Synchronizer
410 communications department
420 counter
430 Control

Claims (13)

receiving a reference time and performing time synchronization with the reference time;
calculating a clock frequency of a system clock based on the reference time; and
Generating a sampling clock using the calculated clock frequency of the system clock and a preset sampling frequency.
Including, signal synchronization method.
According to claim 1,
Synchronizing the phase of the generated sampling clock at a preset phase synchronization time point
Further comprising, signal synchronization method.
According to claim 2,
Synchronizing the phase of the sampling clock,
Signal synchronization method for receiving the phase synchronization time point from a master device providing the reference time, and synchronizing the phase of the sampling clock to the received phase synchronization time point.
According to claim 2,
Synchronizing the phase of the sampling clock,
Synchronizing the phase of the sampling clock after resetting the counter generating the sampling clock at the phase synchronization time point, signal synchronization method.
According to claim 1,
Performing the time synchronization,
Signal synchronization method for performing the time synchronization by receiving the time of the master device as the reference time from the master device.
According to claim 5,
Calculating the clock frequency of the system clock,
Based on a preset unit time, calculating the number of clocks of the system clock in the unit time, and calculating a clock frequency of the system clock using the calculated number of clocks.
communications department; and
control unit
including,
The control unit,
Time synchronization is performed with a reference time received through the communication unit, a clock frequency of a system clock is calculated based on the reference time, and a sampling clock is generated using the calculated clock frequency of the system clock and a preset sampling frequency. , a signal synchronizer.
According to claim 7,
The control unit,
Synchronizing the phase of the generated sampling clock at a preset phase synchronization time point, signal synchronizing device.
According to claim 8,
The control unit,
Signal synchronizing device for receiving the phase synchronization time point from a master device providing the reference time and synchronizing the phase of the sampling clock to the received phase synchronization time point.
According to claim 8,
The control unit,
Signal synchronizing apparatus for synchronizing the phase of the sampling clock after resetting the counter generating the sampling clock at the phase synchronization time point.
According to claim 7,
The control unit,
, Signal synchronization device for performing the time synchronization by receiving the time of the master device as the reference time from the master device.
According to claim 11,
The control unit,
Based on a preset unit time, calculates the number of clocks of the system clock in the unit time, and calculates a clock frequency of the system clock using the calculated number of clocks.
Master device providing reference time; and
multiple slave devices
including,
Each of the slave devices,
Time synchronization is performed with a reference time received from the master device, a clock frequency of the system clock is calculated based on the reference time, and a sampling clock is generated using the calculated clock frequency of the system clock and a preset sampling frequency. , a signal synchronization system.

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