KR20230123220A - Semiconductor wafer analysis apparatus and operating method semiconductor wafer analysis apparatus - Google Patents

Abstract

The semiconductor wafer analysis device includes a wafer map generation module, an information conversion module, a first clustering module, an overlapping map generation module, a second clustering module, and an evaluation module. The wafer map generating module generates wafer map information corresponding to a plurality of wafers. The information conversion module performs low-dimensional conversion of wafer map information. The first clustering module performs primary clustering on low-dimensional information to generate first grouping information. The overlapping map generation module generates overlapping map information by mapping the wafer map information to the first grouping information. The second clustering module performs secondary clustering on the overlapping map information to generate second grouping information. The evaluation module generates evaluation result information based on the second grouping information.

Description

Semiconductor wafer analysis device and operation method of semiconductor wafer analysis device

The present invention relates to a semiconductor wafer analysis device and a method of operating the semiconductor wafer analysis device, and more particularly, to semiconductor wafer analysis capable of analyzing types of defects occurring in a semiconductor integrated circuit, which is a chip manufactured on a semiconductor wafer, through a wafer map. It relates to an operating method of a device and a semiconductor wafer analysis device.

In general, a manufacturing process of a semiconductor integrated circuit is largely divided into a pre-process, a post-process, and a test process. The entire process is called a fabrication process, and is a process of forming patterns for each of a plurality of semiconductor integrated circuits on a wafer made of single crystal silicon. The post process is called an assembly process, and is a process of separating each of the semiconductor integrated circuits formed on the wafer into chips and forming a package to enable connection of external devices and electrical signals. The test process is a process of testing whether the product through the corresponding process is properly formed after the pre-fixing is completed and after the post-process is completed.

The entire process for semiconductor integrated circuits is a representative multi-step process, and is progressing from at least tens to hundreds of steps. The entire process of semiconductor integrated circuits is mainly processed in a high-temperature, high-pressure chamber on a wafer basis, and microfabrication processes are repeatedly performed in various chambers and under various environments. Representative process steps include a deposition process, an exposure process, an etching process, a diffusion process, an ion implantation process, and a thin film deposition process. In the semiconductor integrated circuit, active elements such as transistors and diodes are formed through various processes, and various conductive layers or insulating layers connecting these elements are formed.

The wafer after the entire process is subjected to various electrical test operations in units of chips corresponding to each semiconductor integrated circuit. As a result of the test operation, information on whether or not a defect is present for each chip formed on the wafer is detected. Also, the detected defect information is derived as a wafer map. This test operation targets a plurality of wafers, and a test performer can obtain a defect type for each of the plurality of wafers by analyzing a wafer map corresponding to each of the plurality of wafers.

Analyzing a wafer map to determine a defect type is one of the important techniques for increasing the yield of a semiconductor integrated circuit. In general, outer, central, radial, annular, and scratched types of defects are well known, and algorithms for detecting these types of defects are continuously being researched and developed. However, it is difficult to detect irregular defect types with existing algorithms for detecting standardized defect types, and previously developed methods for controlling atypical defects have limitations in practical use.

An embodiment of the present invention may provide a semiconductor wafer analysis device capable of analyzing not only standardized defect types but also non-standardized defect types through a wafer map and an operating method of the semiconductor wafer analysis device.

The problems of the present invention are not limited to those mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

According to one embodiment of the present invention, a wafer map generating module for generating wafer map information based on test result information corresponding to a plurality of wafers; an information conversion module generating low-dimensional information by performing low-dimensional conversion on defective elements included in the wafer map information; a first clustering module generating first grouping information by performing primary clustering on the low-dimensional information; an overlapping map generating module configured to generate overlapping map information by mapping the wafer map information to the first grouping information; a second clustering module generating second grouping information by comparing the overlapping map information with each other and performing secondary clustering; and an evaluation module configured to generate evaluation result information corresponding to a defect type of each of the plurality of wafers based on the second grouping information.

According to one embodiment of the present invention, generating wafer map information based on test result information corresponding to a plurality of wafers; low-dimensionally transforming defective elements included in the wafer map information; clustering the low-dimensional information generated in the low-dimensional transforming step; and evaluating a defect type of each of the plurality of wafers based on the output information of the clustering step.

An embodiment of the present invention has an effect of increasing the yield of semiconductor integrated circuits formed on a wafer by analyzing even irregular types of defects through a wafer map.

The effects of the present invention are not limited to those mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description below.

1 is a block diagram showing the configuration of a semiconductor wafer analysis system according to an embodiment of the present invention.
FIG. 2 is a block diagram for showing the configuration of the semiconductor wafer analysis apparatus of FIG. 1;
3 is a block diagram for showing the configuration of the information conversion module of FIG. 2;
FIG. 4 is a block diagram showing the configuration of the first clustering module of FIG. 2 .
FIG. 5 is a block diagram showing the configuration of an overlapping map generating module in FIG. 2;
FIG. 6 is a block diagram showing the configuration of the second clustering module of FIG. 2 .
7 is a flowchart illustrating an operating method of the semiconductor wafer analysis apparatus of FIGS. 2 to 6 .

Since the description of the present invention is only an embodiment for structural or functional description, the scope of the present invention should not be construed as being limited by the embodiments described in the text. That is, since the embodiment can be changed in various ways and can have various forms, it should be understood that the scope of the present invention includes equivalents capable of realizing the technical idea. In addition, since the object or effect presented in the present invention does not mean that a specific embodiment should include all of them or only such effects, the scope of the present invention should not be construed as being limited thereto.

Meanwhile, the meaning of terms described in this application should be understood as follows.

Terms such as "first" and "second" are used to distinguish one component from another, and the scope of rights should not be limited by these terms. For example, a first element may be termed a second element, and similarly, a second element may be termed a first element.

Expressions in the singular number should be understood to include plural expressions unless the context clearly dictates otherwise, and terms such as “comprise” or “have” refer to an embodied feature, number, step, operation, component, part, or these. It should be understood that it is intended to indicate that a combination exists, and does not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

In each step, the identification code (eg, a, b, c, etc.) is used for convenience of explanation, and the identification code does not describe the order of each step, and each step clearly follows a specific order in context. Unless otherwise specified, it may occur in a different order than specified. That is, each step may occur in the same order as specified, may be performed substantially simultaneously, or may be performed in the reverse order.

All terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs, unless defined otherwise. Terms defined in commonly used dictionaries should be interpreted as consistent with meanings in the context of the related art, and cannot be interpreted as having ideal or excessively formal meanings unless explicitly defined in the present application.

1 is a block diagram showing the configuration of a semiconductor wafer analysis system 100 according to an embodiment of the present invention.

Referring to FIG. 1 , a semiconductor wafer analysis system 100 may include a semiconductor test device 110 , a semiconductor wafer analysis device 120 , and a test control device 130 .

First of all, the semiconductor test apparatus 110 may be configured to perform various test operations on a plurality of chips formed on each of a plurality of wafers. The semiconductor test apparatus 100 may output test results corresponding to a plurality of wafers as test result information INF_TD. The test result information INF_TD may include defective elements for a plurality of chips formed on each of a plurality of wafers. Here, the defective factor may include whether or not each chip is defective and the number of bad blocks.

Next, the semiconductor wafer analysis apparatus 120 may be configured to generate and analyze a wafer map through the test result information INF_TD. The semiconductor wafer analysis device 120 may output a result of analyzing the wafer map as evaluation result information OUT_FR. A test performer may determine a defect type for each of a plurality of wafers to be tested through the evaluation result information OUT_FR. A more detailed configuration and operating method of the semiconductor wafer analysis device 120 will be described below.

Next, the test control device 130 may be a component for controlling the semiconductor test device 110 and the semiconductor wafer analysis device 120 . The test control device 130 may control a control mode, control time, etc. for each of the semiconductor test device 110 and the semiconductor wafer analysis device 120 by a test performer.

FIG. 2 is a block diagram showing the configuration of the semiconductor wafer analysis apparatus 120 of FIG. 1 .

Referring to FIG. 2 , the semiconductor wafer analysis apparatus 120 includes a wafer map generation module 210, an information conversion module 220, a first clustering module 230, an overlap map generation module 240, a second clustering module ( 250), and an evaluation module 260.

First, the wafer map generating module 210 may be a component for generating wafer map information INF_WM based on test result information INF_TD corresponding to a plurality of wafers. Here, the wafer map information may include information visualizing whether a plurality of chips formed on each of a plurality of wafers are defective and the number of bad blocks. Wafer map information may include binary image information, but is not necessarily limited thereto.

Also, the wafer map information may include category-type defects or parameter-type defects. Here, the categorical defect may include bin (BIN) data corresponding to the state of the chip under test. For example, if the chip is good, empty data can be represented by 1, if the chip is short-circuited, empty data can be represented by 2, and if the chip is open-defective, empty data can be represented by 3. can be expressed In addition, the parametric defect may include data representing characteristics of the chip. For example, if the reference voltage (Vref), threshold voltage (Vt), capacitance, etc. are out of preset reference values, this may be expressed. The wafer map can be expressed in 2D or 3D.

Next, the information conversion module 220 may be a component for generating low-dimensional information INF_LD by performing low-dimensional conversion on defective elements included in the wafer map information INF_WM. The information conversion module 220 may perform low-dimensional conversion on all defect factors included in the wafer map information INF_WM. Hereinafter, the information conversion module 220 will be described in more detail with reference to FIG. 3 .

FIG. 3 is a block diagram showing the configuration of the information conversion module 220 of FIG. 2 .

Referring to FIG. 3 , the information conversion module 220 may include a composite generation module 310 and a low-dimensional conversion module 320 .

First, the composite generating module 310 may be a component for generating a simple complex with all wafer maps included in the wafer map information INF_WM. For example, all wafer maps included in the wafer map information INF_WM may be expressed as points on a high-dimensional space having a dimension of the number of chips included in the wafer, and the points may have a distance relationship. A Vietoris-Rips complex (or VR complex) and a Cech complex may be used as a method for creating a simplex complex.

Next, when generating a single-unit complex, an N-dimensional sphere can be created based on the distance from each point to a nearby point, and a single-unit complex can be created by reflecting the density of points in the area and connecting lines. For example, in the case of a region in which the density of defective elements is relatively high, that is, in the case of a region in which the density of defective elements has a first density, the composite generating module 310 may connect defective elements existing at a first distance. In addition, the composite generating module 310 is present at a second distance greater than the first distance in the case of a region in which the density of defective elements is relatively low, that is, in the case of a region in which the density of defective elements has a second density lower than the first density. Bad elements can be connected. For this operation, the complex generating module 310 may include a UMAP (Uniform Manifold Approximation and Projection) algorithm or the like.

Next, the low-dimensional transformation module 320 may be a component for transforming the simplex complex generated in the complex generation module 310 into a low-dimensional one. The low-dimensional transformation module 320 may generate low-dimensional information INF_LD by transforming the simple substance complex SC into a low-dimensional one. Here, the low-dimensional transformation module 320 may utilize a force-directed graph drawing algorithm and deep learning. For example, the low-dimensional transformation module 320 may transform original data, which is a single-unit complex, into low-dimensional data using a force-directed graph drawing algorithm. In addition, the low-dimensional transformation module 320 may utilize a deep encoder, which is a deep learning model, for input and output of the Force-Directed Graph Drawing algorithm. In addition, the low-dimensional expression of the wafer map is obtained first through a method of first encoding the low-dimensional transformation of the wafer map using deep learning and then decoding it again, and then inputting the low-dimensional expression to the complex generation module to form a single composite complex. can also create For this operation, the low-dimensional transformation module 320 may include an autoencoder method.

Referring back to FIG. 2 , the first clustering module 230 may be a component for generating first grouping information INF_G1 by primary clustering of low-dimensional information. The first clustering module 230 may generate primary clustered first grouping information INF_G1 based on a feature vector included in the low-dimensional information INF_LD. Here, the feature vector may correspond to a point on a low-dimensional manifold expressed by converting the simplex complex into low-dimensional information (INF_LD). The first clustering module 230 may classify feature vectors by grouping similar feature vectors among various feature vectors included in the low-dimensional information INF_LD. As an algorithm for primary clustering, algorithms such as MinibatchKmeans, Hdbscan, and Birch may be used. Hereinafter, the first clustering module 230 will be described in more detail with reference to FIG. 4 .

FIG. 4 is a block diagram showing the configuration of the first clustering module 230 of FIG. 2 .

Referring to FIG. 4 , the first clustering module 230 may include a feature data extraction module 410 and a classification module 420 .

First, the feature data extraction module 410 may be a component for extracting a feature vector included in low-dimensional information INF_LD. As described above, the low-dimensional information INF_LD includes a feature vector, and the feature data extraction module 410 may extract the feature vector based on the low-dimensional information INF_LD.

Next, the classification module 420 may be a component for generating first grouping information INF_G1 by classifying the feature data extracted by the feature data extraction module 410 according to a preset criterion. The classification module 420 may classify feature data by grouping feature data having similarities among a plurality of extracted feature data.

Referring back to FIG. 2 , the overlapping map generation module 240 may be a component for generating overlapping map information INF_OM by mapping the wafer map information INF_WM to the first grouping information INF_G1. The overlapping map generating module 240 may generate overlapping map information INF_OM by averaging the wafer map information INF_WM matched with the first grouping information INF_G1. Hereinafter, the overlapping map generation module 240 will be described in more detail with reference to FIG. 5 .

FIG. 5 is a block diagram showing the configuration of the overlapping map generating module 240 of FIG. 2 .

Referring to FIG. 5 , the overlap map generation module 240 may include a mapping module 510 and a quantification module 520 .

First of all, the mapping module 510 may be a component for receiving wafer map information INF_WM and first grouping information INF_G1 and mapping the wafer map information INF_WM corresponding to the first grouping information INF_G1. For example, the first grouping information INF_G1 may include a plurality of groups. Accordingly, the mapping module 510 may map wafer map information INF_WM corresponding to each of a plurality of groups according to the corresponding group.

Next, the quantization module 520 may be a component for generating quantified overlapping map information INF_OM by averaging output information of the mapping module 510 for each group. As described above, the mapping module 510 may map wafer map information INF_WM corresponding to each of a plurality of groups. Accordingly, the quantification module 520 may generate quantified overlapping map information (INF_OM) by averaging the wafer map information (INF_WM) for each group.

Referring back to FIG. 2 , the second clustering module 250 may be a component for generating second grouping information INF_G2 by comparing overlapping map information INF_OM with each other and performing secondary clustering. The second clustering module 250 may perform secondary clustering on the overlapping map information (INF_OM) according to similarities between them. Here, as indicators for similarity, Dice coefficient based on the location and number of defects, Cosine distance based on the vector of the defect pattern, Euclidean distance based on the shape of the defect pattern, etc. can be used. As an algorithm for secondary clustering, a clustering algorithm such as Kmeans may be used. The second clustering module 250 may be a component for generating secondary clustered second grouping information INF_G2. The second clustering module 250 may generate second grouping information INF_G2 by grouping similar overlapping map information INF_OM. Hereinafter, the second clustering module 250 will be described in more detail.

FIG. 6 is a block diagram showing the configuration of the second clustering module 250 of FIG. 2 .

Referring to FIG. 6 , the second clustering module 250 may include a similarity determination module 610 and a grouping module 620.

First, the similarity determination module 610 may be configured to compare and determine the similarity of overlapping map information (INF_OM). The similarity determination module 610 may determine overlapping map information INF_OM having similar defect types.

Next, the grouping module 620 may be configured to generate second grouping information INF_G2 by grouping the overlapping map information INF_OM according to the output result of the similarity determination module 610 . The grouping module 620 may generate overlapping map information INF_OM having similar defect types as second grouping information INF_G2.

Referring back to FIG. 2 , the evaluation module 260 may be a component for generating evaluation result information OUT_FR corresponding to each defect type of a plurality of wafers based on the second grouping information INF_G2. A test performer may analyze types of defects occurring in a plurality of wafers based on the evaluation result information OUT_FR. Therefore, the test performer can perform follow-up measures for the cause of the defect or optimize the test recipe according to the evaluation result information (OUT_RF).

The semiconductor wafer analysis apparatus 120 according to an embodiment of the present invention may perform low-dimensional conversion including whether a plurality of chips formed on each of a plurality of wafers are defective and the number of bad blocks. In addition, the semiconductor wafer analysis apparatus 120 may obtain a clustering result without omission of irregular defect types by performing second clustering after the first clustering. That is, the semiconductor wafer analyzer 120 may perform analysis on all defect types by obtaining clustering results for not only standardized defect types but also irregular defect types.

FIG. 7 is a flowchart illustrating an operating method 700 of the semiconductor wafer analysis apparatus 120 of FIGS. 2 to 6 .

Referring to FIG. 7 , a method 700 of operating a wafer analysis device 120 includes generating wafer map information (710), performing low-dimensional transformation (720), clustering (730), and evaluating (730). (740).

First, generating wafer map information (710) may be a step for generating wafer map information (INF_WM) based on test result information corresponding to a plurality of wafers. The step 710 of generating wafer map information may be performed by the wafer map generating module 210 of FIG. 2 . As described above, the wafer map generation module 210 may generate wafer map information INF_WM based on test result information INF_TD corresponding to a plurality of wafers.

Next, the low-dimensional conversion step 720 may be a step for low-dimensional conversion of defective elements included in the wafer map information INF_WM. The low-dimensional transformation step 720 may be performed by the information transformation module 220 of FIGS. 2 and 3 . As described above, the low-dimensional conversion module 220 may generate low-dimensional information INF_LD by performing low-dimensional conversion of defective elements included in the wafer map information INF_WM. Although not shown in the drawing, the low-dimensional transforming step 720 may include generating a single-unit composite targeting defective elements through the composite generating module 310 of FIG. 3. Then, the low-dimensional transforming step 720 ) may include a step of generating low-dimensional information (INF_LD) by transforming the simple substance complex into a low-dimensional one through the low-dimensional transformation module 320 of FIG. 3 .

Next, the clustering step 730 may be a step for clustering the low-dimensional information INF_LD generated in the low-dimensional transform step 720 . Clustering (730) may include primary clustering (731), mapping (732), and secondary clustering (733).

The primary clustering step 731 may be a step for performing primary clustering on the low-dimensional information INF_LD based on a feature vector included in the low-dimensional information INF_LD. Step 731 of primary clustering can be performed by the first clustering module 230 of FIGS. 2 and 4 . As described above, the first clustering module 230 may perform primary clustering on the low-dimensional information INF_LD based on a feature vector included in the low-dimensional information INF_LD. Although not shown, the primary clustering step 731 may include extracting feature vectors included in the low-dimensional information INF_LD through the feature data extraction module 410 of FIG. 4 . The primary clustering step 731 may include generating first grouping information INF_G1 by classifying the feature vectors according to a predetermined criterion through the classification module 420 of FIG. 4 .

The mapping step (732) is a step for mapping the first grouping information (INF_G1) generated in the primary clustering step (731) and the wafer map information (INF_WM) generated in the wafer map information generating step (710). can be The mapping step 732 can be performed by the overlap map generation module 240 of FIGS. 2 and 5 . As described above, the overlapping map generation module 240 may generate overlapping map information INF_OM by mapping the wafer map information INF_WM to the first grouping information INF_G1. Although not shown in the figure, the mapping step 732 may include mapping the wafer map information INF_WM corresponding to the first grouping information INF_G1 through the mapping module 510 of FIG. 5 . The mapping step 732 may include generating quantified overlapping map information INF_OM by averaging output information of the mapping module 510 for each group through the quantification module 520 of FIG. 5 .

The secondary clustering step 733 may be a step for secondary clustering the overlapping map information INF_OM output in the mapping step 732 to generate second grouping information INF_G2 based on similarities between them. . Step 733 of secondary clustering can be performed by the second clustering module 250 of FIGS. 2 and 6 . As described above, the second clustering module 250 may perform secondary clustering on overlapping map information (INF_OM) based on similarity between them. Although not shown in the figure, the secondary clustering step 733 may include determining the similarity of overlapping map information INF_OM through the similarity determination module 610 of FIG. 6 . The secondary clustering step 733 includes generating second grouping information INF_G2 by grouping the overlapping map information INF_OM according to the output result of the similarity determination module 610 through the grouping module 620. can do.

Next, the evaluating step 740 may be a step for evaluating the defect types of each of the plurality of wafers based on the output information of the clustering step 730 . In other words, in the evaluating step 740 , the defect flow rate of each of the plurality of wafers may be evaluated based on the second grouping information INF_G2 generated in the secondary clustering step 733 .

The operating method 700 of the semiconductor wafer analysis apparatus 120 according to an embodiment of the present invention performs low-dimensional conversion including defects and the number of bad blocks for a plurality of chips formed on each of a plurality of wafers. can In addition, the operation method 700 of the semiconductor wafer analyzer 120 may obtain a clustering result without omission of irregular defect types by performing first and second clustering on the result of the low-dimensional transformation.

The embodiments described in this specification and the accompanying drawings merely illustrate some of the technical ideas included in the present invention by way of example. Therefore, since the embodiments disclosed herein are intended to explain rather than limit the technical spirit of the present invention, it is obvious that the scope of the technical spirit of the present invention is not limited by these embodiments. All modifications and specific examples that can be easily inferred by those skilled in the art within the scope of the technical idea included in the specification and drawings of the present invention should be construed as being included in the scope of the present invention.

120: semiconductor wafer analysis device 210: wafer map generation module
220: information conversion module 230: first clustering module
240: overlap map generation module 250: second clustering module
260: evaluation module

Claims (19)

a wafer map generation module that generates wafer map information based on test result information corresponding to a plurality of wafers;
an information conversion module generating low-dimensional information by performing low-dimensional conversion on defective elements included in the wafer map information;
a first clustering module generating first grouping information by performing primary clustering on the low-dimensional information;
an overlapping map generating module configured to generate overlapping map information by mapping the wafer map information to the first grouping information;
a second clustering module generating second grouping information by comparing the overlapping map information with each other and performing secondary clustering; and
An evaluation module generating evaluation result information corresponding to the defect type of each of the plurality of wafers based on the second grouping information.
Semiconductor wafer analysis equipment. According to claim 1,
Characterized in that the defect factor includes whether a plurality of chips formed on each of the plurality of wafers are defective and the number of bad blocks
Semiconductor wafer analysis equipment. According to claim 1,
The information conversion module
a complex generating module for generating a simple complex for the defective elements; and
and a low-dimensional transformation module generating the low-dimensional information by transforming the simplex complex.
Semiconductor wafer analysis equipment. According to claim 3,
The composite generating module connects the defective elements existing at a first distance in an area where the defective elements have a first density, and in an area where the defective elements have a second density lower than the first density, the first Characterized in that for connecting the defective element existing at a second distance greater than the distance
Semiconductor wafer analysis equipment. According to claim 3,
Characterized in that the complex generation module includes a UMAP (Uniform Manifold Approximation and Projection) algorithm
Semiconductor wafer analysis equipment. According to claim 3,
Characterized in that the low-dimensional transformation module includes an autoencoder method
Semiconductor wafer analysis equipment. According to claim 1,
The first clustering module
a feature data extraction module extracting a feature vector included in the low-dimensional information; and
A classification module configured to generate the first grouping information by classifying the feature vector according to a predetermined criterion.
Semiconductor wafer analysis equipment. According to claim 1,
The overlap map generation module
a mapping module receiving the wafer map information and the first grouping information and mapping the wafer map information corresponding to the first grouping information; and
And a quantification module for generating the quantified overlapping map information by averaging the output information of the mapping module for each group.
Semiconductor wafer analysis equipment. According to claim 1,
The second clustering module
a similarity determination module that compares and determines the similarity of the overlapping map information; and
And a grouping module generating the second grouping information by grouping the overlapping map information according to the output result of the similarity determination module.
Semiconductor wafer analysis equipment. generating wafer map information based on test result information corresponding to a plurality of wafers;
low-dimensionally transforming defective elements included in the wafer map information;
clustering the low-dimensional information generated in the low-dimensional transforming step; and
Evaluating the defect type of each of the plurality of wafers based on the output information of the clustering step.
A method of operating a semiconductor wafer analysis device. According to claim 10,
Characterized in that the defect factor includes whether a plurality of chips formed on each of the plurality of wafers are defective and the number of bad blocks
A method of operating a semiconductor wafer analysis device. According to claim 10,
The low-dimensional transformation step is
generating a single-unit composite targeting the defective elements; and
generating the low-dimensional information by transforming the simplex complex into a low-dimensional one.
A method of operating a semiconductor wafer analysis device. According to claim 12,
The generating of the single-unit complex may include connecting the defective elements existing at a first distance in an area where the defective elements have a first density, and in an area where the defective elements have a second density lower than the first density. Characterized in that for connecting the defective element existing at a second distance greater than the first distance
A method of operating a semiconductor wafer analysis device. According to claim 10,
Characterized in that the low-dimensional transformation step includes a UMAP (Uniform Manifold Approximation and Projection) algorithm
A method of operating a semiconductor wafer analysis device. According to claim 10,
Characterized in that the low-dimensional transforming step includes an autoencoder method
A method of operating a semiconductor wafer analysis device. According to claim 10,
The clustering step is
performing primary clustering on the low-dimensional information based on a feature vector included in the low-dimensional information;
mapping the first grouping information generated in the primary clustering step with the wafer map information generated in the generating wafer map information; and
Comprising the step of performing secondary clustering to generate second grouping information by comparing output information of the mapping step
A method of operating a semiconductor wafer analysis device. According to claim 16,
The first clustering step is
extracting a feature vector included in the low-dimensional information; and
Generating the first grouping information by classifying the feature vector according to a preset criterion.
A method of operating a semiconductor wafer analysis device. According to claim 16,
The mapping step is
mapping the wafer map information to the first grouping information; and
Generating quantified overlapping map information by averaging the output information of the mapping step for each group.
A method of operating a semiconductor wafer analysis device. According to claim 16,
The second clustering step is
determining similarity of overlapping map information generated in the mapping step; and
Generating the second grouping information by grouping the overlapping map information according to an output result of determining the similarity.
A method of operating a semiconductor wafer analysis device.

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