KR20230117032A - Display device and tiled dipslay device - Google Patents

Abstract

The present invention relates to a display device and a tiled display device. A display device according to an exemplary embodiment includes a plurality of sub-pixels. Among the plurality of sub-pixels, one sub-pixel is disposed on a substrate, and a first pad electrode and a second pad electrode disposed apart from each other on a plane, and a light emitting disposed on the first pad electrode and the second pad electrode. and a first test transistor overlapping the first pad electrode in a thickness direction of the substrate. The first inspection transistor overlaps the light emitting element in a thickness direction of the substrate.

Description

Display device and tiled display device {DISPLAY DEVICE AND TILED DIPSLAY DEVICE}

The present invention relates to a display device and a tiled display device.

As the information society develops, demands for display devices for displaying images are increasing in various forms. When a display device is manufactured in a large size, a defect rate of a light emitting device may increase due to an increase in the number of pixels, and productivity or reliability may decrease. In order to solve this problem, a tile type display device in which a large screen is realized by connecting a plurality of display devices having a relatively small size is being developed.

The display device may be a flat panel display device such as a liquid crystal display, a field emission display, or a light emitting display. The light emitting display device may include an organic light emitting display device including an organic light emitting diode device as a light emitting device, or a light emitting diode display device including an inorganic light emitting diode device such as a light emitting diode (LED) as a light emitting device. In the case of a light emitting diode display, when bonding an inorganic light emitting diode element to a display panel, the pad electrode may be damaged by bonding pressure.

An object to be solved by the present invention is to provide a display device capable of inspecting breakage of a pad electrode.

Another problem to be solved by the present invention is to provide a tile-type display device capable of inspecting damage to a pad electrode.

The tasks of the present invention are not limited to the tasks mentioned above, and other technical tasks not mentioned will be clearly understood by those skilled in the art from the following description.

A display device according to an exemplary embodiment for solving the above problem includes a plurality of sub-pixels. Among the plurality of sub-pixels, one sub-pixel is disposed on a substrate, and a first pad electrode and a second pad electrode disposed apart from each other on a plane, and a light emitting disposed on the first pad electrode and the second pad electrode. and a first inspection transistor overlapping the first pad electrode in a thickness direction of the substrate. The first inspection transistor overlaps the light emitting element in a thickness direction of the substrate.

The sub-pixel may further include a second inspection transistor overlapping the second pad electrode in the thickness direction of the substrate, and the second inspection transistor may overlap the light emitting element in the thickness direction of the substrate.

A gate electrode of the first test transistor and a gate electrode of the second test transistor may be connected to a test enable signal line.

A gate electrode of the first test transistor may be connected to a first test enable signal line, and a gate electrode of the second test transistor may be connected to a second test enable signal line.

A first electrode of the first test transistor and a first electrode of the second test transistor may be connected to a first horizontal power line to which a first power voltage is applied.

The display device may further include a first data line connected to the sub-pixel and applied with a first data voltage, and a second data line connected to the sub-pixel and applied with a second data voltage. The sub-pixel may include a first pixel driver including a first transistor configured to control a control current according to the first data voltage of the first data line, and the first power supply according to the second data voltage of the second data line. A second pixel driver including a second transistor including a second transistor controlling a driving current flowing from a first power line to which a voltage is applied to the light emitting element, and applying the driving current to the light emitting element according to the control current of the first pixel driver and a third pixel driver including a third transistor for adjusting a period of

A second electrode of the first test transistor and a second electrode of the second test transistor may be connected to a second horizontal power line to which a second power voltage is applied.

The first electrode of the light emitting element is connected to the first pad electrode, the second electrode of the light emitting element is connected to the second pad electrode, and the second pad electrode is connected to the second power supply voltage. Can be connected to power wiring.

A first electrode of the first inspection transistor may be connected to a horizontal voltage line, and a second electrode may be connected to a sensing line.

The horizontal voltage line may receive a predetermined voltage.

A first electrode of the second test transistor may be connected to the horizontal voltage line, and a second electrode may be connected to the sensing line.

The light emitting device may be a flip chip type micro light emitting diode device.

A display device according to an exemplary embodiment for solving the above problem includes a plurality of sub-pixels. Among the plurality of sub-pixels, one sub-pixel is disposed on a substrate, and a first pad electrode and a second pad electrode disposed apart from each other on a plane, and a light emitting disposed on the first pad electrode and the second pad electrode. and a first resistance portion overlapping the first pad electrode in a thickness direction of the substrate. The first resistor part overlaps the light emitting element in the thickness direction of the substrate.

A first horizontal voltage wire connected to one end of the first resistance part and a first sensing wire connected to the other end of the first resistance part may be further provided.

The sub-pixel may further include an inspection transistor overlapping the second pad electrode in the thickness direction of the substrate, and the third inspection transistor may overlap the light emitting element in the thickness direction of the substrate.

A gate electrode of the first test transistor may be connected to a test enable signal line, a first electrode may be connected to a horizontal voltage line, and a second electrode may be connected to a sensing line.

The sub-pixel may further include a second resistor portion overlapping the second pad electrode in the thickness direction of the substrate, and the second resistor portion may overlap the light emitting element in the thickness direction of the substrate.

A second horizontal voltage wire connected to one end of the second resistance unit and a second sensing wire connected to the other end of the second resistance unit may be further provided.

The same voltage may be supplied to the first horizontal voltage line and the second horizontal voltage line.

The light emitting device may be a flip chip type micro light emitting diode device.

A display device according to an exemplary embodiment for solving the above problem includes a plurality of sub-pixels. Among the plurality of sub-pixels, one sub-pixel is disposed on a substrate, and a first pad electrode and a second pad electrode disposed apart from each other on a plane, and a light emitting disposed on the first pad electrode and the second pad electrode. and a first dummy transistor overlapping the first pad electrode in a thickness direction of the substrate. The first dummy transistor overlaps the light emitting element in the thickness direction of the substrate, and a gate electrode of the first dummy transistor is connected to a floating line or a gate-off voltage line to which a gate-off voltage is applied.

The sub-pixel may further include a second dummy transistor overlapping the second pad electrode in the thickness direction of the substrate, and the second dummy transistor may overlap the light emitting element in the thickness direction of the substrate.

A gate electrode of the second dummy transistor may be connected to the floating line or the gate-off voltage line.

A tile-type display device according to an exemplary embodiment for solving the above problems includes a plurality of display devices and a joint disposed between the plurality of display devices. Among the plurality of display devices, a first display device includes a plurality of sub-pixels. Among the plurality of sub-pixels, one sub-pixel is disposed on a substrate, and a first pad electrode and a second pad electrode disposed apart from each other on a plane, and a light emitting disposed on the first pad electrode and the second pad electrode. device, a first thin film transistor overlapping the first pad electrode in a thickness direction of the substrate, and a second thin film transistor overlapping the second pad electrode in a thickness direction of the substrate. Each of the first thin film transistor and the second thin film transistor overlaps the light emitting element in a thickness direction of the substrate.

The light emitting device may be a flip chip type micro light emitting diode device.

The first display device may include a substrate, a pad disposed on a first surface of the substrate, a first surface of the substrate, a second surface opposite to the first surface, and a space between the first surface and the second surface. It is disposed on one side of the and may further include a side wiring connected to the pad.

The substrate may be made of glass.

The first display device may further include a connection wire disposed on the second surface of the substrate, and a flexible film connected to the connection wire through a conductive adhesive member. The side wiring may be connected to the connection wiring.

The plurality of display devices may be arranged in a matrix form in M (M is a positive integer) rows and N (N is a positive integer) columns.

Other embodiment specifics are included in the detailed description and drawings.

According to the display device and the tile-type display device according to the embodiments, by disposing the inspection transistor overlapping the light emitting device, the pad electrode that may occur when a predetermined pressure is applied to the light emitting device to attach the light emitting device to the pad electrode It can be inspected for damage.

According to the display device and the tile-type display device according to the exemplary embodiments, by disposing the variable resistor so as to overlap the light emitting device, the pad electrode that may occur when a predetermined pressure is applied to the light emitting device to attach the light emitting device to the pad electrode It can be inspected for damage.

Effects according to the embodiments are not limited by the contents exemplified above, and more various effects are included in this specification.

1 is a layout diagram illustrating a display device according to an exemplary embodiment.
FIG. 2 is an exemplary diagram showing an example of a pixel of FIG. 1 .
FIG. 3 is an exemplary view showing still another example of the pixel of FIG. 1 .
4 are circuit diagrams illustrating a first sub-pixel according to an exemplary embodiment.
5 is a layout diagram illustrating a lower metal layer, an active layer, a first gate metal layer, a second gate metal layer, a first source metal layer, and a second source metal layer of a first sub-pixel according to an exemplary embodiment.
6 is a layout diagram illustrating a third source metal layer of a first sub-pixel according to an exemplary embodiment.
7 is a layout diagram illustrating a fourth source metal layer of a first sub-pixel according to an exemplary embodiment.
8 is a layout diagram illustrating a transparent electrode layer and a first light emitting device of a first sub-pixel according to an exemplary embodiment.
FIG. 9 is an enlarged layout diagram showing area A of FIG. 5 in detail.
FIG. 10 is an enlarged layout diagram showing area B of FIG. 5 in detail.
FIG. 11 is an enlarged layout diagram showing area C of FIG. 5 in detail.
FIG. 12 is a cross-sectional view illustrating an example of a first sub-pixel taken along AA' of FIGS. 5 to 8 .
13 is a cross-sectional view illustrating an example of a first sub-pixel taken along line BB′ of FIGS. 5 to 8 .
14 is circuit diagrams illustrating a first sub-pixel according to another exemplary embodiment.
15 is a circuit diagram illustrating a first sub-pixel according to another exemplary embodiment.
16 is a layout diagram illustrating a lower metal layer, an active layer, a first gate metal layer, a second gate metal layer, a first source metal layer, and a second source metal layer of a first sub-pixel according to another embodiment.
FIG. 17 is an enlarged layout diagram showing area C of FIG. 16 in detail.
18 is a cross-sectional view illustrating an example of a first sub-pixel taken along line C-C′ of FIGS. 16 and 17 .
19 is a circuit diagram illustrating a first sub-pixel according to another exemplary embodiment.
20 is a layout diagram illustrating a lower metal layer, an active layer, a first gate metal layer, a second gate metal layer, a first source metal layer, and a second source metal layer of a first sub-pixel according to another embodiment.
FIG. 21 is an enlarged layout diagram showing area C of FIG. 20 in detail.
22 is a cross-sectional view illustrating an example of a first sub-pixel taken along line D-D′ of FIGS. 20 and 21 .
23 is a circuit diagram illustrating a first sub-pixel according to another exemplary embodiment.
24 is a layout diagram illustrating a lower metal layer, an active layer, a first gate metal layer, a second gate metal layer, a first source metal layer, and a second source metal layer of a first sub-pixel according to another embodiment.
FIG. 25 is an enlarged layout diagram showing area C of FIG. 24 in detail.
26 is a cross-sectional view illustrating an example of a first sub-pixel taken along line E-E′ of FIGS. 24 and 25 .
27 is a circuit diagram illustrating a first sub-pixel according to another exemplary embodiment.
28 is a layout diagram illustrating a lower metal layer, an active layer, a first gate metal layer, a second gate metal layer, a first source metal layer, and a second source metal layer of a first sub-pixel according to another embodiment.
FIG. 29 is an enlarged layout diagram showing area C of FIG. 28 in detail.
30 is a cross-sectional view illustrating an example of a first sub-pixel taken along line F-F′ of FIGS. 28 and 29 .
31 is a circuit diagram illustrating a first sub-pixel according to another exemplary embodiment.
32 is a layout diagram illustrating a lower metal layer, an active layer, a first gate metal layer, a second gate metal layer, a first source metal layer, and a second source metal layer of a first sub-pixel according to another embodiment.
FIG. 33 is an enlarged layout diagram showing area C of FIG. 32 in detail.
34 is a cross-sectional view illustrating an example of a first sub-pixel taken along line G-G′ of FIGS. 32 and 33 .
35 is a circuit diagram illustrating a first sub-pixel according to another embodiment.
36 is a layout diagram illustrating a lower metal layer, an active layer, a first gate metal layer, a second gate metal layer, a first source metal layer, and a second source metal layer of a first sub-pixel according to another embodiment.
FIG. 37 is an enlarged layout diagram showing area C of FIG. 36 in detail.
38 is a cross-sectional view illustrating an example of a first sub-pixel taken along H-H′ of FIGS. 36 and 37 .
39 is a layout diagram illustrating a lower metal layer, an active layer, a first gate metal layer, a second gate metal layer, a first source metal layer, and a second source metal layer of a first sub-pixel according to another embodiment.
40 is a layout diagram illustrating a third source metal layer of a first sub-pixel according to another embodiment.
41 is a layout diagram illustrating a fourth source metal layer of a first sub-pixel according to another embodiment.
42 is a layout diagram illustrating a transparent electrode layer and a first light emitting device of a first sub-pixel according to another embodiment.
43 is a cross-sectional view illustrating an example of a first sub-pixel taken along line II' of FIGS. 39 to 42 .
44 is an exemplary view showing a front surface of a tiled display device according to an exemplary embodiment.
FIG. 45 is an enlarged layout diagram showing area H of FIG. 44 in detail.
FIG. 46 is a cross-sectional view illustrating an example of a tile-type display device taken along line J-J′ of FIG. 45 .
47 is an exemplary view showing a front surface of the first display device according to an exemplary embodiment.
48 is an exemplary view showing a rear surface of the first display device according to an exemplary embodiment.
49 is an exemplary diagram showing an example of a check multiplexer according to an embodiment.
50 is a cross-sectional view illustrating an example of the first display device taken along line NN′ of FIGS. 48 and 49 .
51 is an exemplary view showing a front surface of a first display device according to another embodiment.
52 is a block diagram illustrating a tiled display device according to an exemplary embodiment.
53 is an exemplary diagram illustrating wireless communication between a plurality of display devices of a tile type display device according to an exemplary embodiment.

Advantages and features of the present invention, and methods of achieving them, will become clear with reference to the detailed description of the following embodiments taken in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, only these embodiments make the disclosure of the present invention complete, and common knowledge in the art to which the present invention belongs. It is provided to fully inform the holder of the scope of the invention, and the present invention is only defined by the scope of the claims.

When an element or layer is referred to as being "on" another element or layer, it includes all cases where another element or layer is directly on top of another element or another layer or other element intervenes therebetween. Like reference numbers designate like elements throughout the specification. The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments are illustrative, and the present invention is not limited thereto.

Although first, second, etc. are used to describe various components, these components are not limited by these terms, of course. These terms are only used to distinguish one component from another. Accordingly, it goes without saying that the first element mentioned below may also be the second element within the technical spirit of the present invention.

Each feature of the various embodiments of the present invention can be partially or entirely combined or combined with each other, technically various interlocking and driving are possible, and each embodiment can be implemented independently of each other or can be implemented together in a related relationship. may be

Hereinafter, specific embodiments will be described with reference to the accompanying drawings.

1 is a layout diagram illustrating a display device according to an exemplary embodiment. FIG. 2 is an exemplary diagram showing an example of a pixel of FIG. 1 . FIG. 3 is an exemplary view showing still another example of the pixel of FIG. 1 .

1 to 3, the display device 10 is a device for displaying moving images or still images, and includes a mobile phone, a smart phone, a tablet personal computer (PC), and a smart watch. (smart watch), watch phone (watch phone), mobile communication terminal, electronic notebook, electronic book, PMP (portable multimedia player), navigation, UMPC (Ultra Mobile PC), as well as portable electronic devices such as televisions, laptops, monitors It can be used as a display screen for various products such as billboards, billboards, and the Internet of Things (IoT).

The display panel 100 may be formed in a rectangular plane shape having a long side in the first direction DR1 and a short side in the second direction DR2 crossing the first direction DR1 . A corner where the long side of the first direction DR1 and the short side of the second direction DR2 meet may be rounded to have a predetermined curvature or may be formed at a right angle. The planar shape of the display panel 100 is not limited to a quadrangle and may be formed in a polygonal shape, a circular shape, or an elliptical shape. The display panel 100 may be formed flat, but is not limited thereto. For example, the display panel 100 may include curved portions formed at left and right ends and having a constant curvature or a changing curvature. In addition, the display panel 100 may be formed to be flexible so as to be bent, bent, bent, folded, or rolled.

The display panel 100 may further include pixels PXs, scan lines extending in the first direction DR1 , and data lines extending in the second direction DR2 to display an image. The pixels PX may be arranged in a matrix form in the first and second directions DR1 and DR2 .

Each of the pixels PX may include a plurality of sub-pixels RP, GP, and BP as shown in FIGS. 2 and 3 . 2 and 3 , each of the pixels PX includes three sub-pixels RP, GP, and BP, that is, a first sub-pixel RP, a second sub-pixel GP, and a third sub-pixel BP. ), but the embodiments of the present specification are not limited thereto.

The first sub-pixel RP, the second sub-pixel GP, and the third sub-pixel BP may be connected to one data line among data lines and at least one scan line among scan lines.

Each of the first sub-pixel RP, the second sub-pixel GP, and the third sub-pixel BP may have a rectangular, square, or rhombus planar shape. For example, each of the first sub-pixel RP, the second sub-pixel GP, and the third sub-pixel BP has a short side in the first direction DR1 and a short side in the second direction DR2 as shown in FIG. 2 . It may have a planar shape of a rectangle having a long side. Alternatively, each of the first sub-pixel RP, the second sub-pixel GP, and the third sub-pixel BP has the same length in the first and second directions DR1 and DR2 as shown in FIG. 3 . It may have a planar shape of a square or rhombus including sides.

As shown in FIG. 2 , the first sub-pixel RP, the second sub-pixel GP, and the third sub-pixel BP may be arranged in the first direction DR1 . Alternatively, one of the second sub-pixel GP and the third sub-pixel BP and the first sub-pixel RP are arranged in the first direction DR1, and the other one and the first sub-pixel RP are They may be arranged in the second direction DR2. For example, as shown in FIG. 3 , the first sub-pixel RP and the second sub-pixel GP are arranged in the first direction DR1, and the first sub-pixel RP and the third sub-pixel BP are may be arranged in the second direction DR2.

Alternatively, any one of the first sub-pixel RP and the third sub-pixel BP and the second sub-pixel GP are arranged in the first direction DR1, and the other one and the second sub-pixel GP are They may be arranged in the second direction DR2. Alternatively, any one of the first sub-pixel RP and the second sub-pixel GP and the third sub-pixel BP are arranged in the first direction DR1, and the other one and the third sub-pixel BP are They may be arranged in the second direction DR2.

The first sub-pixel RP includes a first light emitting element emitting a first light, the second sub-pixel GP includes a second light emitting element emitting a second light, and the third sub-pixel BP ) may include a third light emitting element emitting third light. Here, the first light may be light in a red wavelength band, the second light may be light in a green wavelength band, and the third light may be light in a blue wavelength band. The red wavelength band may be a wavelength band of approximately 600 nm to 750 nm, the green wavelength band may be a wavelength band of approximately 480 nm to 560 nm, and the blue wavelength band may be a wavelength band of approximately 370 nm to 460 nm. Examples are not limited to this.

Each of the first sub-pixel RP, the second sub-pixel GP, and the third sub-pixel BP may include an inorganic light emitting element having an inorganic semiconductor as a light emitting element emitting light. For example, the inorganic light emitting device may be a flip chip type micro light emitting diode (LED), but embodiments of the present specification are not limited thereto.

As shown in FIGS. 2 and 3 , the area of the first sub-pixel RP, the area of the second sub-pixel GP, and the area of the third sub-pixel BP may be substantially the same. is not limited to this. At least one of the area of the first sub-pixel RP, the area of the second sub-pixel GP, and the area of the third sub-pixel BP may be different from the other one. Alternatively, any two of the area of the first sub-pixel RP, the area of the second sub-pixel GP, and the area of the third sub-pixel BP may be substantially the same, and the other may be different from the two. can Alternatively, the area of the first sub-pixel RP, the area of the second sub-pixel GP, and the area of the third sub-pixel BP may be different from each other.

4 is a circuit diagram illustrating a first sub-pixel according to an exemplary embodiment.

Referring to FIG. 4 , the first sub-pixel RP according to an exemplary embodiment includes a kth (k is a positive integer) write scan line GWLk, a kth initialization scan line GILk, and a kth control scan line ( GCLk), the kth sweep signal line SWPLk, the kth PWM light emitting line PWELk, the kth PAM light emitting line PAELk, and the check enable signal line IEL. Also, the first sub-pixel RP according to an exemplary embodiment may be connected to the jth data line DLj and the first PAM data line RDL. In addition, the first sub-circuit unit PXC1 includes a first power line VDL1 to which a first power voltage is applied, a second power line VSL to which a second power voltage is applied, and a third power line to which a third power voltage is applied. It may be connected to the line VDL3 , the initialization voltage line VIL to which the initialization voltage VINT is applied, and the gate-off voltage line VGHL to which the gate-off voltage VGH is applied.

The first sub-pixel RP may include a first pixel driving unit PDU1 , a second pixel driving unit PDU2 , a third pixel driving unit PDU3 , a test driving unit IDU, and a first light emitting element REL. there is.

The first light emitting element REL emits light according to the driving current generated by the second pixel driver PDU2. The first light emitting element REL may be disposed between the seventeenth transistor T17 and the second power line VSL. The first electrode of the first light emitting element REL may be connected to the second electrode of the seventeenth transistor T17, and the second electrode may be connected to the second power line VSL. The first electrode of the first light emitting element REL may be an anode electrode, and the second electrode may be a cathode electrode. The first light emitting element REL may be an inorganic light emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode. For example, the first light emitting element REL may be a micro light emitting diode made of an inorganic semiconductor, but is not limited thereto.

The first pixel driver PDU1 controls the voltage of the third node N3 of the third pixel driver PDU3 by generating the control current Ic according to the j th data voltage of the j th data line DLj. Since the pulse width of the driving current flowing through the first light emitting element REL can be adjusted by the control current Ic of the first pixel driving part PDU1, the first pixel driving part PDU1 can operate on the first light emitting element REL. It may be a pulse width modulation unit (PWM unit) that performs pulse width modulation of the driving current that flows.

The first pixel driver PDU1 may include first to seventh transistors T1 to T7 and a first capacitor C1.

The first transistor T1 controls the control current Ic flowing between the second electrode and the first electrode according to the data voltage applied to the gate electrode.

The second transistor T2 is turned on by the k th write scan signal of the k th write scan line GWLk to supply the data voltage of the j th data line DLj to the first electrode of the first transistor T1. do.

The third transistor T3 is turned on by the k-th initialization scan signal of the k-th initialization scan line GILk to connect the initialization voltage line VIL to the gate electrode of the first transistor T1. Accordingly, while the third transistor T3 is turned on, the gate electrode of the first transistor T1 may be discharged to the initialization voltage VINT of the initialization voltage line VIL. The third transistor T3 may include a plurality of transistors connected in series. For example, the third transistor T3 may include a first sub-transistor T31 and a second sub-transistor T32. Accordingly, leakage of the voltage of the gate electrode of the first transistor T1 through the third transistor T3 can be minimized.

The fourth transistor T4 is turned on by the k th write scan signal of the k th write scan wire GWLk to connect the gate electrode and the second electrode of the first transistor T1 . Accordingly, the first transistor T1 may operate as a diode while the fourth transistor T4 is turned on. The fourth transistor T4 may include a plurality of transistors connected in series. For example, the fourth transistor T4 may include a third sub-transistor T41 and a fourth sub-transistor T42. Accordingly, leakage of the voltage of the gate electrode of the first transistor T1 through the fourth transistor T4 may be minimized.

The fifth transistor T5 is turned on by the k th PWM light emitting signal of the k th PWM light emitting wire PWELk to connect the first electrode of the first transistor T1 to the first power supply wire VDL1.

The sixth transistor T6 is turned on by the kth PWM light emitting signal of the kth PWM light emitting wire PWELk and connects the second electrode of the first transistor T1 to the third node of the third pixel driver PDU3 ( N3).

The seventh transistor T7 is turned on by the k th control scan signal of the k th control scan line GCLk to reduce the gate-off voltage VGH of the gate-off voltage line VGHL to the k th sweep signal line SWPLk. It can be supplied to the first node (N1) connected to. Accordingly, a period during which the initialization voltage VINT is applied to the gate electrode of the first transistor T1 and a period during which the data voltage of the j th data line DLj and the threshold voltage Vth1 of the first transistor T1 are programmed. During this time, it is possible to prevent the voltage change of the gate electrode of the first transistor T1 from being reflected to the k th sweep signal of the k th sweep signal line SWPLk by the first capacitor C1.

The first capacitor C1 may be disposed between the gate electrode of the first transistor T1 and the first node N1. One electrode of the first capacitor C1 may be connected to the gate electrode of the first transistor T1, and the other electrode may be connected to the first node N1.

The first node N1 may be a contact point of the k th sweep signal line SWPLk, the second electrode of the seventh transistor T7, and the other electrode of the first capacitor C1.

The second pixel driver PDU2 generates a driving current applied to the first light emitting element REL according to the first PAM data voltage of the first PAM data line RDL. The second pixel driver PDU2 may be a pulse amplitude modulation unit (PAM unit) that performs pulse amplitude modulation. The second pixel driver PDU2 may be a constant current generator generating a constant driving current according to the first PAM data voltage.

Also, the second pixel driver PDU2 of each of the first sub-pixels RP may receive the same first PAM data voltage and generate the same driving current regardless of the luminance of the first sub-pixel RP. Similarly, the second pixel driver PDU2 of each of the second sub-pixels GP may receive the same second PAM data voltage and generate the same second driving current regardless of the luminance of the second sub-pixel GP. there is. The third pixel driver PDU3 of each of the third sub-pixels BP may receive the same third PAM data voltage and generate the same third driving current regardless of the luminance of the third sub-pixel BP.

The second pixel driver PDU2 may include eighth to fourteenth transistors T8 to T14 and a second capacitor C2.

The eighth transistor T8 controls the driving current flowing to the first light emitting element REL according to the voltage applied to the gate electrode.

The ninth transistor T9 is turned on by the k-th write scan signal of the k-th write scan line GWLk to apply the first PAM data voltage of the first PAM data line RDL to the eighth transistor T8. 1 supplied to the electrode.

The tenth transistor T10 is turned on by the kth initialization scan signal of the kth initialization scan line GILk to connect the initialization voltage line VIL to the gate electrode of the eighth transistor T8. Accordingly, while the tenth transistor T10 is turned on, the gate electrode of the eighth transistor T8 may be discharged to the initialization voltage VINT of the initialization voltage line VIL. The tenth transistor T10 may include a plurality of transistors connected in series. For example, the tenth transistor T10 may include a fifth sub-transistor T101 and a sixth sub-transistor T102. Accordingly, leakage of the voltage of the gate electrode of the eighth transistor T8 through the tenth transistor T10 can be minimized.

The eleventh transistor T11 is turned on by the kth write scan signal of the kth write scan line GWLk to connect the gate electrode and the second electrode of the eighth transistor T8. Accordingly, the eighth transistor T8 may operate as a diode while the eleventh transistor T11 is turned on. The eleventh transistor T11 may include a plurality of transistors connected in series. For example, the eleventh transistor T11 may include a seventh sub-transistor T111 and an eighth sub-transistor T112. Accordingly, leakage of the voltage of the gate electrode of the eighth transistor T8 through the eleventh transistor T11 can be minimized.

The twelfth transistor T12 is turned on by the kth PWM light emitting signal of the kth PWM light emitting wire PWELk to connect the first electrode of the eighth transistor T8 to the second power supply wire VDL2.

The thirteenth transistor T13 is turned on by the kth control scan signal of the kth control scan line GCLk and connects the third power line VDL2 to the second node N2. Accordingly, when the thirteenth transistor T13 is turned on, the third power voltage VDD2 of the third power line VDL2 may be supplied to the second node N2.

The fourteenth transistor T14 is turned on by the kth PWM light emitting signal of the kth PWM light emitting wire PWELk and connects the first power wire VDL1 to the second node N2. Accordingly, when the fourteenth transistor T14 is turned on, the first power voltage VDD1 of the first power line VDL1 may be supplied to the second node N2.

The second capacitor C2 may be disposed between the gate electrode of the eighth transistor T8 and the second node N2. One electrode of the second capacitor C2 may be connected to the gate electrode of the eighth transistor T8, and the other electrode may be connected to the second node N2.

The second node N2 may be a contact point of the second electrode of the thirteenth transistor T13, the second electrode of the fourteenth transistor T14, and the other electrode of the second capacitor C2.

The third pixel driver PDU3 adjusts the period during which the driving current is applied to the first light emitting element REL according to the voltage of the third node N3.

The third pixel driver PDU3 may include fifteenth to nineteenth transistors T15 to T19 and a third capacitor C3.

The fifteenth transistor T15 is turned on or off according to the voltage of the third node N3. When the fifteenth transistor T15 is turned on, the driving current of the eighth transistor T8 is supplied to the first light emitting element REL, and when the fifteenth transistor T15 is turned off, the eighth transistor ( The driving current of T8) may not be supplied to the first light emitting element REL. Therefore, the turn-on period of the fifteenth transistor T15 may be substantially the same as the light emission period of the first light emitting element REL.

The sixteenth transistor T16 is turned on by the k th control scan signal of the k th control scan line GCLk and connects the initialization voltage line VIL to the third node N3. Accordingly, while the sixteenth transistor T16 is turned on, the third node N3 may be discharged with the initialization voltage of the initialization voltage line VIL. The sixteenth transistor T16 may include a plurality of transistors connected in series. For example, the sixteenth transistor T16 may include a ninth sub-transistor T161 and a tenth sub-transistor T162. Accordingly, leakage of the voltage of the third node N3 through the sixteenth transistor T16 may be minimized.

The seventeenth transistor T17 is turned on by the kth PAM emission signal of the kth PAM light emitting line PAELk to connect the second electrode of the fifteenth transistor T15 to the first electrode of the first light emitting element REL. connect

The eighteenth transistor T18 is turned on by the k th control scan signal of the k th control scan line GCLk to connect the initialization voltage line VIL to the first electrode of the first light emitting element REL. Accordingly, while the eighteenth transistor T18 is turned on, the first electrode of the first light emitting element REL may be discharged with the initialization voltage of the initialization voltage line VIL.

The nineteenth transistor T19 is turned on by the test signal of the test signal line TSTL to connect the first electrode of the first light emitting element REL to the second power line VSL.

A third capacitor C3 may be disposed between the third node N3 and the initialization voltage line VIL. One electrode of the third capacitor C3 may be connected to the third node N3 and the other electrode may be connected to the initialization voltage line VIL.

The third node N3 is the second electrode of the sixth transistor T6, the gate electrode of the fifteenth transistor T15, the first electrode of the ninth sub-transistor T161, and one electrode of the third capacitor C3. may be the contact point of

The test driver IDU may include a first test transistor T20 and a second test transistor T21. The first test transistor T20 and the second test transistor T21 are turned on by the test enable signal of the test enable signal line IEL to form the first power line VDL1 and the second power line VSL. connect

When a predetermined pressure is applied to the first light emitting element REL to attach the first light emitting element REL to the first sub-pixel RP, the first electrode of the first light emitting element REL performs the first inspection. At least one of the first electrode and the second electrode of the transistor T20 is short-circuited, and the second electrode of the first light emitting element REL is connected to one of the first electrode and the second electrode of the second inspection transistor T21. can be short-circuited. Because of this, the first light emitting element REL may not emit light as intended. That is, by forming the first inspection transistor T20 and the second inspection transistor T21, it is possible to inspect whether the first electrode or the second electrode of the first light emitting element REL is short-circuited with another electrode or wire.

Meanwhile, in FIG. 4 , the source electrode S20 of the first test transistor T20 and the source electrode S21 of the second test transistor T21 are connected to the first power line VDL1, but in the present specification Examples are not limited to this. For example, as shown in FIG. 14 , the source electrode S20 of the first test transistor T20 and the source electrode S21 of the second test transistor T21 may be connected to the third power line VDL2 .

One of the first electrode and the second electrode of each of the first to nineteenth transistors T1 to T19, the first test transistor T20, and the second test transistor T21 is a source electrode, and the other is a drain electrode. may be an electrode. The active layer of each of the first to nineteenth transistors T1 to T19, the first test transistor T20, and the second test transistor T21 is any one of poly silicon, amorphous silicon, and an oxide semiconductor. It may be formed as one. When the active layer of each of the first to nineteenth transistors T1 to T19, the first inspection transistor T20, and the second inspection transistor T21 is polysilicon, low temperature polysilicon (LTPS) can be formed through a process.

In addition, in FIG. 6, the first to nineteenth transistors T1 to T19, the first inspection transistor T20, and the second inspection transistor T21 have been mainly described as being formed of P-type MOSFETs, but in the present specification Examples are not limited to this. For example, each of the first to nineteenth transistors T1 to T19, the first test transistor T20, and the second test transistor T21 may be formed of an N-type MOSFET.

Alternatively, the first sub-transistor T31 of the third transistor T3 and the second sub-transistor ( T32), the third sub-transistor T41 and the fourth sub-transistor T42 of the fourth transistor T4, the fifth sub-transistor T101 and the sixth sub-transistor T102 of the tenth transistor T10, and The seventh sub-transistor T111 and the eighth sub-transistor T112 of the eleventh transistor T11 may be formed of an N-type MOSFET. In this case, the gate electrode of the third sub-transistor T41 of the fourth transistor T4, the gate electrode of the fourth sub-transistor T42, and the gate electrode of the seventh sub-transistor T111 of the eleventh transistor T11. and the gate electrode of the eighth sub-transistor T112 may be connected to the kth control signal. The k th initialization scan signal GILk and the k th control signal may have a pulse generated as a gate-off voltage VGH. In addition, the first sub-transistor T31 and the second sub-transistor T32 of the third transistor T3, the third sub-transistor T41 and the fourth sub-transistor T42 of the fourth transistor T4, The active layers of the fifth sub-transistor T101 and T102 of the transistor T10 and the seventh sub-transistor T111 and the eighth sub-transistor T112 of the 11th transistor T11 are oxide semiconductors. , and the remaining transistors may be formed of polysilicon.

Alternatively, one of the first sub-transistor T31 and the second sub-transistor T32 of the third transistor T3 may be formed of an N-type MOSFET, and the other may be formed of a P-type MOSFET. In this case, among the first sub-transistor T31 and the second sub-transistor T32 of the third transistor T3, a transistor formed of an N-type MOSFET is formed of an oxide semiconductor, and a transistor formed of a P-type MOSFET is formed of polysilicon. can be formed as

Alternatively, one of the third sub-transistor T41 and the fourth sub-transistor T42 of the fourth transistor T4 may be formed of an N-type MOSFET, and the other may be formed of a P-type MOSFET. In this case, among the third sub-transistor T41 and the fourth sub-transistor T42 of the fourth transistor T4, a transistor formed of an N-type MOSFET is formed of an oxide semiconductor, and a transistor formed of a P-type MOSFET is formed of polysilicon. can be formed as

Alternatively, one of the fifth sub-transistor T101 and the sixth sub-transistor T102 of the tenth transistor T10 may be formed of an N-type MOSFET, and the other may be formed of a P-type MOSFET. In this case, among the fifth sub-transistor T101 and the sixth sub-transistor T102 of the tenth transistor T10, a transistor formed of an N-type MOSFET is formed of an oxide semiconductor, and a transistor formed of a P-type MOSFET is formed of polysilicon. can be formed as

Alternatively, one of the seventh sub-transistor T111 and the eighth sub-transistor T112 of the eleventh transistor T11 may be formed of an N-type MOSFET, and the other may be formed of a P-type MOSFET. In this case, among the seventh sub-transistor T111 and the eighth sub-transistor T112 of the eleventh transistor T11, the N-type MOSFET transistor is formed of an oxide semiconductor, and the P-type MOSFET transistor is polysilicon. can be formed as

Meanwhile, the second sub-pixel GP and the third sub-pixel BP according to an exemplary embodiment may be substantially the same as the first pixel driver PXC1 described in conjunction with FIG. 6 . Therefore, descriptions of the second pixel driver PXC2 and the third pixel driver PXC3 according to the exemplary embodiment are omitted.

5 is a layout diagram illustrating a lower metal layer, an active layer, a first gate metal layer, a second gate metal layer, a first source metal layer, and a second source metal layer of a first sub-pixel according to an exemplary embodiment. 6 is a layout diagram illustrating a third source metal layer of a first sub-pixel according to an exemplary embodiment. 7 is a layout diagram illustrating a fourth source metal layer of a first sub-pixel according to an exemplary embodiment. 8 is a layout diagram illustrating a transparent electrode layer and a first light emitting element of a first sub-pixel according to an exemplary embodiment. FIG. 9 is an enlarged layout diagram showing area A of FIG. 5 in detail. FIG. 10 is an enlarged layout diagram showing area B of FIG. 5 in detail. FIG. 11 is an enlarged layout diagram showing area C of FIG. 5 in detail.

5 to 11, an initialization voltage line (VIL), a kth initialization scan line (GILk), a kth write scan line (GWLk), a kth PWM light emitting line (PWELk), a first horizontal power line (HVDL1) ), the second horizontal power line (HVDL2), the third horizontal power line (HVSL1), the fourth horizontal power line (HVSL2), the gate off voltage line (VGHL), the kth sweep signal line (SWPLk), the kth control scan The wiring GCLk, the k th PAM light emitting wiring PAELk, the test enable signal wiring IEL, and the test signal wiring TSTL extend in a first direction DR1 and are spaced apart in a second direction DR2. can be placed. The jth data line DLj, the vertical power line VVDL, and the first PAM data line RDL may extend in the second direction DR2 and be spaced apart from each other in the first direction DR1.

The first power line VDL1 may include a first main power line MVDL and a second horizontal power line HVDL2. The first main power line MVDL and the second horizontal power line HVDL2 may receive the first power voltage.

The second power line VSL may include a second main power line MVSL, a third horizontal power line HVSL1, and a fourth horizontal power line HVSL2. The second main power line MVSL, the third horizontal power line HVSL1, and the fourth horizontal power line HVSL2 may receive the second power voltage.

The third power line VDL2 may include the vertical power line VVDL and the first vertical power line HVDL1. The vertical power line VVDL and the first vertical power line HVDL1 may receive a third power voltage.

The first sub-pixel RP includes first to nineteenth transistors T1 to T19, first and second test transistors T20 and T21, first to sixth capacitor electrodes CE1 to CE6, First to seventh gate connection electrodes GCE1 to GCE7 , first and second data connection electrodes DCE1 and DCE2 , first to seventh connection electrodes CCE1 to CCE7 , first pad connection electrode ANDE1 ), a second pad connection electrode ANDE2, a third pad connection electrode APD1, a fourth pad connection electrode CPD1, a first pad electrode CTE1, and a second pad electrode CTE2.

The first transistor T1 includes a first channel CH1, a first gate electrode G1, a first source electrode S1, and a first drain electrode D1. The first channel CH1 may overlap the first gate electrode G1 in the third direction DR3. The first gate electrode G1 may be connected to the first connection electrode CCE1 through the first contact hole CT1. The first gate electrode G1 may be integrally formed with the first capacitor electrode CE1. The first gate electrode G1 may overlap the second capacitor electrode CE2 in the third direction DR3. The first source electrode S1 may be connected to the second drain electrode D2 and the fifth drain electrode D5. The first drain electrode D1 may be connected to the third sub-source electrode S41 and the sixth source electrode S6. The first source electrode S1 and the first drain electrode D1 may overlap the second capacitor electrode CE2 in the third direction DR3.

The second transistor T2 includes a second channel CH2, a second gate electrode G2, a second source electrode S2, and a second drain electrode D2. The second channel CH2 may overlap the second gate electrode G2 in the third direction DR3. The second gate electrode G2 may be integrally formed with the first gate connection electrode GCE1. The second source electrode S2 may be connected to the first data connection electrode DCE1 through the first data contact hole DCT1. The second drain electrode D2 may be connected to the first source electrode S1. The second drain electrode D2 may be connected to the first source electrode S1.

The first sub-transistor T31 of the third transistor T3 includes a first sub-channel CH31, a first sub-gate electrode G31, a first sub-source electrode S31, and a first sub-drain electrode D31. includes The first sub-channel CH31 may overlap the first sub-gate electrode G31 in the third direction DR3. The first sub-gate electrode G31 may be integrally formed with the second gate connection electrode GCE2. The first sub-source electrode S31 may be connected to the fourth sub-drain electrode D42, and the first sub-drain electrode D31 may be connected to the second sub-source electrode S32. The first sub-source electrode S31 may overlap the kth write scan wire GWLk in the third direction DR3 . The first sub-drain electrode S32 may overlap the initialization voltage line VIL in the third direction DR3.

The second sub-transistor T32 of the third transistor T3 includes a second sub-channel CH32, a second sub-gate electrode G32, a second sub-source electrode S32, and a second sub-drain electrode D32. includes The second sub-channel CH32 may overlap the second sub-gate electrode G32 in the third direction DR3. The second sub-gate electrode G32 may be integrally formed with the second gate connection electrode GCE2. The second sub-source electrode S32 may be connected to the first sub-drain electrode D31, and the second sub-drain electrode D32 may be connected to the initialization voltage line VIL through the first power contact hole VCT1. . The second sub-source electrode S32 and the second sub-drain electrode D32 may overlap the initialization voltage line VIL in the third direction DR3.

The third sub-transistor T41 of the fourth transistor T4 includes a third sub-channel CH41, a third sub-gate electrode G41, a third sub-source electrode S41, and a third sub-drain electrode D41. includes The third sub-channel CH41 may overlap the third sub-gate electrode G41 in the third direction DR3. The third sub-gate electrode G41 may be integrally formed with the first gate connection electrode GCE1. The third sub-source electrode S41 may be connected to the first drain electrode D1, and the third sub-drain electrode D41 may be connected to the fourth sub-source electrode S42.

The fourth sub-transistor T42 of the fourth transistor T4 includes a fourth sub-channel CH42, a fourth sub-gate electrode G42, a fourth sub-source electrode S42, and a fourth sub-drain electrode D42. includes The fourth sub-channel CH42 may overlap the fourth sub-gate electrode G42 in the third direction DR3. The fourth sub-gate electrode G42 may be integrally formed with the second gate connection electrode GCE2. The fourth sub-source electrode S42 may be connected to the third sub-drain electrode D32, and the fourth sub-drain electrode D42 may be connected to the first sub-source electrode S31.

The fifth transistor T5 includes a fifth channel CH5, a fifth gate electrode G5, a fifth source electrode S5, and a fifth drain electrode D5. The fifth channel CH5 may overlap the fifth gate electrode G5 in the third direction DR3. The fifth gate electrode G5 may be integrally formed with the sixth gate connection electrode GCE6. The fifth source electrode S5 may be connected to the first horizontal power line HVDL1 through the second power contact hole VCT2. The fifth drain electrode D5 may be connected to the first source electrode S1. The fifth drain electrode D5 may overlap the extension EX of the second capacitor electrode CE2 in the third direction DR3 .

The sixth transistor T6 includes a sixth channel CH6, a sixth gate electrode G6, a sixth source electrode S6, and a sixth drain electrode D6. The sixth channel CH6 may overlap the sixth gate electrode G6 in the third direction DR3. The sixth gate electrode G6 may be integrally formed with the sixth gate connection electrode GCE6. The sixth source electrode S6 may be connected to the first drain electrode D1. The sixth drain electrode D6 may be connected to the fourth connection electrode CCE4 through the tenth contact hole CT10. The sixth drain electrode D6 may overlap the second connection electrode CCE2 and the first horizontal power line HVDL1 in the third direction DR3.

The seventh transistor T7 includes a seventh channel CH7, a seventh gate electrode G7, a seventh source electrode S7, and a seventh drain electrode D7. The seventh channel CH7 may overlap the seventh gate electrode G7 in the third direction DR3. The seventh gate electrode G7 may be integrally formed with the third gate connection electrode GCE3. The seventh gate electrode G7 may overlap the initialization voltage line VIL in the third direction DR3 . The seventh source electrode S7 may be connected to the gate-off voltage line VGHL through the seventh contact hole CT7. The seventh drain electrode D7 may be connected to the k th sweep signal line SWPLk through the sixth contact hole CT6 .

The eighth transistor T8 includes an eighth channel CH8, an eighth gate electrode G8, an eighth source electrode S8, and an eighth drain electrode D8. The eighth channel CH8 may overlap the eighth gate electrode G8 in the third direction DR3. The eighth gate electrode G8 may extend in the second direction DR2. The eighth gate electrode G8 may be integrally formed with the third capacitor electrode CE3. The eighth source electrode S8 may be connected to the ninth drain electrode D9 and the twelfth drain electrode D12. The eighth drain electrode D8 may be connected to the seventh sub-source electrode S111.

The ninth transistor T9 includes a ninth channel CH9, a ninth gate electrode G9, a ninth source electrode S9, and a ninth drain electrode D9. The ninth channel CH9 may overlap the ninth gate electrode G9 in the third direction DR3. The ninth gate electrode G9 may extend in the second direction DR2. The ninth gate electrode G9 may be integrally formed with the first gate connection electrode GCE1. The ninth source electrode S9 may be connected to the second data connection electrode DCE2 through the third data contact hole DCT3. The ninth drain electrode D9 may be connected to the eighth source electrode D8.

The fifth sub-transistor T101 of the tenth transistor T10 includes a fifth sub-channel CH101, a fifth sub-gate electrode G101, a fifth sub-source electrode S101, and a fifth sub-drain electrode D101. includes The fifth sub-channel CH101 may overlap the fifth sub-gate electrode G101 in the third direction DR3. The fifth sub-gate electrode G101 may be integrally formed with the second gate connection electrode GCE2. The fifth sub-source electrode S101 may be connected to the eighth sub-drain electrode D112, and the fifth sub-drain electrode D101 may be connected to the sixth sub-source electrode S102. The fifth sub-source electrode S101 may overlap the kth write scan wire GWLk in the third direction DR3 . The fifth sub-drain electrode S102 may overlap the initialization voltage line VIL in the third direction DR3 .

The sixth sub-transistor T102 of the tenth transistor T10 includes a sixth sub-channel CH102, a sixth sub-gate electrode G102, a sixth sub-source electrode S102, and a sixth sub-drain electrode D102. includes The sixth sub-channel CH102 may overlap the sixth sub-gate electrode G102 in the third direction DR3. The sixth sub-gate electrode G102 may be integrally formed with the second gate connection electrode GCE2. The sixth sub-source electrode S102 may be connected to the fifth sub-drain electrode D101, and the sixth sub-drain electrode D102 may be connected to the initialization voltage line VIL through the first power contact hole VCT1. . The sixth sub-source electrode S102 and the sixth sub-drain electrode D102 may overlap the initialization voltage line VIL in the third direction DR3.

The seventh sub-transistor T111 of the eleventh transistor T11 includes a seventh sub-channel CH111, a seventh sub-gate electrode G111, a seventh sub-source electrode S111, and a seventh sub-drain electrode D111. includes The seventh sub-channel CH111 may overlap the seventh sub-gate electrode G111 in the third direction DR3. The seventh sub-gate electrode G111 may be integrally formed with the first gate connection electrode GCE1. The seventh sub-source electrode S111 may be connected to the eighth drain electrode D8, and the seventh sub-drain electrode D111 may be connected to the eighth sub-source electrode S112.

The eighth sub-transistor T112 of the eleventh transistor T11 includes an eighth sub-channel CH112, an eighth sub-gate electrode G112, an eighth sub-source electrode S112, and an eighth sub-drain electrode D112. includes The eighth sub-channel CH112 may overlap the eighth sub-gate electrode G112 in the third direction DR3 . The eighth sub-gate electrode G112 may be integrally formed with the first gate connection electrode GCE1. The eighth sub-source electrode S112 may be connected to the seventh sub-drain electrode D111, and the eighth sub-drain electrode D112 may be connected to the fifth sub-source electrode S101.

The twelfth transistor T12 includes a twelfth channel CH12, a twelfth gate electrode G12, a twelfth source electrode S12, and a twelfth drain electrode D12. The twelfth channel CH12 may overlap the twelfth gate electrode G12 in the third direction DR3. The twelfth gate electrode G12 may be integrally formed with the sixth gate connection electrode GCE6. The twelfth source electrode S12 may be connected to the fifth connection electrode CCE5 through the eleventh contact holes CT11.

The thirteenth transistor T13 includes a thirteenth channel CH13, a thirteenth gate electrode G13, a thirteenth source electrode S13, and a thirteenth drain electrode D13. The thirteenth channel CH13 may overlap the thirteenth gate electrode G13 in the third direction DR3. The thirteenth gate electrode G13 may be integrally formed with the third gate connection electrode GCE3. The thirteenth source electrode S13 may be connected to the first horizontal power line HVDL1 through the second power contact hole VCT2. The thirteenth drain electrode D13 may be connected to the second connection electrode CCE2 through the third contact hole CT3.

The fourteenth transistor T14 includes a fourteenth channel CH14, a fourteenth gate electrode G14, a fourteenth source electrode S14, and a fourteenth drain electrode D14. The fourteenth channel CH14 may overlap the fourteenth gate electrode G14 in the third direction DR3. The fourteenth gate electrode G14 may be integrally formed with the sixth gate connection electrode GCE6. The fourteenth source electrode S14 may be connected to the fifth connection electrode CCE5 through the eleventh contact holes CT11. The fourteenth drain electrode D14 may be connected to the second connection electrode CCE2 through the fourth contact hole CT4.

The fifteenth transistor T15 includes a fifteenth channel CH15, a fifteenth gate electrode G15, a fifteenth source electrode S15, and a fifteenth drain electrode D15. The fifteenth channel CH15 may overlap the fifteenth gate electrode G15 in the third direction DR3. The fifteenth gate electrode G15 may be integrally formed with the fifth capacitor electrode CE5. The fifteenth source electrode S15 may be connected to the ninth drain electrode D5. The fifteenth drain electrode D15 may be connected to the seventeenth source electrode S17.

The ninth sub-transistor T161 of the sixteenth transistor T16 includes a ninth sub-channel CH161, a ninth sub-gate electrode G161, a ninth sub-source electrode S161, and a ninth sub-drain electrode D161. includes The ninth sub-channel CH161 may overlap the ninth sub-gate electrode G161 in the third direction DR3. The ninth sub-gate electrode G161 may be integrally formed with the third gate connection electrode GCE3. The ninth sub-source electrode S161 may be connected to the fourth connection electrode CCE4 through the tenth contact hole CT10, and the ninth sub-drain electrode D161 may be connected to the tenth sub-source electrode S162. .

The tenth sub-transistor T162 of the sixteenth transistor T16 includes a tenth sub-channel CH162, a tenth sub-gate electrode G162, a tenth sub-source electrode S162, and a tenth sub-drain electrode D162. includes The tenth sub-channel CH162 may overlap the tenth sub-gate electrode G162 in the third direction DR3. The tenth sub-gate electrode G162 may be integrally formed with the third gate connection electrode GCE3. The tenth sub-source electrode S162 may be connected to the ninth sub-drain electrode D161, and the tenth sub-drain electrode D162 may be connected to the initialization voltage line VIL through the ninth contact hole CT9.

The seventeenth transistor T17 includes a seventeenth channel CH17, a seventeenth gate electrode G17, a seventeenth source electrode S17, and a seventeenth drain electrode D17. The seventeenth channel CH17 may overlap the seventeenth gate electrode G17 in the third direction DR3. The seventeenth gate electrode G17 may be integrally formed with the fifth gate connection electrode GCE5. The seventeenth source electrode S17 may be connected to the fifteenth drain electrode D15. The seventeenth drain electrode D17 may be connected to the seventh connection electrode CCE7 through the sixteenth contact hole CT16.

The eighteenth transistor T18 includes an eighteenth channel CH18, an eighteenth gate electrode G18, an eighteenth source electrode S18, and an eighteenth drain electrode D18. The eighteenth channel CH18 may overlap the eighteenth gate electrode G18 in the third direction DR3. The eighteenth gate electrode G18 may be integrally formed with the third gate connection electrode GCE3. The eighteenth source electrode S18 may be connected to the initialization voltage line VIL through the ninth contact hole CT9. The eighteenth drain electrode D18 may be connected to the seventh connection electrode CCE7 through the sixteenth contact hole CT16.

The nineteenth transistor T19 includes a nineteenth channel CH19, a nineteenth gate electrode G19, a nineteenth source electrode S19, and a nineteenth drain electrode D19. The nineteenth channel CH19 may overlap the nineteenth gate electrode G19 in the third direction DR3. The nineteenth gate electrode G19 may be integrally formed with the seventh gate connection electrode GCE7. The nineteenth source electrode S19 may be connected to the third connection electrode CCE3 through the twenty-first contact hole CT21. The nineteenth drain electrode D19 may be connected to the fourth horizontal power line HVSL2 through the twenty-fourth contact hole CT24.

The first inspection transistor T20 includes a first inspection channel CH20, a first inspection gate electrode G20, a first inspection source electrode S20, and a first inspection drain electrode D20. The first inspection channel CH20 may overlap the first inspection gate electrode G20 in the third direction DR3. The first inspection gate electrode G20 may be integrally formed with the eighth gate connection electrode GCE8. The first test source electrode S20 may be connected to the second horizontal power line HVDL2 through the 29th contact hole CT29. The first test drain electrode D20 may be connected to the third horizontal power line HVSL1 through the thirtieth contact hole CT30.

The second inspection transistor T21 includes a second inspection channel CH21, a second inspection gate electrode G21, a second inspection source electrode S21, and a second inspection drain electrode D21. The second inspection channel CH21 may overlap the second inspection gate electrode G21 in the third direction DR3. The second inspection gate electrode G21 may be integrally formed with the ninth gate connection electrode GCE9. The second test source electrode S21 may be connected to the second horizontal power line HVDL2 through the 32nd contact hole CT32. The second test drain electrode D21 may be connected to the third horizontal power line HVSL1 through the 33rd contact hole CT33.

The first capacitor electrode CE1 may be integrally formed with the first gate electrode G1. The second capacitor electrode CE2 may overlap the first capacitor electrode CE1 in the third direction DR3 . The first capacitor electrode CE1 may be one electrode of the first capacitor C1, and the second capacitor electrode CE2 may be the other electrode of the first capacitor C1.

The second capacitor electrode CE2 includes a hole exposing the first gate electrode G1, and the first connection electrode CCE1 connects the first gate electrode G1 through the first contact hole CT1 in the hole. can be connected to

The second capacitor electrode CE2 may include an extension portion EX extending in the second direction DR2. The extended portion EX of the second capacitor electrode CE2 may cross the kth PWM light emitting line PWELk and the first horizontal voltage line HVDL. The extension EX of the second capacitor CE2 may be connected to the k th sweep signal line SWPLk through the fifth contact hole CT5 .

The third capacitor electrode CE3 may be integrally formed with the eighth gate electrode G8. The fourth capacitor electrode CE4 may overlap the third capacitor electrode CE3 in the third direction DR3 . The third capacitor electrode CE3 may be one electrode of the second capacitor C2, and the fourth capacitor electrode CE4 may be the other electrode of the second capacitor C2.

The fourth capacitor electrode CE4 includes a hole exposing the eighth gate electrode G8, and the sixth connection electrode CCE6 connects the eighth gate electrode G8 through the twelfth contact hole CT12 in the hole. can be connected to

The fifth capacitor electrode CE5 may be integrally formed with the fourth gate connection electrode GCE4 and the fifteenth gate electrode G15. The sixth capacitor electrode CE6 may overlap the fifth capacitor electrode CE5 in the third direction DR3 . The fifth capacitor electrode CE5 may be one electrode of the third capacitor C3, and the sixth capacitor electrode CE6 may be the other electrode of the third capacitor C3. The sixth capacitor electrode CE6 may be connected to the initialization voltage line VIL through the eighteenth contact hole CT18.

The first gate connection electrode GCE1 may be connected to the kth write scan line GWLk through the first gate contact hole GCT1 and the third gate contact hole GCT3. The second gate connection electrode GCE2 may be connected to the kth initial scan line GILk through the second gate contact hole GCT2. The third gate connection electrode GCE3 may be connected to the kth control scan line GCLk through the eighth contact hole CT8. The fourth gate connection electrode GCE4 may be connected to the fourth connection electrode CCE4 through the seventeenth contact hole CT17. The fifth gate connection electrode GCE5 may be connected to the kth PAM light emitting wire PAELk through the nineteenth contact hole CT19. The sixth gate connection electrode GCE6 may be connected to the kth PWM light emitting wire PWELk through the fourteenth contact hole CT14.

The first data connection electrode DCE1 may be connected to the second source electrode S2 through the first data contact hole DCT1 and connected to the jth data line DLj through the second data contact hole DCT2. there is. The second data connection electrode DCE2 is connected to the ninth source electrode S9 through the third data contact hole DCT3 and connected to the first PAM data line RDL through the fourth data contact hole DCT4. can

The first connection electrode CCE1 may extend in the second direction DR2. The first connection electrode CCE1 is connected to the first gate electrode G1 through the first contact hole CT1, and is connected to the first sub-source electrode S31 and the fourth sub-drain through the second contact hole CT2. It may be connected to the electrode D42.

The second connection electrode CCE2 may extend in the first direction DR1. The second connection electrode CCE2 is connected to the twelfth drain electrode D12 through the third contact hole CT3 and connected to the fourteenth drain electrode D14 through the fourth contact hole CT4. It may be connected to the fourth capacitor electrode CE4 through the contact hole CT15.

The third connection electrode CCE3 may be connected to the nineteenth source electrode S19 through the twenty-first contact hole CT21 and connected to the first pad connection electrode ANDE1 through the twenty-second contact hole CT22.

The fourth connection electrode CCE4 may extend in the first direction DR1. The fourth connection electrode CCE4 is connected to the sixth drain electrode D6 and the ninth sub-source electrode S161 through the tenth contact hole CT10 and connected to the fourth gate through the seventeenth contact hole CT17. It may be connected to the electrode GCE4.

The fifth connection electrode CCE5 may extend in the first direction DR1. The fifth connection electrode CCE5 is connected to the twelfth source electrode S12 and the fourteenth source electrode S14 through the eleventh contact hole CT11, and is connected to the fourth capacitor electrode through the fourth power contact hole VDCT4. (CE4).

The sixth connection electrode CCE6 may extend in the second direction DR2. The sixth connection electrode CCE6 is connected to the third capacitor electrode CE3 through the twelfth contact hole CT12, and is connected to the fifth sub source electrode S101 and the eighth sub drain through the thirteenth contact hole CT13. It may be connected to electrode D112.

The seventh connection electrode CCE7 may be connected to the seventeenth drain electrode D17 and the eighteenth drain electrode D18 through the sixteenth contact hole CT16. The seventh connection electrode CCE7 may be connected to the first pad connection electrode ANDE1 through the twentieth contact hole CT20.

The power connection electrode VDCE may extend in the second direction DR2. The power connection electrode VDCE may be connected to the fifth connection electrode CCE5 through the fourth power contact hole VCT4.

The first pad connection electrode ANDE1 may extend in the second direction DR2 . The first pad connection electrode ANDE1 may be connected to the seventh connection electrode CCE7 through the twentieth contact hole CT20 and connected to the third connection electrode CCE3 through the twenty-second contact hole CT22.

The second pad connection electrode ANDE2 may be connected to the first pad connection electrode ANDE1 through the twenty-fifth contact hole CT25.

The third pad connection electrode APD1 may be connected to the second pad connection electrode ANDE2 through the twenty-sixth contact hole CT26.

The first main power line MVDL1 may be connected to the power connection electrode VDCE through the twenty-seventh contact hole CT27. The first main power line MVDL1 may overlap the first to nineteenth transistors T1 to T19. The first main power line MVDL1 may not overlap the first and second test transistors T20 and T21.

The second main power line MVSL may be connected to the third pad connection electrode APD2 . The second main power line MVSL may overlap the first main power line MVDL1. The second main power line MVSL may overlap the first to nineteenth transistors T1 to T19. The second main power line MVSL overlaps the second test transistor T21 but may not overlap the first test transistor T20.

Meanwhile, the layout of the second sub-pixel GP and the layout of the third sub-pixel BP according to an exemplary embodiment may be substantially the same as those of the first sub-pixel RP described in conjunction with FIGS. 5 to 11 . . Therefore, a description of the layout of the second sub-pixel GP and the layout of the third sub-pixel BP according to an exemplary embodiment will be omitted.

FIG. 12 is a cross-sectional view illustrating an example of a first sub-pixel taken along AA' of FIGS. 5 to 8 . 13 is a cross-sectional view illustrating an example of a first sub-pixel taken along line BB′ of FIGS. 5 to 8 .

Referring to FIGS. 12 and 13 , the display panel 100 may include a substrate SUB, a thin film transistor layer, and a light emitting element layer.

The substrate SUB may be made of an insulating material such as glass or polymer resin. For example, when the substrate SUB is made of a polymer resin, it may include polyimide. The substrate SUB may be a flexible substrate capable of being bent, folded, or rolled.

The buffer layer BF may be disposed on the substrate SUB. The buffer layer BF may include a plurality of inorganic layers alternately stacked. For example, the buffer layer BF may be formed of a multilayer in which at least one inorganic layer of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer is alternately stacked.

A thin film transistor layer may be disposed on the buffer layer BF. The thin film transistor layer may include first to nineteenth transistors T1 to T19 and first and second inspection transistors T20 and T21.

An active layer may be disposed on the buffer layer BF. The active layer includes channels, source electrodes, and drain electrodes of the first to nineteenth transistors T1 to T19 and the first and second test transistors T20 and T21. The active layer may include polycrystalline silicon, single crystal silicon, low-temperature polycrystalline silicon, amorphous silicon, or an oxide semiconductor.

The channels CH1 to CH21 of the first to nineteenth transistors T1 to T19 and the first and second test transistors T20 and T21 are gate electrodes G1 to G21 in the third direction DR3. can be overlapped with each other. The source electrodes S1 to S21 and the drain electrodes D1 to D21 of the first to nineteenth transistors T1 to T19 and the first and second test transistors T20 and T21 are provided in the third direction DR3. ) may not overlap with the gate electrodes G1 to G21. The source electrodes S1 to S21 and the drain electrodes D1 to D21 of the first to nineteenth transistors T1 to T19 and the first and second inspection transistors T20 and T21 are silicon semiconductors or oxide semiconductors. It may be a region having conductivity by being doped with ions.

A gate insulating layer 130 may be disposed on the active layer. The gate insulating layer 130 may be formed of an inorganic layer, such as a silicon nitride layer, a silicon oxy nitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

A first gate metal layer may be disposed on the gate insulating layer 130 . The first gate metal layer includes the first to nineteenth gate electrodes G1 to G19 of the first to nineteenth transistors T1 to T19 and the first and second inspection transistors T20 and T21. 2 inspection gate electrodes G20 and G21, a first capacitor electrode CE1, a third capacitor electrode CE3, a fifth capacitor electrode CE5, and first to ninth gate connection electrodes GCE1 to GCE9 includes The first to nineteenth gate electrodes G1 to G19, the first capacitor electrode CE1, the third capacitor electrode CE3, the fifth capacitor electrode CE5, and the first to ninth gate connection electrodes GCE1. ~GCE9) is any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or an alloy thereof It may be formed as a single layer or multiple layers consisting of.

A first interlayer insulating layer 141 may be disposed on the first gate metal layer. The first interlayer insulating layer 141 may be formed of an inorganic layer, such as a silicon nitride layer, a silicon oxy nitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

A second gate metal layer may be disposed on the first interlayer insulating layer 141 . The second gate metal layer may include a second capacitor electrode CE2 , a fourth capacitor electrode CE4 , and a sixth capacitor electrode CE6 . The second gate metal layer may be any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or any one of these. It may be formed of a single layer or multiple layers of alloys.

The second capacitor electrode CE2 overlaps the first capacitor electrode CE1 in the third direction DR3, and the fourth capacitor electrode CE4 overlaps the third capacitor electrode CE3 in the third direction DR3. And, the sixth capacitor electrode CE6 may overlap the fifth capacitor electrode CE5 in the third direction DR3. Since the first interlayer insulating film 141 has a predetermined permittivity, the first capacitor ( C1) can be formed. In addition, the second capacitor C2 may be formed by the third capacitor electrode CE3 , the fourth capacitor electrode CE4 , and the first interlayer insulating layer 141 disposed therebetween. A third capacitor C3 may be formed by the fifth capacitor electrode CE5 , the sixth capacitor electrode CE6 , and the first interlayer insulating layer 141 disposed therebetween.

A second interlayer insulating layer 142 may be disposed on the second gate metal layer. The second interlayer insulating layer 142 may be formed of an inorganic layer, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

A first source metal layer may be disposed on the second interlayer insulating layer 142 . The first source metal layer may include initialization voltage lines (VIL), a kth scan initialization line (GILk), a kth scan write line (GWLk), a kth PWM light emitting line (PWELk), a first horizontal power line (HVDL1), 2 horizontal power line (HVDL2), 3rd horizontal power line (HVSL1), 4th horizontal power line (HVSL2), gate off voltage line (VGHL), kth sweep signal line (SWPLk), kth scan control line (GCLk) ), a kth PAM light emitting line PAELk, a test enable signal line IEL, and a test signal line TSTL. Also, the first source metal layer may include first and second data connection electrodes DCE1 and DCE2 and first to seventh connection electrodes CCE1 to CCE7 . The first source metal layer is any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or any of these. It may be formed of a single layer or multiple layers of alloys.

The kth scan write line GWLk is connected to the first gate through the first gate contact hole GCT1 and the third gate contact hole GCT3 penetrating the first interlayer insulating film 141 and the second interlayer insulating film 142 . It may be connected to the electrode GCE1. The kth scan initialization line GILk may be connected to the second gate connection electrode GCE2 through the second gate contact hole GCT2 penetrating the first interlayer insulating film 141 and the second interlayer insulating film 142 . The kth scan control line GCLk may be connected to the third gate connection electrode GCE3 through the eighth contact hole CT8 penetrating the first interlayer insulating film 141 and the second interlayer insulating film 142 .

The kth PAM light emitting wire PAELk may be connected to the fifth gate connection electrode GCE5 through the 19th contact hole CT19 penetrating the first interlayer insulating film 141 and the second interlayer insulating film 142 . The kth PWM light emitting wire PWELk may be connected to the sixth gate connection electrode GCE6 through the fourteenth contact hole CT14 penetrating the first interlayer insulating film 141 and the second interlayer insulating film 142 . The test signal line TSTL may be connected to the seventh gate connection electrode GCE7 through the twenty-third contact hole CT23 penetrating the first interlayer insulating film 141 and the second interlayer insulating film 142 . The test enable signal line IEL may be connected to the eighth gate connection electrode GCE8 through the twenty-eighth contact hole CT28 penetrating the first interlayer insulating film 141 and the second interlayer insulating film 142 . The test enable signal line IEL may be connected to the ninth gate connection electrode GCE9 through the 31st contact hole CT31 penetrating the first interlayer insulating film 141 and the second interlayer insulating film 142 .

The initialization voltage line VIL is connected to the second sub-drain electrode D32 through the first power contact hole VCT1 penetrating the gate insulating layer 130 , the first interlayer insulating layer 141 , and the second interlayer insulating layer 142 . and the sixth sub-drain electrode D102. The initialization voltage line VIL is connected to the 10th sub-drain electrode D162 and the 10th sub-drain electrode D162 through the ninth contact hole CT9 penetrating the gate insulating film 130 , the first interlayer insulating film 141 , and the second interlayer insulating film 142 . It may be connected to the eighteenth drain electrode D18. The initialization voltage line VIL may be connected to the sixth capacitor electrode CE6 through the eighteenth contact hole CT18 penetrating the second interlayer insulating layer 142 . The gate off voltage line VGHL is applied to the seventh source electrode S7 through the seventh contact hole CT7 penetrating the gate insulating layer 130 , the first interlayer insulating layer 141 , and the second interlayer insulating layer 142 . can be connected

The first horizontal power line HVDL1 is formed through the second power contact hole VCT2 penetrating the gate insulating layer 130 , the first interlayer insulating layer 141 , and the second interlayer insulating layer 142 to form a fifth source electrode S5 . ) and the thirteenth source electrode S13. The fourth horizontal power line HVSL2 extends through the 24th contact hole CT24 penetrating the gate insulating layer 130 , the first interlayer insulating layer 141 , and the second interlayer insulating layer 142 to form a 19th drain electrode D19 . can be connected to

The second horizontal power line HVDL2 is formed through the 29th contact hole CT29 penetrating the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142 to form the first test source electrode S20. ) can be connected to The second horizontal power line HVDL2 is formed through the gate insulating film 130 , the first interlayer insulating film 141 , and the 32nd contact hole CT32 penetrating the second interlayer insulating film 142 to form the second test source electrode S21 . ) can be connected to

The third horizontal power line HVSL1 is formed through the thirtieth contact hole CT30 penetrating the gate insulating layer 130, the first interlayer insulating layer 141, and the second interlayer insulating layer 142 to form the first test drain electrode D20. ) can be connected to The third horizontal power line HVSL1 is formed through the 33rd contact hole CT33 penetrating the gate insulating layer 130 , the first interlayer insulating layer 141 , and the second interlayer insulating layer 142 to form the second test drain electrode D21 . ) can be connected to

The first data connection electrode DCE1 is connected to the second source electrode S2 through the first data contact hole DCT1 penetrating the gate insulating layer 130 , the first interlayer insulating layer 141 , and the second interlayer insulating layer 142 . ) can be connected to The second data connection electrode DCE2 is connected to the ninth source electrode S9 through the third data contact hole DCT3 penetrating the gate insulating layer 130 , the first interlayer insulating layer 141 , and the second interlayer insulating layer 142 . ) can be connected to

The first connection electrode CCE1 is connected to the first gate electrode G1 through the first contact hole CT1 penetrating the first interlayer insulating film 141 and the second interlayer insulating film 142 , and is connected to the gate insulating film 130 . ), and may be connected to the first sub-source electrode S31 and the fourth sub-drain electrode D42 through the second contact hole CT2 penetrating the first interlayer insulating film 141 and the second interlayer insulating film 142. there is.

The second connection electrode CCE2 is connected to the seventeenth drain electrode D17 through the third contact hole CT3 penetrating the gate insulating film 130 , the first interlayer insulating film 141 , and the second interlayer insulating film 142 . connected to the 14th drain electrode D14 through the fourth contact hole CT4 penetrating the gate insulating layer 130, the first interlayer insulating layer 141, and the second interlayer insulating layer 142; It may be connected to the fourth capacitor electrode CE4 through the fifteenth contact hole CT15 penetrating the interlayer insulating layer 142 .

The third connection electrode CCE3 is connected to the 19th source electrode S19 through the 21st contact hole CT21 penetrating the gate insulating layer 130 , the first interlayer insulating layer 141 , and the second interlayer insulating layer 142 . can be connected

The fourth connection electrode CCE4 is connected to the sixth drain electrode D6 through the tenth contact hole CT10 penetrating the gate insulating film 130 , the first interlayer insulating film 141 , and the second interlayer insulating film 142 . and may be connected to the fourth gate connection electrode GCE4 through the seventeenth contact hole CT17 penetrating the first interlayer insulating film 141 and the second interlayer insulating film 142 .

The fifth connection electrode CCE5 connects the twelfth source electrode S12 and the twelfth source electrode S12 through the eleventh contact holes CT11 penetrating the gate insulating film 130 , the first interlayer insulating film 141 , and the second interlayer insulating film 142 . It may be connected to the fourteenth source electrode S14.

The sixth connection electrode CCE6 is connected to the eighth gate electrode G8 through the twelfth contact hole CT12 penetrating the first interlayer insulating film 141 and the second interlayer insulating film 142 , and is connected to the gate insulating film 130 . ), and may be connected to the fifth sub-source electrode S101 and the eighth sub-drain electrode D112 through the thirteenth contact hole CT13 penetrating the first interlayer insulating film 141 and the second interlayer insulating film 142. there is.

The seventh connection electrode CCE7 is connected to the 17th drain electrode D17 through the 16th contact holes CT16 penetrating the gate insulating film 130 , the first interlayer insulating film 141 , and the second interlayer insulating film 142 . It may be connected to the eighteenth drain electrode D18.

A first planarization layer 160 may be disposed on the first source metal layer. The first planarization layer 160 is formed of an organic layer such as acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. It can be. The first planarization layer 160 may be referred to as an organic insulating layer.

A first inorganic insulating layer 161 may be disposed on the first planarization layer 160 . The first inorganic insulating layer 161 may be formed of an inorganic layer, such as a silicon nitride layer, a silicon oxy nitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The second interlayer insulating layer 141 may be referred to as a third insulating layer.

A second source metal layer may be disposed on the first inorganic insulating layer 161 . The second source metal layer may include a jth data line DLj, a vertical power supply line VVDL, and a first PAM data line RDL. Also, the second source metal layer may include a first pad connection electrode ANDE1 and a power connection electrode VDCE. The second source metal layer may be any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or any of these. It may be formed of a single layer or multiple layers of alloys.

The jth data line DLj may be connected to the first data connection electrode DCE1 through the second data contact hole DCT2 penetrating the first planarization layer 160 and the first inorganic insulating layer 161 . The first PAM data line RDL may be connected to the second data connection electrode DCE2 through the fourth data contact hole DCT4 penetrating the first planarization layer 160 and the first inorganic insulating layer 161 . The vertical power line VVDL may be connected to the first horizontal power line HVDL1 through the third power contact hole VCT3 penetrating the first planarization layer 160 and the first inorganic insulating layer 161 . The third power contact hole VCT3 may overlap the second power contact hole VCT2 in the third direction DR3. An area of the third power contact hole VCT3 may be larger than that of the second power contact hole VCT2.

The first pad connection electrode ANDE1 is connected to the seventh connection electrode CCE7 through the twentieth contact hole CT20 penetrating the first planarization layer 160 and the first inorganic insulating layer 161 and is connected to the first planarization layer 160 . It may be connected to the third connection electrode CCE3 through the 22nd contact hole CT22 penetrating the film 160 and the first inorganic insulating film 161 . The power connection electrode VDCE may be connected to the fifth connection electrode CCE5 through the fourth power contact hole VCT4 penetrating the first planarization layer 160 and the first inorganic insulating layer 161 .

A second planarization layer 180 may be disposed on the second source metal layer. The second planarization film 180 is formed of an organic film such as acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. It can be. The second planarization layer 180 may be referred to as an organic insulating layer.

A second inorganic insulating layer 181 may be disposed on the second planarization layer 180 . The second inorganic insulating layer 181 may be formed of an inorganic layer, such as a silicon nitride layer, a silicon oxy nitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The second interlayer insulating layer 141 may be referred to as a third insulating layer.

A third source metal layer may be disposed on the second inorganic insulating layer 181 . The third source metal layer may include the first main power line MVDL1 and the second pad connection electrode ANDE2 . The first main power line MVDL1 may be disposed to cover most of the first sub-pixel RP. The first main power line MVDL1 may be connected to the power connection electrode VDCE through the fifth power contact hole VCT5 penetrating the second planarization layer 180 and the second inorganic insulating layer 181 . The second pad connection electrode ANDE2 may be connected to the first pad connection electrode ANDE1 through the 25th contact hole CT25 penetrating the second planarization layer 180 and the second inorganic insulating layer 181 . The third source metal layer is any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or any of these. It may be formed of a single layer or multiple layers of alloys.

A third planarization layer 190 may be disposed on the third source metal layer. The third planarization layer 190 is formed of an organic layer such as acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. It can be. The third planarization layer 190 may be referred to as an organic insulating layer.

A fourth source metal layer may be disposed on the third planarization layer 190 . The fourth source metal layer may include a second main power line MVSL, a third pad connection electrode APD1, and a fourth pad connection electrode CPD1. The second main power line MVSL may be connected to the fourth pad connection electrode CPD1. That is, the second main power line MVSL and the fourth pad connection electrode CPD1 may be integrally formed. The third pad connection electrode APD1 may be connected to the second pad connection electrode ANDE2 through the twenty-sixth contact hole CT26 penetrating the third planarization layer 190 . The fourth source metal layer is any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or any one of these. It may be formed of a single layer or multiple layers of alloys.

A transparent metal layer may be disposed on the fourth source metal layer. The transparent metal layer may include a first pad electrode CTE1 and a second pad electrode CTE2. The thickness of the first pad electrode CTE1 and the thickness of the second pad electrode CTE2 may be smaller than the thickness of the third pad connection electrode APD1 and the thickness of the fourth pad connection electrode CPD1 .

The first pad electrode CTE1 may be disposed on the third pad connection electrode APD1 , and the second pad electrode CTE2 may be disposed on the fourth pad connection electrode CPD1 . The first pad electrode CTE1 is electrically connected to the first electrode of the first light emitting element REL, and the second pad electrode CTE2 is electrically connected to the second electrode of the first light emitting element REL. . The transparent metal layer may be made of a transparent conductive material (TCO) such as ITO and IZO.

A fourth planarization layer 110 may be disposed on a portion of the third pad connection electrode APD1 . The fourth planarization layer 110 may not be disposed on the first pad electrode CTE1 and the second pad electrode CTE2. That is, the first pad electrode CTE1 and the second pad electrode CTE2 may be exposed without being covered by the fourth planarization layer 110 . The fourth planarization film 110 is formed of an organic film such as acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. It can be. The fourth planarization layer 110 may be referred to as an organic insulating layer.

A fourth inorganic insulating layer 111 may be disposed on the fourth planarization layer 110 . The fourth inorganic insulating layer 111 may not be disposed on the edge of the first pad electrode CTE1 and the edge of the second pad electrode CTE2 . Therefore, at least a portion of the first pad electrode CTE1 and at least a portion of the second pad electrode CTE2 may be exposed without being covered by the fourth inorganic insulating layer 111 . The fourth inorganic insulating layer 111 may be formed of an inorganic layer, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The second interlayer insulating layer 141 may be referred to as a third insulating layer.

A light emitting element layer may be disposed on the first pad electrode CTE1 and the second pad electrode CTE2 . The light emitting device layer may include light emitting devices REL.

13 , the first electrode AE of the first light emitting element REL faces the first pad electrode CTE1, and the second electrode CE of the first light emitting element REL faces the second pad electrode CTE2. ) and a flip-chip type micro LED facing each other. The first light emitting element REL may be formed of an inorganic material such as GaN. The lengths of the first light emitting element REL in the first direction DR1 , in the second direction DR2 , and in the third direction DR3 may be several to hundreds of μm, respectively. For example, each of the lengths of the first light emitting element REL in the first direction DR1 , the second direction DR2 , and the third direction DR3 may be about 100 μm or less.

Not only the first light emitting devices REL, but also the second light emitting devices GLE and the third light emitting devices BLE may be formed by being grown on a semiconductor substrate such as a silicon wafer. The light emitting elements RLE, GLE, and BLE may be directly transferred from the silicon wafer onto the first pad electrodes CTE1 and the second pad electrodes CTE2 of the substrate SUB. Alternatively, the light emitting elements (RLE, GLE, BLE) are applied to the substrate (SUB) through an electrostatic method using an electrostatic head or a stamp method using an elastic polymer material such as PDMS or silicon as a transfer substrate. It may be moved on the first pad electrodes CTE1 and the second pad electrodes CTE2 .

The first light emitting element REL emits light including a base substrate SSUB, an n-type semiconductor NSEM, an active layer MQW, a p-type semiconductor PSEM, a first electrode AE, and a second electrode CE. can be a structure.

The base substrate SSUB may be a sapphire substrate, but embodiments of the present specification are not limited thereto.

The n-type semiconductor NSEM may be disposed on one surface of the base substrate SSUB. For example, the n-type semiconductor NSEM may be disposed on the lower surface of the base substrate SSUB. The n-type semiconductor (NSEM) may be made of GaN doped with an n-type conductive dopant such as Si, Ge, or Sn.

The active layer MQW may be disposed on a portion of one surface of the n-type semiconductor NSEM. The active layer MQW may include a material having a single or multi-quantum well structure. When the active layer MQW includes a material having a multi-quantum well structure, it may have a structure in which a plurality of well layers and barrier layers are alternately stacked. In this case, the well layer may be formed of InGaN, and the barrier layer may be formed of GaN or AlGaN, but is not limited thereto. Alternatively, the active layer (MQW) may have a structure in which semiconductor materials having a high band gap energy and semiconductor materials having a low band gap energy are alternately stacked with each other, and may be composed of other groups 3 to 4 depending on the wavelength range of emitted light. Group 5 semiconductor materials may also be included.

The p-type semiconductor PSEM may be disposed on one surface of the active layer MQW. The p-type semiconductor (PSEM) may be made of GaN doped with a p-type conductive dopant such as Mg, Zn, Ca, Se, or Ba.

The first electrode AE may be disposed on the p-type semiconductor PSEM, and the second electrode CE may be disposed on another part of one surface of the n-type semiconductor NSEM. Another part of one surface of the n-type semiconductor NSEM on which the second electrode CE is disposed may be disposed apart from a part of one surface of the n-type semiconductor NSEM on which the active layer MQW is disposed.

The first electrode AE may be adhered to the first pad electrode CTE1 through a conductive adhesive member such as an anisotropic conductive film (ACF) or an anisotropic conductive paste (ACP). Alternatively, the first electrode AE may be adhered to the first pad electrode CTE1 through a soldering process.

The second electrode CE may be adhered to the second pad electrode CTE2 through a conductive adhesive member such as an anisotropic conductive film ACF or an anisotropic conductive paste ACP. Alternatively, the second electrode CE may be adhered to the second pad electrode CTE2 through a soldering process.

In summary, the first inspection transistor T20 includes the first electrode, the first pad electrode CTE1, the third pad connection electrode APD1, and the first electrode of the first light emitting element REL in the third direction DR3. It can overlap with the PAM data line (RDL). When a predetermined pressure is applied to the first light emitting element REL to attach the first light emitting element REL to the first pad electrode CTE1, the first pad electrode CTE1 and the third pad connection electrode APD1 ), and the second planarization layer 180 and the second inorganic insulating layer 181 supporting the first PAM data line RDL may collapse.

Accordingly, the first electrode of the first light emitting element REL, the first pad electrode CTE1, the third pad connection electrode APD1, and the first PAM data line RDL are the sources of the first test transistor T20. It may be short-circuited to the second horizontal power line HVDL2 connected to the electrode S20. In this case, since a voltage of a different level than the driving voltage according to the driving current is applied to the first electrode of the first light emitting element REL, the first light emitting element REL may not emit light as intended. Alternatively, the first electrode of the first light emitting element REL, the first pad electrode CTE1, the third pad connection electrode APD1, and the first PAM data line RDL are the drain electrode of the first test transistor T20. It may be short-circuited to the third horizontal power line HVSL1 connected to (D20). In this case, since a voltage of a different level than the driving voltage according to the driving current is applied to the second electrode of the first light emitting element REL, the first light emitting element REL may not emit light as intended. That is, by forming the first inspection transistor T20 and the second inspection transistor T21, the first pad electrode CTE1 and the second pad electrode CTE2 are damaged and the first electrode of the first light emitting element REL is damaged. Alternatively, it may be inspected whether the second electrode is short-circuited with other electrodes or wires.

In addition, the second inspection transistor T21 includes the second electrode, the second pad electrode CTE2, the fourth pad connection electrode CPD, and the vertical power line of the first light emitting element REL in the third direction DR3. Can overlap with (VVDL). When a predetermined pressure is applied to the first light emitting element REL to attach the first light emitting element REL to the second pad electrode CTE2, the second pad electrode CTE2 and the fourth pad connection electrode CPD ), and the second planarization layer 180 and the second inorganic insulating layer 181 supporting the vertical power line VVDL may collapse.

Accordingly, the second electrode, the second pad electrode CTE2, the fourth pad connection electrode CPD, and the vertical power line VVDL of the first light emitting element REL are connected to the source electrode of the second inspection transistor T21. It may be short-circuited to the second horizontal power line HVDL2 connected to (S21). In this case, since a voltage of a different level than the driving voltage according to the driving current is applied to the second electrode of the first light emitting element REL, the first light emitting element REL may not emit light as intended. Alternatively, the second electrode, the second pad electrode CTE2, the fourth pad connection electrode CPD, and the vertical power line VVDL of the first light emitting element REL may be connected to the drain electrode of the second test transistor T21 ( D21) may be short-circuited to the third horizontal power line HVSL1. In this case, since a voltage of a different level than the driving voltage according to the driving current is applied to the second electrode of the first light emitting element REL, the first light emitting element REL may not emit light as intended. That is, by forming the first inspection transistor T20 and the second inspection transistor T21, the first pad electrode CTE1 and the second pad electrode CTE2 are damaged and the first electrode of the first light emitting element REL is damaged. Alternatively, it may be inspected whether the second electrode is short-circuited with other electrodes or wires.

15 is a circuit diagram illustrating a first sub-pixel according to another exemplary embodiment. 16 is a layout diagram illustrating a lower metal layer, an active layer, a first gate metal layer, a second gate metal layer, a first source metal layer, and a second source metal layer of a first sub-pixel according to another embodiment. FIG. 17 is an enlarged layout diagram showing area C of FIG. 16 in detail. 18 is a cross-sectional view illustrating an example of a first sub-pixel taken along line C-C′ of FIGS. 16 and 17 .

15 to 18 , the first test gate electrode G20 of the first test transistor T20 is connected to the first test enable signal line IEL1, and the second test transistor T21 There is a difference from the embodiments of FIGS. 4, 5, 11, and 13 in that the test gate electrode G21 is connected to the second test enable signal wire IEL2. In the embodiments of FIGS. 15 to 18, descriptions overlapping those of the embodiments of FIGS. 4, 5, 11, and 13 will be omitted.

Referring to FIG. 15 , the first test transistor T20 is turned on by the first test enable signal of the first test enable signal line IEL1 to connect the first power line VDL1 and the second power line ( VSL) is connected. The second test transistor T21 is turned on by the second test enable signal of the second test enable signal line IEL2 to connect the first power line VDL1 and the second power line VSL.

16 to 18 , the first test enable signal wire IEL1 and the second test enable signal wire IEL2 may extend in the first direction DR1. The first test enable signal line IEL1 may be disposed between the second horizontal power line HVDL2 and the second test enable signal line IEL2 in the second direction DR2 . The second test enable signal wire IEL2 may be disposed between the first test enable signal wire IEL1 and the third horizontal power supply wire HVSL1 in the second direction DR2 .

The first test enable signal wire IEL1 may be connected to the eighth gate connection electrode GCE8 through the twenty-eighth contact hole CT28 penetrating the first interlayer insulating film 141 and the second interlayer insulating film 142. . The second test enable signal wire IEL2 may be connected to the ninth gate connection electrode GCE9 through the 31st contact hole CT31 penetrating the first interlayer insulating film 141 and the second interlayer insulating film 142 . .

19 is a circuit diagram illustrating a first sub-pixel according to another exemplary embodiment. 20 is a layout diagram illustrating a lower metal layer, an active layer, a first gate metal layer, a second gate metal layer, a first source metal layer, and a second source metal layer of a first sub-pixel according to another embodiment. FIG. 21 is an enlarged layout diagram showing area C of FIG. 20 in detail. 22 is a cross-sectional view illustrating an example of a first sub-pixel taken along line D-D′ of FIGS. 20 and 21 .

In the embodiments of FIGS. 19 to 22 , a horizontal voltage line to which a predetermined voltage is applied to the first source electrode S20 of the first test transistor T20 and the second source electrode S21 of the second test transistor T21 (HVL), and the first drain electrode D20 of the first test transistor T20 and the second drain electrode D21 of the second test transistor T21 are connected to the sensing line RL. FIG. , There is a difference from the embodiment of FIGS. 5, 11, and 13. In the embodiments of FIGS. 19 to 22 , overlapping descriptions with the embodiments of FIGS. 4 , 5 , 11 , and 13 will be omitted.

Referring to FIG. 19 , the first test transistor T20 and the second test transistor T21 are turned on by the test enable signal of the test enable signal line IEL to form a horizontal voltage line HVL and a sensing line (RL). When the first test transistor T20 and the second test transistor T21 are turned on, a predetermined voltage of the horizontal voltage line HVL may be detected by the sensing line SENL. The horizontal voltage line HVL may receive a predetermined voltage. For example, the horizontal voltage line HVL includes the first power voltage of the first power line VDL1, the second power voltage of the second power line VSL, the third power voltage of the third power line VDL2, A voltage substantially equal to any one of the gate-off voltage of the gate-off voltage line VGHL and the initialization voltage of the initialization voltage line VIL may be supplied.

When a predetermined pressure is applied to the first light emitting element REL to attach the first light emitting element REL to the first sub-pixel RP, the first electrode of the first light emitting element REL performs the first inspection. At least one of the first electrode and the second electrode of the transistor T20 is short-circuited, and the second electrode of the first light emitting element REL is connected to one of the first electrode and the second electrode of the second inspection transistor T21. can be short-circuited. In this case, a voltage other than the predetermined voltage may be detected by the sensing line SENL. That is, by sensing the voltage of the sensing line SENL through the first inspection transistor T20 and the second inspection transistor T21, the first electrode or the second electrode of the first light emitting element REL is connected to another electrode or line. You can check if it is short-circuited with .

Referring to FIGS. 20 to 22 , the horizontal voltage line HVL and the sensing line SENL may extend in a first direction DR1 and be spaced apart from each other in a second direction DR2 . A test enable signal line IEL may be disposed between the horizontal voltage line HVL and the sensing line SENL in the second direction DR2 .

The first test source electrode S20 of the first test transistor T20 forms a 29th contact hole CT29 penetrating the gate insulating layer 130 , the first interlayer insulating layer 141 , and the second interlayer insulating layer 142 . It can be connected to the horizontal voltage line (HVL) through The first test drain electrode D20 of the first test transistor T20 has a thirtieth contact hole CT30 penetrating the gate insulating layer 130 , the first interlayer insulating layer 141 , and the second interlayer insulating layer 142 . It can be connected to the sensing line SENL through The second inspection source electrode S21 of the second inspection transistor T21 forms a 32nd contact hole CT32 penetrating the gate insulating film 130 , the first interlayer insulating film 141 , and the second interlayer insulating film 142 . It can be connected to the horizontal voltage line (HVL) through The second test drain electrode D21 of the second test transistor T21 forms a 33rd contact hole CT33 penetrating the gate insulating layer 130 , the first interlayer insulating layer 141 , and the second interlayer insulating layer 142 . It can be connected to the sensing line SENL through

23 is a circuit diagram illustrating a first sub-pixel according to another exemplary embodiment. 24 is a layout diagram illustrating a lower metal layer, an active layer, a first gate metal layer, a second gate metal layer, a first source metal layer, and a second source metal layer of a first sub-pixel according to another embodiment. FIG. 25 is an enlarged layout diagram showing area C of FIG. 24 in detail. 26 is a cross-sectional view illustrating an example of a first sub-pixel taken along line E-E′ of FIGS. 24 and 25 .

23 to 26 are horizontal voltage lines to which a predetermined voltage is applied to the first source electrode S20 of the first test transistor T20 and the second source electrode S21 of the second test transistor T21. (HVL), and the first drain electrode D20 of the first test transistor T20 and the second drain electrode D21 of the second test transistor T21 are connected to the sensing line RL. There is a difference from the embodiment of FIG. 18. In the embodiments of FIGS. 23 to 26, descriptions overlapping those of the embodiments of FIGS. 15 to 18 will be omitted.

Meanwhile, the first source electrode S20 of the first test transistor T20 and the second source electrode S21 of the second test transistor T21 are connected to a horizontal voltage line HVL to which a predetermined voltage is applied. The connection of the first drain electrode D20 of the first test transistor T20 and the second drain electrode D21 of the second test transistor T21 to the sensing line RL refers to the embodiments of FIGS. 19 to 22 . Since it is substantially the same as that described in connection, a description thereof will be omitted.

27 is a circuit diagram illustrating a first sub-pixel according to another exemplary embodiment. 28 is a layout diagram illustrating a lower metal layer, an active layer, a first gate metal layer, a second gate metal layer, a first source metal layer, and a second source metal layer of a first sub-pixel according to another embodiment. FIG. 29 is an enlarged layout diagram showing area C of FIG. 28 in detail. 30 is a cross-sectional view illustrating an example of a first sub-pixel taken along line F-F′ of FIGS. 28 and 29 .

The embodiments of FIGS. 27 to 30 differ from the embodiments of FIGS. 19 to 22 in that the second test transistor T21 is deleted and the variable resistor VR is disposed. In the embodiments of FIGS. 27 to 30 , descriptions overlapping those of the embodiments of FIGS. 19 to 22 will be omitted.

Referring to FIG. 27 , the first sensing transistor T20 is disposed between the first horizontal voltage line HVL1 and the first sensing line SENL1, and the variable resistor VR is connected to the second horizontal voltage line HVL2. It may be disposed between the second sensing wires SENL2. The first horizontal voltage line HVL1 and the second horizontal voltage line HVL2 may receive the same voltage. For example, the first horizontal voltage line HVL1 and the second horizontal voltage line HVL2 may include a first power voltage of the first power line VDL1, a second power voltage of the second power line VSL, and a third power voltage of the second power line VSL. A voltage substantially equal to any one of the third power supply voltage of the power line VDL2, the gate-off voltage of the gate-off voltage line VGHL, and the initialization voltage of the initialization voltage line VIL may be supplied. Alternatively, the first horizontal voltage line HVL1 and the second horizontal voltage line HVL2 may receive different voltages. For example, the first horizontal voltage line HVL1 is the first power voltage of the first power line VDL1, the second power voltage of the second power line VSL, and the third power of the third power line VDL2. Voltage, the gate-off voltage of the gate-off voltage line VGHL, and the initialization voltage of the initialization voltage line VIL are supplied with substantially the same voltage, while the second horizontal voltage line HVL2 is the first power supply. The first power voltage of the wiring VDL1, the second power voltage of the second power wiring VSL, the third power voltage of the third power wiring VDL2, the gate-off voltage of the gate-off voltage wiring VGHL, and initialization Among the initialization voltages of the voltage line VIL, a voltage different from the voltage supplied to the first horizontal voltage line HVL1 may be supplied.

When a predetermined pressure is applied to the first light emitting element REL to attach the first light emitting element REL to the first sub-pixel RP, the second electrode of the first light emitting element REL generates a variable resistance ( VR), and due to this, the resistance value of the variable resistor (VR) may change. That is, by sensing the voltage of the second sensing line SENL2 or the resistance value of the variable resistor VR, it may be inspected whether the second electrode of the first light emitting element REL is short-circuited with another electrode or line.

28 to 30 , the first horizontal voltage line HVL1, the second horizontal voltage line HVL2, the first sensing line SENL1, and the second sensing line SENL2 travel in the first direction DR1. , and may be spaced apart from each other in the second direction DR2 . The sensing enable signal line IEL may be disposed between the first horizontal voltage line HVL1 and the first sensing line SENL1.

The variable resistor VR may include a resistor unit RSU having a predetermined resistance. The resistance unit RSU may be a strain gage including a winding wire. One end of the resistor unit RSU may be connected to the second horizontal voltage line HVL2 and the other end may be connected to the second sensing line SENL2. The resistor unit RSU may overlap the first electrode, the second pad electrode CTE2 , and the fourth pad connection electrode CPD1 of the first light emitting element REL in the third direction DR3 .

The first data metal layer may include a resistor unit RSU. The resistor unit RSU may be disposed on the second interlayer insulating layer 142 .

Meanwhile, a pressure sensing layer overlapping the resistance unit RSU may be additionally disposed. The pressure sensing layer may include fine metal particles such as QTC (Quantum Tunneling Composite). For example, the pressure sensing layer may be disposed on the second interlayer insulating layer 142 and the resistor unit RSU may be disposed on the pressure sensing layer, but the exemplary embodiment of the present specification may not be limited thereto.

31 is a circuit diagram illustrating a first sub-pixel according to another exemplary embodiment. 32 is a layout diagram illustrating a lower metal layer, an active layer, a first gate metal layer, a second gate metal layer, a first source metal layer, and a second source metal layer of a first sub-pixel according to another embodiment. FIG. 33 is an enlarged layout diagram showing area C of FIG. 32 in detail. 34 is a cross-sectional view illustrating an example of a first sub-pixel taken along line G-G′ of FIGS. 32 and 33 .

In the embodiments of FIGS. 31 to 34, the first and second test transistors T20 and T21 are deleted and the first and second variable resistors VR1 and VR2 are disposed. Yes, there is a difference. In the embodiments of FIGS. 27 to 30 , descriptions overlapping those of the embodiments of FIGS. 19 to 22 will be omitted.

Referring to FIG. 31 , the first variable resistor VR1 is disposed between the first horizontal voltage line HVL1 and the first sensing line SENL1, and the second variable resistor VR2 is disposed between the second horizontal voltage line HVL2. ) and the second sensing line SENL2. The first horizontal voltage line HVL1 and the second horizontal voltage line HVL2 may receive the same voltage. For example, the first horizontal voltage line HVL1 and the second horizontal voltage line HVL2 may include a first power voltage of the first power line VDL1, a second power voltage of the second power line VSL, and a third power voltage of the second power line VSL. A voltage substantially equal to any one of the third power supply voltage of the power line VDL2, the gate-off voltage of the gate-off voltage line VGHL, and the initialization voltage of the initialization voltage line VIL may be supplied. Alternatively, the first horizontal voltage line HVL1 and the second horizontal voltage line HVL2 may receive different voltages. For example, the first horizontal voltage line HVL1 is the first power voltage of the first power line VDL1, the second power voltage of the second power line VSL, and the third power of the third power line VDL2. While receiving substantially the same voltage as any one of the voltage, the gate-off voltage of the gate-off voltage line VGHL, and the initialization voltage of the initialization voltage line VIL, the second horizontal voltage line HVL2 is the first power supply. The first power voltage of the wiring VDL1, the second power voltage of the second power wiring VSL, the third power voltage of the third power wiring VDL2, the gate-off voltage of the gate-off voltage wiring VGHL, and initialization Among the initialization voltages of the voltage line VIL, a voltage different from the voltage supplied to the first horizontal voltage line HVL1 may be supplied.

When a predetermined pressure is applied to the first light emitting element REL to attach the first light emitting element REL to the first sub-pixel RP, the first electrode of the first light emitting element REL generates a first variable The resistor VR1 may be short-circuited, or the second electrode of the first light emitting element REL may be short-circuited with the second variable resistor VR2. Accordingly, the resistance value of the first variable resistor VR1 or the resistance value of the second variable resistor VR2 may change. That is, by sensing the voltage of the first sensing line SENL1 or the resistance value of the first variable resistor VR1, it is possible to check whether the first electrode of the first light emitting element REL is short-circuited with another electrode or line. . In addition, by sensing the voltage of the second sensing line SENL2 or the resistance value of the second variable resistor VR2, it is possible to check whether the second electrode of the first light emitting element REL is short-circuited with another electrode or line. .

32 to 34 , the first horizontal voltage line HVL1, the second horizontal voltage line HVL2, the first sensing line SENL1, and the second sensing line SENL2 travel in the first direction DR1. , and may be spaced apart from each other in the second direction DR2 .

The first variable resistor VR1 may include a first resistor unit RSU1 having a predetermined resistance, and the second variable resistor VR2 may include a second resistor unit RSU2 having a predetermined resistance. Each of the first resistor unit RSU1 and the second resistor unit RSU2 may be a strain gage including a winding wire.

One end of the first resistor unit RSU1 may be connected to the first horizontal voltage line HVL1 and the other end may be connected to the first sensing line SENL1. The first resistor unit RSU1 may overlap the first electrode of the first light emitting element REL, the first pad electrode CTE1 , and the third pad connection electrode APD1 in the third direction DR3 .

One end of the second resistor unit RSU2 may be connected to the second horizontal voltage line HVL2 and the other end may be connected to the second sensing line SENL2. The second resistor unit RSU2 may overlap the second electrode, the second pad electrode CTE2, and the fourth pad connection electrode CPD1 of the first light emitting element REL in the third direction DR3.

The first data metal layer may include a first resistor unit RSU1 and a second resistor unit RSU2. The first resistor unit RSU1 and the second resistor unit RSU2 may be disposed on the second interlayer insulating layer 142 .

Meanwhile, a first pressure sensing layer overlapping the first resistance unit RSU1 and a second pressure sensing layer overlapping the second resistance unit RSU2 may be additionally disposed. Each of the first pressure sensing layer and the second pressure sensing layer may include fine metal particles such as QTC (Quantum Tunneling Composite). For example, each of the first pressure sensing layer and the second pressure sensing layer is disposed on the second interlayer insulating layer 142 , the first resistor unit RSU1 is disposed on the first pressure sensing layer, and the second resistor unit RSU1 is disposed on the first pressure sensing layer. The unit RUS2 may be disposed on the second pressure sensing layer, but embodiments of the present specification may not be limited thereto.

35 is a circuit diagram illustrating a first sub-pixel according to another embodiment. 36 is a layout diagram illustrating a lower metal layer, an active layer, a first gate metal layer, a second gate metal layer, a first source metal layer, and a second source metal layer of a first sub-pixel according to another embodiment. FIG. 37 is an enlarged layout diagram showing area C of FIG. 36 in detail. 38 is a cross-sectional view illustrating an example of a first sub-pixel taken along H-H′ of FIGS. 36 and 37 .

In the embodiments of FIGS. 35 to 38, first and second dummy transistors DT1 and DT2 are disposed instead of the first and second test transistors T20 and T21, and FIGS. 4, 5, and 11 , and there is a difference from the embodiment of FIG. In the embodiments of FIGS. 35 to 38, descriptions overlapping those of the embodiments of FIGS. 4, 5, 11, and 13 will be omitted.

35 to 38, the first dummy transistor DT1 and the second dummy transistor DT2 have their gate electrodes connected to the floating line FTL instead of the test enable signal line IEL, except for It may be substantially the same as the first test transistor T20 and the second test transistors T20 and T21 shown in FIGS. 4 , 5 , 11 , and 13 . The floating line FTL may be a line to which no signal or voltage is applied. In this case, the first dummy transistor DT1 and the second dummy transistor DT2 may remain turned off.

Alternatively, the gate electrode of the first dummy transistor DT1 and the gate electrode of the second dummy transistor DT2 may be connected to the gate off voltage line VGHL instead of the floating line FTL. In this case, the first dummy transistor DT1 and the second dummy transistor DT2 may remain turned off.

39 is a layout diagram illustrating a lower metal layer, an active layer, a first gate metal layer, a second gate metal layer, a first source metal layer, and a second source metal layer of a first sub-pixel according to another embodiment. 40 is a layout diagram illustrating a third source metal layer of a first sub-pixel according to another embodiment. 41 is a layout diagram illustrating a fourth source metal layer of a first sub-pixel according to another embodiment. 42 is a layout diagram illustrating a transparent electrode layer and a first light emitting device of a first sub-pixel according to another embodiment.

In the embodiments of FIGS. 39 to 42 , the first and second test transistors T20 and T21 are deleted, and the first light emitting element REL is partially selected from among the first to nineteenth transistors T1 to T19. There is a difference from the embodiment of FIGS. 5 to 8 in overlapping with. In FIGS. 39 to 42 , overlapping descriptions with the embodiments of FIGS. 5 to 8 are omitted.

39 to 42, the first light emitting element REL includes some of the first to nineteenth transistors T1 to T19, for example, the seventh transistor T7 and the sixteenth transistor T16. , may overlap the seventeenth transistor T17 and the eighteenth transistor T18. Also, the first pad electrode CTE1 and the third pad connection electrode APD1 may overlap the seventh transistor T7 and the seventeenth transistor T17. The second pad electrode CTE2 and the fourth pad connection electrode CPD1 may overlap the sixteenth transistor T16 and the eighteenth transistor T18.

43 is a cross-sectional view illustrating an example of a first sub-pixel taken along line II' of FIGS. 39 to 42 .

Referring to FIG. 43 , a fifth source metal layer may be disposed on the third inorganic insulating layer 191 . In the fifth source metal layer, a first reinforcement electrode SPE1 and a second reinforcement electrode SPE2 may be disposed. The first reinforcing electrode SPE1 overlaps the first pad electrode CTE1 and the third pad connection electrode APD1 in the third direction DR3, and the second reinforcing electrode SPE2 extends in the third direction DR3. It may overlap the second pad electrode CTE2 and the fourth pad connection electrode CPD.

The third inorganic insulating layer 191 may be disposed between the first reinforcement electrode SPE1 and the third pad connection electrode APD1 and between the second reinforcement electrode SPE2 and the fourth pad connection electrode CPD1 . The third inorganic insulating layer 191 may be formed of an inorganic layer, such as a silicon nitride layer, a silicon oxy nitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

When a predetermined pressure is applied to the first light emitting element REL to attach the first light emitting element REL to the first pad electrode CTE1 and the second pad electrode CTE2, the first pad electrode CTE1 , the third planarization layer 190 and the third inorganic insulating layer 191 supporting the second pad electrode CTE2 , the third pad connection electrode APD1 , and the fourth pad connection electrode CPD1 may collapse. Since the first reinforcing electrode SPE1 and the second reinforcing electrode SPE2 are electrically floating, the third planarization layer 190 and the third inorganic insulating layer 191 collapse due to the pressure applied to the first light emitting element REL. Even if the third pad connection electrode APD1 is short-circuited with the first reinforcing electrode SPE1 and the fourth pad connection electrode CPD1 is short-circuited with the second reinforcing electrode SPE2, the first light emitting element REL emits light. may not affect

In addition, the first reinforcement electrode SPE1 and the second reinforcement electrode SPE2 support the first anode pad electrode APD1 and the first cathode pad electrode CPD1 when the first light emitting element REL is pressed. Therefore, it is possible to prevent the transistors overlapping the first light emitting element REL from being damaged.

44 is an exemplary view showing a front surface of a tiled display device according to an exemplary embodiment.

Referring to FIG. 44 , a tile-type display device TD according to an exemplary embodiment may include a plurality of display devices 11, 12, 13, and 14 and a joint portion SM. For example, the tile-type display device TD may include a first display device 11 , a second display device 12 , a third display device 13 , and a fourth display device 14 .

The plurality of display devices 11, 12, 13, and 14 may be arranged in a matrix form in M (M is a positive integer) rows and N (N is a positive integer) columns. For example, the first display device 11 and the second display device 12 may be adjacent to each other in the first direction DR1 . The first display device 11 and the third display device 13 may be adjacent to each other in the second direction DR2 . The third display device 13 and the fourth display device 14 may be adjacent to each other in the first direction DR1 . The second display device 12 and the fourth display device 14 may be adjacent to each other in the second direction DR2 .

However, the number and arrangement of the plurality of display devices 11 , 12 , 13 , and 14 in the tile-type display device TD are not limited to those shown in FIG. 44 . The number and arrangement of the display devices 11 , 12 , 13 , and 14 in the tile-type display device TD are the respective sizes of the display device 10 and the tile-type display device TD and the shape of the tile-type display device TD. can be determined according to

The plurality of display devices 11, 12, 13, and 14 may have the same size, but the exemplary embodiment of the present specification is not limited thereto. For example, the plurality of display devices 11, 12, 13, and 14 may have different sizes.

Each of the plurality of display devices 11, 12, 13, and 14 may have a rectangular shape including a long side and a short side. The plurality of display devices 11 , 12 , 13 , and 14 may be disposed with long sides or short sides connected to each other. Some or all of the plurality of display devices 11 , 12 , 13 , and 14 are disposed at the edge of the tile-type display device TD and may form one side of the tile-type display device TD. At least one display device among the plurality of display devices 11 , 12 , 13 , and 14 may be disposed on at least one corner of the tile-type display device TD, and may be disposed on two adjacent sides of the tile-type display device TD. can form At least one display device among the plurality of display devices 11, 12, 13, and 14 may be surrounded by other display devices.

Each of the plurality of display devices 11, 12, 13, and 14 may be substantially the same as the display device 100 described in conjunction with FIG. 1 . Therefore, a description of each of the plurality of display devices 11, 12, 13, and 14 is omitted.

The joint SM may include a coupling member or an adhesive member. In this case, the plurality of display devices 11, 12, 13, and 14 may be connected to each other through a coupling member or an adhesive member of the joint SM. The connection portion SM is between the first display device 11 and the second display device 12, between the first display device 11 and the third display device 13, and between the second display device 12 and the fourth display device 12. It may be disposed between the display devices 14 and between the third display device 13 and the fourth display device 14 .

FIG. 45 is an enlarged layout diagram showing area H of FIG. 44 in detail.

Referring to FIG. 45 , the joint SM is a tile-type display where the first display device 11 , the second display device 12 , the third display device 13 , and the fourth display device 14 are adjacent to each other. In the central region of the device TD, it may have a planar shape of a cross, a cross, or a plus sign. The connection portion SM is between the first display device 11 and the second display device 12, between the first display device 11 and the third display device 13, and between the second display device 12 and the fourth display device 12. It may be disposed between the display devices 14 and between the third display device 13 and the fourth display device 14 .

The first display device 11 may include first pixels PX1 arranged in a matrix form in the first and second directions DR1 and DR2 to display an image. The second display device 12 may include second pixels PX2 arranged in a matrix form in the first and second directions DR1 and DR2 to display an image. The third display device 13 may include third pixels PX3 arranged in a matrix form in the first and second directions DR1 and DR2 to display an image. The fourth display device 14 may include fourth pixels PX4 arranged in a matrix form in the first and second directions DR1 and DR2 to display an image.

A minimum distance between neighboring first pixels PX1 in the first direction DR1 is defined as a first horizontal separation distance GH1, and a minimum distance between neighboring second pixels PX2 in the first direction DR1. It may be defined as the second horizontal separation distance GH2. The first horizontal separation distance GH1 and the second horizontal separation distance GH2 may be substantially the same.

A junction part SM may be disposed between the first pixel PX1 and the second pixel PX2 neighboring in the first direction DR1 . The minimum distance G12 between the first pixel PX1 and the second pixel PX2 neighboring in the first direction DR1 is between the first pixel PX1 and the joint SM in the first direction DR1. , the minimum distance GHS2 between the second pixel PX2 and the connection part SM in the first direction DR1, and the width of the connection part SM in the first direction DR1 ( It can be the sum of GSM1).

The minimum distance G12, the first horizontal separation distance GH1, and the second horizontal separation distance GH2 between the first and second pixels PX1 and PX2 neighboring in the first direction DR1 are substantially can be the same as To this end, the minimum distance GHS1 between the first pixel PX1 and the joint part SM in the first direction DR1 is smaller than the first horizontal separation distance GH1, and the second distance in the first direction DR1 is The minimum distance GHS2 between the pixel PX2 and the joint SM may be smaller than the second horizontal separation distance GH2. Also, the width GSM1 of the joint SM in the first direction DR1 may be smaller than the first horizontal separation distance GH1 or the second horizontal separation distance GH2.

The minimum distance between neighboring third pixels PX3 in the first direction DR1 is defined as the third horizontal separation distance GH3, and the minimum distance between neighboring fourth pixels PX4 in the first direction DR1 It may be defined as a fourth horizontal separation distance GH4. The third horizontal separation distance GH3 and the fourth horizontal separation distance GH4 may be substantially the same.

A junction part SM may be disposed between the third pixel PX3 and the fourth pixel PX4 neighboring in the first direction DR1 . The minimum distance G34 between the third pixel PX3 and the fourth pixel PX4 adjacent in the first direction DR1 is between the third pixel PX3 and the junction SM in the first direction DR1. , the minimum distance GHS4 between the fourth pixel PX4 and the junction SM in the first direction DR1, and the width of the junction SM in the first direction DR1 ( It can be the sum of GSM1).

The minimum distance G34, the third horizontal separation distance GH3, and the fourth horizontal separation distance GH4 between the third and fourth pixels PX3 and PX4 neighboring in the first direction DR1 are substantially can be the same as To this end, the minimum distance GHS3 between the third pixel PX3 and the joint part SM in the first direction DR1 is smaller than the third horizontal separation distance GH3, and the fourth distance in the first direction DR1 is The minimum distance GHS4 between the pixel PX4 and the joint SM may be smaller than the fourth horizontal separation distance GH4. Also, the width GSM1 of the joint SM in the first direction DR1 may be smaller than the third horizontal separation distance GH3 or the fourth horizontal separation distance GH4.

The minimum distance between neighboring first pixels PX1 in the second direction DR2 is defined as the first vertical separation distance GV1, and the minimum distance between neighboring third pixels PX3 in the second direction DR2. It may be defined as a third vertical separation distance (GV3). The first vertical separation distance GV1 and the third vertical separation distance GV3 may be substantially the same.

A junction part SM may be disposed between the first pixel PX1 and the third pixel PX3 neighboring in the second direction DR2 . The minimum distance G13 between the neighboring first and third pixels PX1 and PX3 in the second direction DR2 is between the first pixel PX1 and the junction SM in the second direction DR2. , the minimum distance GVS3 between the third pixel PX3 and the connection part SM in the second direction DR2, and the width of the connection part SM in the second direction DR2 ( may be the sum of GSM2).

The minimum distance G13, the first vertical separation distance GV1, and the third vertical separation distance GV3 between the first and third pixels PX1 and PX3 neighboring in the second direction DR2 are substantially can be the same as To this end, the minimum distance GVS1 between the first pixel PX1 and the connection portion SM in the second direction DR2 is smaller than the first vertical separation distance GV1, and the third distance in the second direction DR2 is A minimum distance GVS3 between the pixel PX3 and the joint SM may be smaller than the third vertical separation distance GV3. Also, in the second direction DR2, the width GSM2 of the joint SM may be smaller than the first vertical separation distance GV1 or the third vertical separation distance GV3.

The minimum distance between neighboring second pixels PX2 in the second direction DR2 is defined as the second vertical separation distance GV2, and the minimum distance between neighboring fourth pixels PX4 in the second direction DR2. It may be defined as a fourth vertical separation distance (GV4). The second vertical separation distance GV2 and the fourth vertical separation distance GV4 may be substantially the same.

A junction part SM may be disposed between the second pixel PX2 and the fourth pixel PX4 neighboring in the second direction DR2 . The minimum distance G24 between the second pixel PX2 and the fourth pixel PX4 neighboring in the second direction DR2 is between the second pixel PX2 and the joint SM in the second direction DR2. A minimum distance GVS2 between the fourth pixel PX4 and the junction SM in the second direction DR2, a minimum distance GVS4 between the fourth pixel PX4 and the junction SM in the second direction DR2, and a distance between the junction SM in the second direction DR2 ( may be the sum of GSM4).

The minimum distance G24, the second vertical separation distance GV2, and the fourth vertical separation distance GV4 between the second and fourth pixels PX2 and PX4 neighboring in the second direction DR2 are substantially can be the same as To this end, the minimum distance GVS2 between the second pixel PX2 and the joint part SM in the second direction DR2 is smaller than the second vertical separation distance GV2, and the fourth distance in the second direction DR2 The minimum distance GVS4 between the pixel PX4 and the joint SM may be smaller than the fourth vertical separation distance GV4 . Also, the width GSM2 of the joint SM in the second direction DR2 may be smaller than the second vertical separation distance GV2 or the fourth vertical separation distance GV4 .

As shown in FIG. 45 , the minimum distance between the pixels of the display devices adjacent to each other is not visible between the images displayed by the plurality of display devices 11, 12, 13, and 14. may be substantially equal to the minimum distance between each of the pixels.

FIG. 46 is a cross-sectional view illustrating an example of a tile-type display device taken along line J-J′ of FIG. 45 .

Referring to FIG. 46 , the first display device 11 includes a first display module DPM1 and a first front cover COV1. The second display device 12 includes a second display module DPM2 and a second front cover COV2.

Each of the first display module DPM1 and the second display module DPM2 includes a substrate SUB, a thin film transistor layer, and a light emitting element layer. The thin film transistor layer and the light emitting element layer have already been described in detail with reference to FIGS. 12 and 13 . In FIG. 46, a description overlapping with the embodiment of FIGS. 12 and 13 is omitted.

The substrate SUB has a first surface 41 on which the thin film transistor layer TFTL is disposed, a second surface 42 facing the first surface, and between the first surface 41 and the second surface 42. It may include a first side surface 43 disposed thereon. The first surface 41 may be the front or upper surface of the substrate SUB, and the second surface 42 may be the rear or lower surface of the substrate SUB.

In addition, the substrate SUB further includes a chamfer surface 44 disposed between the first surface 41 and the first side surface 43 and between the second surface 42 and the first side surface 43. can do. The thin film transistor layer TFTL and the light emitting element layer EML may not be disposed on the chamfer surface 44 . Due to the chamfer surface 44 , damage caused by collision between the substrate SUB of the first display device 10 and the substrate of the second display device 10 may be prevented.

The chamfer surface 44 is between each of the other side surfaces other than the first surface 41 and the first side surface 43 and each of the other side surfaces except the second surface 42 and the first side surface 43 It can also be placed between . For example, when the first display device 11 and the second display device 12 have a rectangular plane shape as shown in FIG. 44 , the substrate SUB has a first surface 41, a second side surface, and a third surface. It may be disposed between each of the side and the fourth side and between the second side 42 and each of the second side, the third side, and the fourth side.

The first front cover COV1 may be disposed on the chamfer surface 44 of the substrate SUB. That is, the first front cover COV1 may protrude more than the substrate SUB in the first and second directions DR1 and DR2 . Therefore, the distance GSUB between the substrate SUB of the first display device 11 and the substrate SUB of the second display device 12 is between the first front cover COV1 and the second front cover COV2. may be greater than the distance (GCOV) of

Each of the first front cover COV1 and the second front cover COV2 includes an adhesive member 51, a light transmittance control layer 52 disposed on the adhesive member 51, and a light transmittance control layer 52 disposed on the adhesive member 51. An anti-glare layer 53 may be disposed.

The adhesive member 51 of the first front cover COV1 serves to attach the light emitting element layer EML of the first display module DPM1 and the first front cover COV1. The adhesive member 51 of the second front cover COV2 serves to attach the light emitting element layer EML2 of the second display module DPM2 and the second front cover COV2. The adhesive member 51 may be a transparent adhesive member capable of transmitting light. For example, the adhesive member 51 may be an optically clear adhesive film or an optically clear resin.

The anti-glare layer 53 may be designed to diffusely reflect external light in order to prevent deterioration in visibility of an image by reflecting external light as it is. Accordingly, the contrast ratio of images displayed by the first display device 10 and the second display device 20 may be increased due to the anti-glare layer 53 .

The light transmittance adjusting layer 52 may be designed to reduce transmittance of external light or light reflected from the first display module DPM1 and the second display module DPM2. Accordingly, it is possible to prevent the gap GSUB between the substrate SUB of the first display module DPM1 and the substrate SUB of the second display module DPM2 from being visually recognized from the outside.

The anti-glare layer 53 may be implemented as a polarizing plate, and the light transmittance control layer 52 may be implemented as a phase retardation layer, but the embodiments of the present specification are not limited thereto.

Meanwhile, an example of a tile-type display device cut along K-K', L-L', and M-M' of FIG. 45 is a tile-type display device cut along J-J' described in connection with FIG. 46 . Since it is substantially the same as an example of , a description thereof is omitted.

47 is an exemplary view showing a front surface of the first display device according to an exemplary embodiment. 48 is an exemplary view showing a rear surface of the first display device according to an exemplary embodiment. 49 is a cross-sectional view illustrating an example of the first display device taken along line NN′ of FIGS. 47 and 48 .

Referring to FIGS. 47 and 48 , front display pads DPD, front inspection pads IPD, and front power pads VPD may be front pads disposed on the front surface of the substrate SUB. Front display pads DPD and front inspection pads IPD may be disposed on the upper edge of the substrate SUB, and front power pads VPD may be disposed on the lower edge of the substrate SUB. Front inspection pads (IPDs) may be disposed closer to left and right corners than front display pads (DPDs). That is, some of the front test pads (IPDs) may be disposed closer to the left edge than the front display pads (DPD), and other portions may be disposed closer to the right edge than the front display pads (DPD).

The rear display pads DBD, the rear inspection pads IBD, and the rear power supply pad VBD may be rear pads disposed on the rear surface of the substrate SUB. The rear display pads DBD and the rear inspection pad IBD may be disposed on an upper edge of the substrate SUB, and the rear power pads VBD may be disposed on a lower edge of the substrate SUB. The rear test pads IBD may be disposed closer to left and right corners than the rear display pads DBD. That is, some of the rear test pads IBD may be disposed closer to the left edge than the rear display pads DBD, and some may be disposed closer to the right edge than the rear display pads DBD.

The test multiplexer Imux may be disposed between the front test pads IPD and the sensing enable signal wires IEL, IEL1, and IEL2 and between the front test pads IPD and the sensing wires SENL, SENL1, and SENL2. can The test multiplexer (Imux) connects the front test pads (IPD) and the detection enable signal wires (IEL, IEL1, IEL2) in a 1:P (P is an integer greater than or equal to 2), and connects the front test pads (IPD) and The sensing lines SENL, SENL1, and SENL2 may be connected in a 1:P manner. Due to the test multiplexer Imux, the number of front test pads IPD can be minimized.

The display multiplexer Dmux may be disposed between the front display pads DPD and the sub-pixels RP, GP, and BP. The display multiplexer Dmux may connect the front display pads DPD1 and the data lines DL connected to the sub-pixels RP, GP, and BP in a 1:Q (where Q is an integer greater than or equal to 2). Due to the display multiplexer Dmux, the number of front display pads DPD can be minimized.

Each of the front display pads DPD may include first to fifth sub pads SPD1 , SPD2 , SPD3 , SPD4 , and SPD5 . Front inspection pads IPD and front power pads VPD may also include first to fifth sub pads SPD1 , SPD2 , SPD3 , SPD4 , and SPD5 , respectively.

The first source metal layer further includes a first sub pad SPD1 , the second source metal layer further includes a second sub pad SPD2 , and the third source metal layer further includes a third sub pad SPD3 . , The fifth source metal layer may further include a fourth sub pad SPD4 , and the transparent metal layer may further include a fifth sub pad SPD5 .

The second sub pad SPD2 may be disposed on the first sub pad SPD1, and the third sub pad SPD3 may be disposed on the second sub pad SPD2. The fourth sub pad SPD4 may be disposed on the third sub pad SPD3, and the fifth sub pad SPD5 may be disposed on the fourth sub pad SPD4. The upper surface of the first sub pad SPD1 may contact the lower surface of the second sub pad SPD2, and the upper surface of the second sub pad SPD2 may contact the lower surface of the third sub pad SPD3. The upper surface of the third sub pad SPD3 may contact the lower surface of the fourth sub pad SPD4, and the upper surface of the fourth sub pad SPD4 may contact the lower surface of the fifth sub pad SPD5.

The rear connection line BCL may be disposed on the rear surface of the substrate SUB. The rear connection wiring (BCL) is made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). It may be a single layer or multiple layers made of these alloys.

The second pad PD2 of each of the rear display pads DBD, rear test pads IBD, and rear power pad VBD is disposed at one end of the rear connection line BCL, and the third pad ( PD3) may be disposed at the other end of the rear connection line BCL. The second pad PD2 and the third pad PD3 may be formed of a transparent conductive oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO).

The fifth planarization layer 170 may be disposed on the back surface connection line BCL and the back surface of the substrate SUB. The fifth planarization film 170 is formed of an organic film such as acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. It can be. The fifth planarization layer 170 may be referred to as an organic insulating layer.

The fifth inorganic insulating layer 171 may be disposed on the fifth planarization layer 170 . The fifth inorganic insulating layer 171 may be formed of an inorganic layer, such as a silicon nitride layer, a silicon oxy nitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

The side wiring SIL is formed on the first surface FS, the first chamfered surface CS1, the first side surface SS1, the fifth chamfered surface CS5, and the second surface BS of the substrate SUB. can be placed. The side wiring SIL may be disposed on and connected to the first pad PD1 disposed at the edge of the first surface FS of the substrate SUB. The side line SIL may be disposed on the second pad PD2 disposed at the edge of the second surface BS of the substrate SUB and connected to the second pad PD2. The side wiring SIL may contact the first chamfered surface CS1 , the first side surface SS1 , and the fifth chamfered surface CS5 of the substrate SUB.

The overcoat layer OC is formed on the first surface FS, the first chamfered surface CS1, the first side surface SS1, the fifth chamfered surface CS5, and the second surface BS of the substrate SUB. can be placed. The overcoat layer OC may be disposed to cover the lateral line SIL. The overcoat layer (OC) may be formed of an organic layer such as acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. there is.

The first circuit board 310 and the second circuit board 320 may be disposed on the rear surface of the substrate SUB. The first circuit board 310 may be disposed close to the upper edge of the substrate SUB, and the second circuit board 320 may be disposed close to the lower edge of the substrate SUB. The rear connection wires of the first circuit board 310 and the second circuit board 320 are exposed through the conductive adhesive (CAM) and not covered by the fifth planarization film 170 and the fifth inorganic insulating film 171. It may be connected to the third pad PD3 of (BCL). The conductive adhesive member (CAM) may be an anisotropic conductive film or an anisotropic conductive paste.

The first driving circuit 210 may be mounted on the first circuit board 310 and the second driving circuit 220 may be mounted on the second circuit board 320 . The first driving circuit 210 and the second driving circuit 220 may be integrated circuits.

The first driving circuit 210 includes a first circuit board 310, a rear connection line (BCL), a rear display pad (DBD), a side display pad (SIL), a front display pad (DPD), and a display multiplexer (Dmux). Through this, data voltages may be output to the data lines DL. In addition, the first driving circuit 210 includes a first circuit board 310, a back connection line (BCL), a back test pad (IBD), a side test pad (SIL), a front test pad (IPD), and a test multiplexer (Imux). ), test enable signals may be output to the sensing enable signal lines IEL, IEL1, and IEL2, and sensing voltages of the sensing lines SENL, SENL1, and SENL2 may be sensed.

The second driving circuit 220 is configured through the second circuit board 320, the rear connection line (BCL), the rear power pad (VBD), the side line (SIL), and the front power pad (VPD) through the first power line ( The first power voltage is output to VDL1), the second power voltage is output to the second power line VSL, the third power voltage is output to the third power line VDL2, and the initialization voltage line VIL An initialization voltage may be output to , and a gate-off voltage may be output to the gate-off voltage line VGHL. The second driving circuit 220 may be a DC-DC converter.

50 is an exemplary diagram showing an example of a check multiplexer according to an embodiment.

50, the test multiplexer Imux includes test pad wires IPL1, IPL2, IPL3, and IPL4, test connection wires ICL1, ICL2, ICL3, and ICL4, test switch wires IWL1 to IWL12, and inspection lines IL1 to IL12. Also, the test multiplexer Imux includes a first switch group SWG1 , a second switch group SWG2 , and a third switch group SWG3 . 50 illustrates that the test multiplexer Imux connects the front test pads IPD and the test wires IL1 to IL12 in a 1:3 ratio, but the embodiment of the present specification is not limited thereto. The test wires IL1 to IL12 may correspond to the test enable signal wires IEL, IEL1, and IEL2 or to the detection wires SENL, SENL1, and SENL2.

The test pad lines IPL1 , IPL2 , IPL3 , and IPL4 may extend in the second direction DR2 . The test pad wires IPL1 , IPL2 , IPL3 , and IPL4 may be connected one-to-one to the front test pads IPD and the test connection wires ICL1 , ICL2 , ICL3 , and ICL4 . That is, the test pad wires IPL1 , IPL2 , IPL3 , and IPL4 may be connected to the front test pads IPD and the test connection wires ICL1 , ICL2 , ICL3 , and ICL4 , respectively.

The test connection lines ICL1 , ICL2 , ICL3 , and ICL4 may extend in the first direction DR1 . The test connection wires ICL1 , ICL2 , ICL3 , and ICL4 may be connected to the test switch wires IWL1 to IWL12 . The first test connection wire ICL1 may be connected to the 4k−3 (k is a positive integer) test switch wire. For example, the first test connection wire ICL1 may be connected to the first test switch wire IWL1 , the fifth test switch wire IWL5 , and the ninth test switch wire IWL9 . The second test connection wire ICL2 may be connected to the 4k-2th test switch wire. The second test connection wire ICL2 may be connected to the second test switch wire IWL2 , the sixth test switch wire IWL6 , and the tenth test switch wire IWL10 . The third test connection wire ICL3 may be connected to the 4k−1th test switch wire. The third test connection wire ICL3 may be connected to the third test switch wire IWL3 , the seventh test switch wire IWL7 , and the eleventh test switch wire IWL11 . The fourth test connection wire ICL4 may be connected to the 4k test switch wire. The fourth test connection wire ICL4 may be connected to the fourth test switch wire IWL4 , the eighth test switch wire IWL8 , and the twelfth test switch wire IWL12 .

The first switch group SWG1 may connect the first to fourth test wires IL1 to IL4 to the first to fourth test pad wires IPL1 to IPL4 through the first switch control signal SCS1. . Accordingly, the first to fourth test wires IL1 to IL4 may be connected to the first to fourth test pad wires IPL1 to IPL4 through the first switch group SWG1.

The first switch group SWG1 may include first to fourth switches SW1 to SW4. The first switch SW1 may be disposed between the first test wire IL1 and the first test switch wire IWL1. The second switch SW2 may be disposed between the second test wire IL2 and the second test switch wire IWL2. The third switch SW3 may be disposed between the third test wire IL3 and the third test switch wire IWL3. The fourth switch SW4 may be disposed between the fourth inspection line IL4 and the fourth inspection switch line IWL4.

The second switch group SWG2 may connect the fifth to eighth test wires IL5 to IL8 to the fifth to eighth test pad wires IPL5 to IPL8 through the second switch control signal SCS2. . Accordingly, the fifth to eighth test wires IL5 to IL8 may be connected to the fifth to eighth test pad wires IPL5 to IPL8 through the second switch group SWG2 .

The second switch group SWG2 may include fifth to eighth switches SW5 to SW8. The fifth switch SW5 may be disposed between the fifth test wire IL5 and the fifth test switch wire IWL5. The sixth switch SW6 may be disposed between the sixth test wire IL6 and the sixth test switch wire IWL6. The seventh switch SW7 may be disposed between the seventh test wire IL7 and the seventh test switch wire IWL7. The eighth switch SW8 may be disposed between the eighth test wire IL8 and the eighth test switch wire IWL8.

The third switch group SWG3 may connect the ninth to twelfth test wires IL9 to IL12 to the ninth to twelfth test pad wires IPL9 to IPL12 through the third switch control signal SCS3. . Accordingly, the ninth to twelfth test wires IL9 to IL12 may be connected to the ninth to twelfth test pad wires IPL9 to IPL12 through the third switch group SWG3.

The third switch group SWG3 may include ninth to twelfth switches SW9 to SW12. The ninth switch SW9 may be disposed between the ninth test wire IL9 and the ninth test switch wire IWL9. The tenth switch SW10 may be disposed between the tenth inspection wire IL10 and the tenth inspection switch wire IWL10. The eleventh switch SW11 may be disposed between the eleventh test wire IL11 and the eleventh test switch wire IWL11. The twelfth switch SW12 may be disposed between the twelfth test wire IL12 and the twelfth test switch wire IWL12.

The period during which the first to fourth switches SW1 to SW4 of the first switch group SWG1 are turned on through the first switch control signal SCS1 and the second switch through the second switch control signal SCS2 The period during which the fifth to eighth switches SW5 to SW8 of the group SWG2 are turned on and the ninth to twelfth switches of the third switch group SWG3 through the third switch control signal SCS3 The turn-on periods of (SW9 to SW12) may be different from each other. As a result, the test pad wires IPL1 to IPL4 are connected to the first to fourth test wires IL1 to IL4 through the first switch group SWG1, and the fifth test wires IL1 to IL4 through the second switch group SWG2. It is connected to the eighth test wires IL5 to IL8, and can be connected to the ninth to twelfth test wires IL9 to IL12 through the third switch group SWG3. Therefore, the test pad wires IPL1 to IPL4 are connected to the first to fourth test wires IL1 to IL4 and the fifth to eighth test wires through the first to third switch groups SWG1 , SWG2 , and SWG3 . s IL5 to IL8 and the ninth to twelfth test wires IL9 to IL12 may be sequentially connected. That is, the test multiplexer Imux may connect the front test pads IPD and the test lines IL1 to IL12 in a 1:3 ratio.

Meanwhile, since the display multiplexer Dmux may be implemented similarly to the check multiplexer Imux described in connection with FIG. 50, a detailed description of the display multiplexer Dmux is omitted.

51 is an exemplary view showing a front surface of a first display device according to another embodiment.

Referring to FIG. 51 , the front surface of the first display device 11 may be divided into a plurality of areas A1 to A9. For example, the first display device 11 may be divided into nine areas A1 to A9. The plurality of areas A1 to A9 may have a uniform area. The plurality of areas A1 to A9 may include the same number of pixels PX as each other.

In each of the plurality of regions A1 to A9, the test wires (or the sensing wires SENL, SENL1, and SENL2) may be connected to any one front test pad among the front test pads IPD1 to IPD9. For example, the test wires of the first area A1 are connected to the first front test pad IPD1, the test wires of the second area A2 are connected to the second front test pad IPD2, and the third The test wires of area A3 are connected to the third front test pad IPD3, the test wires of the fourth area A4 are connected to the fourth front test pad IPD4, and the test wires of the fifth area A5 are connected. The wires may be connected to the fifth front test pad IPD5. In addition, the test wires of the sixth area A6 are connected to the sixth front test pad IPD6, the test wires of the seventh area A7 are connected to the seventh front test pad IPD7, and the eighth area ( The test wires of A8) may be connected to the eighth front test pad IPD8, and the test wires of the ninth area A9 may be connected to the ninth front test pad IPD9.

In this case, it may be determined whether at least one of the light emitting elements of all the sub-pixels RP, GP, and BP in each of the plurality of regions A1 to A9 is short-circuited with another electrode or wiring. That is, while minimizing the number of front inspection pads, it is possible to determine in which area a light emitting element of a sub-pixel is short-circuited with another electrode or wiring.

52 is a block diagram illustrating a tiled display device according to an exemplary embodiment. 53 is an exemplary diagram illustrating wireless communication between a plurality of display devices of a tile type display device according to an exemplary embodiment.

52 illustrates the first display device 11 and the host system HOST for convenience of description.

52 and 53, the tiled display device (TD) according to an exemplary embodiment includes a host system (HOST), a broadcast tuning unit 210, a signal processing unit 220, a display unit 230, and a speaker 240. ), a user input unit 250, a HDD 260, a network communication unit 270, a UI generator 280, and a control unit 290.

The host system (HOST) may be implemented as any one of a television system, a home theater system, a set-top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), a mobile phone system, and a tablet.

A user's command may be input to the host system (HOST) in various formats. For example, the host system HOST may receive a command by a user's touch input. Alternatively, a user's command may be input to the host system HOST by inputting a keyboard or a button of a remote controller.

The host system HOST may receive original video data ODATA corresponding to an original video from the outside. The host system HOST may divide the original video data ODATA by the number of display devices. For example, the host system HOST corresponds to the first display device 11 , the second display device 12 , the third display device 13 , and the fourth display device 14 , and the original video data ( ODATA) to the first video data DATA1 corresponding to the first image, the second video data DATA2 corresponding to the second image, the third video data DATA3 corresponding to the third image, and the fourth image. It can be divided into corresponding fourth video data (DATA4). The host system HOST transmits first video data DATA1 to the first display device 11, second video data DATA2 to the second display device 12, and third video data DATA3. ) may be transmitted to the third display device 13 and fourth video data DATA4 may be transmitted to the fourth display device 14 .

The first display device 11 displays a first image according to the first video data DATA1, and the second display device 12 displays a second image according to the second video data DATA2. The display device 13 may display a third image according to the third video data DATA3, and the fourth display device 14 may display a fourth image according to the fourth video data DATA4. Accordingly, the user can watch the original image in which the first to fourth images displayed on the first to fourth display devices 11, 12, 13, and 14 are combined.

The first display device 11 includes a broadcast tuning unit 210, a signal processing unit 220, a display unit 230, a speaker 240, a user input unit 250, a HDD 260, a network communication unit 270, a UI It may include a generation unit 280 and a control unit 290.

The broadcast tuning unit 210 may tune a predetermined channel frequency under the control of the controller 290 to receive a broadcast signal of a corresponding channel through an antenna. The broadcast tuning unit 210 may include a channel detection module and an RF demodulation module.

The broadcast signal demodulated by the broadcast tuning unit 210 is processed by the signal processing unit 220 and output to the display unit 230 and the speaker 240 . Here, the signal processor 220 may include a demultiplexer 221, a video decoder 222, a video processor 223, an audio decoder 224, and an additional data processor 225.

The demultiplexer 221 separates the demodulated broadcast signal into a video signal, an audio signal, and additional data. The separated video signal, audio signal, and additional data are restored by the video decoder 222, the audio decoder 224, and the additional data processor 225, respectively. At this time, the video decoder 222, the audio decoder 224, and the additional data processing unit 225 restore a decoding format corresponding to the encoding format upon transmission of the broadcast signal.

Meanwhile, the decoded video signal is converted by the video processing unit 223 to match the vertical frequency, resolution, aspect ratio, etc. that meet the output standard of the display unit 230, and the decoded audio signal is output to the speaker 240.

The display unit 230 includes a display panel 100 on which an image is displayed and a panel driving unit that controls driving of the display panel 100 .

The user input unit 250 may receive a signal transmitted by the host system HOST. The user input unit 250 transmits commands related to communication with other display devices (DV2 to DV4) as well as data related to channel selection transmitted by the host system (HOST), UI (User Interface) menu selection and manipulation, to the user. It may be prepared so that data for selection and input can be input.

The storage unit 260 stores various software programs including OS programs, recorded broadcast programs, videos, photos, and other data, and may be formed of a storage medium such as a hard disk or non-volatile memory.

The network communication unit 270 is for short-distance communication with the host system (HOST) and other display devices (DV2 to DV4), and is a communication module including an antenna pattern capable of implementing mobile communication, data communication, Bluetooth, RF, Ethernet, and the like. can be implemented

The network communication unit 270 complies with technical standards or communication methods for mobile communication (eg, Global System for Mobile communication (GSM), Code Division Multi Access (CDMA), Code Division Multi Access 2000 (CDMA2000), EV-DO) (Enhanced Voice-Data Optimized or Enhanced Voice-Data Only), WCDMA (Wideband CDMA), HSDPA (High Speed Downlink Packet Access), HSUPA (High Speed Uplink Packet Access), LTE (Long Term Evolution), LTE-A (Long Term Evolution-Advanced), 5G, etc.) may transmit and receive radio signals with at least one of a base station, an external terminal, and a server on a mobile communication network.

The network communication unit 270 may transmit and receive wireless signals in a communication network based on wireless Internet technologies. Wireless Internet technologies include, for example, WLAN (Wireless LAN), Wi-Fi (Wireless-Fidelity), Wi-Fi (Wireless Fidelity) Direct, DLNA (Digital Living Network Alliance), WiBro (Wireless Broadband), WiMAX (World Interoperability for Microwave Access), High Speed Downlink Packet Access (HSDPA), High Speed Uplink Packet Access (HSUPA), Long Term Evolution (LTE), Long Term Evolution-Advanced (LTE-A), and the like. The antenna electrodes AE transmit and receive data according to at least one wireless Internet technology within a range including Internet technologies not listed above.

Also, the first to fourth display devices 11, 12, 13, and 14 may transmit and receive radio signals to each other as shown in FIG. 53 . That is, the first display device 11 can transmit the first radio signal RS1, and the second to fourth display devices 12, 13, and 14 can receive the first radio signal RS1. there is. In addition, the second display device 12 may transmit the second radio signal RS2, and the first, third, and fourth display devices 11, 13, and 14 transmit the second radio signal RS2. can receive In addition, the third display device 13 may transmit a third radio signal RS3, and the first, second, and fourth display devices 11, 12, and 14 transmit the third radio signal RS3. can receive In addition, the fourth display device 14 may transmit a fourth radio signal RS4, and the first to third display devices 11, 12, and 13 may receive the fourth radio signal RS4. there is.

The UI generator 280 generates a UI menu for wireless communication with the host system (HOST) and the second to fourth display devices 12, 13, and 14, and can be implemented by algorithm codes and OSD ICs. . The UI menu for communication with the host system (HOST) and the second to fourth display devices 12, 13, and 14 may be a menu for specifying a digital TV to be communicated with and selecting a desired function.

The controller 290 is in charge of overall control of the first display device 11 and is in charge of communication control of the host system HOST and the second to fourth display devices 12, 13, and 14, It can be implemented by a Micro Controller Unit (MCU) in which the corresponding algorithm code is stored and the stored algorithm code is executed.

The control unit 290 transmits corresponding control commands and data to the host system HOST and the second to fourth display devices 12, 13, and 14 through the network communication unit 270 according to input and selection by the user input unit 250. control to transmit. Of course, when a predetermined control command and data are input from the host system HOST and the second to fourth display devices 12, 13, and 14, an operation is performed according to the corresponding control command.

Although the embodiments of the present invention have been described with reference to the accompanying drawings, those skilled in the art to which the present invention pertains can be implemented in other specific forms without changing the technical spirit or essential features of the present invention. you will be able to understand Therefore, the embodiments described above should be understood as illustrative in all respects and not limiting.

10: display device 100: display panel
SUB: substrate RP, GP, BP: sub pixels
CTE1: first pad electrode CTE2: second pad electrode
REL: first light emitting element T20: first inspection transistor
T21: second test transistor IEL: test enable signal wire
RSU: Resistor SENL: Sense Wire
DT1: first dummy transistor DT2: second dummy transistor
TD: tiled indicator SM: joint
SIL: Side wiring BCL: Connection wiring

Claims (29)

A plurality of sub-pixels are provided;
Any one sub-pixel among the plurality of sub-pixels,
a first pad electrode and a second pad electrode disposed on a substrate and spaced apart from each other on a plane;
a light emitting element disposed on the first pad electrode and the second pad electrode; and
A first inspection transistor overlapping the first pad electrode in the thickness direction of the substrate;
The first inspection transistor overlaps the light emitting element in the thickness direction of the substrate. According to claim 1,
The sub-pixel further includes a second inspection transistor overlapping the second pad electrode in the thickness direction of the substrate;
The second inspection transistor overlaps the light emitting element in the thickness direction of the substrate. According to claim 2,
A gate electrode of the first test transistor and a gate electrode of the second test transistor are connected to a test enable signal line. According to claim 2,
A gate electrode of the first test transistor is connected to a first test enable signal line, and a gate electrode of the second test transistor is connected to a second test enable signal line. According to claim 2,
A first electrode of the first test transistor and a first electrode of the second test transistor are connected to a first horizontal power line to which a first power supply voltage is applied. According to claim 5,
a first data line connected to the sub-pixel and to which a first data voltage is applied; and
a second data line connected to the sub-pixel and to which a second data voltage is applied;
The sub-pixel,
a first pixel driver including a first transistor configured to control a control current according to the first data voltage of the first data line;
a second pixel driver including a second transistor configured to control a driving current flowing from a first power supply line to which the first power voltage is applied to the light emitting element according to the second data voltage of the second data line; and
and a third pixel driver including a third transistor configured to adjust a period for applying the driving current to the light emitting element according to the control current of the first pixel driver. According to claim 2,
The second electrode of the first inspection transistor and the second electrode of the second inspection transistor are connected to a second horizontal power line to which a second power supply voltage is applied. According to claim 7,
The first electrode of the light emitting element is connected to the first pad electrode, the second electrode of the light emitting element is connected to the second pad electrode, and the second pad electrode is connected to the second power supply voltage. An indicator device connected to power wiring. According to claim 2,
A first electrode of the first test transistor is connected to a horizontal voltage line, and a second electrode is connected to a sensing line. According to claim 9,
The display device of claim 1 , wherein a predetermined voltage is supplied to the horizontal voltage line. According to claim 9,
A first electrode of the second inspection transistor is connected to the horizontal voltage line, and a second electrode is connected to the sensing line. According to claim 11,
The light emitting element is a flip chip type micro light emitting diode display device. A plurality of sub-pixels are provided;
Any one sub-pixel among the plurality of sub-pixels,
a first pad electrode and a second pad electrode disposed on a substrate and spaced apart from each other on a plane;
a light emitting element disposed on the first pad electrode and the second pad electrode; and
A first resistance portion overlapping the first pad electrode in the thickness direction of the substrate;
The display device of claim 1 , wherein the first resistance part overlaps the light emitting element in the thickness direction of the substrate. According to claim 13,
a first horizontal voltage line connected to one end of the first resistance part; and
The display device further comprises a first sensing line connected to the other end of the first resistance part. According to claim 13,
The sub-pixel further includes a test transistor overlapping the second pad electrode in a thickness direction of the substrate;
The third inspection transistor overlaps the light emitting element in the thickness direction of the substrate. According to claim 15,
A gate electrode of the test transistor is connected to a test enable signal line, a first electrode is connected to a horizontal voltage line, and a second electrode is connected to a sensing line. According to claim 14,
The sub-pixel further includes a second resistor portion overlapping the second pad electrode in a thickness direction of the substrate;
The second resistor part overlaps the light emitting element in the thickness direction of the substrate. According to claim 17,
a second horizontal voltage line connected to one end of the second resistance part; and
The display device further comprises a second sensing line connected to the other end of the second resistance part. According to claim 18,
The display device of claim 1 , wherein the same voltage is supplied to the first horizontal voltage line and the second horizontal voltage line. A plurality of sub-pixels are provided;
Any one sub-pixel among the plurality of sub-pixels,
a first pad electrode and a second pad electrode disposed on a substrate and spaced apart from each other on a plane;
a light emitting element disposed on the first pad electrode and the second pad electrode; and
a first dummy transistor overlapping the first pad electrode in the thickness direction of the substrate;
the first dummy transistor overlaps the light emitting element in the thickness direction of the substrate;
A gate electrode of the first dummy transistor is connected to a floating line or a gate-off voltage line to which a gate-off voltage is applied. According to claim 20,
The sub-pixel further includes a second dummy transistor overlapping the second pad electrode in a thickness direction of the substrate;
The second dummy transistor overlaps the light emitting element in the thickness direction of the substrate. According to claim 21,
A gate electrode of the second dummy transistor is connected to the floating line or the gate-off voltage line. According to claim 13,
The light emitting element is a flip chip type micro light emitting diode display device. a plurality of display devices; and
a joint portion disposed between the plurality of display devices;
Among the plurality of display devices, a first display device includes a plurality of sub-pixels;
Any one sub-pixel among the plurality of sub-pixels,
a first pad electrode and a second pad electrode disposed on a substrate and spaced apart from each other on a plane;
a light emitting element disposed on the first pad electrode and the second pad electrode;
a first thin film transistor overlapping the first pad electrode in the thickness direction of the substrate;
A second thin film transistor overlapping the second pad electrode in the thickness direction of the substrate;
Each of the first thin film transistor and the second thin film transistor overlaps the light emitting element in a thickness direction of the substrate. According to claim 24,
The light emitting device is a flip chip type micro light emitting diode device. According to claim 24,
The first display device,
Board;
a pad disposed on the first surface of the substrate; and
A tile type further comprising a side wiring disposed on a first surface of the substrate, a second surface opposite to the first surface, and a side surface between the first surface and the second surface and connected to the pad. display device. 27. The method of claim 26,
The substrate is a tile-type display device made of glass. 27. The method of claim 26,
The first display device,
a connection wire disposed on the second surface of the substrate; and
Further comprising a flexible film connected to the connection wire through a conductive adhesive member,
The side wiring is connected to the connection wiring. According to claim 24,
The plurality of display devices are arranged in a matrix form in M (M is a positive integer) rows and N (N is a positive integer) columns.

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