CN116525590A

CN116525590A - Display device and flat display device

Info

Publication number: CN116525590A
Application number: CN202310096255.1A
Authority: CN
Inventors: 卜胜龙; 金玄俊
Original assignee: Samsung Display Co Ltd
Current assignee: Samsung Display Co Ltd
Priority date: 2022-01-28
Filing date: 2023-01-19
Publication date: 2023-08-01

Abstract

The present disclosure relates to a display device and a flat display device. The display device includes a plurality of sub-pixels, wherein one of the plurality of sub-pixels includes: a first pad electrode and a second pad electrode on the substrate and spaced apart from each other in a plan view; a light emitting device on the first and second pad electrodes; and a first inspection transistor overlapping the first pad electrode in a thickness direction of the substrate, wherein the first inspection transistor overlaps the light emitting device in the thickness direction of the substrate.

Description

Display device and flat display device

Technical Field

The present disclosure relates to a display device and a flat display device.

Background

With the development of information-oriented society, there is an increasing demand for display devices for displaying images in various ways. When the display apparatus is manufactured in a large size, a defect rate of the light emitting device may increase due to an increase in the number of pixels, and productivity or reliability may decrease. In order to solve this problem, a tiled display device in which a large screen is realized by connecting a plurality of display devices having relatively small sizes has been developed.

The display device may be a flat panel display device such as a liquid crystal display, a field emission display, and a light emitting display. The light emitting display device may include an organic light emitting diode display including an Organic Light Emitting Diode (OLED) as a light emitting element or an inorganic light emitting diode display including an inorganic light emitting diode as a light emitting element. In the case of an inorganic light emitting diode display, when the inorganic light emitting diode device is bonded to a display panel, the pad electrode may be damaged by bonding pressure.

Disclosure of Invention

Aspects and features of embodiments of the present disclosure provide a display device capable of checking for damage to a pad electrode.

Aspects and features of embodiments of the present disclosure provide a tiled display device capable of inspecting for damage to a pad electrode.

However, embodiments of the present disclosure are not limited to the embodiments set forth herein. The above and other embodiments of the present disclosure will become more readily apparent to those of ordinary skill in the art to which the present disclosure pertains by referencing the detailed description of the present disclosure given below.

According to one or more embodiments of the present disclosure, there is provided a display device including a plurality of sub-pixels. The sub-pixels of the plurality of sub-pixels include: a first pad electrode and a second pad electrode on the substrate and spaced apart from each other in a plan view; a light emitting device on the first and second pad electrodes; and a first inspection transistor overlapping the first pad electrode in a thickness direction of the substrate. The first inspection transistor overlaps the light emitting device in the thickness direction of the substrate.

The sub-pixel may further include a second inspection transistor overlapping the second pad electrode in a thickness direction of the substrate. The second inspection transistor may overlap the light emitting device in a thickness direction of the substrate.

The gate electrode of the first inspection transistor and the gate electrode of the second inspection transistor may be connected to an inspection enable signal line.

The gate electrode of the first check transistor may be connected to the first check enable signal line, and the gate electrode of the second check transistor may be connected to the second check enable signal line.

The first electrode of the first inspection transistor and the first electrode of the second inspection transistor may be connected to a first horizontal power line configured to receive a first power voltage.

The display device may further include: a first data line connected to the sub-pixel and configured to receive a first data voltage; and a second data line connected to the sub-pixel and configured to receive a second data voltage. The sub-pixel may further include: a first pixel driver including a first transistor configured to control a control current according to a first data voltage of a first data line; a second pixel driver including a second transistor configured to control a driving current flowing from a first power line to the light emitting device according to a second data voltage of a second data line, the first power line configured to receive the first power voltage; and a third pixel driver including a third transistor configured to adjust a period in which the driving current is applied to the light emitting device according to the control current of the first pixel driver.

The second electrode of the first inspection transistor and the second electrode of the second inspection transistor may be connected to a second horizontal power line configured to receive a second power voltage.

The first electrode of the light emitting device may be connected to the first pad electrode, the second electrode of the light emitting device may be connected to the second pad electrode, and the second pad electrode may be connected to a second power line configured to receive a second power voltage.

The first electrode of the first check transistor may be connected to a horizontal voltage line, and the second electrode of the first check transistor may be connected to a sensing line.

The horizontal voltage line is configured to receive a predetermined voltage.

The first electrode of the second check transistor may be connected to a horizontal voltage line, and the second electrode of the second check transistor may be connected to a sensing line.

The light emitting device may be a flip chip type micro light emitting diode device.

According to one or more embodiments of the present disclosure, there is provided a display device including a plurality of sub-pixels. The sub-pixels of the plurality of sub-pixels include: a first pad electrode and a second pad electrode on the substrate and spaced apart from each other in a plan view; a light emitting device on the first and second pad electrodes; and a first resistor unit overlapping the first pad electrode in a thickness direction of the substrate. The first resistor unit overlaps the light emitting device in a thickness direction of the substrate.

The display device may further include a first horizontal voltage line connected to one end of the first resistor unit, and a first sensing line connected to the other end of the first resistor unit.

The sub-pixel may further include an inspection transistor overlapping the second pad electrode in a thickness direction of the substrate. The inspection transistor may overlap the light emitting device in a thickness direction of the substrate.

The gate electrode of the check transistor may be connected to the check enable signal line, and the first electrode of the check transistor may be connected to the horizontal voltage line, and the second electrode of the check transistor is connected to the sensing line.

The sub-pixel may further include a second resistor unit overlapping the second pad electrode in a thickness direction of the substrate. The second resistor unit may overlap the light emitting device in a thickness direction of the substrate.

The display device may further include a second horizontal voltage line connected to one end of the second resistor unit, and a second sensing line connected to the other end of the second resistor unit.

The same voltage may be supplied to the first and second horizontal voltage lines.

According to one or more embodiments of the present disclosure, there is provided a display device including a plurality of sub-pixels. The sub-pixels of the plurality of sub-pixels include: a first pad electrode and a second pad electrode on the substrate and spaced apart from each other in a plan view; a light emitting device on the first and second pad electrodes; and a first dummy transistor overlapping the first pad electrode in a thickness direction of the substrate. The first dummy transistor overlaps the light emitting device in a thickness direction of the substrate. The gate electrode of the first dummy transistor is connected to a floating line or a gate-off voltage line configured to receive a gate-off voltage.

The sub-pixel may further include a second dummy transistor overlapping the second pad electrode in a thickness direction of the substrate. The second dummy transistor may overlap the light emitting device in a thickness direction of the substrate.

The gate electrode of the second dummy transistor may be connected to a floating line or a gate-off voltage line.

According to one or more embodiments of the present disclosure, there is provided a tiled display device including a plurality of display devices and a connection member between the plurality of display devices. A first display device of the plurality of display devices includes a plurality of subpixels. The sub-pixels of the plurality of sub-pixels include: a first pad electrode and a second pad electrode on the substrate and spaced apart from each other in a plan view; a light emitting device on the first and second pad electrodes; a first inspection transistor overlapping the first pad electrode in a thickness direction of the substrate; and a second inspection transistor overlapping the second pad electrode in a thickness direction of the substrate. Each of the first inspection transistor and the second inspection transistor overlaps the light emitting device in a thickness direction of the substrate.

The first display device may further include: a pad on the first surface of the substrate; and a lateral line on the first surface of the substrate, the second surface opposite to the first surface, and one lateral surface between the first surface and the second surface, and connected to the pad.

The substrate may comprise glass.

The first display device may further include a connection line on the second surface of the substrate, and a circuit board connected to the connection line through the conductive adhesive member. The lateral line may be connected to the connection line.

The plurality of display devices may be arranged in a matrix form of M (M is a positive integer) rows and N (N is a positive integer) columns.

According to the foregoing and other embodiments of the present disclosure, by disposing the test transistor to overlap the light emitting device, damage to the pad electrode that may occur when a predetermined pressure is applied to the light emitting device to attach the light emitting device to the pad electrode may be inspected.

According to the foregoing and other embodiments of the present disclosure, by disposing the variable resistor to overlap the light emitting device, it is possible to check whether the pad electrode, which may occur when a predetermined pressure is applied to the light emitting device to attach the light emitting device to the pad electrode, is damaged.

Drawings

The above and other embodiments and features of the present disclosure will become more apparent by describing embodiments thereof with reference to the accompanying drawings.

Fig. 1 is a layout diagram illustrating a display device according to one or more embodiments.

Fig. 2 is a diagram illustrating an example of the pixel of fig. 1.

Fig. 3 is a diagram illustrating another example of the pixel of fig. 1.

Fig. 4 is a circuit diagram illustrating a first subpixel in accordance with one or more embodiments.

Fig. 5 is a layout diagram illustrating a lower metal layer, an active layer, a first gate metal layer, a second gate metal layer, a first source metal layer, and a second source metal layer of a first subpixel according to one or more embodiments.

Fig. 6 is a layout diagram illustrating a third source metal layer of a first subpixel in accordance with one or more embodiments.

Fig. 7 is a layout diagram illustrating a fourth source metal layer of a first subpixel in accordance with one or more embodiments.

Fig. 8 is a layout diagram illustrating a transparent electrode layer and a first light emitting device of a first subpixel according to one or more embodiments.

Fig. 9 is an enlarged layout diagram showing the area a of fig. 5 in detail.

Fig. 10 is an enlarged layout diagram showing the region B of fig. 5 in detail.

Fig. 11 is an enlarged layout diagram showing the region C of fig. 5 in detail.

Fig. 12 is a cross-sectional view showing an example of the first sub-pixel taken along the line A-A' of fig. 5 to 8.

Fig. 13 is a cross-sectional view showing an example of the first sub-pixel taken along the line B-B' of fig. 5 to 8.

Fig. 14 is a circuit diagram illustrating a first subpixel in accordance with one or more embodiments.

Fig. 15 is a circuit diagram illustrating a first subpixel in accordance with one or more embodiments.

Fig. 16 is a layout diagram illustrating a lower metal layer, an active layer, a first gate metal layer, a second gate metal layer, a first source metal layer, and a second source metal layer of a first subpixel according to one or more embodiments.

Fig. 17 is an enlarged layout diagram showing the region C of fig. 16 in detail.

Fig. 18 is a cross-sectional view showing an example of the first sub-pixel taken along the line C-C' of fig. 16 and 17.

Fig. 19 is a circuit diagram illustrating a first subpixel in accordance with one or more embodiments.

Fig. 20 is a layout diagram illustrating a lower metal layer, an active layer, a first gate metal layer, a second gate metal layer, a first source metal layer, and a second source metal layer of a first subpixel according to one or more embodiments.

Fig. 21 is an enlarged layout diagram showing the region C of fig. 20 in detail.

Fig. 22 is a cross-sectional view showing an example of the first sub-pixel taken along the line D-D' of fig. 20 and 21.

Fig. 23 is a circuit diagram illustrating a first subpixel in accordance with one or more embodiments.

Fig. 24 is a layout diagram illustrating a lower metal layer, an active layer, a first gate metal layer, a second gate metal layer, a first source metal layer, and a second source metal layer of a first subpixel according to one or more embodiments.

Fig. 25 is an enlarged layout diagram showing the region C of fig. 24 in detail.

Fig. 26 is a cross-sectional view showing an example of the first sub-pixel taken along line E-E' of fig. 24 and 25.

Fig. 27 is a circuit diagram illustrating a first sub-pixel in accordance with one or more embodiments.

Fig. 28 is a layout diagram illustrating a lower metal layer, an active layer, a first gate metal layer, a second gate metal layer, a first source metal layer, and a second source metal layer of a first subpixel according to one or more embodiments.

Fig. 29 is an enlarged layout diagram showing the region C of fig. 28 in detail.

Fig. 30 is a cross-sectional view showing an example of the first sub-pixel taken along the line F-F' of fig. 28 and 29.

Fig. 31 is a circuit diagram illustrating a first subpixel in accordance with one or more embodiments.

Fig. 32 is a layout diagram illustrating a lower metal layer, an active layer, a first gate metal layer, a second gate metal layer, a first source metal layer, and a second source metal layer of a first subpixel according to one or more embodiments.

Fig. 33 is an enlarged layout diagram showing the region C of fig. 32 in detail.

Fig. 34 is a cross-sectional view showing an example of the first sub-pixel taken along the line G-G' of fig. 32 and 33.

Fig. 35 is a circuit diagram illustrating a first subpixel in accordance with one or more embodiments.

Fig. 36 is a layout diagram illustrating a lower metal layer, an active layer, a first gate metal layer, a second gate metal layer, a first source metal layer, and a second source metal layer of a first subpixel according to one or more embodiments.

Fig. 37 is an enlarged layout diagram showing the region C of fig. 36 in detail.

Fig. 38 is a cross-sectional view showing an example of the first sub-pixel taken along the line H-H' of fig. 36 and 37.

Fig. 39 is a layout diagram illustrating a lower metal layer, an active layer, a first gate metal layer, a second gate metal layer, a first source metal layer, and a second source metal layer of a first subpixel according to one or more embodiments.

Fig. 40 is a layout diagram illustrating a third source metal layer of a first subpixel in accordance with one or more embodiments.

Fig. 41 is a layout diagram illustrating a fourth source metal layer of a first subpixel in accordance with one or more embodiments.

Fig. 42 is a layout diagram illustrating a transparent electrode layer and a first light emitting device of a first sub-pixel according to one or more embodiments.

Fig. 43 is a cross-sectional view showing an example of the first sub-pixel taken along the line I-I' of fig. 39 to 42.

Fig. 44 is a diagram illustrating a front surface of a tiled display device in accordance with one or more embodiments.

Fig. 45 is an enlarged layout diagram showing the region H of fig. 44 in detail.

Fig. 46 is a cross-sectional view showing an example of a tiled display device taken along the line J-J' of fig. 45.

Fig. 47 is a plan view illustrating a front surface of a first display device according to one or more embodiments.

Fig. 48 is a plan view illustrating a bottom surface of a first display device in accordance with one or more embodiments.

Fig. 49 is a cross-sectional view showing an example of the first display device taken along the line N-N' of fig. 47 and 48.

Fig. 50 is a diagram illustrating an example of a check multiplexer in accordance with one or more embodiments.

Fig. 51 is a plan view illustrating a front surface of a first display device according to one or more embodiments.

FIG. 52 is a block diagram illustrating a tiled display device in accordance with one or more embodiments.

Fig. 53 is a diagram illustrating wireless communication between multiple display devices of a tiled display device in accordance with one or more embodiments.

Detailed Description

Aspects and features of embodiments of the present disclosure and methods of accomplishing embodiments of the present disclosure may be understood more readily by reference to the detailed description of the embodiments and the accompanying drawings. Hereinafter, embodiments will be described in more detail with reference to the accompanying drawings. The described embodiments may, however, be embodied in various different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey the aspects and features of the disclosure to those skilled in the art. Thus, processes, elements, and techniques not necessary for a complete understanding of aspects and features of the present disclosure by those of ordinary skill in the art may not be described.

Unless otherwise indicated, like reference numerals, characters, or combinations thereof denote like elements throughout the drawings and written description, and thus, the description thereof will not be repeated. Furthermore, portions that are not relevant to the description of one or more embodiments may not be shown in order to make the description clear.

In the drawings, the relative sizes of elements, layers and regions may be exaggerated for clarity. Furthermore, the use of cross-hatching and/or shading is often provided in the drawings to clarify the boundaries between adjacent elements. Thus, unless specified, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, size, proportion, commonality between illustrated elements, and/or any other characteristic, attribute, property, or the like of an element.

Various embodiments are described herein with reference to cross-section illustrations that are schematic illustrations of embodiments and/or intermediate structures. As such, variations in the shape of the drawing due to, for example, manufacturing techniques and/or tolerances, will be expected. Furthermore, the specific structural or functional descriptions disclosed herein are presented only for purposes of describing embodiments of the concepts according to the present disclosure. Accordingly, the embodiments disclosed herein should not be construed as limited to the shapes of regions specifically illustrated, but are to include deviations in shapes that result, for example, from manufacturing.

For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or gradients of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to be limiting. In addition, as will be recognized by those skilled in the art, the described embodiments may be modified in various different ways, all without departing from the scope of the present disclosure.

In the detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the various embodiments. It may be evident, however, that the various embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring the various embodiments.

Spatially relative terms, such as "below," "beneath," "lower," "under," "above," "upper," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "beneath" can encompass both an orientation of above and below. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Similarly, when a first portion is described as being disposed "on" a second portion, this means that the first portion is disposed at an upper or lower side of the second portion, and is not limited to its upper side based on the direction of gravity.

Further, in the present specification, the phrase "on a plane" or "plan view" means that the target portion is viewed from the top, and the phrase "on a section" means that a section formed by vertically cutting the target portion is viewed from the side.

It will be understood that when an element, layer, region or component is referred to as being "formed on," "connected to" or "coupled to" another element, layer, region or component, it can be directly formed on the other element, layer, region or component, be directly connected or directly coupled to the other element, layer, region or component, or be indirectly formed on the other element, layer, region or component, be indirectly connected or indirectly coupled to the other element, layer, region or component, or be indirectly connected or indirectly coupled to the other element, layer, region or component such that one or more intervening elements, layers, regions or components may be present. For example, when a layer, region, or component is referred to as being "electrically connected" or "coupled" to another layer, region, or component, it can be directly electrically connected or coupled to the other layer, region, and/or component, or intervening layers, regions, or components may be present. However, "directly connected/directly coupled" means that one component is directly connected or coupled to another component without intervening components. Meanwhile, other expressions such as "between", "directly between …" or "adjacent …" and "directly adjacent …" describing relationships between components may be similarly interpreted. Furthermore, it will also be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

For purposes of this disclosure, expressions such as "at least one of …" modify the entire list of elements when following the list of elements, rather than modifying individual elements in the list. For example, "at least one of X, Y and Z" and "at least one selected from the group consisting of X, Y and Z" may be interpreted as any combination of two or more of X only, Y only, Z, X, Y only, and Z, such as XYZ, XYY, YZ and ZZ, for example, or any variation thereof. Similarly, expressions such as "at least one of a and B" may include A, B, or a and B. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. For example, expressions such as "a and/or B" may include A, B, or a and B.

It will be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the scope of the present disclosure.

In an example, the DR1 axis, DR2 axis, and/or DR3 axis are not limited to three axes of a rectangular coordinate system, and may be interpreted in a broader sense. For example, the DR1 axis, DR2 axis, and DR3 axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction and/or the third direction.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," "including," "having," "includes" and "including" when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

As used herein, the terms "substantially," "about," "approximately," and similar terms are used as approximation terms and not as degree terms, and are intended to explain the inherent deviations of measured or calculated values that one of ordinary skill in the art would recognize. As used herein, "about" or "approximately" includes the values as well as averages within acceptable deviation ranges for the particular values as determined by one of ordinary skill in the art when considering the measurement in question and the error associated with the particular amount of measurement (i.e., limitations of the measurement system). For example, "about" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. Furthermore, the use of "may" when describing embodiments of the present disclosure refers to "one or more embodiments of the present disclosure.

While one or more embodiments may be implemented differently, the particular process sequence may be performed differently than as described. For example, two consecutively described processes may be performed substantially simultaneously, or in an order opposite to that described.

Furthermore, any numerical range disclosed and/or recited herein is intended to include all sub-ranges subsumed with the same numerical precision within the range recited. For example, a range of "1.0 to 10.0" is intended to include all subranges between (and including 1.0 and 10.0) the minimum value listed 1.0 and the maximum value listed 10.0, i.e., having a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as, for example, 2.4 to 7.6. Any maximum numerical limitation recited herein is intended to include all lower numerical limitations subsumed therein, and any minimum numerical limitation recited in the present specification is intended to include all higher numerical limitations subsumed therein. Accordingly, applicants reserve the right to modify this specification (including the claims) to expressly enumerate any sub-ranges contained within the ranges expressly recited herein.

An electronic or electrical device and/or any other related device or component according to embodiments of the disclosure described herein may be implemented using any suitable hardware, firmware (e.g., application specific integrated circuits), software, or a combination of software, firmware, and hardware. For example, the various components of these devices may be formed on one Integrated Circuit (IC) chip or on separate IC chips. In addition, the various components of these devices may be implemented on a flexible printed circuit film, tape Carrier Package (TCP), printed Circuit Board (PCB), or formed on one substrate.

Further, the various components of these devices may be processes or threads running on one or more processors in one or more computing devices, executing computer program instructions and interacting with other system components to perform the various functions described herein. The computer program instructions are stored in a memory that may be implemented in a computing device using standard memory means such as, for example, random Access Memory (RAM). The computer program instructions may also be stored in other non-transitory computer readable media such as, for example, CD-ROM, flash drives, etc. Moreover, those skilled in the art will recognize that the functionality of various computing devices may be combined or integrated into a single computing device, or that the functionality of a particular computing device may be distributed over one or more other computing devices, without departing from the scope of embodiments of the present disclosure.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and/or the present specification and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Fig. 1 is a layout diagram illustrating a display device according to one or more embodiments. Fig. 2 is a diagram illustrating an example of the pixel of fig. 1. Fig. 3 is a diagram illustrating another example of the pixel of fig. 1.

Referring to fig. 1 to 3, a display device 10 is a device for displaying a moving image or a still image. The display device 10 may be used as a display screen for various products such as televisions, laptop computers, monitors, billboards, and internet of things (IOT) devices, as well as portable electronic devices such as mobile phones, smart phones, tablet personal computers (tablet PCs), smartwatches, watch phones, mobile communication terminals, electronic notebooks, electronic books, portable Multimedia Players (PMPs), navigation systems, and Ultra Mobile PCs (UMPCs).

The display panel 100 may be formed in a rectangular shape having a long side in a first direction DR1 and a short side in a second direction DR2 intersecting the first direction DR 1. The angle at which the long side of the first direction DR1 and the short side of the second direction DR2 meet may be rounded to have an appropriate curvature (e.g., a predetermined curvature), or may be formed as a right angle. The flat shape of the display panel 100 is not limited to a quadrangle, and may be formed in other polygons, circles, or ovals. The display panel 100 may be formed flat, but is not limited thereto. For example, the display panel 100 is formed at left and right ends, and may include a curved portion having a constant curvature or a varying curvature. In addition, the display panel 100 may be flexibly formed to be curved, bent, curved, folded, or curled.

The display panel 100 may further include pixels PX, scan lines extending in the first direction DR1, and data lines extending in the second direction DR2 to display an image. The pixels PX may be arranged in a matrix form in the first direction DR1 and the second direction DR 2. For example, the pixels PX may be arranged along rows and columns of the matrix in the first direction DR1 and the second direction DR 2.

As shown in fig. 2 and 3, each of the pixels PX may include a plurality of sub-pixels RP, GP, and BP. In fig. 2 and 3, each of the pixels PX is illustrated to include three sub-pixels RP, GP, and BP, i.e., a first sub-pixel RP, a second sub-pixel GP, and a third sub-pixel BP, but the embodiment of the present specification is not limited thereto.

The first, second and third subpixels RP, GP and BP may be connected to at least one of the scan lines and one of the data lines.

Each of the first, second, and third subpixels RP, GP, and BP may have a rectangular, square, or diamond-shaped planar shape. For example, as shown in fig. 2, each of the first, second, and third sub-pixels RP, GP, and BP may have a rectangular planar shape having a short side in the first direction DR1 and a long side in the second direction DR 2. Alternatively, as shown in fig. 3, each of the first, second, and third sub-pixels RP, GP, and BP may have a planar shape including a square or diamond shape having the same length in the first and second directions DR1 and DR 2.

As shown in fig. 2, the first, second, and third sub-pixels RP, GP, and BP may be arranged along the first direction DR 1. Alternatively, one of the second and third subpixels GP and BP and the first subpixel RP may be arranged along the first direction DR1, and the other and first subpixels RP may be arranged along the second direction DR 2. For example, as shown in fig. 3, the first and second subpixels RP and GP may be arranged along the first direction DR1, and the first and third subpixels RP and BP may be arranged along the second direction DR 2.

Alternatively, any one of the first and third sub-pixels RP and BP and the second sub-pixel GP may be arranged along the first direction DR1, and the other and second sub-pixels GP may be arranged along the second direction DR 2. Alternatively, any one of the first and second subpixels RP and GP and the third subpixel BP may be arranged along the first direction DR1, and the other and third subpixels BP may be arranged along the second direction DR 2.

The first subpixel RP may include a first light emitting device emitting the first light, the second subpixel GP may include a second light emitting device emitting the second light, and the third subpixel BP may include a third light emitting device emitting the third light. Here, the first light may be light of a red wavelength band, the second light may be light of a green wavelength band, and the third light may be light of a blue wavelength band. The red wavelength band may be a wavelength band of about 600nm to 750nm, the green wavelength band may be a wavelength band of about 480nm to 560nm, and the blue wavelength band may be a wavelength band of about 370nm to 460nm, but the embodiment of the present specification is not limited thereto.

Each of the first, second, and third sub-pixels RP, GP, and BP is a light emitting device that emits light and may include an inorganic light emitting device having an inorganic semiconductor. For example, the inorganic light emitting device may be a flip chip type micro Light Emitting Diode (LED), but the embodiment of the present specification is not limited thereto.

As shown in fig. 2 and 3, the area of the first subpixel RP, the area of the second subpixel GP, and the area of the third subpixel BP may be substantially the same, but the embodiment of the present specification is not limited thereto. At least one of the area of the first subpixel RP, the area of the second subpixel GP, and the area of the third subpixel BP may be different from the other. Alternatively, any two of the area of the first subpixel RP, the area of the second subpixel GP, and the area of the third subpixel BP may be substantially the same, and the other may be different from the two. Alternatively, the area of the first subpixel RP, the area of the second subpixel GP, and the area of the third subpixel BP may be different from each other.

Referring to fig. 4, the first subpixel RP according to one or more embodiments may be connected to a kth (k is a positive integer) write scan line GWLk, a kth initialization scan line GILk, a kth control scan line GCLk, a kth sweep signal line SWPLk, a kth PWM transmit line PWELk, a kth PAM transmit line PAELk, and a check enable signal line IEL. Further, the first subpixel RP according to one or more embodiments may be connected to the j-th data line DLj (j is a positive integer) and the first PAM data line RDL. Further, the first subpixel RP may be connected to a first power line VDL1 to which a first power voltage is applied, a second power line VSL to which a second power voltage is applied, an initialization voltage line VIL to which an initialization voltage is applied, and a gate-off voltage line VGHL to which a gate-off voltage is applied. In one or more embodiments, the first subpixel RP may be connected to the third power line VDL2 to which the third power voltage is applied.

The first subpixel RP may include a first pixel driver PDU1, a second pixel driver PDU2, a third pixel driver PDU3, a check driver IDU, and a first light emitting element REL.

The first light emitting element REL emits light according to a driving current generated by the second pixel driver PDU 2. The first light emitting element REL may be disposed between the seventeenth transistor T17 and the second power line VSL. The first electrode of the first light emitting element REL may be connected to the second electrode of the seventeenth transistor T17, and the second electrode may be connected to the second power line VSL. The first electrode of the first light emitting element REL may be an anode electrode, and the second electrode may be a cathode electrode. The first light emitting element REL may be an inorganic light emitting device including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode. For example, the first light emitting element REL may be a micro light emitting diode formed of an inorganic semiconductor, but is not limited thereto.

The first pixel driver PDU1 generates a control current Ic in response to a j-th data voltage of a j-th data line DLj (also referred to as a first data line) to control the voltage of the third node N3 of the third pixel driver PDU 3. Since the pulse width of the first driving current flowing through the first light emitting element REL may be adjusted by the control current Ic of the first pixel driver PDU1, the first pixel driver PDU1 may be a Pulse Width Modulation (PWM) unit for performing pulse width modulation of the first driving current flowing through the first light emitting element REL.

The first pixel driver PDU1 may include first to seventh transistors T1 to T7 and a first capacitor PC1.

The first transistor T1 controls the control current Ic flowing between the second electrode and the first electrode of the first transistor T1 in response to the data voltage applied to the gate electrode.

The second transistor T2 is turned on by the kth write scan signal of the kth write scan line GWLk to supply the jth data voltage of the jth data line DLj to the first electrode of the first transistor T1.

The third transistor T3 is turned on by a kth initialization scan signal of the kth initialization scan line GILk to connect the initialization voltage line VIL to the gate electrode of the first transistor T1. Accordingly, during the turn-on period of the third transistor T3, the gate electrode of the first transistor T1 may be discharged to the initialization voltage of the initialization voltage line VIL. The third transistor T3 may include a plurality of transistors connected in series. For example, the third transistor T3 may include a first sub-transistor T31 and a second sub-transistor T32. Because of this, the voltage at which the gate electrode of the first transistor T1 leaks through the third transistor T3 can be reduced or minimized.

The fourth transistor T4 is turned on by the kth write scan signal of the kth write scan line GWLk to connect the gate electrode and the second electrode of the first transistor T1. Because of this, the first transistor T1 may operate as a diode (e.g., the first transistor T1 may be diode-connected) during the on period of the fourth transistor T4. The fourth transistor T4 may include a plurality of transistors connected in series. For example, the fourth transistor T4 may include a third sub-transistor T41 and a fourth sub-transistor T42. Because of this, the voltage at which the gate electrode of the first transistor T1 leaks through the fourth transistor T4 can be reduced or minimized.

The fifth transistor T5 is turned on by the kth PWM emission signal of the kth PWM emission line PWELk to connect the first electrode of the first transistor T1 to the third power supply line VDL2.

The sixth transistor T6 is turned on by the kth PWM emission signal of the kth PWM emission line PWELk to connect the second electrode of the first transistor T1 to the third node N3 of the third pixel driver PDU 3.

The seventh transistor T7 is turned on by a kth control scan signal of the kth control scan line GCLk to supply a gate-off voltage of the gate-off voltage line VGHL to the first node N1 connected to the kth sweep signal line SWPLk. Because of this, during a period in which the initialization voltage is applied to the gate electrode of the first transistor T1 and a period in which the j-th data voltage of the j-th data line DLj and the threshold voltage of the first transistor T1 are programmed, a change in the voltage of the gate electrode of the first transistor T1 can be prevented from being reflected in the kth sweep signal of the kth sweep signal line SWPLk by the first capacitor PC 1.

The first capacitor PC1 may be disposed between the gate electrode of the first transistor T1 and the first node N1. One electrode of the first capacitor PC1 may be connected to the gate electrode of the first transistor T1, and the other electrode thereof may be connected to the first node N1.

The first node N1 may be a contact point of the kth sweep signal line SWPLk, the second electrode of the seventh transistor T7, and the other electrode of the first capacitor PC 1.

The second pixel driver PDU2 generates a first driving current applied to the first light emitting element REL in response to the first PAM data voltage of the first PAM data line RDL. The second pixel driver PDU2 may be a Pulse Amplitude Modulation (PAM) unit for performing pulse amplitude modulation. The second pixel driver PDU2 may be a constant current generator generating a constant driving current according to the first PAM data voltage.

Further, the second pixel driver PDU2 of each of the first subpixels RP may receive the same first PAM data voltage and generate the same first driving current regardless of the brightness of the first subpixels RP. Similarly, the second pixel driver PDU2 of each of the second subpixels GP may receive the same second PAM data voltage and generate the same second driving current regardless of the brightness of the second subpixels GP. The third pixel driver PDU3 of each of the third sub-pixels BP may receive the same third PAM data voltage and generate the same third driving current regardless of the brightness of the third sub-pixel BP.

The second pixel driver PDU2 may include eighth to fourteenth transistors T8 to T14 and a second capacitor PC2.

The eighth transistor T8 controls a driving current flowing to the first light emitting element REL in response to a voltage applied to the gate electrode.

The ninth transistor T9 is turned on by the kth write scan signal of the kth write scan line GWLk to supply the first PAM data voltage of the first PAM data line RDL (also referred to as a second data line) to the first electrode of the eighth transistor T8.

The tenth transistor T10 is turned on by a kth initialization scan signal of the kth initialization scan line GILk to connect the initialization voltage line VIL to the gate electrode of the eighth transistor T8. Accordingly, during the turn-on period of the tenth transistor T10, the gate electrode of the eighth transistor T8 may be discharged to the initialization voltage of the initialization voltage line VIL. The tenth transistor T10 may include a plurality of transistors connected in series. For example, the tenth transistor T10 may include a fifth sub-transistor T101 and a sixth sub-transistor T102. Accordingly, the voltage of the gate electrode of the eighth transistor T8 can be reduced or minimized from leaking through the tenth transistor T10.

The eleventh transistor T11 is turned on by the kth write scan signal of the kth write scan line GWLk to connect the gate electrode and the second electrode of the eighth transistor T8. Thus, during the on period of the eleventh transistor T11, the eighth transistor T8 may operate as a diode (e.g., the eighth transistor T8 may be diode-connected). The eleventh transistor T11 may include a plurality of transistors connected in series. For example, the eleventh transistor T11 may include a seventh sub-transistor T111 and an eighth sub-transistor T112. Accordingly, the voltage at which the gate electrode of the eighth transistor T8 leaks through the eleventh transistor T11 can be reduced or minimized.

The twelfth transistor T12 is turned on by the kth PWM emission signal of the kth PWM emission line PWELk to connect the first electrode of the eighth transistor T8 to the first power supply line VDL1.

The thirteenth transistor T13 is turned on by a kth control scan signal of the kth control scan line GCLk to connect the third power supply line VDL2 to the second node N2. Accordingly, when the thirteenth transistor T13 is turned on, the third power voltage of the third power line VDL2 may be supplied to the second node N2.

The fourteenth transistor T14 is turned on by the kth PWM transmission signal of the kth PWM transmission line PWELk to connect the first power line VDL1 to the second node N2. Accordingly, when the fourteenth transistor T14 is turned on, the first power voltage of the first power line VDL1 may be supplied to the second node N2.

The second capacitor PC2 may be disposed between the gate electrode of the eighth transistor T8 and the second node N2. One electrode of the second capacitor PC2 may be connected to the gate electrode of the eighth transistor T8, and the other electrode thereof may be connected to the second node N2.

The second node N2 may be a contact point of the second electrode of the thirteenth transistor T13, the second electrode of the fourteenth transistor T14, and the other electrode of the second capacitor PC 2.

The third pixel driver PDU3 adjusts a period in which the driving current is applied to the first light emitting element REL according to the voltage of the third node N3.

The third pixel driver PDU3 may include fifteenth to nineteenth transistors T15 to T19 and a third capacitor PC3.

The fifteenth transistor T15 is turned on or off according to the voltage of the third node N3. The driving current of the eighth transistor T8 may be supplied to the first light emitting element REL when the fifteenth transistor T15 is turned on, and the driving current of the eighth transistor T8 may not be supplied to the first light emitting element REL when the fifteenth transistor T15 is turned off. Accordingly, the turn-on period of the fifteenth transistor T15 may be substantially the same as the emission period of the first light emitting element REL. The fifteenth transistor T15 may be connected between the eighth transistor T8 and the seventeenth transistor T17.

The sixteenth transistor T16 is turned on by a kth control scan signal of the kth control scan line GCLk to connect the initialization voltage line VIL to the third node N3. Accordingly, during the turn-on period of the sixteenth transistor T16, the third node N3 may be discharged to the initialization voltage of the initialization voltage line VIL. The sixteenth transistor T16 may include a plurality of transistors connected in series. For example, the sixteenth transistor T16 may include a ninth sub-transistor T161 and a tenth sub-transistor T162. Accordingly, the voltage of the third node N3 leaked through the sixteenth transistor T16 can be reduced or minimized.

The seventeenth transistor T17 is turned on by the kth PAM emission signal of the kth PAM emission line PAELk to connect the second electrode of the fifteenth transistor T15 to the first electrode of the first light emitting element REL.

The eighteenth transistor T18 is turned on by the kth control scan signal of the kth control scan line GCLk to connect the initialization voltage line VIL to the first electrode of the first light emitting element REL. Accordingly, during the on period of the eighteenth transistor T18, the first electrode of the first light emitting element REL may be discharged to the initialization voltage of the initialization voltage line VIL.

The nineteenth transistor T19 is turned on by the test signal of the test signal line TSTL to connect the first electrode of the first light emitting element REL to the second power supply line VSL.

The third capacitor PC3 may be disposed between the third node N3 and the initialization voltage line VIL. One electrode of the third capacitor PC3 may be connected to the third node N3, and the other electrode thereof may be connected to the initialization voltage line VIL.

The third node N3 may be a contact point of the second electrode of the sixth transistor T6, the gate electrode of the fifteenth transistor T15, the first electrode of the ninth sub-transistor T161, and one electrode of the third capacitor PC 3.

The inspection driver IDU may include a first test (or inspection) transistor T20 and a second test transistor T21. The first test transistor T20 and the second test transistor T21 are turned on by a check enable signal of the check enable signal line IEL, and connect the first power line VDL1 to the second power line VSL.

When a sufficient pressure (e.g., a predetermined pressure) is applied to the first light emitting element REL to attach the first light emitting element REL to the first subpixel RP, the first electrode of the first light emitting element REL may be shorted with at least one of the first electrode and the second electrode of the first test transistor T20, and the second electrode of the first light emitting element REL may be shorted with one of the first electrode and the second electrode of the second test transistor T21. Therefore, the first light emitting element REL may not emit light as intended. That is, by forming the first test transistor T20 and the second test transistor T21, it is possible to check whether the first electrode or the second electrode of the first light emitting element REL is shorted with the other electrode or the wiring.

In fig. 4, the source electrode S20 (see fig. 11) of the first test transistor T20 and the source electrode S21 (see fig. 11, for example) of the second test transistor T21 are connected to the first power line VDL1, but the present specification is not limited thereto. For example, as shown in fig. 14, the source electrode S20 of the first test transistor T20 and the source electrode S21 of the second test transistor T21 may be connected to the third power supply line VDL2.

Any one of the first electrode and the second electrode of each of the first to nineteenth transistors T1 to T19, the first test transistor T20, and the second test transistor T21 may be a source electrode, and the other may be a drain electrode. The active layer of each of the first to nineteenth transistors T1 to T19, the first test transistor T20, and the second test transistor T21 may be formed of any one of polysilicon, amorphous silicon, and an oxide semiconductor. When the active layer of each of the first to nineteenth transistors T1 to T19, the first test transistor T20, and the second test transistor T21 is made of polysilicon, it may be formed by a Low Temperature Polysilicon (LTPS) process.

Further, although fig. 4 mainly describes a case where each of the first to nineteenth transistors T1 to T19, the first test transistor T20, and the second test transistor T21 is formed as a P-type MOSFET, the embodiment of the present specification is not limited thereto. For example, each of the first to nineteenth transistors T1 to T19, the first test transistor T20, and the second test transistor T21 may be formed as an N-type MOSFET.

Alternatively, in order to improve the black display capability of the first light emitting element REL by blocking the leakage current, in the first subpixel RP, the first and second sub-transistors T31 and T32 of the third transistor T3, the third and fourth sub-transistors T41 and T42 of the fourth transistor T4, the fifth and sixth sub-transistors T101 and T102 of the tenth transistor T10, and the seventh and eighth sub-transistors T111 and T112 of the eleventh transistor T11 may be formed as N-type MOSFETs. In this case, the gate electrodes of the third and fourth sub-transistors T41 and T42 of the fourth transistor T4 and the gate electrodes of the seventh and eighth sub-transistors T111 and T112 of the eleventh transistor T11 may be connected to the kth control scan line GCLk. The kth initialization scan signal and the kth control scan signal may have pulses generated by a gate-off voltage. Further, active layers of the first and second sub-transistors T31 and T32 of the third transistor T3, the third and fourth sub-transistors T41 and T42 of the fourth transistor T4, the fifth and sixth sub-transistors T101 and T102 of the tenth transistor T10, and the seventh and eighth sub-transistors T111 and T112 of the eleventh transistor T11 may be formed of an oxide semiconductor, and active layers of other transistors may be formed of polysilicon.

Alternatively, any one of the first and second sub-transistors T31 and T32 of the third transistor T3 may be formed as an N-type MOSFET, and the other may be formed as a P-type MOSFET. In this case, in the first and second sub-transistors T31 and T32 of the third transistor T3, the active layer of the transistor formed as the N-type MOSFET may be formed of an oxide semiconductor, and the active layer of the transistor formed as the P-type MOSFET may be formed of polysilicon.

Alternatively, any one of the third and fourth sub-transistors T41 and T42 of the fourth transistor T4 may be formed as an N-type MOSFET, and the other may be formed as a P-type MOSFET. In this case, in the third and fourth sub-transistors T41 and T42 of the fourth transistor T4, the active layer of the transistor formed as the N-type MOSFET may be formed of an oxide semiconductor, and the active layer of the transistor formed as the P-type MOSFET may be formed of polysilicon.

Alternatively, any one of the fifth and sixth sub-transistors T101 and T102 of the tenth transistor T10 may be formed as an N-type MOSFET, and the other may be formed as a P-type MOSFET. In this case, in the fifth and sixth sub-transistors T101 and T102 of the tenth transistor T10, the active layer of the transistor formed as an N-type MOSFET may be formed of an oxide semiconductor, and the active layer of the transistor formed as a P-type MOSFET may be formed of polysilicon.

Alternatively, any one of the seventh and eighth sub-transistors T111 and T112 of the eleventh transistor T11 may be formed as an N-type MOSFET, and the other may be formed as a P-type MOSFET. In this case, in the seventh and eighth sub-transistors T111 and T112 of the eleventh transistor T11, the active layer of the transistor formed as the N-type MOSFET may be formed of an oxide semiconductor, and the active layer of the transistor formed as the P-type MOSFET may be formed of polysilicon.

The second subpixel GP and the third subpixel BP according to one or more embodiments may be substantially the same as the first subpixel RP described with reference to fig. 4. Therefore, descriptions of the second subpixel driver GP and the third subpixel driver BP according to one or more embodiments will be omitted.

Fig. 5 is a layout diagram illustrating a lower metal layer, an active layer, a first gate metal layer, a second gate metal layer, a first source metal layer, and a second source metal layer of a first subpixel according to one or more embodiments. Fig. 6 is a layout diagram illustrating a third source metal layer of a first subpixel in accordance with one or more embodiments. Fig. 7 is a layout diagram illustrating a fourth source metal layer of a first subpixel in accordance with one or more embodiments. Fig. 8 is a layout diagram illustrating a transparent electrode layer and a first light emitting device of a first subpixel according to one or more embodiments. Fig. 9 is an enlarged layout diagram showing the area a of fig. 5 in detail. Fig. 10 is an enlarged layout diagram showing the region B of fig. 5 in detail. Fig. 11 is an enlarged layout diagram showing the region C of fig. 5 in detail.

Referring to fig. 5 to 11, the initialization voltage line VIL, the kth initialization scan line GILk, the kth write scan line GWLk, the kth PWM emission line PWELk, the first horizontal power line HVDL1, the second horizontal power line HVDL2, the third horizontal power line HVSL1, the fourth horizontal power line HVSL2, the gate-off voltage line VGHL, the kth sweep signal line SWPLk, the kth control scan line GCLk, the kth PAM emission line PAELk and the test signal line TSTL, and the inspection enable signal line IEL may extend in the first direction DR1 and may be spaced apart from each other in the second direction DR 2. The j-th data line DLj, the vertical power line VVDL, and the first PAM data line RDL may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR 1.

The first power line VDL1 may include a first main power line MVDL and a second horizontal power line HVDL2. The first main power line MVDL and the second horizontal power line HVDL2 may receive the first power voltage.

The second power line VSL may include a second main power line MVSL, a third horizontal power line HVSL1, and a fourth horizontal power line HVSL2. The second main power line MVSL, the third horizontal power line HVSL1, and the fourth horizontal power line HVSL2 may receive the second power voltage.

The third power supply line VDL2 may include a vertical power supply line VVDL and a first horizontal power supply line HVDL1. The vertical power supply line VVDL and the first horizontal power supply line HVDL1 may receive the third power voltage.

The first subpixel RP includes first to nineteenth transistors T1 to T19, first to sixth test transistors T20 and T21, first to sixth capacitor electrodes CE1 to CE6, first to seventh gate connection electrodes GCE1 to GCE7, first and second data connection electrodes DCE1 and DCE2, first to seventh connection electrodes CCE1 to CCE7, first pad connection electrode ANDE1, second pad connection electrode ANDE2, third pad connection electrode APD1, fourth pad connection electrode CPD1, first pad electrode CTE1 and second pad electrode CTE2.

The first transistor T1 includes a first channel CH1, a first gate electrode G1, a first source electrode S1, and a first drain electrode D1. The first channel CH1 may overlap the first gate electrode G1 in a third direction DR3 (e.g., a thickness direction of the substrate). The first gate electrode G1 may be connected to the first connection electrode CCE1 through a first contact hole CT 1. The first gate electrode G1 may be integrally formed with the first capacitor electrode CE1. The first gate electrode G1 may overlap the second capacitor electrode CE2 in the third direction DR 3. The first source electrode S1 may be connected to the second drain electrode D2 and the fifth drain electrode D5. The first drain electrode D1 may be connected to the third sub-source electrode S41 and the sixth source electrode S6. The first source electrode S1 and the first drain electrode D1 may overlap the second capacitor electrode CE2 in the third direction DR 3.

The second transistor T2 includes a second channel CH2, a second gate electrode G2, a second source electrode S2, and a second drain electrode D2. The second channel CH2 may overlap the second gate electrode G2 in the third direction DR 3. The second gate electrode G2 may be integrally formed with the first gate connection electrode GCE 1. The second source electrode S2 may be connected to the first data connection electrode DCE1 through the first data contact hole DCT 1. The second drain electrode D2 may be connected to the first source electrode S1.

The first sub-transistor T31 of the third transistor T3 includes a first sub-channel CH31, a first sub-gate electrode G31, a first sub-source electrode S31, and a first sub-drain electrode D31. The first sub-channel CH31 may overlap the first sub-gate electrode G31 in the third direction DR 3. The first sub-gate electrode G31 may be integrally formed with the second gate connection electrode GCE 2. The first sub-source electrode S31 may be connected to the fourth sub-drain electrode D42, and the first sub-drain electrode D31 may be connected to the second sub-source electrode S32. The first sub-source electrode S31 may overlap the kth write scan line GWLk in the third direction DR 3. The first sub drain electrode D31 may overlap the initialization voltage line VIL in the third direction DR 3.

The second sub-transistor T32 of the third transistor T3 includes a second sub-channel CH32, a second sub-gate electrode G32, a second sub-source electrode S32, and a second sub-drain electrode D32. The second sub-channel CH32 may overlap the second sub-gate electrode G32 in the third direction DR 3. The second sub-gate electrode G32 may be integrally formed with the second gate connection electrode GCE 2. The second sub-source electrode S32 may be connected to the first sub-drain electrode D31, and the second sub-drain electrode D32 may be connected to the initialization voltage line VIL through the first power contact hole VCT 1. The second sub-source electrode S32 and the second sub-drain electrode D32 may overlap the initialization voltage line VIL in the third direction DR 3.

The third sub-transistor T41 of the fourth transistor T4 includes a third sub-channel CH41, a third sub-gate electrode G41, a third sub-source electrode S41, and a third sub-drain electrode D41. The third sub-channel CH41 may overlap the third sub-gate electrode G41 in the third direction DR 3. The third sub-gate electrode G41 may be integrally formed with the first gate connection electrode GCE 1. The third sub-source electrode S41 may be connected to the first drain electrode D1, and the third sub-drain electrode D41 may be connected to the fourth sub-source electrode S42.

The fourth sub-transistor T42 of the fourth transistor T4 includes a fourth sub-channel CH42, a fourth sub-gate electrode G42, a fourth sub-source electrode S42, and a fourth sub-drain electrode D42. The fourth sub-channel CH42 may overlap the fourth sub-gate electrode G42 in the third direction DR 3. The fourth sub-gate electrode G42 may be integrally formed with the first gate connection electrode GCE 1. The fourth sub-source electrode S42 may be connected to the third sub-drain electrode D41, and the fourth sub-drain electrode D42 may be connected to the first sub-source electrode S31.

The fifth transistor T5 includes a fifth channel CH5, a fifth gate electrode G5, a fifth source electrode S5, and a fifth drain electrode D5. The fifth channel CH5 may overlap the fifth gate electrode G5 in the third direction DR 3. The fifth gate electrode G5 may be integrally formed with the sixth gate connection electrode GCE 6. The fifth source electrode S5 may be connected to the first horizontal power line HVDL1 through the second power contact hole VCT 2. The fifth drain electrode D5 may be connected to the first source electrode S1. The fifth drain electrode D5 may overlap the extension portion EX of the second capacitor electrode CE2 in the third direction DR 3.

The sixth transistor T6 includes a sixth channel CH6, a sixth gate electrode G6, a sixth source electrode S6, and a sixth drain electrode D6. The sixth channel CH6 may overlap the sixth gate electrode G6 in the third direction DR 3. The sixth gate electrode G6 may be integrally formed with the sixth gate connection electrode GCE 6. The sixth source electrode S6 may be connected to the first drain electrode D1. The sixth drain electrode D6 may be connected to the fourth connection electrode CCE4 through a tenth contact hole CT 10. The sixth drain electrode D6 may overlap the second connection electrode CCE2 and the first horizontal power line HVDL1 in the third direction DR 3.

The seventh transistor T7 includes a seventh channel CH7, a seventh gate electrode G7, a seventh source electrode S7, and a seventh drain electrode D7. The seventh channel CH7 may overlap the seventh gate electrode G7 in the third direction DR 3. The seventh gate electrode G7 may be integrally formed with the third gate connection electrode GCE 3. The seventh gate electrode G7 may overlap the initialization voltage line VIL in the third direction DR 3. The seventh source electrode S7 may be connected to the gate-off voltage line VGHL through the seventh contact hole CT 7. The seventh drain electrode D7 may be connected to the kth scanning signal line SWPLk through the sixth contact hole CT 6.

The eighth transistor T8 includes an eighth channel CH8, an eighth gate electrode G8, an eighth source electrode S8, and an eighth drain electrode D8. The eighth channel CH8 may overlap the eighth gate electrode G8 in the third direction DR 3. The eighth gate electrode G8 may extend in the second direction DR 2. The eighth gate electrode G8 may be integrally formed with the third capacitor electrode CE 3. The eighth source electrode S8 may be connected to the ninth drain electrode D9 and the twelfth drain electrode D12. The eighth drain electrode D8 may be connected to the seventh sub-source electrode S111.

The ninth transistor T9 includes a ninth channel CH9, a ninth gate electrode G9, a ninth source electrode S9, and a ninth drain electrode D9. The ninth channel CH9 may overlap the ninth gate electrode G9 in the third direction DR 3. The ninth gate electrode G9 may extend in the second direction DR 2. The ninth gate electrode G9 may be integrally formed with the first gate connection electrode GCE 1. The ninth drain electrode D9 may be connected to the second data connection electrode DCE2 through the third data contact hole DCT 3. The ninth source electrode S9 may be connected to the eighth source electrode S8.

The fifth sub-transistor T101 of the tenth transistor T10 includes a fifth sub-channel CH101, a fifth sub-gate electrode G101, a fifth sub-source electrode S101, and a fifth sub-drain electrode D101. The fifth sub-channel CH101 may overlap with the fifth sub-gate electrode G101 in the third direction DR 3. The fifth sub-gate electrode G101 may be integrally formed with the second gate connection electrode GCE 2. The fifth sub-source electrode S101 may be connected to the eighth sub-drain electrode D112, and the fifth sub-drain electrode D101 may be connected to the sixth sub-source electrode S102. The fifth sub-source electrode S101 may overlap the kth write scan line GWLk in the third direction DR 3. The fifth sub drain electrode D101 may overlap the initialization voltage line VIL in the third direction DR 3.

The sixth sub-transistor T102 of the tenth transistor T10 includes a sixth sub-channel CH102, a sixth sub-gate electrode G102, a sixth sub-source electrode S102, and a sixth sub-drain electrode D102. The sixth sub-channel CH102 may overlap with the sixth sub-gate electrode G102 in the third direction DR 3. The sixth sub-gate electrode G102 may be integrally formed with the second gate connection electrode GCE 2. The sixth sub-source electrode S102 may be connected to the fifth sub-drain electrode D101, and the sixth sub-drain electrode D102 may be connected to the initialization voltage line VIL through the first power contact hole VCT 1. The sixth sub-source electrode S102 and the sixth sub-drain electrode D102 may overlap the initialization voltage line VIL in the third direction DR 3.

The seventh sub-transistor T111 of the eleventh transistor T11 includes a seventh sub-channel CH111, a seventh sub-gate electrode G111, a seventh sub-source electrode S111, and a seventh sub-drain electrode D111. The seventh sub-channel CH111 may overlap the seventh sub-gate electrode G111 in the third direction DR 3. The seventh sub-gate electrode G111 may be integrally formed with the first gate connection electrode GCE 1. The seventh sub-source electrode S111 may be connected to the eighth drain electrode D8, and the seventh sub-drain electrode D111 may be connected to the eighth sub-source electrode S112.

The eighth sub-transistor T112 of the eleventh transistor T11 includes an eighth sub-channel CH112, an eighth sub-gate electrode G112, an eighth sub-source electrode S112, and an eighth sub-drain electrode D112. The eighth sub-channel CH112 may overlap with the eighth sub-gate electrode G112 in the third direction DR 3. The eighth sub-gate electrode G112 may be integrally formed with the first gate connection electrode GCE 1. The eighth sub-source electrode S112 may be connected to the seventh sub-drain electrode D111, and the eighth sub-drain electrode D112 may be connected to the fifth sub-source electrode S101.

The twelfth transistor T12 includes a twelfth channel CH12, a twelfth gate electrode G12, a twelfth source electrode S12, and a twelfth drain electrode D12. The twelfth channel CH12 may overlap the twelfth gate electrode G12 in the third direction DR 3. The twelfth gate electrode G12 may be integrally formed with the sixth gate connection electrode GCE 6. The twelfth source electrode S12 may be connected to the fifth connection electrode CCE5 through an eleventh contact hole CT 11.

The thirteenth transistor T13 includes a thirteenth channel CH13, a thirteenth gate electrode G13, a thirteenth source electrode S13, and a thirteenth drain electrode D13. The thirteenth channel CH13 may overlap the thirteenth gate electrode G13 in the third direction DR 3. The thirteenth gate electrode G13 may be integrally formed with the third gate connection electrode GCE 3. The thirteenth source electrode S13 may be connected to the first horizontal power line HVDL1 through the second power contact hole VCT 2. The thirteenth drain electrode D13 may be connected to the second connection electrode CCE2 through the third contact hole CT 3.

The fourteenth transistor T14 includes a fourteenth channel CH14, a fourteenth gate electrode G14, a fourteenth source electrode S14, and a fourteenth drain electrode D14. The fourteenth channel CH14 may overlap the fourteenth gate electrode G14 in the third direction DR 3. The fourteenth gate electrode G14 may be integrally formed with the sixth gate connection electrode GCE 6. The fourteenth source electrode S14 may be connected to the fifth connection electrode CCE5 through an eleventh contact hole CT 11. The fourteenth drain electrode D14 may be connected to the second connection electrode CCE2 through the fourth contact hole CT 4.

The fifteenth transistor T15 includes a fifteenth channel CH15, a fifteenth gate electrode G15, a fifteenth source electrode S15, and a fifteenth drain electrode D15. Fifteenth channel CH15 may be in a third direction DR3 overlaps with the fifteenth gate electrode G15. The fifteenth gate electrode G15 may be integrally formed with the fifth capacitor electrode CE 5. The fifteenth source electrode S15 may be connected to the ninth drain electrode D9. The fifteenth drain electrode D15 may be connected to the seventeenth source electrode S17.

The ninth sub-transistor T161 of the sixteenth transistor T16 includes a ninth sub-channel CH161, a ninth sub-gate electrode G161, a ninth sub-source electrode S161, and a ninth sub-drain electrode D161. The ninth sub-channel CH161 may overlap with the ninth sub-gate electrode G161 in the third direction DR 3. The ninth sub-gate electrode G161 may be integrally formed with the third gate connection electrode GCE 3. The ninth sub-source electrode S161 may be connected to the fourth connection electrode CCE4 through the tenth contact hole CT10, and the ninth sub-drain electrode D161 may be connected to the tenth sub-source electrode S162.

The tenth sub-transistor T162 of the sixteenth transistor T16 includes a tenth sub-channel CH162, a tenth sub-gate electrode G162, a tenth sub-source electrode S162, and a tenth sub-drain electrode D162. The tenth sub-channel CH162 may overlap the tenth sub-gate electrode G162 in the third direction DR 3. The tenth sub-gate electrode G162 may be integrally formed with the third gate connection electrode GCE 3. The tenth sub source electrode S162 may be connected to the ninth sub drain electrode D161, and the tenth sub drain electrode D162 may be connected to the initialization voltage line VIL through the ninth contact hole CT 9.

The seventeenth transistor T17 includes a seventeenth channel CH17, a seventeenth gate electrode G17, a seventeenth source electrode S17, and a seventeenth drain electrode D17. The seventeenth channel CH17 may overlap the seventeenth gate electrode G17 in the third direction DR 3. The seventeenth gate electrode G17 may be integrally formed with the fifth gate connection electrode GCE 5. The seventeenth source electrode S17 may be connected to the fifteenth drain electrode D15. The seventeenth drain electrode D17 may be connected to the seventh connection electrode CCE7 through a sixteenth contact hole CT 16.

The eighteenth transistor T18 includes an eighteenth channel CH18, an eighteenth gate electrode G18, an eighteenth source electrode S18, and an eighteenth drain electrode D18. The eighteenth channel CH18 may overlap with the eighteenth gate electrode G18 in the third direction DR 3. The eighteenth gate electrode G18 may be integrally formed with the third gate connection electrode GCE 3. The eighteenth source electrode S18 may be connected to the initialization voltage line VIL through the ninth contact hole CT 9. The eighteenth drain electrode D18 may be connected to the seventh connection electrode CCE7 through a sixteenth contact hole CT 16.

The nineteenth transistor T19 includes a nineteenth channel CH19, a nineteenth gate electrode G19, a nineteenth source electrode S19, and a nineteenth drain electrode D19. The nineteenth channel CH19 may overlap with the nineteenth gate electrode G19 in the third direction DR 3. The nineteenth gate electrode G19 may be integrally formed with the seventh gate connection electrode GCE 7. The nineteenth source electrode S19 may be connected to the third connection electrode CCE3 through a twenty-first contact hole CT 21. The nineteenth drain electrode D19 may be connected to the fourth horizontal power supply line HVSL2 through a twenty-fourth contact hole CT 24.

The first test transistor T20 includes a first test channel CH20, a first test gate electrode G20, a first test source electrode S20, and a first test drain electrode D20. The first test channel CH20 may overlap the first test gate electrode G20 in the third direction DR 3. The first test gate electrode G20 may be integrally formed with the eighth gate connection electrode GCE 8. The first test source electrode S20 may be connected to the second horizontal power line HVDL2 through a twenty-ninth contact hole CT 29. The first test drain electrode D20 may be connected to the third horizontal power line HVSL1 through a thirty-first contact hole CT 30.

The second test transistor T21 includes a second test channel CH21, a second test gate electrode G21, a second test source electrode S21, and a second test drain electrode D21. The second test channel CH21 may overlap the second test gate electrode G21 in the third direction DR 3. The second test gate electrode G21 may be integrally formed with the ninth gate connection electrode GCE 9. The second test source electrode S21 may be connected to the second horizontal power line HVDL2 through a thirty-second contact hole CT 32. The second test drain electrode D21 may be connected to the third horizontal power line HVSL1 through a thirty-third contact hole CT 33.

The first capacitor electrode CE1 may be integrally formed with the first gate electrode G1. The second capacitor electrode CE2 may overlap the first capacitor electrode CE1 in the third direction DR 3. The first capacitor electrode CE1 may be one electrode of the first capacitor PC1, and the second capacitor electrode CE2 may be the other electrode of the first capacitor PC 1.

The second capacitor electrode CE2 includes a hole exposing the first gate electrode G1, and the first connection electrode CCE1 may be connected to the first gate electrode G1 through a first contact hole CT1 in the hole.

The second capacitor electrode CE2 may include an extension EX extending in the second direction DR 2. The extension part EX of the second capacitor electrode CE2 may cross the kth PWM transmission line PWELk and the first horizontal power supply line HVDL 1. The extension portion EX of the second capacitor electrode CE2 may be connected to the kth sweep signal line SWPLk through the fifth contact hole CT 5.

The third capacitor electrode CE3 may be integrally formed with the eighth gate electrode G8. The fourth capacitor electrode CE4 may overlap the third capacitor electrode CE3 in the third direction DR 3. The third capacitor electrode CE3 may be one electrode of the second capacitor PC2, and the fourth capacitor electrode CE4 may be the other electrode of the second capacitor PC 2.

The fourth capacitor electrode CE4 includes a hole exposing the eighth gate electrode G8, and the sixth connection electrode CCE6 may be connected to the eighth gate electrode G8 through a twelfth contact hole CT12 in the hole.

The fifth capacitor electrode CE5 may be integrally formed with the fourth gate connection electrode GCE4 and the fifteenth gate electrode G15. The sixth capacitor electrode CE6 may overlap the fifth capacitor electrode CE5 in the third direction DR 3. The fifth capacitor electrode CE5 may be one electrode of the third capacitor PC3, and the sixth capacitor electrode CE6 may be the other electrode of the third capacitor PC 3. The sixth capacitor electrode CE6 may be connected to the initialization voltage line VIL through the eighteenth contact hole CT 18.

The first gate connection electrode GCE1 may be connected to the kth write scan line GWLk through the first gate contact hole GCT1 and the third gate contact hole GCT 3. The second gate connection electrode GCE2 may be connected to the kth initialization scan line GILk through a second gate contact hole GCT 2. The third gate connection electrode GCE3 may be connected to the kth control scan line GCLk through an eighth contact hole CT 8. The fourth gate connection electrode GCE4 may be connected to the fourth connection electrode CCE4 through a seventeenth contact hole CT 17. The fifth gate connection electrode GCE5 may be connected to the kth PAM emission line PAELk through a nineteenth contact hole CT 19. The sixth gate connection electrode GCE6 may be connected to the kth PWM emission line PWELk through the fourteenth contact hole CT 14.

The first data connection electrode DCE1 may be connected to the second source electrode S2 through the first data contact hole DCT1, and may be connected to the j-th data line DLj through the second data contact hole DCT 2. The second data connection electrode DCE2 may be connected to the ninth source electrode S9 through the third data contact hole DCT3 and may be connected to the first PAM data line RDL through the fourth data contact hole DCT 4.

The first connection electrode CCE1 may extend in the second direction DR 2. The first connection electrode CCE1 may be connected to the first gate electrode G1 through a first contact hole CT1 and may be connected to the first sub-source electrode S31 and the fourth sub-drain electrode D42 through a second contact hole CT 2.

The second connection electrode CCE2 may extend in the first direction DR 1. The second connection electrode CCE2 may be connected to the twelfth drain electrode D12 through the third contact hole CT3, may be connected to the fourteenth drain electrode D14 through the fourth contact hole CT4, and may be connected to the fourth capacitor electrode CE4 through the fifteenth contact hole CT 15.

The third connection electrode CCE3 may be connected to the nineteenth source electrode S19 through a twenty-first contact hole CT21 and may be connected to the first pad connection electrode ANDE1 through a twenty-second contact hole CT 22.

The fourth connection electrode CCE4 may extend in the first direction DR 1. The fourth connection electrode CCE4 may be connected to the sixth drain electrode D6 and the ninth sub-source electrode S161 through a tenth contact hole CT10, and may be connected to the fourth gate connection electrode GCE4 through a seventeenth contact hole CT 17.

The fifth connection electrode CCE5 may extend in the first direction DR 1. The fifth connection electrode CCE5 may be connected to the twelfth source electrode S12 and the fourteenth source electrode S14 through the eleventh contact hole CT11, and may be connected to the fourth capacitor electrode CE4 through the fourth power contact hole VCT 4.

The sixth connection electrode CCE6 may extend in the second direction DR 2. The sixth connection electrode CCE6 may be connected to the third capacitor electrode CE3 through a twelfth contact hole CT12 and may be connected to the fifth sub-source electrode S101 and the eighth sub-drain electrode D112 through a thirteenth contact hole CT 13.

The seventh connection electrode CCE7 may be connected to the seventeenth drain electrode D17 and the eighteenth drain electrode D18 through a sixteenth contact hole CT 16. The seventh connection electrode CCE7 may be connected to the first pad connection electrode ANDE1 through a twentieth contact hole CT 20.

The power connection electrode VDCE may extend in the second direction DR 2. The power connection electrode VDCE may be connected to the fifth connection electrode CCE5 through a fourth power contact hole VCT 4.

The first pad connection electrode ANDE1 may extend in the second direction DR 2. The first pad connection electrode ANDE1 may be connected to the seventh connection electrode CCE7 through a twentieth contact hole CT20 and may be connected to the third connection electrode CCE3 through a twenty-second contact hole CT 22.

The second pad connection electrode ANDE2 may be connected to the first pad connection electrode ANDE1 (e.g., fig. 12) through a twenty-fifth contact hole CT 25.

The third pad connection electrode APD1 may be connected to the second pad connection electrode ANDE2 (e.g., fig. 12) through a twenty-sixth contact hole CT 26.

In one or more embodiments, the first main power line MVDL may be connected to the power connection electrode VDCE through a twenty-seventh contact hole CT27 (see, e.g., fig. 6). The first main power line MVDL may overlap the first to nineteenth transistors T1 to T19. The first main power line MVDL may not overlap the first and second test transistors T20 and T21.

In one or more embodiments, the second main power line MVSL may be connected to the third pad connection electrode APD1. The second main power line MVSL may overlap with the first main power line MVDL. The second main power line MVSL may overlap the first to nineteenth transistors T1 to T19. The second main power line MVSL may overlap the second test transistor T21, but may not overlap the first test transistor T20.

According to one or more embodiments, the layout of the second subpixel GP and the layout of the third subpixel BP may be substantially the same as the first subpixel RP described with reference to fig. 5 to 11. Therefore, a description of the layout of the second subpixel GP and the layout of the third subpixel BP according to one or more embodiments will be omitted.

Fig. 12 is a cross-sectional view showing an example of the first sub-pixel taken along the line A-A' of fig. 5 to 8. Fig. 13 is a cross-sectional view showing an example of the first sub-pixel taken along the line B-B' of fig. 5 to 8.

Referring to fig. 12 and 13, the display panel 100 may include a substrate SUB, a thin film transistor layer, and a light emitting device layer.

The substrate SUB may be made of an insulating material such as glass or polymer resin. For example, when the substrate SUB is made of a polymer resin, it may include polyimide. The substrate SUB may be a flexible substrate capable of being bent, folded, curled, or the like.

The buffer layer BF may be disposed on the substrate SUB. The buffer layer BF may be formed of a plurality of inorganic layers alternately stacked. For example, the buffer layer BF may be formed as a multilayer in which one or more inorganic layers of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked.

The thin film transistor layer may be disposed on the buffer layer BF. The thin film transistor layer may include first to nineteenth transistors T1 to T19 and first and second test transistors T20 and T21.

The active layer may be disposed on the buffer layer BF. The active layer includes channels, source electrodes, and drain electrodes of the first to nineteenth transistors T1 to T19 and the first and second test transistors T20 and T21. The active layer may include polycrystalline silicon, monocrystalline silicon, low-temperature polycrystalline silicon, amorphous silicon, or an oxide semiconductor.

The channels of the first to nineteenth transistors T1 to T19 and the first and second test transistors T20 and T21 may overlap each of the gate electrodes G1 to G21 in the third direction DR3, respectively. The source and drain electrodes of the first to nineteenth transistors T1 to T19 and the first and second test transistors T20 and T21 may not overlap the gate electrodes G1 to G21 in the third direction DR 3. The source and drain electrodes of the first to nineteenth transistors T1 to T19 and the first and second test transistors T20 and T21 may be conductive regions obtained by doping a silicon semiconductor or an oxide semiconductor with ions.

The gate insulating layer 130 may be disposed on the active layer. The gate insulating layer 130 may be formed of an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

The first gate metal layer may be disposed on the gate insulating layer 130. The first gate metal layer includes first to nineteenth gate electrodes G1 to G19 of the first to nineteenth transistors T1 to T19, first and second test gate electrodes G20 and G21 of the first and second test transistors T20 and T21, first and third capacitor electrodes CE1 and CE3, and fifth capacitor electrodes CE5, and first to ninth gate connection electrodes GCE1 to GCE9. The first to nineteenth gate electrodes G1 to G19, the first capacitor electrode CE1, the third capacitor electrode CE3, the fifth capacitor electrode CE5, and the first to ninth gate connection electrodes GCE1 to GCE9 may be formed as a single layer or a plurality of layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) and alloys thereof.

The first interlayer insulating layer 141 may be disposed on the first gate metal layer. The first interlayer insulating layer 141 may be formed of an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

The second gate metal layer may be disposed on the first interlayer insulating layer 141. The second gate metal layer may include a second capacitor electrode CE2, a fourth capacitor electrode CE4, and a sixth capacitor electrode CE6. The second gate metal layer may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) and alloys thereof.

The second capacitor electrode CE2 may overlap the first capacitor electrode CE1 in the third direction DR3, the fourth capacitor electrode CE4 may overlap the third capacitor electrode CE3 in the third direction DR3, and the sixth capacitor electrode CE6 may overlap the fifth capacitor electrode CE5 in the third direction DR 3. Since the first interlayer insulating layer 141 has a dielectric constant (e.g., a suitable dielectric constant such as a predetermined dielectric constant), the first capacitor PC1 may be formed of the first capacitor electrode CE1, the second capacitor electrode CE2, and the first interlayer insulating layer 141 disposed therebetween. Further, the second capacitor PC2 may be formed of the third capacitor electrode CE3, the fourth capacitor electrode CE4, and the first interlayer insulating layer 141 disposed therebetween. The third capacitor PC3 may be formed of the fifth capacitor electrode CE6, the sixth capacitor electrode CE6, and the first interlayer insulating layer 141 disposed therebetween.

The second interlayer insulating layer 142 may be disposed on the second gate metal layer. The second interlayer insulating layer 142 may be formed of an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The second interlayer insulating layer 142 may be referred to as a third insulating layer.

The first source metal layer may be disposed on the second interlayer insulating layer 142. The first source metal layer may include an initialization voltage line VIL, a kth initialization scan line GILk, a kth write scan line GWLk, a kth PWM emission line PWELk, a first horizontal power line HVDL1, a second horizontal power line HVDL2, a third horizontal power line HVSL1, a fourth horizontal power line HVSL2, a gate-off voltage line VGHL, a kth sweep signal line SWPLk, a kth control scan line GCLk, a kth PAM emission line PAELk, a check enable signal line IEL, and a test signal line TSTL. Further, the first source metal layer may include first and second data connection electrodes DCE1 and DCE2 and first to seventh connection electrodes CCE1 to CCE7. The first source metal layer may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) and alloys thereof.

The kth write scan line GWLk may be connected to the fourth and eighth sub-gate electrodes G42 and G112 through the first and third gate contact holes GCT1 and GCT3 penetrating the first and second interlayer insulating layers 141 and 142, respectively. The kth initialization scan line GILk may be connected to the second gate connection electrode GCE2 through the second gate contact hole GCT2 penetrating the first and second interlayer insulating layers 141 and 142. The kth control scan line GCLk may be connected to the third gate connection electrode GCE3 through an eighth contact hole CT8 penetrating the first and second interlayer insulating layers 141 and 142.

The kth PAM emission line PAELk may be connected to the fifth gate connection electrode GCE5 through a nineteenth contact hole CT19 penetrating the first and second interlayer insulating layers 141 and 142. The test signal line TSTL may be connected to the seventh gate connection electrode GCE7 through the twenty-third contact hole CT23 penetrating the first and second interlayer insulating layers 141 and 142. The inspection enable signal line IEL may be connected to the eighth gate connection electrode GCE8 through the twenty-eighth contact hole CT28 penetrating the first and second interlayer insulating layers 141 and 142. The inspection enable signal line IEL may be connected to the ninth gate connection electrode GCE9 through a thirty-first contact hole CT31 penetrating the first and second interlayer insulating layers 141 and 142.

The initialization voltage line VIL may be connected to the second and sixth sub-drain electrodes D32 and D102 through the first power contact hole VCT1 penetrating the gate insulating layer 130, the first and second interlayer insulating layers 141 and 142. The initialization voltage line VIL may be connected to the tenth sub drain electrode D162 and the eighteenth source electrode S18 through the ninth contact hole CT9 penetrating the gate insulating layer 130, the first interlayer insulating layer 141, and the second interlayer insulating layer 142. The initialization voltage line VIL may be connected to the sixth capacitor electrode CE6 through the eighteenth contact hole CT18 penetrating the second interlayer insulating layer 142. The gate-off voltage line VGHL may be connected to the eighth source electrode S8 through the seventh contact hole CT7 penetrating the gate insulating layer 130, the first interlayer insulating layer 141, and the second interlayer insulating layer 142.

The first horizontal power line HVDL1 may be connected to the fifth and thirteenth source electrodes S5 and S13 through the second power contact hole VCT2 penetrating the gate insulating layer 130, the first and second interlayer insulating layers 141 and 142. The fourth horizontal power line HVSL2 may be connected to the nineteenth drain electrode D19 through a twenty-fourth contact hole CT24 penetrating the gate insulating layer 130, the first interlayer insulating layer 141 and the second interlayer insulating layer 142.

The second horizontal power line HVDL2 may be connected to the first test source electrode S20 through a twenty-ninth contact hole CT29 penetrating the gate insulating layer 130, the first interlayer insulating layer 141 and the second interlayer insulating layer 142. The second horizontal power line HVDL2 may be connected to the second test source electrode S21 through the thirty-second contact hole CT32 penetrating the gate insulating layer 130, the first interlayer insulating layer 141 and the second interlayer insulating layer 142.

The third horizontal power line HVSL1 may be connected to the first test drain electrode D20 through a thirty-first contact hole CT30 penetrating the gate insulating layer 130, the first interlayer insulating layer 141 and the second interlayer insulating layer 142. The third horizontal power line HVSL1 may be connected to the second test drain electrode D21 through a thirty-third contact hole CT33 penetrating the gate insulating layer 130, the first interlayer insulating layer 141 and the second interlayer insulating layer 142.

The first data connection electrode DCE1 may be connected to the second source electrode S2 through a first data contact hole DCT1 penetrating the gate insulating layer 130, the first interlayer insulating layer 141, and the second interlayer insulating layer 142. The second data connection electrode DCE2 may be connected to the ninth source electrode S9 through the third data contact hole DCT3 penetrating the gate insulating layer 130, the first interlayer insulating layer 141, and the second interlayer insulating layer 142.

The first connection electrode CCE1 may be connected to the first gate electrode G1 through a first contact hole CT1 penetrating the first and second interlayer insulating layers 141 and 142, and may be connected to the first and fourth sub-source electrodes S31 and D42 through a second contact hole CT2 penetrating the gate insulating layer 130, the first and second interlayer insulating layers 141 and 142.

The second connection electrode CCE2 may be connected to the thirteenth drain electrode D13 through the third contact hole CT3 penetrating the gate insulating layer 130, the first interlayer insulating layer 141, and the second interlayer insulating layer 142, may be connected to the fourteenth drain electrode D14 through the fourth contact hole CT4 penetrating the gate insulating layer 130, the first interlayer insulating layer 141, and the second interlayer insulating layer 142, and may be connected to the fourth capacitor electrode CE4 through the fifteenth contact hole CT15 penetrating the second interlayer insulating layer 142.

The third connection electrode CCE3 may be connected to the nineteenth source electrode S19 through a twenty-first contact hole CT21 penetrating the gate insulating layer 130, the first interlayer insulating layer 141, and the second interlayer insulating layer 142.

The fourth connection electrode CCE4 may be connected to the sixth drain electrode D6 through a tenth contact hole CT10 penetrating the gate insulating layer 130, the first interlayer insulating layer 141, and the second interlayer insulating layer 142, and may be connected to the fourth gate connection electrode GCE4 through a seventeenth contact hole CT17 penetrating the first interlayer insulating layer 141 and the second interlayer insulating layer 142.

The fifth connection electrode CCE5 may be connected to the twelfth source electrode S12 and the fourteenth source electrode S14 through an eleventh contact hole CT11 penetrating the gate insulating layer 130, the first interlayer insulating layer 141, and the second interlayer insulating layer 142.

The sixth connection electrode CCE6 may be connected to the eighth gate electrode G8 through a twelfth contact hole CT12 penetrating the first and second interlayer insulating layers 141 and 142, and may be connected to the fifth and eighth sub-source electrodes S101 and D112 through a thirteenth contact hole CT13 penetrating the gate insulating layer 130, the first and second interlayer insulating layers 141 and 142.

The seventh connection electrode CCE7 may be connected to the seventeenth drain electrode D17 and the eighteenth drain electrode D18 through a sixteenth contact hole CT16 penetrating the gate insulating layer 130, the first interlayer insulating layer 141, and the second interlayer insulating layer 142.

The first planarization layer 160 may be disposed on the first source metal layer. The first planarization layer 160 may be formed of an organic layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or the like. The first planarization layer 160 may be referred to as a fourth insulating layer.

The first inorganic insulating layer 161 may be disposed on the first planarization layer 160. The first inorganic insulating layer 161 may be formed of an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

The second source metal layer may be disposed on the first inorganic insulating layer 161. The second source metal layer may include a j-th data line DLj, a vertical power line VVDL, and a first PAM data line RDL. In addition, the second source metal layer may include a first pad connection electrode ANDE1 and a power connection electrode VDCE. The second source metal layer may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) and alloys thereof.

The j-th data line DLj may be connected to the first data connection electrode DCE1 through the second data contact hole DCT2 penetrating the first planarization layer 160 and the first inorganic insulating layer 161. The first PAM data line RDL may be connected to the second data connection electrode DCE2 through the fourth data contact hole DCT4 penetrating the first planarization layer 160 and the first inorganic insulating layer 161. The vertical power supply line VVDL may be connected to the first horizontal power supply line HVDL1 through a third power contact hole VCT3 passing through the first planarization layer 160 and the first inorganic insulating layer 161. The third power contact hole VCT3 may overlap the second power contact hole VCT2 in the third direction DR 3. The area of the third power contact hole VCT3 may be larger than the area of the second power contact hole VCT 2.

The first pad connection electrode ANDE1 is connected to the seventh connection electrode CCE7 through a twentieth contact hole CT20 penetrating the first planarization layer 160 and the first inorganic insulating layer 161, and may be connected to the third connection electrode CCE3 through a twenty-second contact hole CT22 penetrating the first planarization layer 160 and the first inorganic insulating layer 161. The power connection electrode VDCE may be connected to the fifth connection electrode CCE5 through a fourth power contact hole VCT4 penetrating the first planarization layer 160 and the first inorganic insulating layer 161.

The second planarization layer 180 may be disposed on the second source metal layer. The second planarization layer 180 may be formed of an organic layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or the like. The second planarization layer 180 may be referred to as a fifth insulating layer.

The second inorganic insulating layer 181 may be disposed on the second planarization layer 180. The second inorganic insulating layer 181 may be formed of an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

The third source metal layer may be disposed on the second inorganic insulating layer 181. The third source metal layer may include a first main power line MVDL and a second pad connection electrode ANDE2. The first main power line MVDL may be disposed to cover a large area of the first subpixel RP. The first main power source line MVDL may be connected to the power connection electrode VDCE through a twenty-seventh contact hole CT27 penetrating the second planarization layer 180 and the second inorganic insulating layer 181. The second pad connection electrode ANDE2 may be connected to the first pad connection electrode ANDE1 through a twenty-fifth contact hole CT25 penetrating the second planarization layer 180 and the second inorganic insulating layer 181. The third source metal layer may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) and alloys thereof.

A third planarization layer 190 may be disposed on the third source metal layer. The third planarization layer 190 may be formed of an organic layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or the like. The third planarization layer 190 may be referred to as a sixth insulating layer.

A fourth source metal layer may be disposed on the third planarization layer 190. The fourth source metal layer may include a second main power line MVSL, a third pad connection electrode APD1, and a fourth pad connection electrode CPD1. The second main power line MVSL may be connected to the fourth pad connection electrode CPD1. That is, the second main power line MVSL and the fourth pad connection electrode CPD1 may be integrally formed. The third pad connection electrode APD1 may be connected to the second pad connection electrode ANDE2 through a twenty-sixth contact hole CT26 penetrating the third planarization layer 190. The fourth source metal layer may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) and alloys thereof.

The transparent electrode layer may be disposed on the fourth source metal layer. The transparent electrode layer may include a first pad electrode CTE1 and a second pad electrode CTE2. The thickness of the first pad electrode CTE1 and the thickness of the second pad electrode CTE2 may be smaller than the thickness of the third pad connection electrode APD1 and the thickness of the fourth pad connection electrode CPD1.

The first pad electrode CTE1 may be disposed on the third pad connection electrode APD1, and the second pad electrode CTE2 may be disposed on the fourth pad connection electrode CPD 1. The first pad electrode CTE1 may be electrically connected to a first electrode of the first light emitting element REL, and the second pad electrode CTE2 may be electrically connected to a second electrode of the first light emitting element REL. The transparent electrode layer may be made of a transparent metal material such as Indium Zinc Oxide (IZO) and Indium Tin Oxide (ITO), for example, a Transparent Conductive Oxide (TCO).

The fourth planarization layer 110 may be disposed on a portion of the third pad connection electrode APD 1. The fourth planarization layer 110 may not be disposed on the first and second pad electrodes CTE1 and CTE 2. That is, the first and second pad electrodes CTE1 and CTE2 may be exposed without being covered by the fourth planarization layer 110. The fourth planarization layer 110 may be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or the like. The fourth planarization layer 110 may be referred to as an organic insulating layer.

A fourth inorganic insulating layer 111 may be disposed on the fourth planarization layer 110. The fourth inorganic insulating layer 111 may not be disposed on the edge of the first pad electrode CTE1 and the edge of the second pad electrode CTE 2. Accordingly, at least a portion of the first pad electrode CTE1 and at least a portion of the second pad electrode CTE2 may be exposed without being covered by the fourth inorganic insulating layer 111. The fourth inorganic insulating layer 111 may be formed of an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

The light emitting device layer may be disposed on the first and second pad electrodes CTE1 and CTE 2. The light emitting device layer may include a first light emitting element REL.

In fig. 13, a flip-chip micro LED in which the first electrode AE of the first light emitting element REL faces the first pad electrode CTE1 and the second electrode CE of the first light emitting element REL faces the second pad electrode CTE2 is illustrated. The first light emitting element REL may be formed of an inorganic material such as GaN. The lengths of the first light emitting elements REL in the first, second and third directions DR1, DR2 and DR3 may each be several to several hundred μm. For example, the lengths of the first light emitting elements REL in the first, second, and third directions DR1, DR2, and DR3 may each have a length of about 100 μm or less.

The first light emitting element REL and the second and third light emitting devices may be grown and formed on a semiconductor substrate such as a silicon wafer. The first light emitting element REL and the second and third light emitting devices may be directly transferred from the silicon wafer onto the first and second pad electrodes CTE1 and CTE2 of the substrate SUB. Alternatively, the first light emitting element REL and the second and third light emitting devices may be transferred onto the first and second pad electrodes CTE1 and CTE2 of the substrate SUB by an electrostatic method using an electrostatic head or a stamp method using an elastic polymer material such as Polydimethylsiloxane (PDMS) or silicone gel as a transfer substrate.

The first light emitting element REL may be a light emitting structure including a base substrate PSUB, an n-type semiconductor NSEM, an active layer MQW, a p-type semiconductor PSEM, a first electrode AE, and a second electrode CE.

The base substrate PSUB may be a sapphire substrate, but the embodiments of the present specification are not limited thereto.

The n-type semiconductor NSEM may be disposed on one surface of the base substrate PSUB. For example, an n-type semiconductor NSEM may be disposed on a lower surface of the base substrate PSUB. The n-type semiconductor NSEM may be made of GaN doped with an n-type conductivity type dopant such as Si, ge, se or Sn.

The active layer MQW may be disposed on a portion of one surface of the n-type semiconductor NSEM. The active layer MQW may include a material having a single quantum well structure or a multiple quantum well structure. When the active layer MQW includes a material having a multi-quantum well structure, the active layer MQW may have a structure in which a plurality of well layers and barrier layers are alternately stacked. In this case, the well layer may be formed of InGaN, and the barrier layer may be formed of GaN or AlGaN, but is not limited thereto. Alternatively, the active layer MQW may have a structure in which semiconductor materials having a large energy band gap and semiconductor materials having a small energy band gap are alternately stacked, and may include other group III to group V semiconductor materials according to a wavelength band of emitted light.

The p-type semiconductor PSEM may be disposed on one surface of the active layer MQW. The p-type semiconductor PSEM may be made of GaN doped with a p-type conductivity type dopant such as Mg, zn, ca or Ba.

The first electrode AE may be disposed on the p-type semiconductor PSEM, and the second electrode CE may be disposed on another portion of one surface of the n-type semiconductor NSEM. The other portion of the one surface of the n-type semiconductor NSEM on which the second electrode CE is disposed may be spaced apart from a portion of the one surface of the n-type semiconductor NSEM on which the active layer MQW is disposed.

The first electrode AE may be adhered to the first pad electrode CTE1 by a conductive adhesive member such as an Anisotropic Conductive Film (ACF) or an Anisotropic Conductive Paste (ACP). Alternatively, the first electrode AE may be adhered to the first pad electrode CTE1 by a soldering process.

The second electrode CE may be adhered to the second pad electrode CTE2 by a conductive adhesive member such as an Anisotropic Conductive Film (ACF) or an Anisotropic Conductive Paste (ACP). Alternatively, the second electrode CE may be adhered to the second pad electrode CTE2 through a soldering process.

In summary, the first test transistor T20 may overlap the first electrode AE, the first pad electrode CTE1, the third pad connection electrode APD1, and the first PAM data line RDL of the first light emitting element REL in the third direction DR 3. When a sufficient pressure (e.g., a predetermined pressure) is applied to the first light emitting element REL to attach the first light emitting element REL to the first pad electrode CTE1, the third planarization layer 190 supporting the first and third pad connection electrodes APD1 and the second planarization layer 180 supporting the first PAM data line RDL may collapse.

Accordingly, the first electrode AE, the first pad electrode CTE1, the third pad connection electrode APD1, and the first PAM data line RDL of the first light emitting element REL may be short-circuited with the second horizontal power line HVDL2 connected to the first test source electrode S20 of the first test transistor T20. In this case, since a voltage of a different level from the driving voltage according to the driving current is applied to the first electrode AE of the first light emitting element REL, the first light emitting element REL may not emit light as intended. Alternatively, the first pad electrode CTE1, the third pad connection electrode APD1, and the first PAM data line RDL may be shorted with the third horizontal power line HVSL1 connected to the first test drain electrode D20 of the first test transistor T20. In this case, since a voltage of a different level from the driving voltage according to the driving current is applied to the second electrode CE of the first light emitting element REL, the first light emitting element REL may not emit light as intended. That is, by forming the first test transistor T20 and the second test transistor T21, it is possible to check whether the first electrode AE or the second electrode CE is shorted with the other electrode or the wiring due to the damage of the first pad electrode CTE1 and the second pad electrode CTE 2.

Further, the second test transistor T21 may overlap the second electrode CE, the second pad electrode CTE2, the fourth pad connection electrode CPD1, and the vertical power supply line VVDL of the first light emitting element REL in the third direction DR 3. When a sufficient pressure (e.g., a predetermined pressure) is applied to the first light emitting element REL to attach the first light emitting element REL to the second pad electrode CTE2, the third planarization layer 190 supporting the second pad electrode CTE2 and the fourth pad connection electrode CPD1 and the second planarization layer 180 supporting the vertical power supply line VVDL and the second inorganic insulating layer 181 may collapse.

Accordingly, the second electrode CE, the second pad electrode CTE2, the fourth pad connection electrode CPD1, and the vertical power supply line VVDL of the first light emitting element REL may be short-circuited with the second horizontal power supply line HVDL2 connected to the second test source electrode S21 of the second test transistor T21. In this case, since a voltage of a different level from the driving voltage according to the driving current is applied to the second electrode CE of the first light emitting element REL, the first light emitting element REL may not emit light as intended. Alternatively, the second electrode CE, the second pad electrode CTE2, the fourth pad connection electrode CPD1, and the vertical power supply line VVDL of the first light emitting element REL may be short-circuited with the third horizontal power supply line HVSL1 connected to the second test drain electrode D21 of the second test transistor T21. In this case, since a voltage of a different level from the driving voltage according to the driving current is applied to the second electrode CE of the first light emitting element REL, the first light emitting element REL may not emit light as intended. That is, by forming the first test transistor T20 and the second test transistor T21, it is possible to check whether the first electrode AE or the second electrode CE is shorted with the other electrode or the wiring due to the damage of the first pad electrode CTE1 and the second pad electrode CTE 2.

Fig. 15 is a circuit diagram illustrating a first subpixel in accordance with one or more embodiments. Fig. 16 is a layout diagram illustrating a lower metal layer, an active layer, a first gate metal layer, a second gate metal layer, a first source metal layer, and a second source metal layer of a first subpixel according to one or more embodiments. Fig. 17 is an enlarged layout diagram showing the region C of fig. 16 in detail. Fig. 18 is a cross-sectional view showing an example of the first sub-pixel taken along the line C-C' of fig. 16 and 17.

The embodiment of fig. 15 to 18 is different from the embodiments of fig. 4, 5, 11 and 13 in that the first test gate electrode G20 of the first test transistor T20 is connected to the first inspection enable signal line IEL1, and the second test gate electrode G21 of the second test transistor T21 is connected to the second inspection enable signal line IEL2. In the embodiment of fig. 15 to 18, a description overlapping with the description of the embodiment of fig. 4, 5, 11, and 13 will be omitted.

Referring to fig. 15, the first test transistor T20 is turned on by a first check enable signal of the first check enable signal line IEL1 to connect the first power line VDL1 and the second power line VSL. The second test transistor T21 is turned on by a second check enable signal of the second check enable signal line IEL2 to connect the first power line VDL1 and the second power line VSL.

Referring to fig. 16 to 18, the first and second inspection enable signal lines IEL1 and IEL2 may extend in the first direction DR 1. The first inspection enable signal line IEL1 may be disposed between the second horizontal power line HVDL2 and the second inspection enable signal line IEL2 in the second direction DR 2. The second inspection enable signal line IEL2 may be disposed between the first inspection enable signal line IEL1 and the third horizontal power line HVSL1 in the second direction DR 2.

The first inspection enable signal line IEL1 may be connected to the eighth gate connection electrode GCE8 through the twenty-eighth contact hole CT28 penetrating the first and second interlayer insulating layers 141 and 142. The second inspection enable signal line IEL2 may be connected to the ninth gate connection electrode GCE9 through a thirty-first contact hole CT31 penetrating the first and second interlayer insulating layers 141 and 142.

Fig. 19 is a circuit diagram illustrating a first subpixel in accordance with one or more embodiments. Fig. 20 is a layout diagram illustrating a lower metal layer, an active layer, a first gate metal layer, a second gate metal layer, a first source metal layer, and a second source metal layer of a first subpixel according to one or more embodiments. Fig. 21 is an enlarged layout diagram showing the region C of fig. 20 in detail. Fig. 22 is a cross-sectional view showing an example of the first sub-pixel taken along the line D-D' of fig. 20 and 21.

The embodiment of fig. 19 to 22 is different from the embodiments of fig. 4, 5, 11, and 13 in that the first test source electrode S20 of the first test transistor T20 and the second test source electrode S21 of the second test transistor T21 are connected to the horizontal voltage line HVL to which an appropriate voltage (e.g., a predetermined voltage) is applied, and the first test drain electrode D20 of the first test transistor T20 and the second test drain electrode D21 of the second test transistor T21 are connected to the sense line SENL. In the embodiments of fig. 19 to 22, descriptions overlapping with those of the embodiments of fig. 4, 5, 11, and 13 will be omitted.

Referring to fig. 19, the first and second test transistors T20 and T21 are turned on by a test enable signal of the test enable signal line IEL, and then the horizontal voltage line HVL is connected to the sense line SENL. When the first and second test transistors T20 and T21 are turned on, an appropriate voltage (e.g., a predetermined voltage) of the horizontal voltage line HVL may be sensed by the sensing line SENL. The horizontal voltage line HVL may receive an appropriate voltage (e.g., a predetermined voltage). For example, the horizontal voltage line HVL may be supplied with a voltage substantially equal to one of the first power voltage of the first power supply line VDL1, the second power voltage of the second power supply line VSL, the third power voltage of the third power supply line VDL2, the gate-off voltage of the gate-off voltage line VGHL, and the initialization voltage of the initialization voltage line VIL.

When a sufficient pressure (e.g., a predetermined pressure) is applied to the first light emitting element REL to attach the first light emitting element REL to the first subpixel RP, the first electrode AE of the first light emitting element REL may be short-circuited with at least one of the first electrode and the second electrode of the first test transistor T20, and the second electrode CE of the first light emitting element REL may be short-circuited with one of the first electrode and the second electrode of the second test transistor T21. In this case, voltages other than an appropriate voltage (e.g., a predetermined voltage) may be sensed by the sense line SENL. That is, by sensing the voltage of the sensing line SENL passing through the first and second test transistors T20 and T21, the short circuit of the first electrode or the second electrode of the first light emitting element REL with the other electrode or the wiring can be checked.

Referring to fig. 20 to 22, the horizontal voltage line HVL and the sensing line SENL may extend in the first direction DR1 and may be disposed to be spaced apart from each other in the second direction DR 2. The check enable signal line IEL may be disposed between the horizontal voltage line HVL and the sense line SENL in the second direction DR 2.

The first test source electrode S20 of the first test transistor T20 may be connected to the horizontal voltage line HVL through a twenty-ninth contact hole CT29 penetrating the gate insulating layer 130, the first interlayer insulating layer 141 and the second interlayer insulating layer 142. The first test drain electrode D20 of the first test transistor T20 may be connected to the sensing line SENL through the thirty-first contact hole CT30 penetrating the gate insulating layer 130, the first interlayer insulating layer 141, and the second interlayer insulating layer 142. The second test source electrode S21 of the second test transistor T21 may be connected to the horizontal voltage line HVL through the thirty-second contact hole CT32 penetrating the gate insulating layer 130, the first interlayer insulating layer 141 and the second interlayer insulating layer 142. The second test drain electrode D21 of the second test transistor T21 may be connected to the sensing line SENL through a thirty-third contact hole CT33 penetrating the gate insulating layer 130, the first interlayer insulating layer 141, and the second interlayer insulating layer 142.

Fig. 23 is a circuit diagram illustrating a first subpixel in accordance with one or more embodiments. Fig. 24 is a layout diagram illustrating a lower metal layer, an active layer, a first gate metal layer, a second gate metal layer, a first source metal layer, and a second source metal layer of a first subpixel according to one or more embodiments. Fig. 25 is an enlarged layout diagram showing the region C of fig. 24 in detail. Fig. 26 is a cross-sectional view showing an example of the first sub-pixel taken along line E-E' of fig. 24 and 25.

The embodiment of fig. 23 to 26 is different from the embodiment of fig. 15 to 18 in that the first test source electrode S20 of the first test transistor T20 and the second test source electrode S21 of the second test transistor T21 are connected to the horizontal voltage line HVL to which an appropriate voltage (e.g., a predetermined voltage) is applied, and the first test drain electrode D20 of the first test transistor T20 and the second test drain electrode D21 of the second test transistor T21 are connected to the sense line SENL. In the embodiment of fig. 23 to 26, a description overlapping with that of the embodiment of fig. 15 to 18 will be omitted.

Since the first test source electrode S20 of the first test transistor T20 and the second test source electrode S21 of the second test transistor T21 are connected to the horizontal voltage line HVL to which an appropriate voltage (e.g., a predetermined voltage) is applied, and the first test drain electrode D20 of the first test transistor T20 and the second test drain electrode D21 of the second test transistor T21 are connected to the sense line SENL substantially the same as described in connection with the embodiment of fig. 19 to 22, a description thereof will be omitted.

Fig. 27 is a circuit diagram illustrating a first sub-pixel in accordance with one or more embodiments. Fig. 28 is a layout diagram illustrating a lower metal layer, an active layer, a first gate metal layer, a second gate metal layer, a first source metal layer, and a second source metal layer of a first subpixel according to one or more embodiments. Fig. 29 is an enlarged layout diagram showing the region C of fig. 28 in detail. Fig. 30 is a cross-sectional view showing an example of the first sub-pixel taken along the line F-F' of fig. 28 and 29.

The embodiment of fig. 27 to 30 is different from the embodiment of fig. 19 to 22 in that the first test transistor T20 is omitted and a variable resistor VR is provided. In the embodiment of fig. 27 to 30, a description overlapping with that of the embodiment of fig. 19 to 22 will be omitted.

Referring to fig. 27, the second test transistor T21 may be disposed between the first horizontal voltage line HVL1 and the first sensing line SENL1, and the variable resistor VR may be disposed between the second horizontal voltage line HVL2 and the second sensing line SENL 2. The first and second horizontal voltage lines HVL1 and HVL2 may receive the same voltage. For example, the first and second horizontal voltage lines HVL1 and HVL2 may be supplied with voltages substantially equal to one of the first power voltage of the first power line VDL1, the second power voltage of the second power line VSL, the third power voltage of the third power line VDL2, the gate-off voltage of the gate-off voltage line VGHL, and the initialization voltage of the initialization voltage line VIL. Alternatively, the first and second horizontal voltage lines HVL1 and HVL2 may receive different voltages. For example, the first horizontal voltage line HVL1 may be supplied with a voltage substantially equal to one of the first power voltage of the first power supply line VDL1, the second power voltage of the second power supply line VSL, the third power voltage of the third power supply line VDL2, the gate-off voltage of the gate-off voltage line VGHL, and the initialization voltage of the initialization voltage line VIL. In one or more embodiments, the second horizontal voltage line HVL2 may be supplied with a voltage different from the voltage supplied to the first horizontal voltage line HVL1 among the first power voltage of the first power supply line VDL1, the second power voltage of the second power supply line VSL, the third power voltage of the third power supply line VDL2, the gate-off voltage of the gate-off voltage line VGHL, and the initialization voltage of the initialization voltage line VIL.

When a sufficient pressure (e.g., a predetermined pressure) is applied to the first light emitting element REL to attach the first light emitting element REL to the first subpixel RP, the second electrode CE of the first light emitting element REL is short-circuited with the variable resistor VR, or the resistance value of the variable resistor VR may be changed. That is, by sensing the voltage of the second sensing line SENL2 or the resistance value of the variable resistor VR, it is possible to check whether the second electrode CE of the first light emitting element REL is shorted with another electrode or wiring.

Referring to fig. 28 to 30, the first horizontal voltage line HVL1, the second horizontal voltage line HVL2, the first sensing line SENL1 and the second sensing line SENL2 extend in the first direction DR1 and may be disposed to be spaced apart from each other in the second direction DR 2. The check enable signal line IEL may be disposed between the first horizontal voltage line HVL1 and the first sensing line SENL 1.

The variable resistor VR may include a resistor unit RSU having a suitable resistance (e.g., a predetermined resistance). The resistor unit RSU may be a strain gauge comprising winding wiring. One end of the resistor unit RSU may be connected to the second horizontal voltage line HVL2, and the other end may be connected to the second sensing line SENL2. The resistor unit RSU may overlap the second electrode CE, the second pad electrode CTE2, and the fourth pad connection electrode CPD1 of the first light emitting element REL in the third direction DR 3.

The first source metal layer may include a resistor unit RSU. The resistor unit RSU may be disposed on the second interlayer insulating layer 142.

In one or more embodiments, a pressure sensing layer overlapping the resistor unit RSU may be additionally provided. The pressure sensing layer may include fine metal particles such as Quantum Tunneling Composites (QTCs). For example, the pressure sensing layer may be disposed on the second interlayer insulating layer 142, and the resistor unit RSU may be disposed on the pressure sensing layer, but the embodiment of the present specification may not be limited thereto.

Fig. 31 is a circuit diagram illustrating a first subpixel in accordance with one or more embodiments. Fig. 32 is a layout diagram illustrating a lower metal layer, an active layer, a first gate metal layer, a second gate metal layer, a first source metal layer, and a second source metal layer of a first subpixel according to one or more embodiments. Fig. 33 is an enlarged layout diagram showing the region C of fig. 32 in detail. Fig. 34 is a cross-sectional view showing an example of the first sub-pixel taken along the line G-G' of fig. 32 and 33.

The embodiment of fig. 31 to 34 is different from the embodiment of fig. 19 to 22 in that the first test transistor T20 and the second test transistor T21 are deleted, and the first variable resistor VR1 and the second variable resistor VR2 are provided. In the embodiment of fig. 31 to 34, a description overlapping with that of the embodiment of fig. 19 to 22 will be omitted.

Referring to fig. 31, the first variable resistor VR1 may be disposed between the first horizontal voltage line HVL1 and the first sensing line SENL1, and the second variable resistor VR2 may be disposed between the second horizontal voltage line HVL2 and the second sensing line SENL 2. The first and second horizontal voltage lines HVL1 and HVL2 may receive the same voltage. For example, the first and second horizontal voltage lines HVL1 and HVL2 may be supplied with voltages substantially equal to one of the first power voltage of the first power line VDL1, the second power voltage of the second power line VSL, the third power voltage of the third power line VDL2, the gate-off voltage of the gate-off voltage line VGHL, and the initialization voltage of the initialization voltage line VIL. Alternatively, the first and second horizontal voltage lines HVL1 and HVL2 may receive different voltages. For example, the first horizontal voltage line HVL1 may be supplied with a voltage substantially equal to one of the first power voltage of the first power supply line VDL1, the second power voltage of the second power supply line VSL, the third power voltage of the third power supply line VDL2, the gate-off voltage of the gate-off voltage line VGHL, and the initialization voltage of the initialization voltage line VIL. In one or more embodiments, the second horizontal voltage line HVL2 may be supplied with a voltage different from the voltage supplied to the first horizontal voltage line HVL1 among the first power voltage of the first power supply line VDL1, the second power voltage of the second power supply line VSL, the third power voltage of the third power supply line VDL2, the gate-off voltage of the gate-off voltage line VGHL, and the initialization voltage of the initialization voltage line VIL.

When a sufficient pressure (e.g., a predetermined pressure) is applied to the first light emitting element REL to attach the first light emitting element REL to the first subpixel RP, the first electrode AE of the first light emitting element REL may be shorted with the first variable resistor VR1, or the second electrode CE of the first light emitting element REL may be shorted with the second variable resistor VR 2. Therefore, the resistance value of the first variable resistor VR1 or the resistance value of the second variable resistor VR2 can be changed. That is, by sensing the voltage of the first sensing line SENL1 or the resistance value of the first variable resistor VR1, it is possible to check whether the first electrode AE of the first light emitting element REL is shorted with another electrode or wiring. Further, by sensing the voltage of the second sensing line SENL2 or the resistance value of the second variable resistor VR2, it is possible to check whether the second electrode CE of the first light emitting element REL is shorted with another electrode or wiring.

Referring to fig. 32 to 34, the first horizontal voltage line HVL1, the second horizontal voltage line HVL2, the first sensing line SENL1 and the second sensing line SENL2 may extend in the first direction DR1 and may be disposed to be spaced apart from each other in the second direction DR 2.

The first variable resistor VR1 may include a first resistor unit RSU1 having a suitable resistance (e.g., a predetermined resistance), and the second variable resistor VR2 may include a second resistor unit RSU2 having a suitable resistance (e.g., a predetermined resistance). Each of the first resistor unit RSU1 and the second resistor unit RSU2 may be a strain gauge including a serpentine wire.

One end of the first resistor unit RSU1 may be connected to the first horizontal voltage line HVL1, and the other end may be connected to the first sensing line SENL1. The first resistor unit RSU1 may overlap the first electrode AE, the first pad electrode CTE1, and the third pad connection electrode APD1 of the first light emitting element REL in the third direction DR 3.

One end of the second resistor unit RSU2 may be connected to the second horizontal voltage line HVL2, and the other end may be connected to the second sensing line SENL2. The second resistor unit RSU2 may overlap the second electrode CE, the second pad electrode CTE2, and the fourth pad connection electrode CPD1 of the first light emitting element REL in the third direction DR 3.

The first source metal layer may include a first resistor unit RSU1 and a second resistor unit RSU2. The first and second resistor units RSU1 and RSU2 may be disposed on the second interlayer insulating layer 142.

In one or more embodiments, a first pressure sensing layer overlapping the first resistor unit RSU1 and a second pressure sensing layer overlapping the second resistor unit RSU2 may be additionally provided. Each of the first and second pressure sensing layers may include fine metal particles such as Quantum Tunneling Composites (QTCs). For example, each of the first and second pressure sensing layers is disposed on the second interlayer insulating layer 142, the first resistor unit RSU1 is disposed on the first pressure sensing layer, and the second resistor unit RSU2 may be disposed on the second pressure sensing layer, but the embodiment of the present specification may not be limited thereto.

Fig. 35 is a circuit diagram illustrating a first subpixel in accordance with one or more embodiments. Fig. 36 is a layout diagram illustrating a lower metal layer, an active layer, a first gate metal layer, a second gate metal layer, a first source metal layer, and a second source metal layer of a first subpixel according to one or more embodiments. Fig. 37 is an enlarged layout diagram showing the region C of fig. 36 in detail. Fig. 38 is a cross-sectional view showing an example of the first sub-pixel taken along the line H-H' of fig. 36 and 37.

The embodiment of fig. 35 to 38 is different from the embodiments of fig. 4, 5, 11 and 13 in that the first dummy transistor DT1 and the second dummy transistor DT2 are provided instead of the first test transistor T20 and the second test transistor T21. In the embodiments of fig. 35 to 38, descriptions overlapping with those of the embodiments of fig. 4, 5, 11, and 13 will be omitted.

Referring to fig. 35 to 38, the first and second dummy transistors DT1 and DT2 may be substantially the same as the first and second test transistors T20 and T21 shown in fig. 4, 5, 11, and 13 except that their gate electrodes are connected to the floating line FTL instead of the inspection enable signal line IEL. The floating line FTL may be a line to which no signal or voltage is applied. In this case, the first dummy transistor DT1 and the second dummy transistor DT2 may maintain an off state.

Alternatively, the gate electrode of the first dummy transistor DT1 and the gate electrode of the second dummy transistor DT2 may be connected to the gate-off voltage line VGHL instead of the floating line FTL. In this case, the first dummy transistor DT1 and the second dummy transistor DT2 may maintain an off state.

Fig. 39 is a layout diagram illustrating a lower metal layer, an active layer, a first gate metal layer, a second gate metal layer, a first source metal layer, and a second source metal layer of a first subpixel according to one or more embodiments. Fig. 40 is a layout diagram illustrating a third source metal layer of a first subpixel in accordance with one or more embodiments. Fig. 41 is a layout diagram illustrating a fourth source metal layer of a first subpixel in accordance with one or more embodiments. Fig. 42 is a layout diagram illustrating a transparent electrode layer and a first light emitting device of a first sub-pixel according to one or more embodiments.

The embodiment of fig. 39 to 42 is different from the embodiment of fig. 5 to 8 in that the first test transistor T20 and the second test transistor T21 are deleted, and the first light emitting element REL overlaps some of the first to nineteenth transistors T1 to T19. In the embodiment of fig. 39 to 42, a description overlapping with that of the embodiment of fig. 5 to 8 will be omitted.

Referring to fig. 39 to 42, the first light emitting element REL may overlap some of the first to nineteenth transistors T1 to T19, for example, the seventh and sixteenth transistors T7 and T16, the seventeenth transistor T17, and the eighteenth transistor T18. Further, the first pad electrode CTE1 and the third pad connection electrode APD1 may overlap the seventh transistor T7 and the seventeenth transistor T17. The second pad electrode CTE2 and the fourth pad connection electrode CPD1 may overlap the sixteenth transistor T16 and the eighteenth transistor T18.

Referring to fig. 43, a fifth source metal layer may be disposed on the third inorganic insulating layer 191. The first reinforcing electrode SPE1 and the second reinforcing electrode SPE2 may be disposed on the third planarization layer 190. The first reinforcement electrode SPE1 may overlap the first and third pad electrodes CTE1 and APD1 in the third direction DR3, and the second reinforcement electrode SPE2 may overlap the second and fourth pad electrodes CTE2 and CPD 1.

The third inorganic insulating layer 191 may be disposed between the first reinforcing electrode SPE1 and the third pad connection electrode APD1 and between the second reinforcing electrode SPE2 and the fourth pad connection electrode CPD 1. The third inorganic insulating layer 191 may be formed of an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

When a sufficient pressure (e.g., a predetermined pressure) is applied to the first light emitting element REL to attach the first light emitting element REL to the first pad electrode CTE1, the third inorganic insulating layer 191 and the third planarization layer 190 supporting the first pad electrode CTE1, the second pad electrode CTE2, the third pad connection electrode APD1 and the fourth pad connection electrode CPD1 may collapse. Since the first and second reinforcing electrodes SPE1 and SPE2 are electrically floating, the third planarization layer 190 and the third inorganic insulating layer 191 collapse due to the pressure applied to the first light emitting element REL. Accordingly, the third pad connection electrode APD1 is short-circuited with the first reinforcing electrode SPE1, and the fourth pad connection electrode CPD1 is short-circuited with the second reinforcing electrode SPE2, but light emitted from the first light emitting element REL emitting light may not be affected.

Further, when the first reinforcing electrode SPE1 and the second reinforcing electrode SPE2 press the first light emitting element REL, the transistor overlapping the first light emitting element REL can be prevented from being damaged. Because the first and second reinforcement electrodes SPE1 and SPE2 serve to support the third and fourth pad connection electrodes APD1 and CPD1.

Referring to fig. 44, a tiled display device TD according to one or more embodiments may include a plurality of display devices 11, 12, 13, and 14, and a connection member (or seam) SM. For example, the tile display device TD may include a first display device 11, a second display device 12, a third display device 13, and a fourth display device 14.

The plurality of display devices 11, 12, 13, and 14 may be arranged in a matrix form of M (M is a positive integer) rows and N (N is a positive integer) columns. For example, the first display device 11 and the second display device 12 may be adjacent to each other in the first direction DR 1. The first display device 11 and the third display device 13 may be adjacent to each other in the second direction DR 2. The third display device 13 and the fourth display device 14 may be adjacent to each other in the first direction DR 1. The second display device 12 and the fourth display device 14 may be adjacent to each other in the second direction DR 2.

However, the number and arrangement of the plurality of display devices 11, 12, 13, and 14 in the tile display device TD are not limited to those shown in fig. 44. The number and arrangement of the display devices 11, 12, 13, and 14 in the tile device TD may be determined in response to the sizes of the display devices and the tile device TD and the shape of the tile device TD.

The plurality of display devices 11, 12, 13, and 14 may have the same size as each other, but the embodiment of the present disclosure is not limited thereto. For example, the plurality of display devices 11, 12, 13, and 14 may have different sizes.

Each of the plurality of display devices 11, 12, 13, and 14 may have a rectangular shape including long sides and short sides. The plurality of display devices 11, 12, 13, and 14 may be disposed such that long sides or short sides thereof are connected to each other. Some or all of the plurality of display devices 11, 12, 13, and 14 may be disposed at an edge of the tile device TD, and one side of the tile device TD may be disposed. At least one of the plurality of display devices 11, 12, 13, and 14 may be disposed at least one corner of the tile display device TD, and may form two adjacent sides of the tile display device TD. At least one of the plurality of display devices 11, 12, 13, and 14 may be surrounded by other display devices.

Each of the plurality of display devices 11, 12, 13, and 14 may be substantially the same as the display device 10 described with reference to fig. 1. Therefore, a description of each of the plurality of display devices 11, 12, 13, and 14 will be omitted.

The connection member SM may include a coupling member or an adhesive member. In this case, the plurality of display devices 11, 12, 13, and 14 may be connected to each other by a coupling member or an adhesive member of the connection member SM. The connection member SM may be disposed between the first display device 11 and the second display device 12, between the first display device 11 and the third display device 13, between the second display device 12 and the fourth display device 14, and between the third display device 13 and the fourth display device 14.

Referring to fig. 45, the connection member SM may have a cross or plus planar shape in a central region of the tile display device TD in which the first display device 11, the second display device 12, the third display device 13, and the fourth display device 14 are adjacent to each other. The first display device 11 may include first pixels PX1 arranged in a matrix form along the first direction DR1 and the second direction DR2 to display an image. The second display device 12 may include second pixels PX2 arranged in a matrix form along the first direction DR1 and the second direction DR2 to display an image. The third display device 13 may include third pixels PX3 arranged in a matrix form along the first direction DR1 and the second direction DR2 to display an image. The fourth display device 14 may include fourth pixels PX4 arranged in a matrix form along the first direction DR1 and the second direction DR2 to display an image.

The minimum distance between the adjacent first pixels PX1 in the first direction DR1 may be defined as a first horizontal separation distance GH1, and the minimum distance between the adjacent second pixels PX2 in the first direction DR1 may be defined as a second horizontal separation distance GH2. The first horizontal separation distance GH1 and the second horizontal separation distance GH2 may be substantially the same.

The connection member SM may be disposed between the first pixel PX1 and the second pixel PX2 adjacent in the first direction DR 1. The minimum distance GH12 between the adjacent first and second pixels PX1 and PX2 in the first direction DR1 may be a sum of the minimum distance GHs1 between the first pixel PX1 and the connection member SM in the first direction DR1, the minimum distance GHs2 between the second pixel PX2 and the connection member SM in the first direction DR1, and the width GSM1 of the connection member SM in the first direction DR 1.

The minimum distance GH12, the first horizontal separation distance GH1, and the second horizontal separation distance GH2 between the first pixel PX1 and the second pixel PX2 adjacent in the first direction DR1 may be substantially the same. For this, a minimum distance GHS1 between the first pixel PX1 and the connection member SM in the first direction DR1 may be smaller than the first horizontal separation distance GH1, and a minimum distance GHS2 between the second pixel PX2 and the connection member SM in the first direction DR1 may be smaller than the second horizontal separation distance GH2. Further, the width GSM1 of the connection member SM in the first direction DR1 may be smaller than the first horizontal separation distance GH1 or the second horizontal separation distance GH2.

The minimum distance between the adjacent third pixels PX3 in the first direction DR1 may be defined as a third horizontal separation distance GH3, and the minimum distance between the adjacent fourth pixels PX4 in the first direction DR1 may be defined as a fourth horizontal separation distance GH4. The third horizontal separation distance GH3 and the fourth horizontal separation distance GH4 may be substantially the same.

The connection member SM may be disposed between the third pixel PX3 and the fourth pixel PX4 adjacent in the first direction DR 1. The minimum distance G34 between the third pixel PX3 and the fourth pixel PX4 adjacent in the first direction DR1 may be a sum of the minimum distance GHS3 between the third pixel PX3 and the connection member SM in the first direction DR1, the minimum distance GHS4 between the fourth pixel PX4 and the connection member SM in the first direction DR1, and the width GSM1 of the connection member SM in the first direction DR 1.

The minimum distance G34, the third horizontal separation distance GH3, and the fourth horizontal separation distance GH4 between the third pixel PX3 and the fourth pixel PX4 adjacent in the first direction DR1 may be substantially the same. For this, a minimum distance GHS3 between the third pixel PX3 and the connection member SM in the first direction DR1 may be smaller than the third horizontal separation distance GH3, and a minimum distance GHS4 between the fourth pixel PX4 and the connection member SM in the first direction DR1 may be smaller than the fourth horizontal separation distance GH4. Further, in the first direction DR1, the width GSM1 of the connection member SM may be smaller than the third horizontal separation distance GH3 or the fourth horizontal separation distance GH4.

The minimum distance between the adjacent first pixels PX1 in the second direction DR2 may be defined as a first vertical separation distance GV1, and the minimum distance between the adjacent third pixels PX3 in the second direction DR2 may be defined as a third vertical separation distance GV3. The first and third vertical separation distances GV1 and GV3 may be substantially the same.

The connection member SM may be disposed between the first pixel PX1 and the third pixel PX3 adjacent in the second direction DR 2. The minimum distance GH13 between the adjacent first and third pixels PX1 and PX3 in the second direction DR2 may be a sum of the minimum distance GVS1 between the first pixel PX1 and the connection member SM in the second direction DR2, the minimum distance GVS3 between the third pixel PX3 and the connection member SM in the second direction DR2, and the width GSM2 of the connection member SM in the second direction DR 2.

The minimum distance GH13, the first vertical separation distance GV1, and the third vertical separation distance GV3 between the adjacent first and third pixels PX1 and PX3 in the second direction DR2 may be substantially the same. For this, the minimum distance GVS1 between the first pixel PX1 and the connection member SM in the second direction DR2 may be smaller than the first vertical separation distance GV1, and the minimum distance GVS3 between the third pixel PX3 and the connection member SM in the second direction DR2 may be smaller than the third vertical separation distance GV3. Further, in the second direction DR2, the width GSM2 of the connection member SM may be smaller than the first vertical separation distance GV1 or the third vertical separation distance GV3.

The minimum distance between the second pixels PX2 adjacent in the second direction DR2 may be defined as a second vertical separation distance GV2, and the minimum distance between the fourth pixels PX4 adjacent in the second direction DR2 may be defined as a fourth vertical separation distance GV4. The second vertical separation distance GV2 and the fourth vertical separation distance GV4 may be substantially the same.

The connection member SM may be disposed between the second pixel PX2 and the fourth pixel PX4 adjacent in the second direction DR 2. The minimum distance G24 between the second pixel PX2 and the fourth pixel PX4 adjacent in the second direction DR2 may be a sum of the minimum distance GVS2 between the second pixel PX2 and the connection member SM in the second direction DR2, the minimum distance GVS4 between the fourth pixel PX4 and the connection member SM in the second direction DR2, and the width GSM2 of the connection member SM in the second direction DR 2.

The minimum distance G24, the second vertical separation distance GV2, and the fourth vertical separation distance GV4 between the second pixel PX2 and the fourth pixel PX4 adjacent in the second direction DR2 may be substantially the same. For this, the minimum distance GVS2 between the second pixel PX2 and the connection member SM in the second direction DR2 may be smaller than the second vertical separation distance GV2, and the minimum distance GVS4 between the fourth pixel PX4 and the connection member SM in the second direction DR2 may be smaller than the fourth vertical separation distance GV4. Further, in the second direction DR2, the width GSM2 of the connection member SM may be smaller than the second vertical separation distance GV2 or the fourth vertical separation distance GV4.

As shown in fig. 45, in order to prevent the connection member SM from being recognized between images displayed by the plurality of display devices 11, 12, 13, and 14, the minimum distance between pixels of adjacent display devices may be substantially equal to the minimum distance between each of the pixels.

Referring to fig. 46, the first display device 11 includes a first display module DPM1 and a first front cover COV1. The second display device 12 includes a second display module DPM2 and a second front cover COV2.

Each of the first display module DPM1 and the second display module DPM2 includes a substrate SUB, a thin film transistor layer TFTL, and a light emitting device layer. The thin film transistor layer TFTL and the light emitting device layer have been described in detail with reference to fig. 12 and 13. In fig. 46, a description overlapping with the embodiment of fig. 12 and 13 will be omitted.

The substrate SUB may include a first surface 41 on which the thin film transistor layer TFTL is disposed, a second surface 42 opposite to the first surface 41, and a first side surface 43 disposed between the first surface 41 and the second surface 42. The first surface 41 may be a front surface or an upper surface of the substrate SUB, and the second surface 42 may be a bottom surface or a lower surface of the substrate SUB.

In addition, the substrate SUB may further include a chamfer surface 44 disposed between the first surface 41 and the first side surface 43 and between the second surface 42 and the first side surface 43. The thin film transistor layer TFTL and the light emitting device layer may not be disposed on the chamfer surface 44. Due to the chamfer surface 44, damage caused by collision of the substrate SUB of the first display device 11 with the substrate SUB of the second display device 12 can be prevented.

The chamfer surface 44 may be provided between the first surface 41 and each of the other side surfaces than the first side surface 43 and between the second surface 42 and each of the other side surfaces than the first side surface 43. For example, when the first display device 11 and the second display device 12 have rectangular planar shapes as shown in fig. 44, the chamfer surface 44 may be provided between the first surface 41 and each of the second surface 42, the third surface, and the fourth surface, and between the second surface 42 and each of the first surface 41, the third surface, and the fourth surface.

The first front cover COV1 may be disposed on the chamfer surface 44 of the substrate SUB. That is, the first front cover COV1 may protrude more than the substrate SUB in the first direction DR1 and the second direction DR 2. Accordingly, the distance GSUB between the substrate SUB of the first display device 11 and the substrate SUB of the second display device 12 may be greater than the distance GCOV between the first front cover COV1 and the second front cover COV2.

Each of the first and second front covers COV1 and COV2 may include an adhesive member 51, a light transmittance controlling layer 52 disposed on the adhesive member 51, and an anti-glare layer 53 disposed on the light transmittance controlling layer 52.

The adhesive member 51 of the first front cover COV1 serves to attach the light emitting device layer of the first display module DPM1 to the first front cover COV1. The adhesive member 51 of the second front cover COV2 serves to attach the light emitting device layer of the second display module DPM2 to the second front cover COV2. The adhesive member 51 may be a transparent adhesive member capable of transmitting light. For example, the adhesive member 51 may be an optically transparent adhesive film or an optically transparent resin.

The anti-glare layer 53 may be designed to diffusely reflect external light to prevent degradation of image visibility by reflecting external light as it is. Accordingly, due to the anti-glare layer 53, the contrast of the images displayed by the first display device 11 and the second display device 12 can be increased.

The light transmittance control layer 52 may be designed to reduce the transmittance of external light or light reflected from the first and second display modules DPM1 and DPM 2. Accordingly, the distance GSUB between the substrate SUB of the first display module DPM1 and the substrate SUB of the second display module DPM2 can be prevented from being visually recognized from the outside.

The anti-glare layer 53 may be implemented as a polarizer, and the light transmittance controlling layer 52 may be implemented as a phase retardation layer, but the embodiment of the present specification is not limited thereto.

Since the example of the tile device TD cut along the lines K-K ', L-L', and M-M 'of fig. 45 is substantially the same as the example of the tile device TD cut along the line J-J' described in connection with fig. 46, a description thereof will be omitted.

Fig. 47 is a plan view illustrating a front surface of a first display device according to one or more embodiments. Fig. 48 is a plan view illustrating a bottom surface of a first display device in accordance with one or more embodiments. Fig. 49 is a cross-sectional view showing an example of the first display device taken along the line N-N' of fig. 47 and 48.

Referring to fig. 47 and 48, the front display pad DPD, the front inspection pad IPD, and the front power pad VPD may be front pads disposed on the front surface of the substrate SUB. The front display pad DPD and the front inspection pad IPD may be disposed on an upper edge of the substrate SUB, and the front power pad VPD may be disposed on a lower edge of the substrate SUB. The front inspection pad IPD may be disposed closer to the left and right corners than the front display pad DPD. That is, some of the front inspection pads IPD may be disposed closer to the left edge than the front display pad DPD, and other front inspection pads IPD may be disposed closer to the right edge than the front display pad DPD.

The bottom display pad DBD, the bottom check pad IBD, and the bottom power pad VBD may be bottom pads disposed on the bottom surface of the substrate SUB. The bottom display pad DBD and the bottom inspection pad IBD may be disposed on an upper edge of the substrate SUB, and the bottom power pad VBD may be disposed on a lower edge of the substrate SUB. The bottom inspection pad IBD may be disposed closer to the left and right corners than the bottom display pad DBD. That is, some of the bottom check pads IBD may be disposed closer to the left edge than the bottom display pads DBD, and other bottom check pads IBD may be disposed closer to the right edge than the bottom display pads DBD.

The inspection multiplexer Imux may be disposed between the front inspection pad IPD, the inspection enable signal lines IEL, IEL1, and IEL2, the front inspection pad IPD, and the sense lines SENL, SENL1, and SENL2. The inspection multiplexer Imux may connect the pre-inspection pad IPD and the inspection enable signal lines IEL, IEL1, and IEL2 in a manner of 1:P (P is an integer greater than or equal to 2), and may connect the pre-inspection pad IPD and the sense lines SENL, SENL1, and SENL2 in a manner of 1:P. Due to the inspection multiplexer Imux, the number of pre-inspection pads IPD can be reduced or minimized.

The display multiplexer Dmux may be disposed between the front display pad DPD and the sub-pixels RP, GP and BP. The display multiplexer Dmux may connect the data line DL and the subpixels RP, GP and BP connected to the front display pad DPD in a manner of 1:Q (Q is an integer greater than or equal to 2). The number of front display pads DPD can be reduced or minimized due to the display multiplexer Dmux.

Each of the front display pads DPD may include a first sub-pad SPD1, a second sub-pad SPD2, a third sub-pad SPD3, a fourth sub-pad SPD4, and a fifth sub-pad SPD5. The front inspection pad IPD and the front power pad VPD may also include a first sub-pad SPD1, a second sub-pad SPD2, a third sub-pad SPD3, a fourth sub-pad SPD4, and a fifth sub-pad SPD5, respectively.

The first source metal layer may further include a first sub-pad SPD1, the second source metal layer may further include a second sub-pad SPD2, and the third source metal layer may further include a third sub-pad SPD3, the fourth source metal layer may further include a fourth sub-pad SPD4, and the transparent electrode layer may further include a fifth sub-pad SPD5.

The second sub-pad SPD2 may be disposed on the first sub-pad SPD1, and the third sub-pad SPD3 may be disposed on the second sub-pad SPD 2. The fourth sub-pad SPD4 may be disposed on the third sub-pad SPD3, and the fifth sub-pad SPD5 may be disposed on the fourth sub-pad SPD 4. An upper surface of the first sub-pad SPD1 may contact a lower surface of the second sub-pad SPD2, and an upper surface of the second sub-pad SPD2 may contact a lower surface of the third sub-pad SPD 3. An upper surface of the third sub-pad SPD3 may contact a lower surface of the fourth sub-pad SPD4, and an upper surface of the fourth sub-pad SPD4 may contact a lower surface of the fifth sub-pad SPD5.

A bottom connection line (also referred to as a connection line) BCL may be provided on the bottom surface of the substrate SUB. The bottom connection line BCL may be formed as a single layer or a plurality of layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) and alloys thereof.

The second pad PD2 of each of the bottom display pad DBD, the bottom check pad IBD, and the bottom power pad VBD is disposed at one end of the bottom connecting line BCL, and the third pad PD3 may be disposed at the other end of the bottom connecting line BCL. The second and third pads PD2 and PD3 may be formed of transparent conductive oxides such as Indium Tin Oxide (ITO) and Indium Zinc Oxide (IZO).

The fifth planarization layer 170 may be disposed on the bottom connection line BCL and the bottom surface of the substrate SUB. The fifth planarization layer 170 may be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or the like. The fifth planarization layer 170 may be referred to as an organic insulating layer.

A fifth inorganic insulating layer 171 may be disposed on the fifth planarization layer 170. The fifth inorganic insulating layer 171 may be formed of an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

The side SIL may be disposed on the first surface 41, the chamfer surface 44, the first side surface 43, and the second surface 42 of the substrate SUB. The lateral line SIL may be connected to a front display pad DPD disposed on an edge of the first surface 41 of the substrate SUB. The lateral line SIL may be connected to a second pad PD2, the second pad PD2 being disposed on an edge of the second surface 42 of the substrate SUB. The side SIL may contact the chamfer surface 44 and the first side surface 43 of the substrate SUB.

The overcoat OC may be disposed on the first surface 41, the chamfer surface 44, the first side surface 43, and the second surface 42 of the substrate SUB. The overcoat layer OC may be formed to cover the side SIL. The overcoat OC may be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or the like.

The first circuit board 310 and the second circuit board 320 may be disposed on a bottom surface of the substrate SUB. The first circuit board 310 may be disposed near an upper edge of the substrate SUB, and the second circuit board 320 may be disposed near a lower edge of the substrate SUB. Each of the first and second circuit boards 310 and 320 may be connected to the third pad PD3 of the bottom connecting line BCL, which is not covered by the fifth planarization layer 170 and the fifth inorganic insulating layer 171 but is exposed, through the conductive adhesive member CAM. The conductive adhesive member CAM may be an anisotropic conductive film or an anisotropic conductive paste.

The first driving circuit 210 may be mounted on the first circuit board 310, and the second driving circuit 220 may be mounted on the second circuit board 320. The first and second driving circuits 210 and 220 may be integrated circuits.

The first driving circuit 210 may output the data voltage to the data line DL through the first circuit board 310, the bottom connection line BCL, the bottom display pad DBD, the lateral line SIL, the front display pad DPD, and the display multiplexer Dmux. In addition, the first driving circuit 210 may output the inspection enable signal to the inspection enable signal lines IEL, IEL1, and IEL2 through the first circuit board 310, the bottom connection line BCL, the bottom inspection pad IBD, the lateral line SIL, the front inspection pad IPD, and the inspection multiplexer Imux, and may sense the sensing voltages of the sensing lines SENL, SENL1, and SENL 2.

The second driving circuit 220 may output the first power voltage to the first power line VDL1, the second power voltage to the second power line VSL, and the third power voltage to the third power line VDL2, the initialization voltage to the initialization voltage line VIL, and the gate-off voltage to the gate-off voltage line VGHL through the second circuit board 320, the bottom connection line BCL, the bottom power pad VBD, the lateral line SIL, and the front power pad VPD. The second driving circuit 220 may be a dc-dc converter.

Referring to fig. 50, the inspection multiplexer Imux includes inspection pad lines IPL1, IPL2, IPL3, and IPL4, inspection connection lines ICL1, ICL2, ICL3, and ICL4, inspection switch lines IWL1 to IWL12, and inspection lines IL1 to IL12. Further, the inspection multiplexer Imux includes a first switch group SWG1, a second switch group SWG2, and a third switch group SWG3. The inspection multiplexer Imux connects the pre-inspection pad IPD and the inspection lines IL1 to IL12 at a ratio of 1:3 is shown in fig. 50, but the embodiment of the present specification is not limited thereto. The inspection lines IL1 to IL12 may correspond to the inspection enable signal lines IEL, IEL1, and IEL2, or may correspond to the sense lines SENL, SENL1, and SENL2.

The inspection pad lines IPL1, IPL2, IPL3, and IPL4 may extend in the second direction DR 2. The inspection pad lines IPL1, IPL2, IPL3, and IPL4 may be connected to the front inspection pad IPD and the inspection connection lines ICL1, ICL2, ICL3, and ICL4 one to one. That is, the inspection pad lines IPL1, IPL2, IPL3, and IPL4 may be connected to the front inspection pad IPD and the inspection connection lines ICL1, ICL2, ICL3, and ICL4, respectively.

The check connection lines ICL1, ICL2, ICL3 and ICL4 may extend in the first direction DR 1. The inspection connection lines ICL1, ICL2, ICL3, and ICL4 may be connected to inspection switch lines IWL1 to IWL12. The first check connection line ICL1 may be connected to a 4k-3 (k is a positive integer) check switch line. For example, the first inspection connection line ICL1 may be connected to the first inspection switch line IWL1, the fifth inspection switch line IWL5, and the ninth inspection switch line IWL9. The second check connection line ICL2 may be connected to a 4k-2 th check switch line. The second inspection connection line ICL2 may be connected to the second inspection switch line IWL2, the sixth inspection switch line IWL6, and the tenth inspection switch line IWL10. The third check connection line ICL3 may be connected to the 4k-1 th check switch line. The third inspection connection line ICL3 may be connected to the third inspection switch line IWL3, the seventh inspection switch line IWL7, and the eleventh inspection switch line IWL11. The fourth check connection line ICL4 may be connected to a 4 k-th check switch line. The fourth inspection connection line ICL4 may be connected to the fourth inspection switch line IWL4, the eighth inspection switch line IWL8, and the twelfth inspection switch line IWL12.

The first switch group SWG1 may connect the first to fourth inspection lines IL1 to IL4 to the first to fourth inspection pad lines IPL1 to IPL4 through the first switch control signal SCS 1. Accordingly, the first to fourth inspection lines IL1 to IL4 may be connected to the first to fourth inspection pad lines IPL1 to IPL4 through the first switch group SWG 1.

The first switch group SWG1 may include first to fourth switches SW1 to SW4. The first switch SW1 may be disposed between the first inspection line IL1 and the first inspection switch line IWL 1. The second switch SW2 may be disposed between the second inspection line IL2 and the second inspection switch line IWL 2. The third switch SW3 may be disposed between the third inspection line IL3 and the third inspection switch line IWL 3. The fourth switch SW4 may be disposed between the fourth inspection line IL4 and the fourth inspection switch line IWL 4.

The second switch group SWG2 may connect the fifth to eighth inspection lines IL5 to IL8 to the first to fourth inspection pad lines IPL1 to IPL4 through the second switch control signal SCS 2. Accordingly, the fifth to eighth inspection lines IL5 to IL8 may be connected to the first to fourth inspection pad lines IPL1 to IPL4 through the second switch group SWG 2.

The second switch group SWG2 may include fifth to eighth switches SW5 to SW8. The fifth switch SW5 may be disposed between the fifth inspection line IL5 and the fifth inspection switch line IWL 5. The sixth switch SW6 may be disposed between the sixth inspection line IL6 and the sixth inspection switch line IWL 6. The seventh switch SW7 may be disposed between the seventh inspection line IL7 and the seventh inspection switch line IWL 7. The eighth switch SW8 may be provided between the eighth inspection line IL8 and the eighth inspection switch line IWL 8.

The third switch group SWG3 may connect the ninth to twelfth inspection lines IL9 to IL12 to the first to fourth inspection pad lines IPL1 to IPL4 through the third switch control signal SCS 3. Accordingly, the ninth to twelfth inspection lines IL9 to IL12 may be connected to the first to fourth inspection pad lines IPL1 to IPL4 through the third switch group SWG 3.

The third switch group SWG3 may include ninth to twelfth switches SW9 to SW12. The ninth switch SW9 may be provided between the ninth inspection line IL9 and the ninth inspection switch line IWL 9. The tenth switch SW10 may be disposed between the tenth inspection line IL10 and the tenth inspection switch line IWL 10. The eleventh switch SW11 may be disposed between the eleventh inspection line IL11 and the eleventh inspection switch line IWL 11. The twelfth switch SW12 may be provided between the twelfth inspection line IL12 and the twelfth inspection switch line IWL 12.

The period in which the first to fourth switches SW1 to SW4 of the first switch group SWG1 are turned on by the first switch control signal SCS1, the period in which the fifth to eighth switches SW5 to SW8 of the second switch group SWG2 are turned on by the second switch control signal SCS2, and the period in which the ninth to twelfth switches SW9 to SW12 of the third switch group SWG3 are turned on by the third switch control signal SCS3 may be different from each other. For this, the inspection pad lines IPL1 to IPL4 may be connected to the first to fourth inspection lines IL1 to IL4 through the first switch group SWG1, and may be connected to the fifth to eighth inspection lines IL5 to IL8 through the second switch group SWG2, and may be connected to the ninth to twelfth inspection lines IL9 to IL12 through the third switch group SWG 3. Accordingly, the inspection pad lines IPL1 to IPL4 can be sequentially connected to the first to fourth inspection lines IL1 to IL4, the fifth to eighth inspection lines IL5 to IL8, and the ninth to twelfth inspection lines IL9 to IL12 through the first, second, and third switch groups SWG1, SWG2, and SWG 3. That is, the inspection multiplexer Imux may connect the pre-inspection pad IPD and the inspection lines IL1 to IL12 at a ratio of 1:3.

Since the display multiplexer Dmux may be implemented similarly to the check multiplexer Imux described with reference to fig. 50, a detailed description of the display multiplexer Dmux will be omitted.

Referring to fig. 51, the front surface of the first display device 11 may be divided into a plurality of areas A1 to A9. For example, the first display device 11 may be divided into 9 areas A1 to A9. The plurality of areas A1 to A9 may have a uniform area. The plurality of areas A1 to A9 may include the same number of pixels PX.

In each of the plurality of areas A1 to A9, the inspection line (or the sensing lines SENL, SENL1, and SENL 2) may be connected to one of the front inspection pads IPD1 to IPD9. For example, the inspection line of the first area A1 may be connected to the first front inspection pad IPD1, the inspection line of the second area A2 may be connected to the second front inspection pad IPD2, the inspection line of the third area A3 may be connected to the third front inspection pad IPD3, the inspection line of the fourth area A4 may be connected to the fourth front inspection pad IPD4, and the inspection line of the fifth area A5 may be connected to the fifth front inspection pad IPD5. Further, the inspection line of the sixth area A6 may be connected to the sixth front inspection pad IPD6, the inspection line of the seventh area A7 may be connected to the seventh front inspection pad IPD7, the inspection line of the eighth area A8 may be connected to the eighth front inspection pad IPD8, and the inspection line of the ninth area A9 may be connected to the ninth front inspection pad IPD9.

In this case, it may be determined whether at least one of the light emitting devices of all the sub-pixels RP, GP, and BP in each of the plurality of regions A1 to A9 is shorted with another electrode or wiring. That is, it is possible to determine in which region the light emitting device of the sub-pixel is shorted with another electrode or wiring while reducing or minimizing the number of pre-inspection pads.

FIG. 52 is a block diagram illustrating a tiled display device in accordance with one or more embodiments. Fig. 53 is a diagram illustrating wireless communication between multiple display devices of a tiled display device in accordance with one or more embodiments.

In fig. 52, for convenience of description, the first display device 11 and the HOST system HOST are shown.

Referring to fig. 52 and 53, a tiled display device TD according to one or more embodiments may include a HOST system HOST, a broadcast tuning unit 210, a signal processing unit 220, a display unit 230, a speaker 240 and a user input unit 250, a Hard Disk Drive (HDD) 260, a network communication unit 270, a User Interface (UI) generating unit 280, and a control unit 290.

HOST system HOST may be implemented as one of a television system, home theater system, set-top box, navigation system, DVD player, blu-ray player, personal computer PC, mobile phone system, and tablet.

The user's command may be entered into HOST system HOST in various formats. For example, HOST system HOST may receive commands through user touch input. Alternatively, the user's command may be input to HOST system HOST through a keyboard input or a button input of the remote controller.

HOST system HOST may receive original video data corresponding to an original image from outside. HOST system HOST may divide the original video data according to the number of display devices. For example, the HOST system HOST corresponds to the first display device 11, the second display device 12, the third display device 13, and the fourth display device 14, so that the original video data can be divided into first video data corresponding to a first image, second video data corresponding to a second image, third video data corresponding to a third image, and fourth video data corresponding to a fourth image. HOST system HOST may transmit first video data to first display device 11, second video data to second display device 12, third video data to third display device 13, and fourth video data to fourth display device 14.

The first display device 11 may display a first image according to the first video data, and the second display device 12 may display a second image according to the second video data. Further, the third display device 13 may display a third image according to the third video data, and the fourth display device 14 may display a fourth image according to the fourth video data. Accordingly, the user can view the original image in which the first to fourth images displayed on the first, second, third, and fourth display devices 11, 12, 13, and 14 are combined.

The first display device 11 may include a broadcast tuning unit 210, a signal processing unit 220, a display unit 230, a speaker 240, a user input unit 250, an HDD 260, a network communication unit 270, a UI generating unit 280, and a control unit 290.

The broadcast tuning unit 210 may receive broadcast signals of the corresponding channels through the antennas by tuning an appropriate channel frequency (e.g., a predetermined channel frequency) under the control of the control unit 290. The broadcast tuning unit 210 may include a channel detection module and an RF demodulation module.

The broadcast signal demodulated by the broadcast tuning unit 210 is processed by the signal processing unit 220 and output to the display unit 230 and the speaker 240. The signal processing unit 220 may include a demultiplexer 221, a video decoder 222, a video processing unit 223, an audio decoder 224, and an additional data processing unit 225.

The demultiplexer 221 separates the demodulated broadcast signal into a video signal, an audio signal, and additional data. The separated video signal, audio signal, and additional data are restored by the video decoder 222, audio decoder 224, and additional data processing unit 225, respectively. In this case, when the broadcast signal is transmitted, the video decoder 222, the audio decoder 224, and the additional data processing unit 225 restore a decoding format corresponding to the encoding format.

On the other hand, the decoded video signal is converted into a vertical frequency, resolution, aspect ratio, etc. satisfying the output standard of the display unit 230 by the video processing unit 223, and the decoded audio signal is output to the speaker 240.

The display unit 230 includes a display panel 100 on which an image is displayed and a panel driver controlling driving of the display panel 100.

User input unit 250 may receive signals transmitted by HOST system HOST. The user input unit 250 allows the user to select not only data related to channel selection and User Interface (UI) menu selection and manipulation of channels transmitted by the HOST system HOST, but also commands related to communication with other display devices 11, 12, 13, and 14. Further, the user input unit 250 allows data for input to enter.

The HDD 260 stores various software programs including OS programs, recorded broadcasting programs, moving pictures, photographs, and other data. The HDD 260 may be made of a storage medium such as a hard disk or a nonvolatile memory.

The network communication unit 270 is used for short-range communication with the HOST system HOST and other display devices 11, 12, 13, and 14. The network communication unit 270 may implement a communication module including an antenna pattern that may implement mobile communication, data communication, bluetooth, RF, ethernet, etc.

The network communication unit 270 may transmit wireless signals to and receive wireless signals from at least one of a base station, an external terminal, and a server over a mobile communication network constructed according to a technical standard or a communication method for mobile communication, such as global system for mobile communication (GSM), code Division Multiple Access (CDMA), code division multiple access 2000 (CDMA 2000), enhanced voice data optimization or enhanced voice data only (EV-DO), wideband CDMA (WCDMA), high Speed Downlink Packet Access (HSDPA), high Speed Uplink Packet Access (HSUPA), long Term Evolution (LTE), long term evolution-advanced (LTE-a), 5G, etc.

The network communication unit 270 may transmit and receive wireless signals in a communication network according to a wireless internet technology. Wireless internet technologies include, for example, WLAN (wireless LAN), wi-Fi (wireless fidelity) direct, DLNA (digital living network alliance), wiBro (wireless broadband), wiMAX (worldwide interoperability for microwave access), high Speed Downlink Packet Access (HSDPA), high Speed Uplink Packet Access (HSUPA), long Term Evolution (LTE), long term evolution-advanced (LTE-a), and the like. The antenna pattern transmits and receives data according to at least one wireless internet technology within a range including even internet technologies not listed above.

Further, as shown in fig. 53, each of the first display device 11, the second display device 12, the third display device 13, and the fourth display device 14 may include an antenna pattern to transmit and receive wireless signals to and from each other. The first display device 11 may transmit the first wireless signal RS1, and the second display device 12, the third display device 13, and the fourth display device 14 may receive the first wireless signal RS1. Further, the second display device 12 may transmit the second wireless signal RS2, and the first display device 11, the third display device 13, and the fourth display device 14 may receive the second wireless signal RS2. In addition, the third display device 13 may transmit the third wireless signal RS3, and the first, second, and fourth display devices 11, 12, and 14 receive the third wireless signal RS3. Further, the fourth display device 14 may transmit the fourth wireless signal RS4, and the first, second, and third display devices 11, 12, and 13 may receive the fourth wireless signal RS4.

The UI generating unit 280 that generates the UI menu for wireless communication with the HOST system HOST and the second display device 12, the third display device 13, and the fourth display device 14 may be implemented by an algorithm code and an on-screen display integrated circuit (OSD IC). The UI menu for communicating with the HOST system HOST and the second display device 12, the third display device 13, and the fourth display device 14 may be a menu for designating a corresponding digital TV for communication and selecting a desired function.

The control unit 290 is responsible for overall control of the first display device 11 and for communication control of the HOST system HOST and the second display device 12 to the fourth display device 14. In the control unit 290, a corresponding algorithm code for control is stored, and the corresponding algorithm code may be implemented by a Micro Controller Unit (MCU).

Based on the input and selection of the user input unit 250, the control unit 290 controls to transmit corresponding control commands and data to the HOST system HOST and the second, third and fourth display devices 12, 13 and 14 through the network communication unit 270. When appropriate control commands (e.g., predetermined control commands) and data are received from the HOST system HOST and the second, third, and fourth display devices 12, 13, and 14, the control unit 290 performs operations according to the control commands.

Claims

1. A display device, comprising:

a plurality of sub-pixels, emitting light,

wherein the sub-pixels of the plurality of sub-pixels include:

a first pad electrode and a second pad electrode on the substrate and spaced apart from each other in a plan view;

a light emitting device on the first and second pad electrodes; and

A first inspection transistor overlapping with the first pad electrode in a thickness direction of the substrate,

wherein the first inspection transistor overlaps the light emitting device in the thickness direction of the substrate.

2. The display device according to claim 1, wherein the sub-pixel further includes a second inspection transistor overlapping the second pad electrode in the thickness direction of the substrate, and

wherein the second inspection transistor overlaps the light emitting device in the thickness direction of the substrate.

3. The display device according to claim 2, wherein a gate electrode of the first inspection transistor and a gate electrode of the second inspection transistor are connected to an inspection enable signal line.

4. The display device according to claim 2, wherein a gate electrode of the first inspection transistor is connected to a first inspection enable signal line, and a gate electrode of the second inspection transistor is connected to a second inspection enable signal line.

5. The display device according to claim 2, wherein the first electrode of the first inspection transistor and the first electrode of the second inspection transistor are connected to a first horizontal power supply line configured to receive a first power voltage.

6. The display device according to claim 5, further comprising:

a first data line connected to the sub-pixel and configured to receive a first data voltage; and

a second data line connected to the sub-pixel and configured to receive a second data voltage;

wherein the sub-pixel further comprises:

a first pixel driver including a first transistor configured to control a control current according to the first data voltage of the first data line;

a second pixel driver including a second transistor configured to control a driving current flowing from a first power line to the light emitting device according to the second data voltage of the second data line, the first power line configured to receive the first power voltage; and

a third pixel driver including a third transistor configured to adjust a period in which the driving current is applied to the light emitting device according to the control current of the first pixel driver.

7. The display device according to claim 2, wherein the second electrode of the first inspection transistor and the second electrode of the second inspection transistor are connected to a second horizontal power supply line configured to receive a second power voltage.

8. The display apparatus according to claim 7, wherein a first electrode of the light emitting device is connected to the first pad electrode, a second electrode of the light emitting device is connected to the second pad electrode, and the second pad electrode is connected to a second power line configured to receive the second power voltage.

9. The display device according to claim 2, wherein a first electrode of the first check transistor is connected to a horizontal voltage line, and a second electrode of the first check transistor is connected to a sensing line.

10. The display device of claim 9, wherein the horizontal voltage line is configured to receive a predetermined voltage.

11. The display device according to claim 9, wherein a first electrode of the second check transistor is connected to the horizontal voltage line, and a second electrode of the second check transistor is connected to the sensing line.

12. The display apparatus of claim 11, wherein the light emitting device is a flip chip micro light emitting diode device.

13. A display device, comprising:

a plurality of sub-pixels, emitting light,

wherein the sub-pixels of the plurality of sub-pixels include:

a light emitting device on the first and second pad electrodes; and

a first resistor unit overlapping the first pad electrode in a thickness direction of the substrate,

wherein the first resistor unit overlaps the light emitting device in the thickness direction of the substrate.

14. The display device according to claim 13, further comprising:

a first horizontal voltage line connected to one end of the first resistor unit; and

and a first sensing line connected to the other end of the first resistor unit.

15. The display device according to claim 13, wherein the sub-pixel further comprises an inspection transistor overlapping the second pad electrode in the thickness direction of the substrate, and

wherein the inspection transistor overlaps the light emitting device in the thickness direction of the substrate.

16. The display device according to claim 15, wherein a gate electrode of the inspection transistor is connected to an inspection enable signal line, and a first electrode of the inspection transistor is connected to a horizontal voltage line, and a second electrode of the inspection transistor is connected to a sensing line.

17. The display device according to claim 14, wherein the sub-pixel further comprises a second resistor unit overlapping the second pad electrode in the thickness direction of the substrate, and

wherein the second resistor unit overlaps the light emitting device in the thickness direction of the substrate.

18. The display device according to claim 17, further comprising:

a second horizontal voltage line connected to one end of the second resistor unit; and

and a second sensing line connected to the other end of the second resistor unit.

19. The display device according to claim 18, wherein the same voltage is supplied to the first horizontal voltage line and the second horizontal voltage line.

20. A display device, comprising:

a plurality of sub-pixels, emitting light,

wherein the sub-pixels of the plurality of sub-pixels include:

a light emitting device on the first and second pad electrodes; and

a first dummy transistor overlapping the first pad electrode in a thickness direction of the substrate,

Wherein the first dummy transistor overlaps the light emitting device in the thickness direction of the substrate, an

Wherein a gate electrode of the first dummy transistor is connected to a floating line or a gate-off voltage line configured to receive a gate-off voltage.

21. The display device according to claim 20, wherein the sub-pixel further comprises a second dummy transistor overlapping the second pad electrode in the thickness direction of the substrate, and

wherein the second dummy transistor overlaps the light emitting device in the thickness direction of the substrate.

22. The display device according to claim 21, wherein a gate electrode of the second dummy transistor is connected to the floating line or the gate-off voltage line.

23. The display apparatus of claim 20, wherein the light emitting device is a flip chip micro light emitting diode device.

24. A tiled display device, comprising:

a plurality of display devices; and

a connection member between the plurality of display devices,

wherein a first display device of the plurality of display devices comprises a plurality of sub-pixels emitting light,

wherein the sub-pixels of the plurality of sub-pixels include:

a light emitting device on the first and second pad electrodes;

a first inspection transistor overlapping the first pad electrode in a thickness direction of the substrate; and

a second inspection transistor overlapping with the second pad electrode in the thickness direction of the substrate,

wherein each of the first inspection transistor and the second inspection transistor overlaps the light emitting device in the thickness direction of the substrate.

25. A tiled display arrangement according to claim 24, wherein the light emitting devices are flip chip micro light emitting diode devices.

26. A tiled display device according to claim 24, wherein the first display device further comprises:

a pad on the first surface of the substrate; and

a side line on the first surface of the substrate, a second surface opposite to the first surface, and one side surface between the first surface and the second surface, and connected to the pad.

27. A tiled display device according to claim 26, wherein the substrate comprises glass.

28. A tiled display device according to claim 26, wherein the first display device further comprises:

a connection line on the second surface of the substrate; and

a circuit board connected to the connection line through a conductive adhesive member,

wherein the side wire is connected to the connection wire.

29. A tiled display device according to claim 26, wherein the plurality of display devices are arranged in a matrix of M rows and N columns, where M and N are positive integers.