KR20230103898A - Light Emitting Display Device - Google Patents

Abstract

This specification relates to a light emitting display device in which external light reflection is prevented and display quality is improved. A light emitting display device according to this specification includes a substrate, a driving layer, a planarization film, anode electrodes, a bank, a light emitting layer, and a cathode electrode. The driving layer is disposed on the substrate. A planarization film is disposed over the drive layer. Anode electrodes are arranged at regular intervals on the planarization film. The bank is disposed between the anode electrodes, defining a light emitting region. The light emitting layer is disposed over the bank and anode electrodes. A cathode electrode is disposed on the light emitting layer. A reflectivity control layer is interposed in one of the upper region of the bank and the upper region of the planarization film.

Description

Light emitting display device {Light Emitting Display Device}

This specification relates to a light emitting display device having improved display quality by preventing reflection of external light.

A light emitting display device has a structure in which a polarizing element is disposed to suppress external light (or external light) reflection. A polarizing element for suppressing external light reflection has a problem of reducing the amount of light provided by a display device, and also has a problem of being an expensive component. Therefore, there is a need to develop a structure of a light emitting display capable of suppressing reflection of external light without adding a polarizing element.

Some embodiments of this specification are to overcome the problems of the prior art, and to provide a light emitting display device capable of improving display quality by suppressing reflection of external light.

Some embodiments of this specification are directed to providing a light emitting display capable of suppressing reflection of external light without adding a polarizing element.

Some embodiments of this specification are directed to providing a light emitting display device capable of minimizing or preventing deterioration in display quality due to reflection of external light by a cathode electrode.

Some embodiments of the present specification are directed to providing a light emitting display device capable of minimizing or preventing deterioration in display quality due to reflection of external light due to uneven thickness of a cathode electrode having a low reflection structure.

To achieve the above object, a light emitting display device according to this specification includes a substrate, a driving layer, a planarization film, anode electrodes, a bank, a light emitting layer, and a cathode electrode. The driving layer is disposed on the substrate. A planarization film is disposed over the drive layer. Anode electrodes are arranged at regular intervals on the planarization film. The bank is disposed between the anode electrodes, defining a light emitting region. The light emitting layer is disposed over the bank and anode electrodes. A cathode electrode is disposed on the light emitting layer. A reflectivity control layer is interposed in one of the upper region of the bank and the upper region of the planarization film.

In one example, the cathode electrode may include a first cathode electrode layer disposed on the light emitting layer; a second cathode electrode layer disposed on the first cathode electrode layer; and a third cathode electrode layer disposed on the second cathode electrode layer.

For example, the first cathode electrode layer is a metal material having a thickness of 100 Å to 200 Å. The second cathode electrode layer is a conductive organic layer containing a domain material and a dopant. The third cathode electrode layer is a metal material having a thickness of 2,000 Å to 4,000 Å.

In one example, the first cathode electrode layer has a first thickness in a first region of the substrate. In the second region of the substrate, it has a second thickness greater than the first thickness.

For example, the reflectance control layer has a third thickness in the first region of the substrate. The second region of the substrate has a fourth thickness greater than the third thickness.

For example, in the first region, with respect to the incident light incident through the substrate, the ratio of the sum of the first reflected light reflected from the reflectivity control layer and the third reflected light reflected from the third cathode electrode layer is the light reflected from the first cathode electrode layer. A difference from the light quantity ratio of the second reflected light is within 2%. The first reflected light and the third reflected light have the same phase. Phases of the second reflected light and the third reflected light are opposite to each other.

For example, in the second region, with respect to incident light incident through the substrate, the total light amount ratio of the first reflected light reflected from the reflectivity control layer and the third reflected light reflected from the third cathode electrode layer is the light reflected from the first cathode electrode layer. A difference from the light quantity ratio of the second reflected light is within 2%. The first reflected light and the third reflected light have the same phase. Phases of the second reflected light and the third reflected light are opposite to each other.

For example, the reflectance control layer is disposed within the bank. The reflectance control layer has a refractive index different from that of the bank.

For example, the reflectance control layer is disposed within the planarization film. The reflectance control layer has a refractive index different from that of the planarization layer.

For example, the driving layer further includes wires including a first metal layer and a second metal layer stacked on the first metal layer.

For example, a difference between a light quantity ratio of the first reflected light reflected from the first metal layer and a light quantity ratio of the second reflected light reflected from the second metal layer with respect to incident light incident through the substrate is within 2%. Phases of the first reflected light and the second reflected light are opposite to each other.

For example, the first metal layer includes a metal oxide material having a thickness of 100 Å to 500 Å. The second metal layer includes a metal material having a thickness of 2,000 Å to 4,000 Å.

The light emitting display device according to this specification includes a cathode electrode having a low-reflection structure, so that image quality deterioration due to reflection of external light does not occur. In addition, since a low-reflection structure is applied to the wires, image quality degradation due to reflection of external light does not occur. In addition, in manufacturing a cathode electrode having a low reflection structure, a light emitting display device having a compensating low reflection structure capable of removing residual reflection of external light caused by failure to secure uniformity in thickness is provided. The light emitting display device according to this specification has a structure capable of suppressing reflection by external light without having a polarizer, and provides excellent image quality.

1 is a plan view showing a schematic structure of a light emitting display device according to this specification.
2 is a diagram showing a circuit configuration of one pixel constituting a light emitting display device according to this specification.
3 is a plan view showing the structure of pixels arranged in a light emitting display device according to this specification.
FIG. 4 is a cross-sectional view showing the structure of a light emitting display device having a low reflection structure according to the first embodiment of this specification, taken along line II′ of FIG. 3 .
5 is an enlarged cross-sectional view illustrating a cathode electrode having a low reflection structure in a light emitting display device according to a first embodiment of this specification.
6 is an enlarged cross-sectional view illustrating a light blocking layer and wiring having a low reflection structure in a light emitting display device according to a first embodiment of the present specification.
7 is an enlarged cross-sectional view illustrating a structure of a light emitting display device having a low reflection structure according to a second embodiment of this specification.
8 is an enlarged cross-sectional view illustrating a structure of a light emitting display device having a low reflection structure according to a third embodiment of the present specification.
FIG. 9 is a view showing a change in thickness of a metal thin film deposited for each region when a thin metal thin film is increased in a horizontally long rectangular display panel.
10 is a cross-sectional view illustrating an external light reflection mechanism when a first cathode electrode layer having a non-uniform thickness is stacked on a substrate on which a light emitting layer is stacked.
11A is an enlarged cross-sectional view illustrating a structure and a light path of a thin region of a first cathode electrode layer according to a fourth embodiment of the present specification.
11B is an enlarged cross-sectional view illustrating a structure and a light path of a thick region of a first cathode electrode layer according to a fourth embodiment of this specification.
12A is an enlarged cross-sectional view illustrating a structure and a light path of a thin region of a first cathode electrode layer according to a fifth embodiment of the present specification.
12B is an enlarged cross-sectional view illustrating a structure and a light path of a thick region of a first cathode electrode layer according to a fifth embodiment of the present specification.

Advantages and features of this specification, and methods of achieving them, will become clear with reference to examples described later in detail in conjunction with the accompanying drawings. However, this specification is not limited to the examples disclosed below, but will be implemented in a variety of different forms, and only one example in this specification makes the disclosure of this specification complete, and is common in the art to which the invention in this specification belongs. It is provided to completely inform those who have knowledge of the scope of the invention, and the invention in this specification is only defined by the scope of the claims.

The shape, size, ratio, angle, number, etc. disclosed in the drawings for explaining an example of this specification are illustrative, and are not limited to those shown here. Like reference numbers designate like elements throughout the specification. In addition, in describing examples of this specification, if it is determined that a detailed description of a related known technology may unnecessarily obscure the gist of the specification, the detailed description will be omitted.

When 'includes', 'has', 'consists of', etc. mentioned in this specification specification are used, other parts may be added unless 'only' is used. In the case where a component is expressed in the singular, the case including the plural is included unless otherwise explicitly stated.

In interpreting the components, even if there is no separate explicit description, it is interpreted as including the error range.

In the case of a description of a positional relationship, for example, 'on top of', 'on top of', 'at the bottom of', 'next to', etc. Or, unless 'directly' is used, one or more other parts may be located between the two parts.

In the case of a description of a temporal relationship, for example, 'immediately' or 'directly' when a temporal precedence relationship is described in terms of 'after', 'following', 'next to', 'before', etc. It can also include non-continuous cases unless is used.

Although first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of this specification.

The term "at least one" should be understood to include all possible combinations from one or more related items. For example, "at least one of the first item, the second item, and the third item" means two of the first item, the second item, and the third item as well as each of the first item, the second item, and the third item. It may mean a combination of all items that can be combined from one or more.

Each feature of the various examples in this specification can be partially or entirely combined or combined with each other, technically various interlocking and driving are possible, and each embodiment can be implemented independently of each other or can be implemented together in an association relationship. there is.

Hereinafter, an example of a light emitting display device according to this specification will be described in detail with reference to the accompanying drawings. In adding reference numerals to components of each drawing, the same components may have the same numerals as much as possible even if they are displayed on different drawings.

Hereinafter, a light emitting display device according to this specification will be described in detail with reference to the accompanying drawings. Since the scales of the components shown in the drawings have different scales from actual ones for convenience of explanation, they are not limited to the scales shown in the drawings.

1 is a diagram showing a schematic structure of a light emitting display device according to this specification. In FIG. 1 , the X-axis represents a direction parallel to the scan line, the Y-axis represents a direction parallel to the data wire, and the Z-axis represents the height direction of the display device.

Referring to FIG. 1 , a light emitting display device according to this specification includes a substrate 110, a gate (or scan) driver 200, a pad unit 300, a source driving integrated circuit 410, a flexible circuit film 430, A circuit board 450 and a timing controller 500 are included.

The substrate 110 may include an insulating material or a material having flexibility. The substrate 110 may be made of glass, metal, or plastic, but is not limited thereto. When the light emitting display device is a flexible display device, the substrate 110 may be made of a flexible material such as plastic. For example, a transparent polyimide material may be included.

The substrate 110 may be divided into a display area AA and a non-display area NDA. The display area AA is an area where an image is displayed, and may be defined in most areas including the central portion of the substrate 110, but is not limited thereto. Scan lines (or gate lines), data lines, and pixels are formed in the display area AA. The pixels include a plurality of sub-pixels, and each of the plurality of sub-pixels includes scan lines and data lines.

The non-display area NDA is an area on which an image is not displayed, and may be defined at an edge of the substrate 110 to surround all or part of the display area AA. A gate driving unit 200 and a pad unit 300 may be formed in the non-display area NDA.

The gate driver 200 supplies scan (or gate) signals to scan lines according to a gate control signal input from the timing controller 500 through the pad unit 300 . The gate driver 200 may be formed in the non-display area NDA of one edge of the display area AA of the base substrate 110 in a gate driver in panel (GIP) method. The GIP method refers to a structure in which the gate driver 200 is directly formed on the substrate 110 . For example, the gate driver 200 may be configured with a shift register, and the GIP method refers to a structure in which transistors constituting the shift register of the gate driver 200 are directly formed on the substrate 110 .

The pad part 300 may be disposed in the non-display area NDA of one edge of the display area AA of the substrate 110 . The pad unit 300 may include data pads connected to each of the data lines and gate pads connected to the gate driver 200 .

The source driving integrated circuit 410 receives digital video data and a source control signal from the timing controller 500 . The source driving integrated circuit 410 converts digital video data into analog data voltages according to a source control signal and supplies them to data lines. When the source driving integrated circuit 410 is manufactured as a chip, it may be mounted on the flexible circuit film 430 in a chip on film (COF) or chip on plastic (COP) method.

Wires connecting the pad unit 300 and the source driving integrated circuit 410 and wires connecting the pad unit 300 and the circuit board 450 may be formed on the flexible circuit film 430 . The flexible circuit film 430 is attached on the pad part 300 by using an anisotropic conducting film, so that the pad part 300 and wires of the flexible circuit film 430 can be connected.

Circuit board 450 may be attached to flexible circuit films 430 . A plurality of circuits implemented as driving chips may be mounted on the circuit board 450 . For example, the timing controller 500 may be mounted on the circuit board 450 . The circuit board 450 may be a printed circuit board or a flexible printed circuit board.

The timing controller 500 receives digital video data and timing signals from an external system board through a cable of the circuit board 450 . The timing controller 500 generates a gate control signal for controlling the operation timing of the gate driver 200 and a source control signal for controlling the source driving integrated circuits 410 based on the timing signal. The timing controller 500 supplies a gate control signal to the gate driver 200 and a source control signal to the source driving integrated circuits 410 . Depending on the product, the timing control unit 500 may be integrated with the source driving integrated circuit 410 into one driving chip and may be mounted on the board 110 to be connected to the pad unit 300 .

<First Embodiment>

Hereinafter, the first embodiment will be described with reference to FIGS. 2 to 4 . 2 is a diagram showing a circuit configuration of one pixel constituting a light emitting display device according to this specification. 3 is a plan view showing the structure of pixels according to this specification. FIG. 4 is a cross-sectional view showing the structure of a light emitting display device having a low reflection structure according to the first embodiment of this specification, taken along line II′ of FIG. 3 .

Referring to FIGS. 2 to 4 , one pixel of the light emitting display device may be defined by a scan line SL, a data line DL, and a driving current line VDD. A switching thin film transistor (ST), a driving thin film transistor (DT), a light emitting diode (OLE), and a storage capacitance (Cst) are included in one pixel of the light emitting display device. A high potential voltage for driving the light emitting diode OLE is applied to the driving current line VDD.

For example, the switching thin film transistor ST may be configured to be connected to the scan line SL and the data line DL. The switching thin film transistor ST includes a gate electrode SG, a source electrode SS, and a drain electrode SD. The gate electrode SG is connected to the scan line SL. The source electrode SS is connected to the data line DL, and the drain electrode SD is connected to the driving thin film transistor DT. The switching thin film transistor ST serves to select a pixel to be driven by applying a data signal to the driving thin film transistor DT.

The driving thin film transistor DT serves to drive the light emitting diode OLE of the pixel selected by the switching thin film transistor ST. The driving thin film transistor DT includes a gate electrode DG, a source electrode DS and a drain electrode DD. The gate electrode DG is connected to the drain electrode SD of the switching thin film transistor ST. For example, the gate electrode DG of the driving thin film transistor DT may be connected to the drain electrode SD of the switching thin film transistor ST through a drain contact hole DH passing through the gate insulating layer GI. In the driving thin film transistor DT, the source electrode DS is connected to the driving current line VDD, and the drain electrode DD is connected to the anode electrode ANO of the light emitting diode (or light emitting element) OLE. An auxiliary capacitance Cst may be formed between the gate electrode DG of the driving thin film transistor DT and the anode electrode ANO of the light emitting diode OLE.

The driving thin film transistor DT is disposed between the driving current line VDD and the light emitting diode OLE. The driving thin film transistor DT adjusts the amount of current flowing from the driving current line VDD to the light emitting diode OLE according to the voltage difference between the gate electrode DG and the source electrode DS.

The light emitting diode OLE includes an anode electrode ANO, an emission layer EL, and a cathode electrode CAT. The light emitting diode OLE emits light according to the current controlled by the driving thin film transistor DT. In other words, the light emitting diode OLE may display an image by emitting light according to the current controlled by the driving thin film transistor DT. The anode electrode ANO of the light emitting diode OLE is connected to the drain electrode DD of the driving thin film transistor DT, and the cathode electrode CAT is connected to the low-voltage line VSS to which a low potential voltage is supplied. . That is, the light emitting diode OLE is driven by the current flowing from the driving current line VDD to the low power line through the driving thin film transistor DT.

A cross-sectional structure of the light emitting display device according to the first embodiment of this specification will be described with reference to FIG. 4 . A light blocking layer LS is stacked on the substrate 110 . The light blocking layer LS may be used as a data line DL and a driving current line VDD. In addition, the light blocking layer LS may be further disposed in an island shape spaced apart from the data line DL and the driving current line VDD by a predetermined distance and overlapping the semiconductor layers SA and DA. The light blocking layer LS, which is not used as a wiring, blocks external light incident on the semiconductor layers SA and DA to prevent the characteristics of the semiconductor layers SA and DA from being deteriorated. In particular, the light blocking layer LS is preferably disposed to overlap the channel region overlapping the gate electrodes SG and DG in the semiconductor layers SA and DA. In addition, it is preferable that the light blocking layer LS overlaps portions of the source-drain electrodes SS, SD, DS, and DD that contact the semiconductor layers SA and DA.

A buffer layer BUF is stacked on the light blocking layer LS to cover the entire surface of the substrate 110 . A semiconductor layer SA of the switching thin film transistor ST and a semiconductor layer DA of the driving thin film transistor DT are formed on the buffer layer BUF. In particular, it is preferable that the channel regions of the semiconductor layers SA and DA overlap with the light blocking layer LS.

A gate insulating layer GI is stacked on the surface of the substrate 110 on which the semiconductor layers SA and DA are formed. A gate electrode SG overlapping the semiconductor layer SA of the switching thin film transistor ST and a gate electrode DG overlapping the semiconductor layer DA of the driving thin film transistor DT are formed on the gate insulating film GI. has been In addition, both sides of the gate electrode SG of the switching thin film transistor ST have a source electrode SS that is spaced apart from the gate electrode SG and contacts one side of the semiconductor layer SA, and A drain electrode SD contacting the other side is formed. Similarly, on both sides of the gate electrode DG of the driving thin film transistor DT, the source electrode DS, which is spaced apart from the gate electrode DG and contacts one side of the semiconductor layer DA, and the semiconductor layer DA A drain electrode DD contacting the other side is formed.

The gate electrodes SG and DG and the source-drain electrodes SS, SD, DS and DD are formed on the same layer, but are spatially or electrically separated from each other. In addition, the source electrode SS of the switching thin film transistor ST is connected to the data line DL formed as a part of the light blocking layer LS through a contact hole passing through the gate insulating film GI and the buffer layer BUF. there is. Similarly, the source electrode DS of the driving thin film transistor DT is connected to the driving current line VDD formed as a part of the light blocking layer LS through a contact hole penetrating the gate insulating film GI and the buffer layer BUF. has been As such, the switching thin film transistor ST and the driving thin film transistor DT are formed on the substrate 110 .

A passivation layer PAS is stacked on the substrate 110 on which the thin film transistors ST and DT are formed. The protective film PAS is preferably formed of an inorganic film such as silicon oxide or silicon nitride. A color filter CF is formed on the passivation layer PAS. The color filter CF is a component representing a color assigned to each pixel. For example, the color filter CF may have a size and shape corresponding to the size of an entire pixel area. As another example, the color filter CF may be disposed to overlap the light emitting diode OLE with a slightly larger size than the size of the light emitting diode OLE to be formed later.

A planarization layer PL is stacked on the color filter CF. The planarization layer PL is a thin film for flattening the surface of the substrate 110 on which the thin film transistors ST and DT are formed when it is not uniform. To make the height difference uniform, the planarization layer PL may be formed of an organic material. A pixel contact hole PH exposing a part of the drain electrode DD of the driving thin film transistor DT is formed in the passivation layer PAS and the planarization layer PL.

An anode electrode ANO is formed on the upper surface of the planarization layer PL. The anode electrode ANO is connected to the drain electrode DD of the driving thin film transistor DT through the pixel contact hole PH. Components of the anode electrode ANO may vary according to the light emitting structure of the light emitting diode OLE. For example, in the case of a bottom emission type that provides light in the direction of the substrate 110, it may be formed of a transparent conductive material. As another example, when light is emitted in an upward direction facing the substrate 110, it may be formed of a metal material having excellent light reflectivity.

A bank BA is formed to cover the edge of the anode electrode ANO. A central region of the anode electrode ANO in which the bank BA is not stacked may be defined as the light emitting region.

A light emitting layer EL is laminated on the anode electrode AN0. The light emitting layer EL may be formed over the entire display area AA of the substrate 110 to cover the anode electrode ANO and the bank BA. The light emitting layer EL according to an example may include two or more vertically stacked light emitting units to emit white light. For example, the light emitting layer EL may include a first light emitting part and a second light emitting part for emitting white light by mixing the first light and the second light.

As another example, the light emitting layer EL may include any one of a blue light emitting part, a green light emitting part, and a red light emitting part for emitting light corresponding to a color set in a pixel. In addition, the light emitting diode OLE may further include a functional layer for improving light emitting efficiency and/or lifetime of the light emitting layer EL.

The cathode electrode CAT is stacked to make surface contact with the light emitting layer EL. The cathode electrode CAT is formed over the entire substrate 110 to be commonly connected to the light emitting layer EL formed in all pixels. In the case of a large-area display device such as a TV set, the cathode electrode CAT is formed as a single layer over a large area, and it is desirable to maintain a uniform low voltage over a wide width of the cathode electrode CAT. Therefore, in the case of a large area display device, it is preferable to form the cathode electrode CAT with an opaque metal material. That is, in the case of a large area display device, it is preferable to form a bottom emission type structure.

In the case of the bottom emission type, the anode electrode ANO is formed of a transparent conductive material. For example, an oxide conductive material such as indium zinc oxide or indium tin oxide may be included. In addition, in the case of the bottom emission type, the cathode electrode CAT includes a metal material having excellent light reflection efficiency. For example, the cathode electrode (CAT) is made of silver (Ag), aluminum (Al), molybdenum (Mo), gold (Au), magnesium (Mg), calcium (Ca), titanium (Ti), copper (Cu) Alternatively, it may be made of any one material selected from barium (Ba) or two or more alloy materials.

In particular, in this specification, a low-reflection structure is provided to prevent external light from being reflected by metal components of the display device. For example, it has a structure for preventing external light from being reflected by the cathode electrode CAT formed over almost the entire area of the substrate 110 . In addition, it has a structure for preventing external light from being reflected by the light blocking layer LS formed on the layer closest to the substrate 110 . Furthermore, it has a structure for preventing external light from being reflected by the gate line SL exposed on the lower surface of the substrate 110 without overlapping with the light blocking layer LS.

Further referring to FIG. 5 , the structure of the cathode electrode CAT capable of suppressing external light reflection in the light emitting display device according to the first embodiment of this specification will be described. 5 is an enlarged cross-sectional view illustrating a cathode electrode having a low reflection structure in a light emitting display device according to a first embodiment of this specification.

In the bottom emission type light emitting display according to this specification, the cathode electrode CAT includes three cathode electrode layers. For example, the cathode electrode CAT includes a first cathode electrode layer CAT1, a second cathode electrode layer CAT2, and a third cathode electrode layer CAT3 sequentially stacked on the light emitting layer EL. The first cathode electrode layer CAT1 is first stacked so as to directly contact the light emitting layer EL. The first cathode electrode layer CAT1 may include a metal material having low sheet resistance. For example, it may be formed of a metal material selected from aluminum (Al), silver (Ag), molybdenum (Mo), gold (Au), magnesium (Mg), calcium (Ca), or barium (Ba). Considering the manufacturing process and manufacturing cost, a case in which the first cathode electrode layer CAT1 is formed of aluminum will be described as the most preferred example.

When the first cathode electrode layer CAT1 is made of aluminum, it is preferably formed to a thickness of 100 Å to 200 Å. Metallic materials such as aluminum are opaque and have very high reflectivity. However, if aluminum is formed very thin, it can transmit light. For example, in a thin thickness of 200 Å or less, a portion (40% to 50%) of incident light may be reflected and the rest (50% to 60%) may be transmitted.

The second cathode electrode layer CAT2 may include a conductive resin material. The conductive resin material may include a domain material made of a resin material having high electron mobility and a dopant that lowers barrier energy of the domain material. The resin material having high electron mobility may include any one selected from among Alq3, TmPyPB, Bphen, TAZ, and TPB. Alq3 is an abbreviation for Tris(8-hydroxyquinoline) Aluminum, and is a complex with a chemical formula of Al(C ₉ H ₆ NO) ₃ . TmPyPB is an organic substance that is an abbreviation for 1,3,5-tri(m-pyrid-3-yl-phenyl)benzene. Bphen is an organic substance that is the abbreviation for Bathophenanthroline. TAZ is an organic substance that is an abbreviation for 1,2,3-triazole. TPB is an organic substance that stands for triphenyl bismuth. Since these organic materials have high electron mobility, they can be used in light emitting devices.

The dopant material may include an alkali-based doping material. For example, it may include lithium (Li), cesium (Cs), cesium oxide (Cs ₂ O ₃ ), cesium nitride (CsN ₃ ), rubidium (Rb), and rubidium oxide (Rb ₂ O). Other dopant materials may include fullerenes having high electron mobility properties. Fullerene is a general term for molecules in which carbon atoms are arranged in a spherical, ellipsoidal or cylindrical shape. As an example, it may include Buckminster-fullerene (C ₆₀ ; Buckminster-fullerene) in which 60 carbon atoms are mainly bonded in a soccer ball shape. In addition, higher order fullerenes such as C ₇₀ , C ₇₆ , C ₇₈ , C ₈₂ , C ₉₀ , C ₉₄ and C ₉₆ may be included.

The second cathode electrode layer CAT2 may be made of the same material as the electron transport layer or electron injection layer included in the light emitting layer EL. However, unlike the electron transport layer or the electron injection layer, a higher electron mobility is preferred. For example, in the case of the electron transport layer or the electron transport layer, the electron mobility is 5.0×10 ^-4 (S/m) to 9.0×10 ^-1 (S/m), while the second cathode electrode layer (CAT2) has an electron mobility It is preferable that is 1.0×10 ^-3 (S/m) to 9.0×10 ⁺¹ (S/m). To this end, it is preferable that the dopant content of the conductive resin material constituting the second cathode electrode layer CAT2 is higher than that of the electron transport layer or the electron injection layer.

For example, the electron transport layer or the electron injection layer preferably has a dopant doping concentration of 2% to 10%, while the second cathode electrode layer CAT2 is a conductive resin material having a dopant doping concentration of 10% to 30%. The domain material itself, in which the doping concentration of the dopant is 0%, may have an electrical conductivity of 1.0×10 ⁻⁴ (S/m) to 5.0×10 ⁻³ (S/m). By injecting 10% to 30% of the dopant into the domain material, the electrical conductivity of the second cathode electrode layer (CAT2) is improved from 1.0×10 ^-3 (S/m) to 9.0×10 ⁺¹ (S/m), thereby forming a cathode electrode layer. can be used as

In some cases, the second cathode electrode layer CAT2 may have the same conductivity as that of the electron functional layer (electron transport layer and/or electron injection layer) of the light emitting layer EL. In this case, the sheet resistance can be maintained at a sufficiently low value by the first cathode electrode layer CAT1 made of aluminum.

The third cathode electrode layer CAT3 may be formed of the same metal material as the first cathode electrode layer CAT1. The third cathode electrode layer CAT3 preferably has a sufficient thickness so that the sheet resistance of the cathode electrode CAT can maintain a constant value regardless of the position of the substrate SUB while being able to reflect all without transmitting light. . For example, the third cathode electrode layer CAT3 is formed of a metal material having a low sheet resistance to a relatively thicker thickness than the first and second cathode electrode layers CAT1 and CAT2 in order to lower the sheet resistance of the entire cathode electrode CAT. It is desirable to do For example, the third cathode electrode layer CAT3 may be formed of aluminum having a thickness of 2,000 Å to 4,000 Å.

The cathode electrode layer CAT having such a thickness and a stacked structure may minimize reflectance of light incident from a lower direction (first cathode electrode layer CAT1). The portion suppressing external light reflection may be a display area that can mainly affect image information. Therefore, it is desirable to implement a low reflection structure in the cathode electrode CAT that is commonly applied throughout the display area AA. Hereinafter, description will be made with reference to arrows indicating light paths shown in FIG. 5 .

Looking at the structure of the cathode electrode (CAT) constituting the light emitting diode (OLE), the incident light (①) entering from the bottom of the cathode electrode (CAT) passes through the transparent anode electrode (ANO) and the light emitting layer (EL), thereby forming the first cathode electrode layer. It is partially reflected from the lower surface of (CAT1) and proceeds toward the substrate 110 as primary reflected light (②). Since the first cathode electrode layer CAT1 has a thickness of less than 200 Å, it does not reflect all of the incident light ①. For example, only about 40% of incident light ① is reflected as primary reflected light ②, and the remaining 60% passes through the first cathode electrode layer CAT1. The transmitted light ③ passing through the first cathode electrode layer CAT1 passes through the transparent second cathode electrode layer CAT2 as it is. Then, the transmitted light ③ is reflected by the third cathode electrode layer CAT3. Since the third cathode electrode layer CAT3 has a thickness of 2,000 Å to 4,000 Å, all of the transmitted light ③ is reflected and proceeds toward the substrate 110 as secondary reflected light ④.

At this time, by adjusting the thickness of the second cathode electrode layer CAT2, the phases of the first reflected light ② and the second reflected light ④ may be set to offset each other. As a result, the reflected light luminance, which is the intensity of the reflected light incident from the lower portion of the cathode electrode CAT and reflected, can be reduced to a level of 2%.

Meanwhile, among the lights emitted from the light emitting layer EL, the amount of light emitted toward the cathode electrode CAT may be reduced by about 2% through the same light path toward the substrate 110 . However, since light emitted from the light emitting layer EL is emitted in all directions, the amount of light reduced by the cathode electrode CAT is only about 50% of the total amount of light, and the remaining 50% is emitted toward the substrate 110. do.

The light emitting display device according to the first embodiment may be a bottom emission type having a triple-layered cathode electrode (CAT). In addition, the reflectance of external light can be suppressed as much as possible by the structure of the cathode electrode CAT of the triple layer stack structure. Therefore, there is no need to dispose a polarizer for reducing external light reflection outside the substrate 110 . The polarizer has a positive effect of suppressing reflection of external light, but has a negative effect of reducing the amount of light emitted from the light emitting layer EL by at least 50%.

In the light emitting display device according to the first embodiment, the amount of light emitted from the light emitting layer EL is reduced by about 50% by the cathode electrode CAT having a triple layered structure, but this is almost the same as the amount of light emitted by the polarizer. Accordingly, the light emitting display device according to this specification can minimize reflection of external light while providing the same level of light emitting efficiency of the light emitting layer (EL) without using a very expensive polarizing element.

Hereinafter, a structure for suppressing external light reflection in the light blocking layer LS and the gate line SL will be described with reference to FIG. 6 . 6 is an enlarged cross-sectional view illustrating a light blocking layer having a low reflection structure and a gate wire in a light emitting display device according to a first embodiment of the present specification.

In the first embodiment, the light blocking layer LS, the gate electrodes SG and DG formed on the same layer as the gate line SL, the source-drain electrodes SS, SD, DS, and DD, and the driving drain electrode DD A structure for suppressing reflection of external light may be further applied to the connection line VDL extending from ) and connecting the driving current line VDD (hereinafter, collectively referred to as the gate line SL). For example, the gate wiring unit may have a structure in which the first metal layer 101 and the second metal layer 200 are stacked.

The first metal layer 101 includes a low-reflective metal oxide material. The low reflection metal oxide material is preferably formed of at least one of Molybdenum-Titanium-Oxide (MTO), Molybdenum-Copper-Oxide (MoCuOx), and Tungsten Oxide (WOx). . The second metal layer 200 includes a low resistance metal material. For example, the low-resistance metal material is preferably formed of a metal material such as copper (Cu), aluminum (Au), silver (Ag), or gold (Au).

Here, the first metal layer 101 is an oxide and is a layer for refractive index matching. For example, since the refractive index of the first metal layer 101, which is an oxide, is significantly different from the refractive index of the second metal layer 200, which is a metal material, light reflected from the first metal layer 101 and the second metal layer 200 It is possible to suppress the reflection of external light by canceling the phase of the light reflected from the .

For example, as shown in FIG. 6 , incident light ① penetrating the substrate 110 under the light blocking layer LS and the gate line SL is partially reflected from the lower surface of the first metal layer 101 The primary reflected light (②) travels toward the substrate 110. The first metal layer 101 is an oxide and has high transparency, and due to a difference in refractive index at the interface with the substrate 110, it cannot reflect all of the incident light ①. For example, only about 40% of incident light ① is reflected as primary reflected light ②, and the remaining 60% passes through the first metal layer 101 . The transmitted light ③ passing through the first metal layer 101 is reflected by the opaque second metal layer 200 . Since the second metal layer 200 is formed of an opaque metal material, all of the transmitted light ③ is reflected and proceeds toward the substrate 110 as secondary reflected light ④.

At this time, by adjusting the thickness of the first metal layer 101, the phases of the primary reflected light (②) and the secondary reflected light (④) may be set to offset each other. For example, when it is desired to selectively lower reflectance of green light, to which the human eye reacts most sensitively, the thickness of the first metal layer 101 may be set to correspond to a multiple of a half-wavelength of green light. For example, when a typical wavelength of green light is 550 nm, the first metal layer 101 may be formed to have a thickness of any one of 275 Å, 550 Å, 825 Å, and 1,100 Å, which is a multiple of 275 nm, which is a half-wavelength of green light. As a result, the reflected light luminance, which is the intensity of the reflected light incident and reflected from the lower portions of the light blocking layer LS and the gate line SL, may be reduced to a level of 2%.

As described above, the light emitting display device according to the first embodiment of this specification applies a low reflection structure to the cathode electrode CAT made of the widest metal material, so that reflection of external light in the cathode electrode CAT can be suppressed. In addition, reflection of external light may be suppressed by applying a low reflection structure using an oxide metal layer to the light blocking layer LS and the gate line SL not covered by the light blocking layer LS.

A bottom emission type light emitting display having such a structure sees an image in the direction of the substrate. When external light is incident from the direction of the substrate and is reflected by the wires and the cathode electrode, image information is disturbed by the reflected light, and a user may not properly perceive the image information. However, since the light emitting display according to this specification has a low-reflection structure in the wiring and the cathode electrode, the reflectance of external light can be reduced to about 2% or less compared to the incident amount of external light, so that a problem in image quality due to external light does not occur.

In particular, in the case of a large-area TV, several people view an image through a display device in a relatively wide viewing angle range. Therefore, since the range in which external light is reflected is wide, image information distortion due to external light reflection may occur severely. Accordingly, the light emitting display device according to this specification has a structure capable of suppressing reflection of external light, so that normal image information can be provided to many people viewing the display device from various angles without distortion of image quality due to external light.

In the case of manufacturing such a large area display device, it is very difficult to form a thin film layer having the same thickness when forming a thin film layer over a large area. For example, in the case of a low-reflection wire having an external light reflection preventing function, the second metal layer 200 is stacked on the first metal layer 101 as shown in FIG. 6 . The first metal layer 101 has a refractive index matching function and may have a sufficient thickness to be stacked with a constant thickness over a large area.

<Second Embodiment>

Hereinafter, a second embodiment of this specification will be described with reference to FIG. 7 . 7 is an enlarged cross-sectional view illustrating a structure of a light emitting display device having a low reflection structure according to a second embodiment of this specification.

Referring to FIG. 7 , in the light emitting display device according to the second embodiment, a driving layer TL is formed on a substrate 110 . The driving layer TL refers to a layer in which the gate line SL, data line DL, driving current line VDD, switching thin film transistor ST and driving thin film transistor DT are formed as described in FIG. 4 . A detailed description of the driving layer TL is omitted since it is the same as that described in FIG. 4 . A planarization layer PL is stacked on the driving layer TL.

An anode electrode ANO is formed on the planarization layer PL. A bank BA is formed between the anode electrodes ANO to define a light emitting area. An emission layer EL is stacked on the anode ANO and the bank BA to cover the entire substrate 110 . A cathode electrode CAT is stacked on the light emitting layer EL to cover the entire substrate 110 .

In the second embodiment, the cathode electrode CAT may have a low reflection structure as described in the first embodiment. However, in the second embodiment, a low reflection structure is applied to the planarization layer PL. Accordingly, in the second embodiment, the cathode electrode CAT may have a single reflective electrode structure without a low reflective structure.

For example, in the process of coating the planarization layer PL on the entire substrate 110 after the driving layer TL is formed, the reflectance control layer IM is added in the middle of the planarization layer PL. Here, the reflectance control layer IM is a refractive index control layer, and preferably includes an organic material similar to that of the planarization layer PL, but is formed of a material having a refractive index different from that of the planarization layer PL. In addition, since external light reflection mainly occurs at the cathode electrode CAT, it is preferable to form it as close to the top of the planarization layer PL as possible.

The thickness of the reflectance control layer (IM) is preferably set to offset external light reflected by inverting the phase of reflected light through the optical path, in consideration of the wavelength of main light to be prevented from being reflected. As a result, reflected light can be suppressed in a manner similar to the light path in the wiring having the low reflection structure described in FIG. 6 .

For example, as shown in FIG. 7 , incident light ① penetrating the substrate 110 and entering from the bottom of the planarization film PL is partially reflected from the lower surface of the reflectance control layer IM, and the primary reflected light ( ②) proceeds toward the substrate 110 . The reflectance control layer IM does not reflect all of the incident light ① due to a difference in refractive index at the interface with the planarization film PL. For example, only about 40% of incident light ① is reflected as primary reflected light ②, and the remaining 60% passes through the reflectance control layer IM. The transmitted light (③) passing through the reflectance control layer (IM) is reflected again at the interface between the reflectance control layer (IM) and the planarization layer (PL). At least 80% of the transmitted light ③ is reflected and proceeds toward the substrate 110 as secondary reflected light ④. The remaining 20% may be absorbed by the reflectance control layer IM and/or the planarization layer PL. As a result, the first reflected light (②) and the second reflected light (④) may have a similar light quantity.

At this time, by adjusting the thickness of the reflectance control layer (IM), the phases of the primary reflected light (②) and the secondary reflected light (④) can be set to offset each other. For example, when it is desired to selectively lower the reflectance of green light, to which the human eye reacts most sensitively, the thickness of the reflectance control layer (IM) may be set in proportion to a multiple of a half-wavelength of green light. For example, when a representative wavelength of green light is 550 nm, the reflectance control layer IM may be formed to have a thickness of 275 Å, which is proportional to 275 nm, which is a half-wavelength of green light, or an integer multiple thereof.

In the second embodiment, reflection of external light by the reflective material stacked on the planarization layer PL may be suppressed. In addition, by applying the wiring having the low reflection structure described in FIG. 6 of the first embodiment, reflection of external light by a reflective material under the planarization layer PL can be suppressed. As a result, the light emitting display device according to the second embodiment can reduce the luminance of reflected light, which is the intensity of reflected light of external light, on the entire substrate 110 to a level of 2%.

<Third Embodiment>

Hereinafter, a second embodiment of this specification will be described with reference to FIG. 8 . 8 is an enlarged cross-sectional view illustrating a structure of a light emitting display device having a low reflection structure according to a third embodiment of the present specification.

Referring to FIG. 8 , in the light emitting display device according to the third embodiment, a driving layer TL is formed on a substrate 110 . The driving layer TL refers to a layer in which the gate line SL, the data line DL, the driving current line VDD, the switching thin film transistor ST, and the driving thin film transistor DT are formed. A planarization layer PL is stacked on the driving layer TL.

An anode electrode ANO is formed on the planarization layer PL. A bank BA is formed between the anode electrodes ANO to define a light emitting area. An emission layer EL is stacked on the anode ANO and the bank BA to cover the entire substrate 110 . A cathode electrode CAT is stacked on the light emitting layer EL to cover the entire substrate 110 .

In the third embodiment, the cathode electrode CAT may or may not have the low reflection structure described in the first embodiment. When the cathode electrode CAT has a low-reflection structure, reflection of external light can be more effectively prevented. However, in the case of the bottom emission type, the ratio occupied by the light emitting area is about 35% to 40%. That is, the ratio of the area occupied by the bank BA in the substrate 110 is 60% to 75%, which is a large percentage. In particular, the higher the resolution, the larger the ratio of the area occupied by the bank BA.

Therefore, even if only the external light reflectance by the cathode electrode CAT stacked on the bank BA is lowered, the external light reflectance can be sufficiently reduced by 60% or more. Thus, the third embodiment has a structure capable of suppressing external light reflection in the bank BA area.

For example, after forming the anode electrode (ANO), in the process of applying the bank (BA) material to the entire surface of the substrate 110, a reflectance control layer (IM) in the middle of the bank (BA) material or on top of the bank (BA) material ) is added. Subsequently, the bank BA is formed by patterning the bank BA material layer including the reflectance control layer IM. The bank BA covers an edge of the anode electrode ANO, exposes a central portion of the anode electrode ANO, and defines a light emitting area. Here, the reflectance control layer (IM) is a refractive index control layer, and preferably includes an organic material similar to the bank (BA) material, but is formed of a material having a refractive index different from that of the bank (BA) material.

In addition, since reflection of external light mainly occurs at the cathode electrode CAT, it is preferable to form it as close to the upper part of the bank BA as possible. The reflectance control layer IM may be formed to be included in the bank BA, or an upper layer of the bank BA may be formed as the reflectance control layer IM. In FIG. 8 , a case in which the upper layer of the bank BA is formed of the reflectivity control layer IM will be described.

The thickness of the reflectance control layer (IM) is preferably set to offset external light reflected by inverting the phase of reflected light through the optical path, in consideration of the wavelength of main light to be prevented from being reflected.

For example, as shown in FIG. 8 , incident light (①) penetrating the substrate 110 and entering from the bottom of the bank (BA) is partially reflected from the lower surface of the reflectance control layer (IM) to generate primary reflected light (②). ) and proceeds toward the substrate 110. The reflectance control layer IM does not reflect all of the incident light ① due to a difference in refractive index at the interface with the bank BA. For example, only about 40% of incident light ① is reflected as primary reflected light ②, and the remaining 60% passes through the reflectance control layer IM. The transmitted light ③ passing through the reflectance control layer IM passes through the light emitting layer EL and is reflected at the cathode electrode CAT. At least 80% of the transmitted light ③ is reflected and proceeds toward the substrate 110 as secondary reflected light ④. The remaining 20% may be absorbed in the reflectance control layer IM and/or the light emitting layer EL. As a result, the first reflected light (②) and the second reflected light (④) may have a similar light quantity.

At this time, by adjusting the thickness of the reflectance control layer (IM), the phases of the primary reflected light (②) and the secondary reflected light (④) can be set to offset each other. For example, when it is desired to selectively lower the reflectance of green light, to which the human eye reacts most sensitively, the thickness of the reflectance control layer (IM) may be set in proportion to a multiple of a half-wavelength of green light. For example, when a representative wavelength of green light is 550 nm, the reflectance control layer IM may be formed to have a thickness of 275 Å, which is proportional to 275 nm, which is a half-wavelength of green light, or an integer multiple thereof.

In the third embodiment, reflection of external light by the reflective material stacked on the bank BA may be suppressed. In addition, by applying the wiring having the low reflection structure described in FIG. 6 of the first embodiment, reflection of external light by a reflective material under the planarization layer PL can be suppressed. In the third embodiment, the case where external light reflection by the cathode electrode CAT exposed to the light emitting region in which the bank BA is not formed is not suppressed has been described. However, since the area ratio of the area where the bank BA is not formed is 40% or less compared to the substrate 110, in the case of a display device used in an environment where strong external light such as sunlight does not exist, reflection of external light can be significantly suppressed. can

<Fourth Embodiment>

In the case of a cathode having an external light reflection prevention function, as shown in FIG. 5 , it has a structure including a first cathode electrode layer CAT1, a second cathode electrode layer CAT2, and a third cathode electrode layer CAT3. In this structure, since the third cathode electrode layer CAT3 has a thickness sufficiently thick to reflect all incident light, it can be stacked with a relatively constant thickness over a large area. However, in the case of the first cathode electrode layer CAT1, since it must have semi-permeability, it must have a very thin thickness of 100 Å to 200 Å. As such, it may be very difficult to form the very thin first cathode electrode layer CAT1 with a uniform thickness over a very large area of 40 inches or more. As a result, a problem in that the external light reflectance is greater than a designed target value may occur because the phase-offset external light reflection amount is reduced.

Hereinafter, in the fourth embodiment, when the cathode electrode having the external light reflecting structure according to the first embodiment of this specification is applied to a large-area light emitting display device, the thickness of the first cathode electrode layer is not uniformly stacked, so that the external light reflectance is reduced. A structure capable of compensating for an image quality non-uniformity problem caused by non-uniformity will be described.

Looking at a process of forming a display panel of a large area light emitting display device applicable to a large TV, for example, a cathode electrode layer may be stacked while transferring a substrate in a predetermined direction. In this case, variations in thickness that occur when depositing a very thin film may have the same profile for each display panel due to process characteristics.

As shown in FIG. 9 , in the case of a rectangular display panel, a central portion may be formed thinner than both side edge portions. FIG. 9 is a view showing a change in thickness of a deposited metal thin film for each region when a thin metal thin film is deposited on a rectangular display panel long in a horizontal direction (X direction). For example, when an aluminum metal layer is to be deposited to a thickness of 200 Å, the central region (C) of the substrate 110 is deposited to a thickness of 180 Å, and both edge regions, that is, the right edge region (R) and the left edge region (L) ) can be deposited to a thickness of 200 Å. In addition, when the aluminum metal layer is to be deposited to a thickness of 170 Å, it can be deposited to a thickness of 140 Å in the central region C of the substrate 110 and to a thickness of 170 Å in both edge regions L and R. As another example, when the aluminum metal layer is to be deposited to a thickness of 140 Å, it can be deposited to a thickness of 110 Å in the central region C of the substrate 110 and to a thickness of 140 Å in both edge regions L and R of the substrate 110. .

Hereinafter, a situation that may occur when the thickness of the first cathode electrode layer CAT1 is not constant will be described with reference to FIG. 10 . 10 is a cross-sectional view illustrating an external light reflection mechanism when a first cathode electrode layer having a non-uniform thickness is stacked on a substrate on which a light emitting layer is stacked.

Referring to FIG. 10 , a driving layer TL is formed on a large-area substrate 110 having a diagonal length of 40 inches or more. A planarization layer PL covering the substrate 110 is stacked on the driving layer TL. A plurality of anode electrodes ANO are disposed at regular intervals on the planarization layer PL. Banks BA are disposed on the anode ANO to cover the edges and expose the central portion to define a light emitting area. An emission layer EL is stacked on the bank BA and the anode electrode ANO.

A first cathode electrode layer CAT1 is stacked on the light emitting layer EL. A second cathode electrode layer CAT2 is stacked on the first cathode electrode layer CAT1. A third cathode electrode layer CAT3 is stacked on the second cathode electrode layer CAT2. In this structure, the first thickness t1 of the first cathode electrode layer CAT1 stacked on the central region C of the substrate 110 is the first thickness t1 of the first cathode electrode layer CAT1 stacked on the right edge region R. 2 may be thinner than the thickness t2. For example, when the thickness of the first cathode electrode layer CAT1 for the low reflection structure is set to 150 Å, the first thickness t1 may be 120 Å and the second thickness t2 may be 150 Å. Here, the central region C may be referred to as a first region, and the right edge region R may be referred to as a second region. Alternatively, the central region C may be referred to as the second region, and the right edge region R may be referred to as the second region.

In this case, reflection of external light may be suppressed in the right edge region R by the reflected light mechanism as shown in FIG. 5 . That is, referring to the right edge region R of FIG. 10 , when the amount of incident light ① is 100%, the amount of primary reflected light ② is 50% and the amount of transmitted light ③ is 50%. can Here, light absorptivity is not considered. Then, the light amount of the secondary reflected light ④ may be 50%. At this time, the phases of the first reflected light ② and the second reflected light ④ can be adjusted to be opposite to each other according to the thicknesses of the first cathode electrode CAT1 and the second cathode electrode layer CAT2. As shown in the waveform shown in FIG. 10, the amplitudes (ⓐ, ⓒ) of the first reflected light (②) are the same as the amplitudes (ⓑ, ⓓ) of the second reflected light (④), and the phases are opposite. As a result, external light reflection can be suppressed.

However, referring to the central region (C), the phases of the primary reflected light (②) and the secondary reflected light (④) are adjusted to be opposite by the thickness of the first cathode electrode layer (CAT1) and the second cathode electrode layer (CAT2). there is. However, since the thickness of the first cathode electrode layer CAT1 is thinner than the right edge area R, the amount of light of the first reflected light ② is smaller than that of the right edge area R where the thickness of the first cathode electrode layer CAT1 is thick. can For example, only the amount of light corresponding to 40% of the incident light ① may be the first reflected light ②. In this case, 60% of the incident light (①) becomes transmitted light (③), and then becomes secondary reflected light (④). As shown in the waveform shown in the central region (C) of FIG. 10, the amplitude (ⓐ) of the first reflected light (②) is smaller than the amplitude (ⓑ) of the second reflected light (④), and the phases are opposite. As a result, in the central region C, about 10% of the incident light ①, which is the difference between the light amount of the first reflected light ② and the second reflected light ④, can be recognized as external light reflection.

As such, if the first cathode electrode layer CAT1 is applied non-uniformly, a difference in external light reflectance occurs, resulting in an external light non-uniformity phenomenon. This may be a factor in deteriorating display quality of the display device.

Hereinafter, with reference to FIGS. 11A and 11B, an external light reflection suppression structure capable of preventing non-uniform reflection of external light that occurs when the thickness of the first cathode electrode layer CAT1 is not constant in the fourth embodiment will be described. . 11A and 11B are cross-sectional enlarged views showing the structure of a light emitting display device according to a fourth embodiment of this specification. 11A is an enlarged cross-sectional view showing the structure and light path of the central region C where the first cathode electrode layer is thin. 11B is an enlarged cross-sectional view illustrating the structure and light path of the right edge region R of the first cathode electrode layer having a thick thickness.

In the fourth embodiment, the reflectance control layer (IM) described in the second and third embodiments is configured together with a cathode electrode having a low reflection structure to compensate for the change in thickness of the first cathode electrode layer (CAT1). We propose a reflection structure.

Referring to FIGS. 11A and 11B , looking at the structure of the central region C in which the first cathode electrode layer CAT1 is thinly formed, the anode electrodes ANO are disposed on the planarization layer PL at regular intervals. A bank BA is formed on the anode electrode ANO to cover the edge area and expose the central portion. A reflectivity control layer IM is interposed in the bank BA. Unlike the case of the third embodiment, the reflectivity control layer IM may be disposed inside the bank BA. For example, the reflectance control layer IM may have a structure disposed in an upper region of the bank BA. However, it is not limited thereto, and may be disposed in a lower area of the bank BA. Since the reflectance adjusting layer IM is for suppressing the amount of reflected light by using the phase difference, it can be set at an appropriate position where the phase difference can occur.

An emission layer EL is stacked on the bank BA and the anode electrode ANO. A first cathode electrode layer CAT1 is stacked on the light emitting layer. A second cathode electrode layer CAT2 is stacked on the first cathode electrode layer CAT1. A third cathode electrode layer CAT3 is stacked on the second cathode electrode layer CAT2.

In the fourth embodiment, a case in which the first cathode electrode layer CAT1 has a thickness smaller in the central region C than in the right edge region R will be described. For example, the first cathode electrode layer CAT1 applied to the central region C has a first thickness t1, and the second cathode electrode layer CAT1 applied to the right edge region R has a second thickness t2. ) has The first thickness t1 is smaller than the second thickness t2. For example, the first thickness t1 may be 120 Å, and the second thickness t2 may be 150 Å.

In this way, in order to compensate for the fact that the thickness of the first cathode electrode layer CAT1 is not constant over the entire substrate 110, the reflectance control layer IM is used. The reflectivity control layer IM has a third thickness t3 in the central region C and a fourth thickness t4 in the right edge region R. The third thickness t3 is thinner than the fourth thickness t4. For example, the third thickness t3 may be 700 Å, and the fourth thickness t4 may be 1,000 Å.

The amount of light reflected from the reflectance control layer (IM) having a small thickness is less than the amount of light reflected from the reflectance control layer (IM) having a thick thickness. For example, the reflectance adjusting layer IM having the third thickness t3 applied to the central region C may have a light reflectance of 20%. In addition, the reflectance control layer IM having the fourth thickness t4 applied to the right edge region R may be adjusted to have a light reflectance of 30%.

As described above, even if the first cathode electrode layer CAT1 is formed of a metal material, if it has a very thin thickness, some of the incident light may be reflected and the rest may be transmitted. Light transmittance and light reflectance of the first cathode electrode layer CAT1 may vary depending on its thickness.

The amount of light reflected from the thin first cathode electrode layer CAT1 is smaller than the amount of light reflected from the thick first cathode electrode layer CAT1. As an example, the first cathode electrode layer CAT1 having the first thickness t1 applied to the central region C may have a light reflectivity of 62.5%. In addition, the first cathode electrode layer CAT1 having the second thickness t2 applied to the right edge region R may have a light reflectance of 71.4%.

Referring to FIG. 11A illustrating the central region C of the substrate, the incident light ① passing through the substrate 110 and entering from the bottom of the bank BA is partially reflected from the lower surface of the reflectance control layer IM and The differential reflected light ② proceeds toward the substrate 110 . The reflectance control layer IM does not reflect all of the incident light ① due to a difference in refractive index at the interface with the bank BA. According to the conditions described above, only about 20% of the incident light ① is reflected as primary reflected light ②, and the remaining 80% passes through the reflectance control layer IM. The first transmitted light ③ passing through the reflectance control layer IM passes through the light emitting layer EL and is partially reflected by the first cathode electrode layer CAT1. According to the conditions described above, 62.5% of the first transmitted light ③ is reflected from the first cathode electrode layer CAT1 and proceeds toward the substrate 110 as secondary reflected light ④. Therefore, the light amount of the secondary reflected light ④ is 50% of the incident light ①. 37.5% of the first transmitted light ③ passes through the first cathode electrode layer CAT1 and the light emitting layer EL to become second transmitted light ⑤. The second transmitted light ⑤ is reflected as tertiary reflected light ⑥ by the third cathode electrode layer CAT3. Therefore, the tertiary reflected light (⑥) is 30% of the incident light (①). As a result, the sum of the first reflected light (②) and the third reflected light (⑥) is 50% of the incident light (①), and is equal to 50% of the second reflected light (④).

At this time, by adjusting the thickness of the reflectance adjusting layer (IM) and the upper layer of the bank (BA), the phases of the primary reflected light (②) and the secondary reflected light (④) are reversed, and the second cathode electrode layer (CAT2) By adjusting the thickness, the phases of the secondary reflected light ④ and the tertiary reflected light ⑥ can be reversed. Referring to the light waveform of FIG. 11A, the sum of the amplitude (ⓐ) of the first-order reflected light (②) and the amplitude (ⓒ) of the third-order reflected light (⑥) is equal to the amplitude (ⓑ) of the second-order reflected light (④). . The phase of the first reflected light (②) and the third reflected light (⑥) are the same, and the phase of the first reflected light (②) is opposite to the phase of the second reflected light (④). As a result, the external light reflectance can be reduced to 2% or less even in the central region C where the thickness of the first cathode electrode layer CAT1 is thin.

Referring to FIG. 11B illustrating the right edge region R of the substrate, incident light ① penetrating the substrate 110 and entering from the bottom of the bank BA is partially reflected from the lower surface of the reflectance control layer IM, The primary reflected light (②) travels toward the substrate 110. The reflectance control layer IM does not reflect all of the incident light ① due to a difference in refractive index at the interface with the bank BA. According to the conditions described above, only about 30% of the incident light ① is reflected as primary reflected light ②, and the remaining 70% passes through the reflectance control layer IM. The first transmitted light ③ passing through the reflectance control layer IM passes through the light emitting layer EL and is partially reflected by the first cathode electrode layer CAT1. According to the conditions described above, 71.4% of the first transmitted light ③ is reflected from the first cathode electrode layer CAT1 and proceeds toward the substrate 110 as secondary reflected light ④. Therefore, the light amount of the secondary reflected light ④ is 50% of the incident light ①. 28.6% of the first transmitted light ③ passes through the first cathode electrode layer CAT1 and the light emitting layer EL to become second transmitted light ⑤. The second transmitted light ⑤ is reflected as tertiary reflected light ⑥ by the third cathode electrode layer CAT3. Therefore, the tertiary reflected light (⑥) is 20% of the incident light (①). As a result, the sum of the first reflected light (②) and the third reflected light (⑥) is 50% of the incident light (①), and is equal to 50% of the second reflected light (④).

At this time, by adjusting the thickness of the reflectance control layer (IM), as in the central region (C), the phases of the primary reflected light (②) and the secondary reflected light (④) are reversed, and the second cathode electrode layer (CAT2) By adjusting the thickness of , the phases of the secondary reflected light ④ and the tertiary reflected light ⑥ can be reversed. Referring to the light waveform of FIG. 11B, the sum of the amplitude (ⓐ') of the first reflected light (②) and the amplitude (ⓒ') of the third reflected light (⑥) is the amplitude (ⓑ') of the second reflected light (④). is the same as The phase of the first reflected light (②) and the phase of the third reflected light (⑥) are the same, and the phase of the first reflected light (②) is opposite to the phase of the second reflected light (④). As a result, the external light reflectance may be reduced to 2% or less in the right edge region R where the thickness of the first cathode electrode layer CAT1 is thick.

In the fourth embodiment, considering that the first cathode electrode layer CAT1 is not uniformly formed, the reflectance control layer IM is applied to the entire inside of the bank BA. Therefore, considering the reflectance of the reflectance control layer IM, the reflectance of the first cathode electrode layer CAT1 is adjusted to be less than 50%. At this time, it is preferable to apply the reflectance adjusting layer IM to have the same profile in consideration of the cross-sectional profile of the stack on which the first cathode electrode layer CAT1 is applied.

For example, a profile in which the first cathode electrode layer CAT1 is thin in the central region C of the substrate 110 and thick in the left and right edge regions L and R may always occur due to manufacturing process conditions. Considering this point, the reflectance control layer (IM) follows a profile formed to be thin in the central region (C) of the substrate 110 and thick in the edge regions (L and R), the same as the first cathode electrode layer (CAT1). can be deposited. At this time, by adjusting the total thickness of the reflectance control layer IM and adjusting the thicknesses of the layers interposed between the first cathode electrode layer CAT1 and the external light due to the thickness change of the first cathode electrode layer CAT1. The reflection leakage can be compensated.

In the above fourth embodiment, the case where the first cathode electrode layer CAT1 is configured to have a thickness of 150 Å so that the reflectance of the first cathode electrode layer CAT1 is about 50% has been described. That is, in the fourth embodiment, even though the first cathode electrode layer CAT1 is formed to have a thickness of 150 Å, the first cathode electrode layer CAT1 is not laminated with the same thickness over the entire substrate, particularly in the central region C of the substrate. In , even if the reflectance is reduced by being laminated to a thickness of 120 Å, a configuration for preventing deviations in the reflectance has been described.

<Fifth Embodiment>

Unlike the fourth embodiment, it may be necessary to laminate the first cathode electrode layer CAT1 to a very thin thickness of 100 Å. Even in this case, as shown in FIG. 9 , the first cathode electrode layer CAT1 is deposited with an uneven thickness. In this case, the reflectance adjusting layer may be stacked differently from the fourth embodiment.

Hereinafter, a fifth embodiment of this specification will be described with reference to FIGS. 12A and 12B. 12A is an enlarged cross-sectional view illustrating a structure and a light path of a thin region of a first cathode electrode layer according to a fifth embodiment of the present specification. 12B is an enlarged cross-sectional view illustrating a structure and a light path of a thick region of a first cathode electrode layer according to a fifth embodiment of the present specification.

Referring to FIGS. 12A and 12B , looking at the structure of the central region C in which the first cathode electrode layer CAT1 is thinly formed, the anode electrodes ANO are disposed on the planarization layer PL at regular intervals. A bank BA is formed on the anode electrode ANO to cover the edge area and expose the central portion. A reflectivity control layer IM is interposed in the bank BA. Unlike the case of the third embodiment, the reflectivity control layer IM has a structure disposed in an upper region of the bank BA inside the bank BA.

An emission layer EL is stacked on the bank BA and the anode electrode ANO. A first cathode electrode layer CAT1 is stacked on the light emitting layer. A second cathode electrode layer CAT2 is stacked on the first cathode electrode layer CAT1. A third cathode electrode layer CAT3 is stacked on the second cathode electrode layer CAT2.

Also in the fifth embodiment, the first cathode electrode layer CAT1 has a thinner thickness in the central region C than in the right edge region R. However, in the fifth embodiment, a case in which the thickness of the first cathode electrode CAT1 is formed to be 100 Å thinner than that of the fourth embodiment will be described. For example, the first cathode electrode layer CAT1 applied to the central region C has a first thickness t1, and the second cathode electrode layer CAT1 applied to the right edge region R has a second thickness t2. ) has The first thickness t1 is smaller than the second thickness t2. For example, the first thickness t1 may be 80 Å, and the second thickness t2 may be 100 Å. Also here, the central area C may be referred to as a first area, and the right edge area R may be referred to as a second area. Alternatively, the central region C may be referred to as the second region, and the right edge region R may be referred to as the second region.

In this way, in order to compensate for the fact that the thickness of the first cathode electrode layer CAT1 is not constant over the entire substrate 110, the reflectance control layer IM is used. The reflectivity control layer IM has a third thickness t3 in the central region C and a fourth thickness t4 in the right edge region R. The third thickness t3 is thicker than the fourth thickness t4. For example, the third thickness t3 may be 1,000 Å, and the fourth thickness t4 may be 700 Å.

The amount of light reflected from the reflectance control layer (IM) having a small thickness is less than the amount of light reflected from the reflectance control layer (IM) having a thick thickness. For example, the reflectance adjusting layer IM having the third thickness t3 applied to the central region C may have a light reflectance of 30%. In addition, the reflectance adjusting layer IM having the fourth thickness t4 applied to the right edge region R may have a light reflectance of 20%.

The amount of light reflected from the thin first cathode electrode layer CAT1 is smaller than the amount of light reflected from the thick first cathode electrode layer CAT1. As an example, the first cathode electrode layer CAT1 having the first thickness t1 applied to the central region C may have a light reflectivity of 28.6%. In addition, the first cathode electrode layer CAT1 having the second thickness t2 applied to the right edge region R may have a light reflectivity of 37.5%. Since the thickness of the first cathode electrode layer CAT1 of the fifth embodiment is thinner than that of the first cathode electrode layer CAT1 of the fourth embodiment, the overall reflectance has a smaller value.

Referring to FIG. 12A describing the central region C of the substrate, the incident light ① passing through the substrate 110 and entering from the bottom of the bank BA is partially reflected from the lower surface of the reflectance control layer IM and The differential reflected light ② proceeds toward the substrate 110 . The reflectance control layer IM does not reflect all of the incident light ① due to a difference in refractive index at the interface with the bank BA. According to the conditions described above, only about 30% of the incident light ① is reflected as primary reflected light ②, and the remaining 70% passes through the reflectance control layer IM. The first transmitted light ③ passing through the reflectance control layer IM passes through the light emitting layer EL and is partially reflected by the first cathode electrode layer CAT1. According to the conditions described above, 28.6% of the first transmitted light ③ is reflected from the first cathode electrode layer CAT1 and proceeds toward the substrate 110 as secondary reflected light ④. Therefore, the light amount of the secondary reflected light ④ is 20% of the incident light ①. 71.4% of the first transmitted light ③ passes through the first cathode electrode layer CAT1 and the light emitting layer EL to become second transmitted light ⑤. The second transmitted light ⑤ is reflected as tertiary reflected light ⑥ by the third cathode electrode layer CAT3. Therefore, the tertiary reflected light (⑥) is 50% of the incident light (①). As a result, the sum of the first reflected light (②) and the second reflected light (④) is 50% of the incident light (①), and is equal to 50% of the third reflected light (⑥).

At this time, by adjusting the thickness of the reflectance control layer (IM) and the upper layer of the bank (BA), the phases of the primary reflected light (②) and the secondary reflected light (④) are made the same, and the second cathode electrode layer (CAT2) By adjusting the thickness, the phases of the secondary reflected light ④ and the tertiary reflected light ⑥ can be reversed. Referring to the light waveform of FIG. 12A, the sum of the amplitude (ⓐ) of the first-order reflected light (②) and the amplitude (ⓑ) of the second-order reflected light (④) is equal to the amplitude (ⓒ) of the third-order reflected light (⑥). . The phase of the first-order reflected light (②) is the same as the phase of the second-order reflected light (④), and the phase is opposite to that of the third-order reflected light (⑥). As a result, the external light reflectance can be reduced to 2% or less even in the central region C where the thickness of the first cathode electrode layer CAT1 is thin.

Referring to FIG. 12B describing the right edge region R of the substrate, the incident light ① penetrating the substrate 110 and entering from the bottom of the bank BA is partially reflected from the lower surface of the reflectance control layer IM, The primary reflected light (②) travels toward the substrate 110. The reflectance control layer IM does not reflect all of the incident light ① due to a difference in refractive index at the interface with the bank BA. According to the conditions described above, only about 20% of the incident light ① is reflected as primary reflected light ②, and the remaining 80% passes through the reflectance control layer IM. The first transmitted light ③ passing through the reflectance control layer IM passes through the light emitting layer EL and is partially reflected by the first cathode electrode layer CAT1. According to the conditions described above, 37.5% of the first transmitted light ③ is reflected from the first cathode electrode layer CAT1 and proceeds toward the substrate 110 as secondary reflected light ④. Therefore, the light quantity of the secondary reflected light ④ is 30% of the incident light ①. 62.5% of the first transmitted light ③ passes through the first cathode electrode layer CAT1 and the light emitting layer EL to become second transmitted light ⑤. The second transmitted light ⑤ is reflected as tertiary reflected light ⑥ by the third cathode electrode layer CAT3. Therefore, the tertiary reflected light (⑥) is 50% of the incident light (①). As a result, the sum of the first reflected light (②) and the second reflected light (④) is 50% of the incident light (①), and is equal to 50% of the third reflected light (⑥).

At this time, the thickness of the reflectance control layer (IM) is adjusted to make the phases of the primary reflected light (②) and the secondary reflected light (④) the same as in the central region (C), and the second cathode electrode layer (CAT2) By adjusting the thickness of , the phases of the secondary reflected light ④ and the tertiary reflected light ⑥ can be reversed. Referring to the light waveform of FIG. 12B, the sum of the amplitude (ⓐ') of the first reflected light (②) and the amplitude (ⓑ') of the second reflected light (④) is the amplitude (ⓒ') of the third reflected light (⑥). is the same as The phase of the first-order reflected light (②) is the same as the phase of the second-order reflected light (④), and the phase is opposite to that of the third-order reflected light (⑥). As a result, the external light reflectance may be reduced to 2% or less in the right edge region R where the thickness of the first cathode electrode layer CAT1 is thick.

In the fifth embodiment, considering that the first cathode electrode layer CAT1 is not uniformly formed, the reflectance control layer IM is applied to the entire inside of the bank BA. Therefore, considering the reflectance of the reflectance control layer IM, the reflectance of the first cathode electrode layer CAT1 is adjusted to be less than 50%. At this time, it is preferable to apply the reflectance adjusting layer (IM) to have a different profile in consideration of the profile to which the first cathode electrode layer (CAT1) is applied.

For example, a profile in which the first cathode electrode layer CAT1 is thin in the central region C of the substrate 110 and thick in the left and right edge regions L and R may occur due to manufacturing process conditions. In consideration of this point, the reflectance control layer (IM) follows a profile in which, unlike the first cathode electrode layer (CAT1), it is thick in the central region (C) and thin in the edge regions (L and R) of the substrate 110. can be deposited. At this time, by adjusting the total thickness of the reflectance control layer IM and adjusting the thicknesses of the layers interposed between the first cathode electrode layer CAT1 and the external light due to the thickness change of the first cathode electrode layer CAT1. The reflection leakage can be compensated.

In the fourth and fifth embodiments, only the case where the reflectance control layer (IM) is formed on the bank (BA) has been described, but is not limited thereto, and the reflectance control layer on the planarization film (PL) described in the second embodiment (IM), the same effect can be achieved. As a result, reflection of external light leaking due to variation in thickness of the first cathode layer CAT1 is compensated by the reflectance control layer IM, and thus reflection of external light may be suppressed within a designed tolerance range of 2%.

Comparing the previously described fourth and fifth embodiments, in the case of the fourth embodiment, the phases of the first reflected light ② and the second reflected light ④ are opposite, whereas in the case of the fifth embodiment, the first The phases of the reflected light (②) and the secondary reflected light (④) are the same.

The upper end of the bank BA and the light emitting layer EL are interposed between the first reflected light ② and the second reflected light ④. Here, the thickness of the light emitting layer EL may be determined according to the type of light emitting diode OLE to be formed. Therefore, depending on the thickness of the light emitting layer EL, the phases of the first reflected light ② and the second reflected light ④ may be opposite or the same.

That is, when the phases of the first reflected light ② and the second reflected light ④ are reversed due to the thickness of the light emitting layer EL, the structure according to the fourth embodiment is applied, and the first reflected light ② and the second reflected light When the phases of the differential reflected light ④ are the same, it is preferable to apply the structure according to the fifth embodiment.

The features, structures, effects, etc. described in the above-described examples of this specification are included in at least one example of this specification, and are not necessarily limited to only one example. Furthermore, the features, structures, effects, etc. illustrated in at least one example of this specification can be combined or modified with respect to other examples by those skilled in the art to which this specification belongs. Therefore, contents related to these combinations and variations should be construed as being included in the scope of this specification.

This specification described above is not limited to the foregoing embodiments and accompanying drawings, and it is common in the technical field to which this specification belongs that various substitutions, modifications, and changes are possible within the scope without departing from the technical details of this specification. It will be clear to those who have knowledge of Therefore, the scope of this specification is indicated by the following claims, and all changes or modifications derived from the meaning and scope of the claims and equivalent concepts should be interpreted as being included in the scope of this specification.

OLE: light emitting diode ANO: anode electrode
EL: light emitting layer CAT: cathode electrode
CAT1: first cathode electrode layer CAT2: second cathode electrode layer
CAT3: Third cathode electrode layer IM: Reflectance control layer
101: first metal layer 200: second metal layer
BUF: buffer layer LS: light blocking layer

Claims (12)

a driving layer disposed on the substrate;
a planarization film disposed over the driving layer;
a plurality of anode electrodes disposed at regular intervals on the planarization film;
a bank disposed between the anode electrodes to define a light emitting area;
a light emitting layer disposed on the bank and the anode electrode;
a cathode electrode disposed on the light emitting layer; and
A light emitting display device comprising a reflectivity control layer disposed on one of an upper region of the bank and an upper region of the planarization layer. According to claim 1,
The cathode electrode is
a first cathode electrode layer disposed on the light emitting layer;
a second cathode electrode layer disposed on the first cathode electrode layer; and
A light emitting display device comprising a third cathode electrode layer disposed on the second cathode electrode layer. According to claim 2,
The first cathode electrode layer is a metal material having a thickness of 100 Å to 200 Å,
The second cathode electrode layer is a conductive organic layer including a domain material and a dopant,
The light emitting display device of claim 1 , wherein the third cathode electrode layer is a metal material having a thickness of 2,000 Å to 4,000 Å. According to claim 2,
The first cathode electrode layer,
a first thickness in a first region of the substrate;
A light emitting display device having a second thickness greater than the first thickness in the second region of the substrate. According to claim 4,
The reflectance control layer,
a third thickness in the first region of the substrate;
The light emitting display device having a fourth thickness smaller than the third thickness in the second region of the substrate. According to claim 5,
In the first area,
With respect to the incident light incident through the substrate, the ratio of the sum of the first reflected light reflected from the reflectance adjusting layer and the second reflected light reflected from the first cathode electrode layer is the third reflected light reflected from the third cathode electrode layer. The difference from the light amount ratio is within 2%,
The first reflected light and the second reflected light have the same phase,
The second reflected light and the third reflected light have opposite phases. According to claim 5,
In the second region,
With respect to the incident light incident through the substrate, the ratio of the sum of the first reflected light reflected from the reflectance adjusting layer and the second reflected light reflected from the first cathode electrode layer is the third reflected light reflected from the third cathode electrode layer. The difference from the light amount ratio is within 2%,
The first reflected light and the second reflected light have the same phase,
The second reflected light and the third reflected light have opposite phases. According to claim 1,
The reflectance control layer is disposed in the bank,
The reflectance control layer has a refractive index different from that of the bank. According to claim 1,
The reflectance control layer is disposed within the planarization film,
The light emitting display device of claim 1 , wherein the reflectance control layer has a refractive index different from that of the planarization layer. According to claim 1,
The driving layer further includes wiring,
The wiring is
A light emitting display device further comprising wires including a first metal layer and a second metal layer stacked on the first metal layer. According to claim 10,
Compared to the incident light incident through the substrate, the difference between the light amount ratio of the first reflected light reflected from the first metal layer and the light amount ratio of the second reflected light reflected from the second metal layer is within 2%,
Phases of the first reflected light and the second reflected light are opposite to each other. According to claim 10,
The first metal layer includes a metal oxide material having a thickness of 100 Å to 500 Å,
The second metal layer includes a metal material having a thickness of 2,000 Å to 4,000 Å.

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