KR20230103721A - Light Emitting Display Device - Google Patents

Abstract

The present invention may comprise: a substrate having a plurality of sub-pixels; a scan line of a first direction on the substrate, and a data line and a power supply voltage line of a second direction intersecting the first direction; a flattening layer covering the scan line, the data line, and the power supply voltage line on the substrate; a bank exposing a light emitting part of each of the plurality of sub-pixels on the flattening layer; a spacer equipped in one part of the bank; and a metal pattern equipped between the spacer and the bank and connected to the power supply voltage line. Therefore, the present invention is capable of improving a reliability of the device.

Description

Light Emitting Display Device {Light Emitting Display Device}

The present specification relates to a light emitting display device capable of preventing defects due to conductive foreign substances penetrating on a spacer by using a metal pattern.

Recently, as we entered the full-fledged information age, the display field that visually expresses electrical information signals has developed rapidly. Display Device) has been developed and is rapidly replacing the existing cathode ray tube (CRT).

Specific examples of such a flat panel display device include a liquid crystal display device (LCD), a plasma display panel device (PDP), a field emission display device (FED), and an organic light emitting display device. (Organic Light Emitting Device: OLED) etc. are mentioned.

Among them, a light emitting display device that does not require a separate light source is being considered as a competitive application for compact device and vivid color display.

The light emitting display device includes a light emitting element, and the light emitting element is covered with an encapsulation structure to protect an internal functional layer. However, there is a problem in that the internal structure of the light emitting device is damaged due to foreign substances generated during the process or ions that are introduced into the light emitting device due to foreign substances.

The present specification has been devised to solve the above problems, and relates to a light emitting display device capable of preventing ionic defects by applying a metal pattern corresponding to a spacer vulnerable to penetration of foreign substances.

The light emitting display device according to the exemplary embodiment of the present specification includes a metal pattern between a spacer and a bank, and a positive power supply voltage is applied to the metal pattern to trap conductive ions remaining in the light emitting display device and prevent the influence of the light emitting element. and improve the reliability of the device.

A light emitting display device according to an embodiment of the present specification includes a substrate having a plurality of sub-pixels, a scan line in a first direction on the substrate, a data line and a power supply voltage line in a second direction crossing the first direction, and , a planarization layer covering the scan line, the data line, and the power supply voltage line on the substrate, a bank exposing the light emitting part of each of a plurality of sub-pixels on the planarization layer, and a part of the bank provided A spacer and a metal pattern provided between the spacer and the bank and connected to the power voltage line through a first contact hole penetrating the planarization layer and the bank.

The light emitting display device of the present specification has the following effects.

The light emitting display device according to the exemplary embodiment of the present specification includes a metal pattern between a spacer and a bank, a contact hole passing through an insulating film, and connecting the contact hole to a passing lower power supply voltage line. By applying a positive (or positive) power supply voltage to the light emitting display device, conductive ions remaining in the light emitting display device can be captured with a metal pattern, defects caused by conductivity can be prevented, and reliability of the device can be improved. .

1 is a plan view illustrating a light emitting display device according to the present specification.
FIG. 2 is a plan view illustrating an area A of FIG. 1 in a light emitting display device according to an exemplary embodiment of the present specification.
3 is a cross-sectional view taken along the line II-I' of FIG. 2 according to an embodiment of the present specification.
4 is a circuit diagram of one sub-pixel of FIG. 2 .
5 is a cross-sectional view illustrating a movement path of conductive ions when a foreign material is generated in the light emitting display device of the present specification.
6 is a cross-sectional view illustrating movement of conductive ions when a foreign material is generated in a light emitting display device according to a comparative example.
7A and 7B are cross-sectional views illustrating examples of light emitting elements in the light emitting display device of the present specification.
8 is a plan view illustrating a light emitting display device according to another exemplary embodiment of the present specification.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present specification will be described. Like reference numbers throughout the specification indicate substantially the same elements. In the following description, if it is determined that a detailed description of a technology or configuration related to the present specification may unnecessarily obscure the gist of the present specification, the detailed description will be omitted. In addition, the component names used in the following description are selected in consideration of the ease of writing the specification, and may be different from the part names of the actual product.

The shape, size, ratio, angle, number, etc. disclosed in the drawings for explaining various embodiments of the present specification are illustrative, so the present specification is not limited to those shown in the drawings. Like reference numerals designate like elements throughout this specification. In addition, in describing the present specification, if it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present specification, the detailed description will be omitted. When 'includes', 'has', 'consists of', etc. mentioned in this specification is used, other parts may be added unless 'only' is used. In the case where a component is expressed in the singular, the case including the plural is included unless otherwise explicitly stated.

In interpreting the components included in various embodiments of the present specification, even if there is no separate explicit description, it is interpreted as including an error range.

In describing various embodiments of the present specification, in the case of describing a positional relationship, for example, 'on ~', '~ on top', '~ on the bottom', '~ next to', etc. When the positional relationship of parts is described, one or more other parts may be located between two parts unless 'immediately' or 'directly' is used.

In describing various embodiments of the present specification, in the case of explaining the temporal relationship, for example, 'after', 'after', 'after', 'before', etc. When is described, it may also include non-continuous cases unless 'immediately' or 'directly' is used.

In describing various embodiments of the present specification, 'first ~', 'second ~', etc. may be used to describe various components, but these terms are only used to distinguish between identical and similar components. am. Accordingly, elements modified as 'first to' in this specification may be the same as elements modified as 'second to' within the technical spirit of the present specification, unless otherwise noted.

Each feature of the various embodiments of the present specification may be partially or entirely combined or combined with each other, technically various interlocking and driving are possible, and each of the various embodiments may be implemented independently of each other or together in an association relationship. may be

Hereinafter, a light emitting display device and a manufacturing method of the present specification will be described.

The light emitting display device of the present specification includes light emitting elements capable of self-emitting light in an array configured in the display device without a separate light source unit. For example, such a display device includes an organic light emitting display device, a micro LED display device, and an electrophoretic display device. , a quantum dot light emitting display device, etc. may be considered. The listed examples are just examples, and a display device capable of self-emission can be extended to other applications.

1 is a plan view illustrating a light emitting display device of the present specification, and FIG. 2 is a plan view illustrating an area A of FIG. 1 in the light emitting display device according to an exemplary embodiment of the present specification. Also, FIG. 3 is a cross-sectional view taken along line II to I' of FIG. 2 according to an exemplary embodiment. 4 is a circuit diagram of one sub-pixel of FIG. 2 .

1 to 3 , the light emitting display device according to an exemplary embodiment of the present specification includes a substrate 100 having a plurality of sub-pixels, and scan lines (Scan1 (121), Scan2 ( 122a, 122b)), the data line (DL) 163 and the power voltage line (VDL) 161 in the second direction crossing the first direction, and the scan line (Scan1) on the substrate 100 (121), Scan2 (122a, 122b), a planarization layer 170 covering the data line (DL) 163 and the power voltage line (VDL) 161, and on the planarization layer 170, A bank 180 exposing light emitting parts REM, GEM, and BEM of each of a plurality of sub-pixels, a spacer 190 provided in a part of the bank, and provided between the spacer 190 and the bank 180 The metal pattern 185 is included.

The metal pattern 185 is connected to the power voltage line VDL 161 through the first contact hole CT4 penetrating the planarization layer 170 and the bank 180, thereby forming an upper surface of the bank 180. A positive supply voltage can be applied to The power supply voltage line VDL 161 is a line for supplying the positive driving voltage EVDD to the driving transistor DT, to which a positive power supply voltage of approximately +10V or more is applied. Referring to FIG. 4 , a driving transistor DT and a fourth switching transistor T4 are provided between the power supply voltage line VDL and the first electrode of the light emitting element OLED, and at least the first electrode of the light emitting element has a power source. A voltage corresponding to a value obtained by subtracting the voltage applied to the driving transistor DT and the fourth switching transistor T4 from the supply voltage of the voltage line VDL is applied, and the amount applied to the metal pattern 185 The power supply voltage of is greater than the voltage applied to the first electrode. Therefore, even if conductive ions penetrate into the spacer 190, they do not move toward the first electrode 210 of the light emitting device, and the power voltage is passed through the metal pattern 185 having a higher applied voltage than the first electrode 210. Since it is captured on the line 161 side, defects caused by conductive ions and foreign matter can be prevented.

As shown in FIG. 1 , the substrate 100 includes a display area AA where a plurality of sub-pixels are disposed, a driver outside the display area AA, and scan lines Scan1 (121) provided in the driver and the display area AA. Scan2 (122a, 122b)), the data line (DL) 163 and the power supply voltage line (VDL) 161) of the second direction intersecting the first direction from the outside and transmitting the link wiring and a non-display area NA including (not shown).

In the non-display area AA, the link wiring is connected to the pad electrode provided on the edge of the substrate 100, and the pad electrode is connected to the printed circuit film including the integrated circuit (IC) provided on the substrate 100. It can be. In addition, the printed circuit film may be connected to the circuit board outside the board 100 .

Referring to FIGS. 2 and 3 , the light emitting units EM (REM, GEM, and BEM) of the sub-pixels are defined as an open area of the bank 180 . In the sub-pixel, the outside of the light emitting part (EM: REM, GEM, BEM) becomes a non-emitting part (NEM). The region where the bank 180 is formed becomes a non-light emitting region. Since the bank 180 opens a plurality of light emitting units EM corresponding to each sub-pixel across the display area AA of the substrate 100 and is integrally formed, the non-emitting areas NEM of the sub-pixels are adjacent to each other. They are continuous without interruption between them. The sub-pixel does not mean an area separated by a structure on the substrate 100, but includes an area around one light emitting unit (EM: REM, GEM, BEM) and is the smallest unit to emit color. means the area that operates as Adjacent sub-pixels include scan lines (Scan1 (121), Scan2 (122a, 122b)) and data lines (DL) in a second direction (Y direction in FIG. 2) crossing the first direction (X direction in FIG. 2). ) 163 and the power voltage line (VDL) 161 may be shared at least in part.

Meanwhile, in the light emitting display device of the present specification, the metal pattern 185 is formed to correspond to the spacer 190 . Since the spacer 190 protrudes in the vertical direction (Z direction) and is a structure to which foreign matter easily adheres, when a foreign matter occurs on the spacer 190, the second electrode 230 and the first inorganic Seams such as cracks may occur in the structure of the encapsulation layer 310 . In this case, the conductive ions remaining in the light emitting display device may come into the interior by the seam. In the light emitting display device of the present specification, the conductive ions are captured by a positive power supply voltage applied to the metal pattern 185 so that the conductive foreign material is not removed. This is to prevent the light emitting element 200 (OLED) inside the light emitting display device from being affected. In addition, the conductive ions mainly remain negative ions in the process. Since the positive power voltage of the metal pattern 185 is applied to attract negative ions with a strong electric field, the flow of conductive ions is prevented and light emission due to conductive ions is prevented. A change in the internal configuration of the device can be prevented.

The metal pattern 185 is provided on the upper surface of the bank 180 and is formed by patterning a separate metal after forming the bank 180 .

The metal pattern 185 is provided for an electrical function, and is made of a metal having strong corrosion resistance and acid resistance and good conductivity, such as aluminum (Al), titanium (Ti), copper (Cu), and molybdenum (Mo). Alternatively, it may be formed in a multi-layer structure. The metal pattern 185 may include a single metal or an alloy including listed metals.

The metal pattern 185 has a width equal to or smaller than that of the spacer 190 . More preferably, the metal pattern 185 may have a smaller width than the lower width of the spacer 190 . That is, the second electrode 230 adjacent to the spacer 190 and the metal pattern 185 are electrically separated by making the metal pattern 185 smaller than the lower width of the spacer 190 . The metal pattern 185 can serve as an electrical path for conductive ions entering through a crack when a foreign substance penetrates the upper part of the spacer 190 or when a seam such as a crack is generated in the structure above the spacer 190. Therefore, a sufficient distance is provided between the metal pattern 185 and the second electrode 230 to prevent the second electrode 185 or the internal stack 220 from being affected by conductive ions.

The light emitting element 200 (OLED) is provided in each of the sub-pixels and can operate individually by first electrodes 210 (210R, 210G, 210B) independently formed in each sub-pixel. there is. The light emitting device 200 may include first electrodes 210 (210R, 210G, 210B) and second electrodes 230 and a functional stack 220 that face each other. The first electrodes 210 (210R, 210G, 210B) are individually provided and may be separated for each sub-pixel.

When the light emitting device is an organic light emitting device, the function stack 220 of the light emitting device may include an organic layer, and at least the organic layer includes the light emitting layer. In addition to the light emitting layer, in the functional stack 220, a hole injection layer and a hole transport layer may be formed between the first electrode and the light emitting layer, and an electron transport layer and electron injection layer may be formed between the light emitting layer and the second electrode. At least one or more of the plurality of layers included in the functional stack 220 may be formed not only in the light emitting part EM but also in the non-emitting part NEM, and a layer integrally formed over the entire display area AA may have its integrity and In terms of continuity, it is also called a common layer. The functional stack 220 shown in FIG. 3 shows only the light emitting layer as an example, and when the functional stack includes at least one common layer of a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer, the common layer is It is uniformly formed not only in the light emitting portion EM but also in the non-emitting portion NEM. When the common layer is provided, the common layer may be formed on the top surface of the bank 180 and the top surface and side surfaces of the spacer 190 .

Each line shown in FIG. 2 follows, but is not limited to, a first direction (X direction) and a second direction (Y direction), and may be disposed along a diagonal direction that is constantly inclined in the X direction, and intersects each other. The intersection angle of the scan lines 122a, 122b, and 121 and the data line 163 may be an acute angle other than 90 degrees.

In addition, FIG. 2 is shown to show the corresponding positions of each line and the light emitting units REM, GEM, and BEM, and specific configurations of transistors or storage capacitors are omitted. Depending on the arrangement of the transistors, each of the lines 121, 122a, 122b, 123, 161, 162, 163, and 164 may further have protrusions, and the protrusions may have different widths. Alternatively, the scan lines 121, 122a, and 122b, the emission control line ( EM) may have an avoidance region skewed upward or downward from the illustrated shape in an area overlapping the first electrodes 210R, 210G, and 210B in the illustrated first direction, and the data line 163, power voltage The line 161, the base voltage line 162, and the reference line RL 164 are shifted to the right or left of the illustrated shape in the region overlapping the first electrodes 210R, 210G, and 210B in the illustrated second direction. You can have a true avoidance area.

2 shows that the blue light emitting part (BEM) has a larger area than the red light emitting part (REM) and green light emitting part (GEM), which means that the visibility of blue is relatively low, and a light emitting element emitting blue color in the same area can emit other colors. This is to compensate for the insufficient efficiency compared to the light emitting device that emits light by area. If the blue light emitting device has the same efficiency as the other color light emitting device, each of the light emitting units REM, GEM, and BEM may have the same area.

Meanwhile, FIG. 2 shows a shape in which a red light emitting part REM and a green light emitting part GEM along the second direction are adjacent to one blue light emitting part BEM along the second direction. This is an example considering optical characteristics, and the arrangement or shape of the light emitting unit may be changed according to the color characteristics of the light emitting display device.

In addition, each of the light emitting units REM, GEM, and BEM is provided in the first electrodes 210R, 210G, and 210B, and a region where the first electrodes 210R, 210G, and 210G overlap the bank 180 is a non-light emitting portion. , and upper portions of the first electrodes 210R, 210G, and 210G in the open area of the bank 180 (within the dotted line area in FIG. 2 ) are exposed from the bank 180 .

The spacer 190 is preferably spaced apart from the first electrodes 210R, 210G, and 210B. This is to separate the first electrodes 210R, 210G, and 210B to which electrical signals are applied from the cause of defects caused by the foreign matter, since the spacer 190 is structurally protruded in the vertical direction and relatively easily penetrated by foreign matter. am.

A spacer 190 may be provided between at least the light emitting units REM, GEM, and BEM emitting different colors. The spacer 190 is located above the bank 180, and during the process of forming the internal stack 220 of the light emitting device, especially when a fine metal mask (FMM) is applied, the fine metal mask and the spacer 190 are formed first. , to prevent sagging of the fine metal mask to protect the structure formed on the substrate 100 from the fine metal mask, and also to prevent the collapse of the shape of the bank 180 under the lower spacer 190, thereby increasing the reliability of the internal structure This is to proceed with the deposition process of the internal stack 220 while maintaining the .

The spacer 190 may be located at the same position or different positions between the light emitting units REM, GEM, and BEM.

The spacer 190 overlaps the power voltage line 161, and the lower metal pattern 185 formed with a smaller width than the spacer 190 is connected to the power voltage line 161, the bank 180, and the planarization layer 170. ) through the first contact hole CT.

Also, as shown in FIG. 2 , the data line 163 and the base power supply line (VSL: 162) are spaced apart from and provided in parallel with the power supply voltage line (VDL: 161), and may overlap the spacer 190. . The base power supply line (VSL: 162) is a line to which a low potential voltage is applied.

In order, the planarization layer 170 is formed, the first electrode of each light emitting unit (REM, GEM, BEM) is formed, and a bank material such as photo acrylic or polyimide is coated on the entire surface, and then the light emitting unit EM In the same process of forming an open region exposing the upper portion of the first electrodes 210R, 210G, and 210B corresponding to the bank 180 and the planarization layer 170 to expose a portion of the upper portion of the power voltage line 161 A first contact hole CT4 penetrating both may be formed.

In addition, the inside of the first contact hole CT4 is filled, and a metal material is deposited on the substrate 100 including the upper part of the bank 180, and after formation, the metal material is left only in a predetermined area on the bank 180 to form the upper part of the bank 180. A metal pattern 185 remaining on a part of the surface is formed. As shown in FIG. 2 , the metal pattern 185 may be circular, square, or other polygonal shape. The metal pattern 185 has a smaller area than the spacer 190 and can be changed into various shapes as long as resistance is not increased when connected to the power voltage line 161 .

Referring to FIG. 3 , an array configuration provided in sub-pixels in addition to the light emitting element 200 will be described.

The substrate 100 may be a glass substrate or a plastic film.

When the light emitting display device is implemented as a flexible device, the substrate 100 may be a thin glass substrate or a plastic film that is etched and flexible. When the substrate 100 is a plastic film, it may include one or more polyimide films. When the substrate 100 includes a plurality of layers of films, an interlayer insulating layer may be provided between the films.

A buffer layer 110 is provided on the substrate 100 to prevent impurities remaining on the substrate 100 or moisture passing through the substrate 100 from affecting the array configuration on the substrate 100 . The buffer layer 110 may be a nitride film, an oxide film, an oxynitride film, or an insulating film including a metal in some cases.

The active layer 120 is provided on a predetermined portion on the buffer layer 110 . As shown in FIG. 3 , the active layer 120 may be integral, may be separated according to the number of transistors included in sub-pixels, or may be shared by one or more transistors. The active layer 120 may include at least one of polysilicon, amorphous silicon, and an oxide semiconductor.

A gate insulating layer 130 is formed on the active layer 120, and a first scan line (Scan1: 121), a second scan line (Scan2, 122a, 122b) and an emission control line are formed on the gate insulating layer 130. (EM: 123) and a first storage electrode 124 are provided.

The first interlayer insulating film 140 covers the first scan line (Scan1: 121), the second scan line (Scan2, 122a, 122b), the emission control line (EM: 123), and the first storage electrode 124. is provided

A second storage electrode 150 is provided on the first interlayer insulating layer 140 and overlaps with the first storage electrode 124 .

A second interlayer insulating layer 155 is provided to cover the second storage electrode 150 .

For example, the fourth switching transistor T4 of FIG. 4 includes a gate electrode integrated with the active layer 120 and the second scan line 122b, and a source electrode connected to both sides of the active layer 120 at a distance from each other ( 166) and a drain electrode 165.

Here, contact holes CT1 and CT2 are provided in the second interlayer insulating film 155, the first interlayer insulating film 140, and the gate insulating film 130 to expose a spaced upper part of the active layer 120, The active layer 120 is spaced apart and connected to each other through the contact holes CT1 and CT2, and a source electrode 166 and a drain electrode 165 are provided. In the same process of forming the fourth switching transistor T4, the first to third switching transistors T1, T2, and T3, the fifth switching transistor T5, and the storage capacitor Cst may be formed.

The planarization layer 170 covers the switching transistors T1 to T5, the driving transistor DT, and the storage capacitor Cst, and is formed by planarizing the surface.

The storage capacitor Cst includes first and second storage electrodes 124 and 150 overlapping each other and a first interlayer insulating layer 140 therebetween. In some cases, the active layer 120 overlaps with the first storage electrode 124, and the gate insulating layer 130 between the first storage electrode 124 and the active layer 120 is made of a triple electrode. A storage capacitor Cst may be defined.

Also, the second electrode 230 of the light emitting device 200 may be integrally provided in the display area AA of the substrate 100 like the common layer of the internal stack 220 . In this case, the second electrode 230 is continuously connected to the light emitting part EM and the non-emitting part NEM of the sub-pixel. Accordingly, the second electrode 230 is also provided on the top and side surfaces of the spacer 190 . For example, when the light emitting layer of the internal stack 220 is provided in the light emitting part EM and a part of the non-light emitting part NEM around the light emitting part EM, the second electrode 230 extends to the outside of the light emitting layer and The second electrode 230 is also provided on the top and side surfaces of the spacer 190 .

An encapsulation structure 300 covering the light emitting element 200 and protecting the light emitting element 200 from external moisture and air is provided. The encapsulation structure 300 may have, for example, a structure in which the inorganic layers 310 and 330 and the organic encapsulation layer 320 are alternated. The inorganic encapsulation layers 310 and 330 and the organic encapsulation layer 320 of the encapsulation structure 300 formed after the light emitting device 200 are formed at a low temperature to prevent denaturation of an internal stack in the light emitting device 200 . When forming a film at a low temperature, the temperature may be, for example, 120° C. or less.

As shown in FIG. 4 , a sub-pixel may include, for example, five switching transistors T1 to T5, one driving transistor DT, one storage capacitor Cst, and one light emitting diode (OLED). there is. Cgv may be a compensation capacitor provided for compensation and may be omitted.

The first switching transistor T1 converts the data voltage Vd applied through the data line DL to the voltage of the storage capacitor Cst in response to the first scan signal Vscan1 applied through the first scan line Scan1. It may serve to transfer to the first storage electrode.

The second switching transistor T2 electrically connects the gate electrode of the driving transistor DT and the second storage electrode of the storage capacitor Cst in response to the second scan signal Vscan2 applied through the second scan line Scan2. (to make the driving transistor DT into a diode connection state for threshold voltage compensation).

The third switching transistor T3 responds to the emission control signal (or the third scan signal) applied through the emission control line (or third scan line) EM, and the reference voltage applied through the reference voltage line RL. (VREF: initialization voltage) may be transferred to the first storage electrode of the storage capacitor Cst.

The fourth switching transistor T4 transfers the driving current generated from the driving transistor DT to the first electrode of the light emitting element OLED in response to the light emitting control signal Vem applied through the light emitting control line EM. can play a role

The fifth switching transistor T5 converts the compensation voltage applied through the reference voltage line RL in response to the second scan signal Vscan2 applied through the second scan line Scan2 to the light emitting element OLED. 1 supplied to the electrode.

The storage capacitor Cst may serve to store the data voltage and drive the driving transistor DT based on the stored data voltage. The light emitting device OLED may emit light based on the driving current generated from the driving transistor DT.

The sub-pixel shown in FIG. 4 can compensate for the threshold voltage of the driving transistor DT based on the second and third switching transistors T2 and T3, and emits light based on the fourth switching transistor T4. There are various advantages, such as being able to control the light emission time of the element OLED.

Meanwhile, in FIG. 4 , it has been described as an example that the transistors included in the sub-pixel are all P-type. However, all of the transistors included in the sub-pixel may be formed of N-type or may be implemented in a mixed structure of P-type and N-type transistors. In addition, FIG. 4 is only illustrated and described to help understand the planar and cross-sectional structures of various signal lines and power lines connected to sub-pixels in connection with the above embodiment, and the present specification is not limited thereto.

Meanwhile, the metal pattern 185 of the present specification is provided to correspond to the spacer 190 . However, the seam caused by the foreign material on the spacer 190 and the conductive foreign material caused by the seam may be limited to some of the spacers provided on the substrate 100 . The metal patterns 185 of the present specification are provided to correspond to each spacer 190, and each metal pattern 185 is connected to a power supply voltage line (VDL: 161) to which a positive power supply voltage is applied to maintain a stabilized potential. do.

Hereinafter, referring to FIG. 5 , a movement path of conductive ions when a foreign material is generated is examined.

5 is a cross-sectional view illustrating a movement path of ions when a conductive foreign material is generated in the light emitting display device of the present specification. 6 is a cross-sectional view illustrating movement of conductive ions when a foreign material is generated in a light emitting display device according to a comparative example.

After the spacer 190 is formed, a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer of the internal stack 220 may be formed by a deposition method.

In this case, a deposition mask may be used, and the spacer 190 may directly or indirectly contact the deposition mask. In this case, since the spacer 190 is structurally at a high position, the foreign material FR may remain. In addition, even if the foreign material FR is not directly attached to the spacer 190 in the deposition process, when the foreign material generated during the process remains in the light emitting display device after the formation of the encapsulation structure 300, the inside of the thick encapsulation structure 300 The foreign material FR remaining in the organic layer 320 of may remain on the relatively high spacer 190 .

As shown in FIG. 5 , the thick foreign material FR remains in the spacer 190 and causes a crack in the thin second electrode 230 or the internal stack 220 to create a seam where the crack occurs. In addition, F- ions remaining during the process may permeate into the spacer 190 through the seam. As shown in FIG. 5 , in the light emitting display device of the present specification, penetrating negative ions may be captured by the metal pattern 185 to which a positive power supply voltage is applied, preventing the light emitting element 200 from being affected.

The foreign material FR is an organic component including carbon, which remains in a deposition mask for performing a deposition process on a plurality of panels or is transferred while in contact with the substrate. In addition, it is a material in which materials piled up or scattered during the deposition process several times or dozens of times can be aggregated and has an amorphous shape.

As shown in FIG. 6 , the foreign material 25 is thicker than the structure of the light emitting element rather than causing a problem in itself, so that the internal stack 22 and the second electrode 23 of the light emitting element meet the foreign material 25 and A structural defect is created on the surface, and a crack is induced at the side of the foreign material 25 in the inorganic encapsulation layer 31 formed subsequently. In addition, the crack becomes a path through which impurities such as F- ions remaining in the organic encapsulation layer 32 penetrate, pass through the second electrode 23 having a thin thickness, and affect the internal stack 22. In particular, the impurities The light emitting layer, which is highly sensitive to ions, may be damaged. When the light emitting layer includes a phosphorescent material, it includes a phosphorescent dopant having a ligand bond with a heavy metal such as iridium. The F-ion breaks the bond between the phosphorescent dopant and promotes deterioration of the light emitting layer affected by the foreign matter, which has a direct effect on luminance and lifespan. that can affect

The light emitting display device of the present specification includes a metal pattern 185 between the spacer 190 and the bank 180 to correspond to the spacer 190, which is a weak portion into which foreign matter can penetrate, in preparation for such a foreign material. By applying a positive power supply voltage to 185, conductive ions are collected by the metal pattern 185 rather than the first electrode 210 of the light emitting element (OLED) to which a relatively low voltage is applied, thereby increasing the efficiency of the light emitting element by conductive ions. impact can be avoided.

7A and 7B are cross-sectional views illustrating examples of light emitting elements in the light emitting display device of the present specification.

As shown in FIG. 7A, the light emitting device of the present specification includes, for example, an internal stack 220 between the first electrode 210 and the second electrode 230 with one light emitting layer and a single layer having a common layer below and above the stack. It can be provided in the form of a stack.

That is, the internal stack 220 according to FIG. 7A may include a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). A hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (ETL) other than the light emitting layer (EML) may be common layers.

As another example, as shown in FIG. 7B , the internal stack 220 formed between the first electrode 210 and the second electrode 230 of the light emitting element OLED includes a plurality of stacks divided by the charge generation layer 225. may be layered. In addition, the plurality of organic layers may include layers in which some layers are commonly formed in sub-pixels and provided only in corresponding sub-pixels, such as a color emission layer. Accordingly, the internal stack 220 may include a layer commonly formed in sub-pixels and a layer spaced apart for each sub-pixel.

The example shown in FIG. 7B shows an example in which two stacks 221 to 224 and 226 to 228 are stacked, but is not limited thereto, and the organic stack 220 may be made of three or more stacks or may be made of a single stack. . In the case of a plurality of stacks, an advantage is that a long lifespan is secured for the same luminance compared to a single stack. There is an advantage of a plurality of stacks in a light emitting display device such as a vehicle requiring a long lifespan.

Meanwhile, the lower stack includes a hole injection layer 221 including a p-type dopant to facilitate injection of holes through an interface with the first electrode 210, a first hole transport layer 222, and first light emitting layers 223a and 223b. , 223c), and a first electron transport layer 224 .

The charge generation layer 225 may be formed by stacking an n-type charge generation layer 225a and a p-type charge generation layer 225b, or may be formed as a single layer.

The upper stack may include a second hole injection layer 226 , second emission layers 227a , 227b and 227c , a second electron transport layer 228 and an electron injection layer 229 .

Looking at each sub-pixel (R_SP, G_SP, B_SP) is as follows.

The first red emission layer 223a of the red sub-pixel R_SP is provided in the lower stack, and the auxiliary hole transport layer 226a is further provided on the second hole transport layer 226 in the upper stack. ) is formed on the second red light emitting layer 227a.

The first green light-emitting layer 223b of the green sub-pixel G_SP is provided in the lower stack, and the second green light-emitting layer 227b is formed on the second hole transport layer 226 in the upper stack.

The first blue light emitting layer 223c of the blue sub-pixel B_SP is provided in the lower stack, and the second blue light emitting layer 227c is formed on the second hole transport layer 226 in the upper stack.

The first red light emitting layer 223a, the first green light emitting layer 223b, and the first blue light emitting layer 223c in the same lower stack, and the second red light emitting layer 227a and the second green light emitting layer 227b in the same upper stack and the second blue light-emitting layer 227c have different vertical distances to the first electrode 210 due to different resonance effects for each color wavelength, and for this purpose, they have different heights. In addition, in consideration of the process requirements of the second hole transport layer 226 formed in common with adjacent sub-pixels in the upper stack in the red sub-pixel SP and the light-emitting area of the second red light-emitting layer 227a, An auxiliary hole transport layer 226a may be further provided between the second hole transport layer 226 and the second red emission layer 227a. The auxiliary hole transport layer 226a may be omitted in some cases.

Meanwhile, in the illustrated example, the first and second red light-emitting layers 223a and 227a may emit phosphorescent light, and the first and second green light-emitting layers 223b and 227b and the first and second blue light-emitting layers 223a and 223b may emit light. This fluorescence can be emitted. However, this is an example, and in addition to red, green or blue may also be formed as a phosphorescent light emitting layer.

However, in such a structure in which the color light emitting layer is divided into sub-pixels of each color, in order to form each color light emitting layer, a color light emitting layer deposition process must be performed using a fine metal mask having an opening corresponding to the light emitting part of a predetermined sub-pixel. do. In this case, in the process of using the fine metal mask for forming the color light emitting layer, the foreign material FR of the chamber or the fine metal mask may be transferred to the spacer 190 on the substrate 100, and the present specification describes such foreign material FR Even if the conductive ions generated during the process of having the steep slope of the side are penetrated, they are captured by the spacer 190 and the lower metal pattern 185 to prevent the effect of the conductive ions.

On the other hand, the second electrode 230 may further include a capping layer 235 thereon to protect the light emitting element OLED and to enhance a light extraction effect. The capping layer 235 may be formed by stacking an organic capping layer 235a and an inorganic capping layer 235b in order to enhance a light extraction effect due to a difference in refractive index.

An encapsulation layer 300 including an inorganic encapsulation layer 310 and an organic encapsulation layer 320 is applied on the capping layer 235 .

8 is a plan view illustrating a light emitting display device according to another exemplary embodiment of the present specification.

8 is a light emitting display device according to another exemplary embodiment of the present specification, and includes spacers 490 between stripe-shaped light emitting units EM1, EM2, EM3, and EM4 and a metal pattern 485 corresponding to the spacers 490. will be equipped with Applying a positive power voltage by connecting the metal pattern 485 to the power voltage line VDL is as described above.

As shown in FIG. 8 , the light emitting units EM1 , EM2 , EM3 , and EM4 may further include, for example, a white light emitting unit in addition to a red light emitting unit, a green light emitting unit, and a blue light emitting unit.

In addition, a spacer 490 is provided between the light emitting units emitting different colors, a metal pattern 485 is provided below the spacer 490, and spaced apart from the spacer 490, each light emitting unit EM1, EM2, A first electrode 410 of a light emitting device provided to cover EM3 and EM4 may be formed. For example, when the light emitting layer includes a phosphorescent dopant, it is particularly vulnerable to conductive ions, and when conductive ions are introduced into the light emitting device, deterioration due to this and defects such as black spots may occur. The light emitting display device of the present specification may prevent conductive ions from flowing into the light emitting device and ensure the stability of the internal stack 230 by trapping the conductive ions in the metal pattern and its lower side with a strong electric field in the metal pattern.

Areas other than the light emitting parts EM1 , EM2 , EM3 , and EM4 are non-light emitting parts, and the banks 480 are provided in the non-emitting parts. A metal pattern 485 is provided between the bank 480 and the spacer 490 . The lower vertical structure of the metal pattern 485 is described in FIG. 3 .

The light emitting display device of the present specification includes a metal pattern between a spacer and a bank, the metal pattern has a contact hole penetrating an insulating film, the contact hole is connected to a passing lower power supply voltage line, and a positive power source is formed by the metal pattern By applying a voltage, conductive ions remaining in the light emitting display device may be captured by the metal pattern, defects due to conductivity may be prevented, and reliability of the device may be improved.

To this end, a light emitting display device according to an embodiment of the present specification includes a substrate having a plurality of sub-pixels, a scan line in a first direction on the substrate, a data line in a second direction crossing the first direction, and a power supply. a voltage line, a planarization layer covering the scan line, the data line, and the power supply voltage line on the substrate, a bank exposing a light emitting unit of each of a plurality of sub-pixels on the planarization layer, and a portion of the bank and a metal pattern provided between the spacer and the bank and connected to the power voltage line through a first contact hole passing through the planarization layer and the bank.

Each of the sub-pixels includes a light emitting element, and the light emitting element comprises: a first electrode between the planarization layer and the bank in the light emitting part and an edge overlapping the bank, and an upper part of the first electrode of the light emitting part. and an organic layer provided on the side of the bank and a second electrode provided on the organic layer.

A positive power supply voltage may be applied to the power supply voltage line.

The power voltage line may receive a higher positive power voltage than the voltage applied to the first electrode.

The metal pattern may be provided on an upper surface of the bank and may have a width smaller than that of the spacer.

The planarization layer covers a plurality of thin film transistors connected to at least one of the scan line, the data line, and the power supply voltage line, and at least one of the plurality of thin film transistors is provided on the planarization layer of each sub-pixel. It may be connected to the first electrode through a contact hole.

The first electrode provided in each of the sub-pixels may be spaced apart from the spacer in a plane.

The spacer may be provided between light emitting units emitting different colors.

The spacer may overlap the power voltage line.

The data line and the base power line may be spaced apart from the power supply line and provided in parallel, and may overlap the spacer.

The organic layer may include a light emitting layer, a first common layer between the first electrode and the light emitting layer, and a second common layer between the light emitting layer and the second electrode.

In addition, the organic layer may include a plurality of light emitting layers, and may further include a common layer between the plurality of light emitting layers.

The first and second common layers and the common layer may be continuous in the sub-pixels.

Alternatively, at least one of the light emitting layer between the first electrode and the second electrode, the first common layer, and the second common layer may be continuous in the plurality of sub-pixels.

On the other hand, the present specification described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible within a range that does not depart from the technical spirit of the present specification. It will be clear to those skilled in the art.

100: substrate 120: active layer
121: first scan line 122a, 122b: second scan line
123: emission control line 161: power voltage line
162 base voltage line 163 data line
180: bank 185: metal pattern
190: spacer 200, OLED: light emitting element
210: first electrode 220: inner stack
230: second electrode 300: light emitting structure
310, 330: inorganic encapsulation layer 320: organic encapsulation layer
FR: foreign body 164: reference line

Claims (14)

a substrate having a plurality of sub-pixels;
a scan line in a first direction on the substrate, a data line and a power supply voltage line in a second direction crossing the first direction;
a planarization layer covering the scan line, the data line, and the power voltage line on the substrate;
a bank exposing a light emitting part of each of the plurality of sub-pixels on the planarization layer;
a spacer provided on a portion of the bank; and
and a metal pattern disposed between the spacer and the bank and connected to the power voltage line. According to claim 1,
The metal pattern is connected to the power voltage line through a first contact hole penetrating the planarization layer and the bank. According to claim 1,
A light emitting element is provided in each of the sub-pixels,
The light emitting element,
a first electrode between the planarization layer and the bank in the light emitting unit, the first electrode having an edge overlapping the bank;
an organic layer provided on an upper portion of the first electrode of the light emitting unit and a side portion of the bank; and
A light emitting display device including a second electrode provided on the organic layer. According to claim 1,
The light emitting display device of claim 1 , wherein a positive power supply voltage is applied to the power supply voltage line. According to claim 3,
The power voltage line receives a positive power voltage higher than the voltage applied to the first electrode. According to claim 1,
The metal pattern is provided on an upper surface of the bank and has a width smaller than that of the spacer. According to claim 3,
The planarization layer covers a plurality of thin film transistors connected to at least one of the scan line, the data line, and the power supply voltage line;
At least one of the plurality of thin film transistors is connected to the first electrode of each sub-pixel through a second contact hole provided in the planarization layer. According to claim 1,
The first electrode provided in each of the sub-pixels is spaced apart from the spacer in a planar manner. According to claim 1,
The spacer is provided between light emitting units emitting different colors. According to claim 1,
The spacer overlaps the power voltage line. According to claim 1,
The data line and the base power line are provided in parallel and spaced apart from the power voltage line, and overlap with the spacer. According to claim 3,
The organic layer includes a light emitting layer, a first common layer between the first electrode and the light emitting layer, and a second common layer between the light emitting layer and the second electrode. According to claim 12,
The organic layer includes a plurality of light emitting layers, and a common layer is further provided between the plurality of light emitting layers. According to claim 12,
At least one of the light emitting layer between the first electrode and the second electrode, the first common layer, and the second common layer is continuous in the plurality of sub-pixels.

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