KR20230102307A - Display device - Google Patents

Abstract

A display device according to an exemplary embodiment of the present invention includes a substrate on which a plurality of sub-pixels are defined, and a plurality of data wires connected to the plurality of sub-pixels, wherein each of the plurality of sub-pixels includes a driving gate electrode and a driving source electrode. and a driving transistor including a driving drain electrode, a first transistor including a first drain electrode connected to the driving gate electrode, and a second transistor including a second source electrode connected to a plurality of data lines, wherein the first drain The electrode is spaced apart from a peripheral area of the second source electrode. Therefore, by disposing the first drain electrode away from the second source electrode, it is possible to minimize voltage fluctuations of the first drain electrode and the driving gate electrode connected to the first drain electrode due to the voltage output from the data line.

Description

Display device {DISPLAY DEVICE}

The present invention relates to a display device, and more particularly, to a display device with reduced flicker during low-speed driving.

Display devices used in computer monitors, TVs, mobile phones, etc. include Organic Light Emitting Displays (OLEDs) that emit light by themselves, and Liquid Crystal Displays (LCDs) that require a separate light source. there is.

The range of applications of display devices is diversifying from computer monitors and TVs to personal portable devices, and research into display devices having a reduced volume and weight while having a large display area is being conducted.

Meanwhile, the display device may be driven in various ways to reduce power consumption. One of them is a method of varying the driving frequency of the display device at high speed or low speed according to the type of displayed image.

An object of the present invention is to provide a display device capable of stably compensating luminance while reducing power consumption through low-speed driving.

Another object to be solved by the present invention is to provide a display device in which fluctuations in a voltage of a gate electrode of a driving transistor are minimized during low-speed driving.

Another object to be solved by the present invention is to provide a display device in which parasitic capacitance between a gate electrode of a driving transistor and a data line is reduced.

Another object to be solved by the present invention is to provide a display device in which flicker is minimized by stably maintaining a voltage of a gate electrode of a driving transistor.

The tasks of the present invention are not limited to the tasks mentioned above, and other tasks not mentioned will be clearly understood by those skilled in the art from the following description.

In order to solve the above problems, a display device according to an exemplary embodiment of the present invention includes a substrate on which a plurality of sub-pixels are defined, and a plurality of data lines connected to the plurality of sub-pixels, each of the plurality of sub-pixels. Silver, a driving transistor including a driving gate electrode, a driving source electrode and a driving drain electrode, a first transistor including a first drain electrode connected to the driving gate electrode, and a second source electrode including a plurality of data lines. It includes two transistors, and the first drain electrode is disposed spaced apart from a peripheral area of the second source electrode. Therefore, by disposing the first drain electrode away from the second source electrode, it is possible to minimize voltage fluctuations of the first drain electrode and the driving gate electrode connected to the first drain electrode due to the voltage output from the data line.

Other embodiment specifics are included in the detailed description and drawings.

According to the present invention, power consumption of the display device may be reduced by driving the display device at a low speed.

The present invention can minimize luminance fluctuation when the display device is driven at a low speed.

The present invention can reduce parasitic capacitance between the gate electrode of the driving transistor and the data line.

According to the present invention, the voltage of the gate electrode of the driving transistor can be stably maintained to minimize luminance fluctuation.

Effects according to the present invention are not limited by the contents exemplified above, and more various effects are included in the present invention.

1 is a schematic configuration diagram of a display device according to an exemplary embodiment of the present invention.
2 is a circuit diagram of a sub-pixel of a display device according to an exemplary embodiment of the present invention.
3 is a driving timing diagram of sub-pixels of a display device according to an exemplary embodiment of the present invention.
4 is a plan view of a sub-pixel of a display device according to an exemplary embodiment of the present invention.
5 is a cross-sectional view taken along V-V′ of FIG. 4;
6 is a plan view of a sub-pixel of a display device according to a comparative example.
FIG. 7 is a cross-sectional view along line VII-VII' of FIG. 6;

The advantages and features of the present invention, and how to achieve them, will become clear with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different shapes, only these embodiments make the disclosure of the present invention complete, and common knowledge in the art to which the present invention pertains. It is provided to completely inform the person who has the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, areas, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are illustrative, and the present invention is not limited thereto. Like reference numbers designate like elements throughout the specification. In addition, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted. When 'includes', 'has', 'consists', etc. mentioned in the present invention is used, other parts may be added unless 'only' is used. In the case where a component is expressed in the singular, the case including the plural is included unless otherwise explicitly stated.

In interpreting the components, even if there is no separate explicit description, it is interpreted as including the error range.

In the case of a description of a positional relationship, for example, 'on top of', 'on top of', 'at the bottom of', 'next to', etc. Or, unless 'directly' is used, one or more other parts may be located between the two parts.

When an element or layer is referred to as “on” another element or layer, it includes all cases where another element or layer is directly on top of another element or another layer or other element intervenes therebetween.

In addition, although first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component mentioned below may also be the second component within the technical spirit of the present invention.

Like reference numbers designate like elements throughout the specification.

The area and thickness of each component shown in the drawings is shown for convenience of description, and the present invention is not necessarily limited to the area and thickness of the illustrated component.

Each feature of the various embodiments of the present invention can be partially or entirely combined or combined with each other, technically various interlocking and driving are possible, and each embodiment can be implemented independently of each other or can be implemented together in a related relationship. may be

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic configuration diagram of a display device according to an exemplary embodiment of the present invention. In FIG. 1 , only the substrate 110 and the plurality of sub-pixels SP among various components of the display device 100 are illustrated for convenience of description.

The substrate 110 is configured to support various components included in the display device 100 and may be made of an insulating material. For example, the substrate 110 may be made of glass or resin. In addition, the substrate 110 may be made of a polymer or plastic, or may be made of a material having flexibility.

The substrate 110 includes a display area AA and a non-display area NA.

The display area AA is an area where a plurality of sub-pixels SP are disposed to display an image. A light emitting element and a driving circuit for driving the light emitting element may be disposed in each of the plurality of sub-pixels SP of the display area AA. The light emitting device may vary according to the type of display device 100 . For example, when the display device 100 is an organic light emitting display device, the light emitting element may be an organic light emitting element including an anode, an organic layer, and a cathode. In addition to this, a micro LED (light-emitting diode), a quantum dot light-emitting diode (QLED) including a quantum dot (QD), or the like may be further used as a light emitting device.

The non-display area NA is an area in which an image is not displayed, and is an area where various wires, driving ICs, etc. for driving the sub-pixels SP disposed in the display area AA are disposed. For example, various ICs such as a gate driver IC and a data driver IC and driving circuits may be disposed in the non-display area NA. Meanwhile, the non-display area NA may be located on the rear surface of the substrate 110, that is, the surface without the sub-pixel SP, or may be omitted, and is not limited to what is shown in the drawings.

A plurality of sub-pixels SP are defined in the display area AA of the substrate 110 . Each of the plurality of sub-pixels SP is an individual unit emitting light, and a light emitting element and a driving circuit are formed in each of the plurality of sub-pixels SP. For example, the plurality of sub-pixels SP may include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and/or a white sub-pixel, but are not limited thereto.

Hereinafter, the plurality of sub-pixels SP will be described in more detail with reference to FIGS. 2 and 3 .

2 is a circuit diagram of a sub-pixel of a display device according to an exemplary embodiment of the present invention. 3 is a driving timing diagram of sub-pixels of a display device according to an exemplary embodiment of the present invention. 2 is a circuit diagram of a sub-pixel SP disposed in an n-th row among a plurality of sub-pixels SP.

Referring to FIG. 2 , each of the plurality of sub-pixels SP includes a first transistor T1 , a second transistor T2 , a third transistor T3 , a fourth transistor T4 , a fifth transistor T5 , It includes a sixth transistor T6, a driving transistor DT, a storage capacitor Cst, and a light emitting element EL. Each of the plurality of sub-pixels SP includes a plurality of scan lines SL1, SL2, and SL3, a data line DL, an emission control signal line EML, an initialization line IL, an anode reset line ARL, and It is connected to the upper power line (VDD) and the low potential power line (VSS).

The plurality of transistors of the plurality of sub-pixels SP may be formed of different types of transistors. For example, one of the plurality of transistors may be a transistor using an oxide semiconductor as an active layer. Oxide semiconductor materials have a low off-current, so they are suitable for switching transistors that maintain a short turn-on time and a long turn-off time.

For another example, another one of the plurality of transistors may be a transistor having low temperature poly-silicon (LTPS) as an active layer. Since the polysilicon material has high mobility, low power consumption, and excellent reliability, it may be suitable for the driving transistor DT.

Meanwhile, the plurality of transistors may be N-type transistors or P-type transistors. Since electrons are carriers in the N-type transistor, electrons can flow from the source electrode to the drain electrode, and current can flow from the drain electrode to the source electrode. Since holes are carriers in the P-type transistor, holes can flow from the source electrode to the drain electrode, and current can flow from the source electrode to the drain electrode. For example, one transistor among the plurality of transistors may be an N-type transistor, and another transistor among the plurality of transistors may be a P-type transistor.

For example, the first transistor T1 may be an N-type transistor and include an oxide semiconductor as an active layer. The driving transistor DT, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are P-type transistors and low-temperature polysilicon. It may be a transistor serving as an active layer. However, the material constituting the active layer of the plurality of transistors and the type of the plurality of transistors are examples, and are not limited thereto.

The first transistor T1 includes a first gate electrode GE1, a first drain electrode DE1, and a first source electrode SE1. The first gate electrode GE1 is connected to the first scan line SL1 in the nth row, the first drain electrode DE1 is connected to the second node N2, and the first source electrode SE1 is connected to the second node N2. It is connected to node 3 (N3). The first transistor T1 is turned on by the first scan signal SCAN1(n) to electrically connect the second node N2 and the third node N3. In this case, since the first transistor T1 is implemented as an oxide semiconductor transistor having a low off-state current, leakage of current from the driving gate electrode GED of the driving transistor DT can be minimized.

The second transistor T2 includes a second gate electrode GE2, a second source electrode SE2, and a second drain electrode DE2. The second gate electrode GE2 is connected to the second scan line SL2 in the n-th row, the second source electrode SE2 is connected to the data line DL, and the second drain electrode DE2 is connected to the first It is connected to node N1. The second transistor T2 is turned on by the second scan signal SCAN2(n) to transfer the data voltage Vdata from the data line DL to the first node N1.

The third transistor T3 includes a third gate electrode GE3, a third source electrode SE3, and a third drain electrode DE3. The third gate electrode GE3 is connected to the emission control signal line EML in the nth row, and the third source electrode SE3 and the third drain electrode DE3 are connected to the high potential power line VDD and the first node. (N1) is connected between them. The third transistor T3 may be turned on by the emission control signal EM(n) to transfer the high-potential power supply voltage to the first node N1.

The fourth transistor T4 includes a fourth gate electrode GE4, a fourth source electrode SE4, and a fourth drain electrode DE4. The fourth gate electrode GE4 is connected to the emission control signal line EML in the n-th row, and the fourth source electrode SE4 and the fourth drain electrode DE4 are connected to the third node N3 and the fourth node ( N4) is connected between them. The fourth transistor T4 may be turned on by the emission control signal EM(n) to transfer the driving current from the driving transistor DT to the light emitting element EL.

The fifth transistor T5 includes a fifth gate electrode GE5, a fifth source electrode SE5, and a fifth drain electrode DE5. The fifth gate electrode GE5 is connected to the third scan line SL3 in the n-th row, and the fifth source electrode SE5 and the fifth drain electrode DE5 are connected to the initialization line IL and the third node N3. ) are connected between The fifth transistor T5 may be turned on by the third scan signal SCAN3(n) to transfer the initialization voltage Vini(n) to the third node N3.

The sixth transistor T6 includes a sixth gate electrode GE6, a sixth source electrode SE6, and a sixth drain electrode DE6. The sixth gate electrode GE6 is connected to the third scan line SL3 in the n+1th row, and the sixth source electrode SE6 and the sixth drain electrode DE6 are connected to the anode reset line ARL and the fourth scan line SL3. It is connected between nodes N4. The sixth transistor T6 may be turned on by the third scan signal SCAN3(n+1) to transfer the anode reset voltage VAR to the fourth node N4.

The driving transistor DT includes a driving gate electrode GED, a driving source electrode SED, and a driving drain electrode DED. The driving gate electrode GED is connected to the second node N2, the driving source electrode SED is connected to the first node N1, and the driving drain electrode DED is connected to the third node N3. . The driving transistor DT may supply a driving current to the light emitting element EL.

The storage capacitor Cst includes a plurality of capacitor electrodes. Some of the plurality of capacitor electrodes are connected to the high potential power line VDD, and others are connected to the second node N2. A voltage of the driving gate electrode GED of the driving transistor DT may be stored in the storage capacitor Cst.

The light emitting element EL includes an anode and a cathode. The anode of the light emitting element EL is connected to the fourth node N4, and the cathode is connected to the low potential power line VSS to which the low potential power voltage is supplied. The light emitting element EL may emit light by a driving current from the driving transistor DT.

Meanwhile, the display device 100 according to an embodiment of the present invention may be driven in a frame skip method. Specifically, in order to reduce the power consumption of the display device 100, an image may be output at a low speed for a still image or the like. The frame skipping method is one of the low-speed driving methods. When driving in the frame skipping method, the data voltage Vdata may not be input to the pixel circuit in some frames. For example, the frame skipping method may include a refresh frame inputting the data voltage Vdata and a reset frame skipping without inputting the data voltage Vdata. By adding a reset frame between refresh frames in which the data voltage Vdata is written, the writing cycle of the data voltage Vdata can be controlled to be long, and power consumption can be reduced. Also, in the reset frame, since the data voltage Vdata input in the previous refresh frame is maintained until the next refresh frame, some components of the display device 100 may not be driven and power consumption may be reduced. .

Specifically, referring to FIG. 3 , the data voltage Vdata may be output to the data line DL during the refresh frame. In this case, in order to perform a sampling operation of inputting the data voltage Vdata to the sub-pixel SP, the second transistor T2 connected to the data line DL may be turned on. Therefore, during the refresh frame, the data voltage Vdata is output to the data line DL, and the second transistor T2 is turned on to transmit the data voltage Vdata to the first node N1 and the driving source electrode. (SED).

During the reset frame, a parking voltage Vpark may be output to the data line DL. The parking voltage Vpark output to the data line DL may be maintained at a specific level until the next refresh frame. That is, during the reset frame, the data voltages Vdata of the data line DL may be parked at a predetermined voltage level to reduce power consumption. In this case, the data voltage Vdata of the data line DL is an AC voltage in the refresh frame, but in the reset frame, the parking voltage Vpark may be a DC voltage at a constant level to reduce power consumption.

Also, during the reset frame, the second transistor T2 connected to the data line DL may be turned off so that the parking voltage Vpark is not input to the sub-pixel SP and sampled. The second transistor T2 may remain turned off during the reset frame in which the parking voltage Vpark is output. Therefore, the parking voltage Vpark applied to the second source electrode SE2 is not transferred to the second drain electrode DE2.

Also, the voltage of the second node N2 during the reset frame, that is, the voltage of the driving gate electrode GED and the first drain electrode DE1 of the driving transistor DT is determined by the data voltage Vdata in the previous refresh frame. The set voltage can be continuously maintained. For example, the voltage of the second node N2 may be set based on the data voltage Vdata input during the refresh frame and the threshold voltage of the driving transistor DT.

Meanwhile, during the reset frame, the parking voltage Vpark output to the data line DL is not input into the sub-pixel SP, but may form parasitic capacitance with other components of the sub-pixel SP. For example, parasitic capacitance due to the parking voltage Vpark may be formed between the data line DL and the second node N2. If parasitic capacitance is formed between the data line DL from which the parking voltage Vpark is output and the second node N2, the voltage of the second node N2 and the driving gate electrode GED of the driving transistor DT ) may fluctuate, causing flicker. In particular, in the reset frame, the luminance set in the previous refresh frame should be maintained, but if the voltage of the second node N2 is changed due to the parasitic capacitance, the luminance cannot be maintained and flicker may be intensified.

Therefore, in the display device 100 according to an exemplary embodiment of the present invention, the first drain electrode connected to the data line DL to which the parking voltage Vpark is transmitted, the second source electrode SE2, and the second node N2. Parasitic capacitance may be minimized by separating DE1 and the driving gate electrode GED from each other.

Hereinafter, the structure of the sub-pixel SP of the display device 100 according to an exemplary embodiment of the present invention will be described with reference to FIGS. 4 and 5 .

4 is a plan view of a sub-pixel of a display device according to an exemplary embodiment of the present invention. 5 is a cross-sectional view taken along V-V′ of FIG. 4; In FIG. 4 , for convenience of explanation, the light emitting element EL is omitted, and the area PA around the second source electrode SE2 is shown as a thick solid line.

Referring to FIG. 4 , a buffer layer 111 is disposed on a substrate 110 . The buffer layer 111 may reduce penetration of moisture or impurities through the substrate 110 . The buffer layer 111 may include, for example, a single layer or a multi-layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. However, the buffer layer 111 may be omitted depending on the type of substrate 110 or the type of thin film transistor, but is not limited thereto.

A first transistor T1 including a first active layer ACT1 , a first gate electrode GE1 , a first drain electrode DE1 , and a first source electrode SE1 is disposed on the buffer layer 111 .

A first gate insulating layer 112a and a first interlayer insulating layer 113 are disposed on the buffer layer 111 , and a first lower gate electrode of the first gate electrode GE1 is disposed on the first interlayer insulating layer 113 . (GE1a) is placed.

The first gate insulating layer 112a is a layer for insulating an active layer and a gate electrode of another transistor, for example, a driving active layer ACTD and a driving gate electrode GED. The first gate insulating layer 112a may be formed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

The first interlayer insulating layer 113 is an insulating layer for protecting the lower components and insulating each component from other components, and may be composed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx). Not limited.

A first lower gate electrode GE1a of the first gate electrode GE1 is disposed on the first interlayer insulating layer 113 . The first lower gate electrode GE1a may be integrally formed with the first lower scan wire SL1a of the first scan wire SL1. The first lower gate electrode GE1a is formed of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. It may consist of, but is not limited thereto.

A second interlayer insulating layer 114 is disposed on the first lower gate electrode GE1a, and a first active layer ACT1 is disposed on the second interlayer insulating layer 114.

The second interlayer insulating layer 114 is an insulating layer for protecting the lower components and insulating each component from other components, and may be composed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx). Not limited.

The first active layer ACT1 may be made of an oxide semiconductor material, but is not limited thereto.

A second gate insulating layer 112b is disposed on the first active layer ACT1, and a first upper gate electrode GE1b of the first gate electrode GE1 is disposed on the second gate insulating layer 112b. . The first upper gate electrode GE1b may be integrally formed with the first upper scan wire SL1b of the first scan wire SL1. The first upper gate electrode GE1b may be disposed to overlap the first active layer ACT1 with the second gate insulating layer 112b interposed therebetween.

5 illustrates that the second gate insulating layer 112b is disposed only under the first upper gate electrode GE1b, the second gate insulating layer 112b may be formed on the entire surface of the substrate 110, but is limited thereto. It doesn't work.

The first gate electrode GE1 may have a dual gate structure including a first upper gate electrode GE1b and a first lower gate electrode GE1a disposed with the first active layer ACT1 interposed therebetween. However, the first gate electrode GE1 may include only one of the first upper gate electrode GE1b and the first lower gate electrode GE1a, but is not limited thereto.

A third interlayer insulating layer 115 is disposed on the first gate electrode GE1 , and a first drain electrode DE1 and a first source electrode SE1 are disposed on the third interlayer insulating layer 115 .

The third interlayer insulating layer 115 is an insulating layer for protecting the lower components and insulating each component from other components, and may be composed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx). Not limited.

The first drain electrode DE1 and the first source electrode SE1 are electrically connected to the first active layer ACT1 through a contact hole formed in the third interlayer insulating layer 115 . Also, the first drain electrode DE1 may extend toward the driving gate electrode GED and be electrically connected to the driving gate electrode GED through contact holes formed in the plurality of insulating layers. The first source electrode SE1 may be integrated with the driving drain electrode DED of the driving transistor DT and electrically connected to the driving drain electrode DED. The first drain electrode DE1 and the first source electrode SE1 are formed of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium ( Cr) or an alloy thereof, but is not limited thereto.

A second transistor T2 including a second active layer ACT2 , a second gate electrode GE2 , a second source electrode SE2 and a second drain electrode DE2 is disposed on the buffer layer 111 .

A second active layer ACT2 is disposed on the buffer layer 111 . The second active layer ACT2 may be made of low temperature poly-silicon (LTPS), but is not limited thereto.

A first gate insulating layer 112a is disposed on the second active layer ACT2, and a second gate electrode GE2 is disposed on the first gate insulating layer 112a. The second gate electrode GE2 may be integrally formed with the second scan line SL2. The second gate electrode GE2 is made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. It may be configured, but is not limited thereto.

A first interlayer insulating layer 113 , a second interlayer insulating layer 114 , and a third interlayer insulating layer 115 are disposed on the second gate electrode GE2 , and a first interlayer insulating layer 115 is disposed on the second gate electrode GE2 . 2 source electrodes SE2 are disposed. The second source electrode SE2 may be electrically connected to the data line DL. In this case, the planarization layer 116 may be disposed on the second source electrode SE2, the data line DL may be disposed on the planarization layer 116, and the second source electrode SE2 may be disposed on the planarization layer ( 116), it may be electrically connected to the data line DL through a contact hole formed thereon. The second source electrode SE2 is made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. It may be configured, but is not limited thereto.

A second drain electrode DE2 is disposed on the buffer layer 111 . The second drain electrode DE2 may be integrally formed with the second active layer ACT2 and electrically connected to the driving source electrode SED. However, the second drain electrode DE2 may be formed of the same material on the same layer as the second source electrode SE2, but is not limited thereto.

A third transistor T3 including a third active layer ACT3, a third gate electrode GE3, a third source electrode SE3 and a third drain electrode DE3 is disposed on the buffer layer 111.

A third active layer ACT3 is disposed on the buffer layer 111 . The third active layer ACT3 may be made of low temperature poly-silicon (LTPS), but is not limited thereto.

A first gate insulating layer 112a is disposed on the third active layer ACT3, and a third gate electrode GE3 is disposed on the first gate insulating layer 112a. The third gate electrode GE3 may be integrally formed with the emission control signal line EML. The third gate electrode GE3 is made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. It may be configured, but is not limited thereto.

A first interlayer insulating layer 113 , a second interlayer insulating layer 114 , and a third interlayer insulating layer 115 are disposed on the third gate electrode GE3 , and a first interlayer insulating layer 115 is disposed on the third gate electrode GE3 . 3 source electrodes SE3 are disposed. The third source electrode SE3 is electrically connected to the high potential power line VDD through the second capacitor electrode C2 of the storage capacitor Cst.

A third drain electrode DE3 is disposed on the buffer layer 111 . The third drain electrode DE3 is integral with the third active layer ACT3 and may be electrically connected to the second drain electrode DE2 and the driving source electrode SED. However, the third drain electrode DE3 may be formed of the same material on the same layer as the third source electrode SE3, but is not limited thereto.

A fourth transistor T4 including a fourth active layer ACT4 , a fourth gate electrode GE4 , a fourth source electrode SE4 and a fourth drain electrode DE4 is disposed on the buffer layer 111 .

A fourth active layer ACT4 is disposed on the buffer layer 111 . The fourth active layer ACT4 may be made of low temperature poly-silicon (LTPS), but is not limited thereto.

A first gate insulating layer 112a is disposed on the fourth active layer ACT4, and a fourth gate electrode GE4 is disposed on the first gate insulating layer 112a. The fourth gate electrode GE4 may be integrally formed with the emission control signal line EML. The fourth gate electrode GE4 is made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. It may be configured, but is not limited thereto.

A first interlayer insulating layer 113 , a second interlayer insulating layer 114 , and a third interlayer insulating layer 115 are disposed on the fourth gate electrode GE4 , and a first interlayer insulating layer 115 is disposed on the third interlayer insulating layer 115 . Four source electrodes SE4 and a fourth drain electrode DE4 are disposed. The fourth source electrode SE4 is integrally formed with the driving drain electrode DED, and the fourth drain electrode DE4 may be electrically connected to the light emitting element EL. The fourth source electrode SE4 and the fourth drain electrode DE4 are formed of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium ( Cr) or an alloy thereof, but is not limited thereto.

A fifth transistor T5 including a fifth active layer ACT5 , a fifth gate electrode GE5 , a fifth source electrode SE5 and a fifth drain electrode DE5 is disposed on the buffer layer 111 .

A fifth active layer ACT5 is disposed on the buffer layer 111 . The fifth active layer ACT5 may be made of low temperature poly-silicon (LTPS), but is not limited thereto.

A first gate insulating layer 112a is disposed on the fifth active layer ACT5, and a fifth gate electrode GE5 is disposed on the first gate insulating layer 112a. The fifth gate electrode GE5 may be integrally formed with the third scan line SL3. The fifth gate electrode GE5 is made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. It may be configured, but is not limited thereto.

A first interlayer insulating layer 113 , a second interlayer insulating layer 114 , and a third interlayer insulating layer 115 are disposed on the fifth gate electrode GE5 , and a first interlayer insulating layer 115 is disposed on the third interlayer insulating layer 115 . A fifth source electrode SE5 and a fifth drain electrode DE5 are disposed. The fifth source electrode SE5 is formed integrally with the initialization line IL, and the fifth drain electrode DE5 is connected to the first source electrode SE1, the driving drain electrode DED, and the fourth source electrode SE4. can be made integrally. The fifth source electrode SE5 and the fifth drain electrode DE5 are formed of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium ( Cr) or an alloy thereof, but is not limited thereto.

A sixth transistor T6 including a sixth active layer ACT6 , a sixth gate electrode GE6 , a sixth source electrode SE6 and a sixth drain electrode DE6 is disposed on the buffer layer 111 .

A sixth active layer ACT6 is disposed on the buffer layer 111 . The sixth active layer ACT6 may be made of low temperature poly-silicon (LTPS), but is not limited thereto.

A first gate insulating layer 112a is disposed on the sixth active layer ACT6, and a sixth gate electrode GE6 is disposed on the first gate insulating layer 112a. The sixth gate electrode GE6 may be integrally formed with the third scan line SL3. The sixth gate electrode GE6 is formed of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. It may be configured, but is not limited thereto.

A first interlayer insulating layer 113 and a second interlayer insulating layer 114 are disposed on the sixth gate electrode GE6 , and a sixth source electrode SE6 is disposed on the second interlayer insulating layer 114 . . The sixth source electrode SE6 may be integrally formed with the anode reset line ARL. The sixth source electrode SE6 is made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. It may be configured, but is not limited thereto.

A third interlayer insulating layer 115 is disposed on the sixth source electrode SE6 , and a sixth drain electrode DE6 is disposed on the third interlayer insulating layer 115 . The sixth drain electrode DE6 may be integrally formed with the fourth drain electrode DE4. The sixth drain electrode DE6 is made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. It may be configured, but is not limited thereto.

A driving transistor DT including a driving active layer ACTD, a driving gate electrode GED, a driving source electrode SED and a driving drain electrode DED is disposed on the buffer layer 111 .

The driving active layer ACTD of the driving transistor DT is disposed on the buffer layer 111 . The driving active layer ACTD may be made of low temperature poly-silicon (LTPS), but is not limited thereto.

A driving gate electrode GED is disposed on the first gate insulating layer 112a. The driving gate electrode GED may be integrally formed with the first capacitor electrode C1 of the storage capacitor Cst. The driving gate electrode GED is made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. It may be, but is not limited thereto.

A first interlayer insulating layer 113 , a second interlayer insulating layer 114 , and a third interlayer insulating layer 115 are disposed on the driving gate electrode GED. The first interlayer insulating layer 113, the second interlayer insulating layer 114, and the third interlayer insulating layer 115 are insulating layers for protecting the underlying structure and are made of silicon oxide (SiOx) or silicon nitride (SiNx). It may consist of a layer or a multi-layer, but is not limited thereto.

A driving source electrode SED is disposed on the buffer layer 111 and a driving drain electrode DED is disposed on the third interlayer insulating layer 115 . The driving source electrode SED is integrally formed with the driving active layer ACTD and may be electrically connected to the second drain electrode DE2 and the third drain electrode DE3. The driving source electrode SED, the second drain electrode DE2 and the third drain electrode DE3 may be integrally formed and electrically connected to each other.

Also, the driving drain electrode DED may be integrally formed with the first source electrode SE1. The driving drain electrode DED is made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. It may be, but is not limited thereto.

The storage capacitor Cst includes a first capacitor electrode C1 and a second capacitor electrode C2. A first capacitor electrode C1 is disposed on the first gate insulating layer 112a, and a second capacitor electrode C2 is disposed on the first interlayer insulating layer 113. The first capacitor electrode C1 and the second capacitor electrode C2 may be insulated with the first interlayer insulating layer 113 interposed therebetween.

The first capacitor electrode C1 may be integrally formed with the driving gate electrode GED of the driving transistor DT. That is, the first capacitor electrode C1 may function as a driving gate electrode GED.

The second capacitor electrode C2 has one end connected to the high-potential power line VDD disposed on the planarization layer 116 and the other end disposed on the third interlayer insulating layer 115. The third source electrode SE3 ) and electrically connected. At this time, the second capacitor electrode C2 disposed between the first capacitor electrode C1 and the first drain electrode DE1 is the first capacitor electrode C1 and the first drain electrode functioning as the driving gate electrode GED. It includes a hole for electrically connecting (DE1). The first drain electrode DE1 may be electrically connected to the first capacitor electrode C1 under the second capacitor electrode C2 and the driving gate electrode GED through a hole formed in the second capacitor electrode C2.

A planarization layer 116 is disposed on the plurality of transistors and the storage capacitor Cst. The planarization layer 116 may planarize an upper portion of the substrate 110 on which the plurality of transistors and the storage capacitor Cst are disposed, and may protect the plurality of transistors and the storage capacitor Cst. The planarization layer 116 may be composed of a single layer or multiple layers, and may be made of, for example, benzocyclobutene or an acryl-based organic material, but is not limited thereto.

A data line DL and a high potential power line VDD are disposed on the planarization layer 116 . The data line DL extends in a column direction and may be electrically connected to the second source electrode SE2 through a contact hole formed in the planarization layer 116 .

The high potential power line VDD may extend in a column direction. The high potential power line VDD is connected to the second capacitor electrode C2 and the third source electrode ( SE3) can be electrically connected.

Meanwhile, the first drain electrode DE1 electrically connected to the second node N2 may be disposed on the same layer as the second source electrode SE2 connected to the data line DL. The first drain electrode DE1 electrically connected to the driving gate electrode GED may be disposed on the third interlayer insulating layer 115 like the second source electrode SE2 . If parasitic capacitance is formed between the second source electrode SE2 and the first drain electrode DE1 during the reset frame in which the parking voltage Vpark is applied to the data line DL and the second source electrode SE2, driving The voltage of the driving gate electrode GED of the transistor DT is varied, and thus flicker may occur and luminance may vary.

Therefore, in the display device 100 according to an exemplary embodiment of the present invention, the distance between the second source electrode SE2 and the first drain electrode DE1 may be increased by changing the arrangement structure of the first drain electrode DE1. and parasitic capacitance between the first drain electrode DE1 and the second source electrode SE2 may be minimized. For example, the driving gate electrode GED is disposed spaced apart from the area PA surrounding the second source electrode SE2, and most of the first drain electrode DE1 overlaps the driving gate electrode GED. can Accordingly, the first drain electrode DE1 and the driving gate electrode GED may be spaced apart from the peripheral area PA of the second source electrode SE2 .

The area PA around the second source electrode SE2 is an area surrounding the second source electrode SE2 and may be an area within a predetermined radius from the second source electrode SE2. The peripheral area PA may be determined according to an area where parasitic capacitance is formed by the parking voltage Vpark applied to the second source electrode SE2. The location and size of the peripheral area PA may be determined by the area of the second source electrode SE2, the distance between the second source electrode SE2 and another conductive layer, etc., which are variables that determine the parasitic capacitance. For example, since the parasitic capacitance decreases as the distance between the second source electrode SE2 and the other conductive layer increases, an area of a certain radius where the parasitic capacitance is formed at a significant level may be determined as the peripheral area PA. In this case, since the conductive layer disposed outside the peripheral area PA is far from the second source electrode SE2, parasitic capacitance with the second source electrode SE2 is not formed, or even if it is formed, it is insignificant. can be formed Conversely, the conductive layer disposed inside the peripheral area PA may have a close distance to the second source electrode SE2, so parasitic capacitance may be large enough to cause voltage fluctuations.

For another example, as the area and size of the second source electrode SE2 increases, the parasitic capacitance may increase, and the area of the peripheral area PA may also increase.

Therefore, by forming the first drain electrode DE1 and the driving gate electrode GED outside the peripheral area PA, the parasitics between the second source electrode SE2 of the second node N2 and the data line DL Capacitance can be minimized.

However, the location, shape, and size of the peripheral area PA shown in FIG. 4 are examples, and are not limited thereto.

In the area PA around the second source electrode SE2, the first active layer ACT1 is disposed instead of the first drain electrode DE1. Specifically, a first active layer ACT1 and a first drain electrode DE1 may be disposed between the first gate electrode GE1 and the driving gate electrode GED. In this case, if at least a portion of the first gate electrode GE1 overlaps or is disposed adjacent to the peripheral area PA, the area between the first gate electrode GE1 and the driving gate electrode GED is in the peripheral area PA. In the overlapping region, the first active layer ACT1 may be disposed instead of the first drain electrode DE1. In addition, the first drain electrode DE1 may be disposed in a region between the first gate electrode GE1 and the driving gate electrode GED that does not overlap the peripheral region PA.

At this time, even if the first active layer ACT1 is disposed in the area PA surrounding the second source electrode SE2, the first active layer ACT1 and the second source electrode SE2 are formed by the third interlayer insulating layer 115. Since they are disposed on different planes by , a separation distance between the first active layer ACT1 and the second source electrode SE2 can be secured and parasitic capacitance can be reduced.

Hereinafter, the parasitic capacitance reduction effect of the present invention will be described in more detail with reference to the display device 10 according to the comparative example.

6 is a plan view of a sub-pixel of a display device according to a comparative example. FIG. 7 is a cross-sectional view along line VII-VII' of FIG. 6; In FIG. 6 , only portions where the first drain electrode DE1 , the second source electrode SE2 , and the first active layer ACT1 are located are enlarged for convenience of description.

Referring to FIGS. 6 and 7 , the first active layer ACT1 may extend only in the horizontal direction. In this case, one end of the first active layer ACT1 may be disposed on the side of the second source electrode SE2 and inside the peripheral area PA.

A first drain electrode DE1 may be disposed between the first active layer ACT1 and the driving gate electrode GED. One end of the first drain electrode DE1 is one end of the first active layer ACT1 and is disposed inside the area PA around the second source electrode SE2, and the other end of the first drain electrode DE1 is a driving gate. It may be disposed on the electrode GED. Also, the first drain electrode DE1 extends in a column direction and may be disposed parallel to the data line DL.

In the display device 10 according to the comparative example, one end of the first drain electrode DE1 and one end of the second source electrode SE2 may be disposed adjacent to each other. For example, one end of the first drain electrode DE1 is disposed on the area PA surrounding the second source electrode SE2 so that a gap between the first drain electrode DE1 and the second source electrode SE2 is formed. can decrease Accordingly, parasitic capacitance may be formed between the second source electrode SE2 and the first drain electrode DE1 during the reset frame to a level capable of varying the voltage of the second node N2. In particular, since the first drain electrode DE1 and the second source electrode SE2 are disposed on the same plane, parasitic capacitance may be easily generated in a lateral direction. In addition, since the first drain electrode DE1 is disposed parallel to the data line DL, parasitic capacitance may also be formed between the first drain electrode DE1 and the data line DL during the reset frame.

If parasitic capacitance is formed between the first drain electrode DE1 and the second source electrode SE2 and between the first drain electrode DE1 and the data line DL, the first drain electrode DE1 and the first A voltage of the driving gate electrode GED connected to the drain electrode DE1 may vary due to parasitic capacitance. Therefore, in the display device 10 according to the comparative example, the first drain electrode DE1 is disposed inside the area PA surrounding the second source electrode SE2 and adjacent to the data line DL. Parasitic capacitance may be formed between the first drain electrode DE1 and the second source electrode SE2 and between the first drain electrode DE1 and the data line DL. Therefore, during low-speed driving, the voltage of the second node N2 may fluctuate due to the parasitic capacitance between the second node N2 and the data line DL, and flicker and luminance fluctuation may occur.

Therefore, in the display device 100 according to an exemplary embodiment of the present invention, the first drain electrode DE1 connected to the second node N2 is spaced apart from the data line DL and the second source electrode SE2 as much as possible so that the low speed During driving, parasitic capacitance between the second node N2 and the data line DL and voltage fluctuation of the second node N2 may be minimized. The first drain electrode DE1 connected between the driving gate electrode GED and the first active layer ACT1 may be disposed outside the peripheral area PA of the second source electrode SE2. The first drain electrode DE1 that transfers the voltage to the driving gate electrode GED may be disposed outside the area PA surrounding the second source electrode SE2 to minimize parasitic capacitance with the second source electrode SE2. can In addition, in the region between the first gate electrode GE1 and the driving gate electrode GED disposed on the peripheral region PA, the first active layer ACT1 is applied to the peripheral region PA and the first active layer ACT1 instead of the first drain electrode DE1. It may be disposed adjacent to the peripheral area PA. For example, one end of the first active layer ACT1 is disposed to overlap the first gate electrode GE1 in the peripheral area PA, and the other end extends toward the outside of the peripheral area PA to form a first drain electrode ( DE1). The other end of the first active layer ACT1 disposed outside the peripheral area PA and the first drain electrode DE1 may overlap the driving gate electrode GED.

Therefore, while connecting the first drain electrode DE1 to the first active layer ACT1 by connecting the first drain electrode DE1 to the remaining portion of the first active layer ACT1 extending outside the peripheral area PA, The first drain electrode DE1 may be disposed in a location other than the peripheral area PA. In addition, even when the first active layer ACT1 is disposed adjacent to the second source electrode SE2 and the data line DL, the third interlayer insulation is between the first active layer ACT1 and the second source electrode SE2. Since the layer 115 is disposed and the third interlayer insulating layer 115 and the planarization layer 116 are disposed between the first active layer ACT1 and the data line DL, the first active layer ACT1 and the second interlayer insulating layer 115 are disposed. Parasitic capacitance between the two source electrodes SE2 and between the first active layer ACT1 and the data line DL may be minimized.

For example, in the display device 10 according to the comparative example in which the first drain electrode DE1 and the second source electrode SE2 are disposed adjacent to each other, the second node N2 and the second source electrode SE2 and Parasitic capacitance between the data lines DL may be about 0.8 fF, and in the display device 100 according to an exemplary embodiment of the present invention, the second node N2, the second source electrode SE2, and the data line DL Since the parasitic capacitance of the liver is about 0.4 fF, the parasitic capacitance can be reduced by 50% or more. Therefore, in the display device 100 according to an exemplary embodiment of the present invention, the arrangement structure of the first drain electrode DE1 and the first active layer ACT1 is changed to generate a second voltage according to the parking voltage Vpark during low-speed driving. Voltage fluctuations of the node N2 can be minimized, and flicker and luminance fluctuations can be improved.

A display device according to embodiments of the present invention can be described as follows.

A display device according to an exemplary embodiment of the present invention includes a substrate on which a plurality of sub-pixels are defined, and a plurality of data wires connected to the plurality of sub-pixels, wherein each of the plurality of sub-pixels includes a driving gate electrode and a driving source electrode. and a driving transistor including a driving drain electrode, a first transistor including a first drain electrode connected to the driving gate electrode, and a second transistor including a second source electrode connected to a plurality of data lines, wherein the first drain The electrode is spaced apart from a peripheral area of the second source electrode.

According to another feature of the present invention, the area around the second source electrode may be an area within a predetermined radius from the second source electrode.

According to another feature of the present invention, the first transistor further includes a first gate electrode disposed spaced apart from the first drain electrode, and a first active layer connected to the first drain electrode, wherein the first gate electrode is at least A portion may overlap the surrounding area.

According to another feature of the present invention, a first interlayer insulating layer disposed between the substrate and the first active layer, a second interlayer insulating layer disposed between the first interlayer insulating layer and the first active layer, and the first active layer A third interlayer insulating layer disposed thereon may be further included, and the first drain electrode and the second source electrode may be disposed on the third interlayer insulating layer.

According to another feature of the present invention, the driving gate electrode may be disposed outside the peripheral area.

According to another feature of the present invention, the first drain electrode and the first active layer are disposed in an area between the first gate electrode and the driving gate electrode, and overlap with a peripheral area in the area between the first gate electrode and the driving gate electrode. A first active layer may be disposed in the area to be formed.

According to another feature of the present invention, the first drain electrode may be disposed in a region between the first gate electrode and the driving gate electrode that does not overlap with the peripheral region.

According to another feature of the present invention, one end of the first active layer overlaps the peripheral region and the first gate electrode, the other end of the first active layer extends toward the outside of the peripheral region, and the first drain electrode overlaps the peripheral region. It is disposed on the outer side of and may be in contact with the other end of the first active layer.

According to another feature of the present invention, the other end of the first drain electrode and the first active layer may overlap the driving gate electrode.

According to another feature of the present invention, during a refresh frame in which a data voltage is applied to a plurality of data lines, the second transistor is turned on to transfer the data voltage to the driving source electrode, and a parking voltage is applied to the plurality of data lines. During the reset frame, the second transistor may remain turned off.

According to another feature of the present invention, a parking voltage may be applied to the second source electrode during the reset frame, and the driving gate electrode and the first drain electrode may maintain voltages set in a refresh frame prior to the reset frame during the reset frame.

Although the embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and may be variously modified without departing from the technical spirit of the present invention. . Therefore, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but to explain, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The protection scope of the present invention should be construed according to the claims below, and all technical ideas within the equivalent range should be construed as being included in the scope of the present invention.

100: display device
110: substrate
111: buffer layer
112a: first gate insulating layer
112b: second gate insulating layer
113: first interlayer insulating layer
114: second interlayer insulating layer
115: third interlayer insulating layer
116: planarization layer
SP: sub pixel
AA: display area
NA: non-display area
PA: peripheral area
T1: first transistor
ACT1: first active layer
GE1: first gate electrode
SE1: first source electrode
DE1: first drain electrode
T2: second transistor
ACT2: second active layer
GE2: second gate electrode
SE2: second source electrode
DE2: second drain electrode
T3: third transistor
ACT3: third active layer
GE3: third gate electrode
SE3: third source electrode
DE3: third drain electrode
T4: fourth transistor
ACT4: fourth active layer
GE4: fourth gate electrode
SE4: fourth source electrode
DE4: fourth drain electrode
T5: fifth transistor
ACT5: fifth active layer
GE5: fifth gate electrode
SE5: fifth source electrode
DE5: fifth drain electrode
T6: sixth transistor
ACT6: sixth active layer
GE6: sixth gate electrode
SE6: sixth source electrode
DE6: sixth drain electrode
ACTD: driving active layer
GED: driving gate electrode
SED: driving source electrode
DED: driving drain electrode
Cst: storage capacitor
C1: first capacitor electrode
C2: second capacitor electrode
EL: light emitting element
N1: first node
N2: second node
N3: third node
N4: fourth node
SL1: first scan wire
SL2: 2nd scan wire
SL3: third scan wire
DL: data wire
EML: light emission control signal wiring
IL: initialization wire
ARL: anode reset wire
VDD: high potential power wiring
VSS: Low Potential Power Wiring
SCAN1(n): first scan signal
SCAN2(n): second scan signal
SCAN3(n), SCAN3(n+1): 3rd scan signal
Vdata: data voltage
Vpark: Parking voltage
EM(n): emission control signal
Vini(n): initialization voltage
VAR: anode reset voltage

Claims (11)

a substrate on which a plurality of sub-pixels are defined; and
A plurality of data lines connected to the plurality of sub-pixels;
Each of the plurality of sub-pixels,
a driving transistor including a driving gate electrode, a driving source electrode, and a driving drain electrode;
a first transistor including a first drain electrode connected to the driving gate electrode; and
A second transistor including a second source electrode connected to the plurality of data lines;
The first drain electrode is disposed spaced apart from a peripheral area of the second source electrode. According to claim 1,
The area around the second source electrode is an area within a predetermined radius from the second source electrode. According to claim 2,
The first transistor,
a first gate electrode spaced apart from the first drain electrode; and
Further comprising a first active layer connected to the first drain electrode,
At least a portion of the first gate electrode overlaps the peripheral region. According to claim 3,
a first interlayer insulating layer disposed between the substrate and the first active layer;
a second interlayer insulating layer disposed between the first interlayer insulating layer and the first active layer; and
Further comprising a third interlayer insulating layer disposed on the first active layer,
The first drain electrode and the second source electrode are disposed on the third interlayer insulating layer. According to claim 3,
The driving gate electrode is disposed outside the peripheral area. According to claim 3,
the first drain electrode and the first active layer are disposed in a region between the first gate electrode and the driving gate electrode;
The display device of claim 1 , wherein the first active layer is disposed in a region between the first gate electrode and the driving gate electrode and overlapping the peripheral region. According to claim 6,
The display device of claim 1 , wherein the first drain electrode is disposed in a region between the first gate electrode and the driving gate electrode that does not overlap with the peripheral region. According to claim 6,
one end of the first active layer overlaps the peripheral region and the first gate electrode, and the other end of the first active layer extends toward the outside of the peripheral region;
The first drain electrode is disposed outside the peripheral area and contacts the other end of the first active layer. According to claim 8,
The first drain electrode and the other end of the first active layer overlap the driving gate electrode. According to claim 1,
During a refresh frame in which a data voltage is applied to the plurality of data lines, the second transistor is turned on to transmit the data voltage to the driving source electrode;
The display device, wherein the second transistor maintains a turned-off state during a reset frame in which a parking voltage is applied to the plurality of data lines. According to claim 10,
The parking voltage is applied to the second source electrode during the reset frame;
The driving gate electrode and the first drain electrode maintain a voltage set in the refresh frame before the reset frame during the reset frame.

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