KR20230098971A - Nonvolatile memory devices and methods of programming in nonvolatile memory devices - Google Patents

Abstract

A non-volatile memory device according to example embodiments includes at least one memory block and a control circuit. The at least one memory block includes a plurality of cell strings in which a string select transistor, a plurality of memory cells, and a ground select transistor are disposed in series in a vertical direction between a bit line and a source line, and the plurality of cells arranged in the vertical direction is divided into stacks of the plurality of stacks, and each of the plurality of stacks includes at least one dummy word line disposed adjacent to a boundary of the plurality of stacks. The control circuit applies a program voltage to a selected word line of the plurality of cell strings in a program execution period, and at least one of the plurality of stacks disposed vertically above a selected stack to which the selected word line belongs. A program operation is controlled such that a level of a dummy voltage applied to the at least one dummy word line of an upper stack is reduced during the program execution period.

Description

Non-volatile memory device and programming method of non-volatile memory device

The present invention relates to a semiconductor device, and more particularly, to a non-volatile memory device and a method for programming the non-volatile memory device.

Semiconductor memory devices for storing data can be largely classified into volatile memory devices and non-volatile memory devices. In a volatile memory device such as dynamic random access memory (DRAM), in which data is stored by charging or discharging cell capacitors, stored data is maintained while power is applied, but stored data is lost when power is cut off. Meanwhile, the non-volatile memory device may store data even when power is cut off. Volatile memory devices are mainly used as main memories of computers, etc., and non-volatile memory devices are used as large-capacity memories for storing programs and data in a wide range of application devices such as computers and portable communication devices.

Recently, a non-volatile memory device in which memory cells are stacked in three dimensions, such as a vertical NAND flash memory device, has been actively researched to improve the degree of integration of semiconductor memory devices. As memory devices increase in density and capacity, disturbance received by unselected memory cells during a program operation of a nonvolatile memory device increases.

One object of the present invention is to provide a non-volatile memory device capable of reducing path disturb.

One object of the present invention is to provide a method for programming a non-volatile memory device capable of reducing path disturb.

A non-volatile memory device according to example embodiments includes at least one memory block and a control circuit. The at least one memory block includes a plurality of cell strings in which a string select transistor, a plurality of memory cells, and a ground select transistor are disposed in series in a vertical direction between a bit line and a source line, and the plurality of cells arranged in the vertical direction is divided into stacks of the plurality of stacks, and each of the plurality of stacks includes at least one dummy word line disposed adjacent to a boundary of the plurality of stacks. The control circuit applies a program voltage to a selected word line of the plurality of cell strings in a program execution period, and at least one of the plurality of stacks disposed vertically above the selected stack to which the selected word line belongs. A program operation is controlled such that a level of a dummy voltage applied to the at least one dummy word line of an upper stack is reduced during the program execution period.

A method of programming a nonvolatile memory device according to embodiments of the present invention includes a plurality of cell strings in which a string select transistor, a plurality of memory cells, and a ground select transistor are disposed in series in a vertical direction between a bit line and a source line. Divide at least one memory block of a plurality of stacks into a plurality of stacks (each of the plurality of stacks includes at least one dummy word line disposed adjacent to a boundary of the plurality of stacks), and in a program execution section, the plurality of stacks A program voltage is applied to a selected word line of cell strings of , and the at least one dummy word line of at least one upper stack disposed vertically higher than a selected stack to which the selected word line belongs among the plurality of stacks. The level of the dummy voltage applied to is reduced during the program execution period.

A non-volatile memory device according to example embodiments includes at least one memory block and a control circuit. The at least one memory block includes a plurality of cell strings in which a string select transistor, a plurality of memory cells, and a ground select transistor are disposed in series in a vertical direction between a bit line and a source line, and the physical block, and each of the plurality of sub-blocks includes at least one boundary word line adjacent to another sub-block and internal word lines excluding the at least one boundary word line. While applying a program voltage to a selected word line of the plurality of cell strings in a program execution period, the control circuit may include at least one of the plurality of sub-blocks disposed above the selected sub-block to which the selected word line belongs in the vertical direction. A program operation is controlled such that the level of the dummy voltage applied to the at least one boundary word line of one upper sub-block is reduced during the program execution period.

According to embodiments of the present invention, voltages applied to dummy word lines of an upper stack disposed above a selected stack among a plurality of stacks are reduced in a program execution period, and the dummy word lines are connected to the dummy word lines. Path disturbance due to a program voltage and a program pass voltage that can be received from the selected stack can be reduced by turning off the dummy memory cells.

1 is a flowchart illustrating a method of programming a non-volatile memory device according to example embodiments.
2 is a timing diagram illustrating a method of programming a nonvolatile memory device according to example embodiments.
FIG. 3 is a flowchart illustrating in detail a step of decreasing the level of a dummy voltage in the program execution period in the method of FIG. 1 according to embodiments of the present invention, and FIG. 4 is a timing diagram illustrating the method of FIG. 3 .
5 is a block diagram illustrating a configuration of a memory system according to example embodiments.
6 is a block diagram illustrating a nonvolatile memory device in the memory system of FIG. 5 according to example embodiments.
FIG. 7 is a block diagram illustrating an example of a memory cell array in the nonvolatile memory device of FIG. 6 .
8A is a circuit diagram illustrating one of the memory blocks of FIG. 7 .
8B to 8D each show one of the cell strings of FIG. 8A according to embodiments of the present invention.
FIG. 9 is a block diagram illustrating a configuration of a control circuit in the nonvolatile memory device of FIG. 6 according to example embodiments.
10 is a block diagram illustrating a configuration of a voltage generator in the nonvolatile memory device of FIG. 6 according to example embodiments.
11 is a diagram illustrating operation sections included in each of a plurality of program loops.
12 is a diagram illustrating an example of a structure of one cell string according to embodiments of the present invention.
13 is a diagram illustrating an example of a structure of one memory cell included in the cell string of FIG. 12 .
14A is a circuit diagram illustrating a structure of a memory block according to example embodiments, and FIG. 14B is a perspective view illustrating a memory block corresponding to the structure of FIG. 14A.
15 is a cross-sectional view illustrating an example of a boundary layer included in a nonvolatile memory device according to example embodiments.
16 is a diagram illustrating a program operation according to embodiments of the present invention.
FIG. 17 is a timing diagram illustrating an embodiment of a programming method for a first stack according to the program operation of FIG. 16 .
18 is a cross-sectional view illustrating a memory block divided into three stacks according to example embodiments.
FIG. 19 shows an embodiment of a program method for stacks of memory blocks of FIG. 18, and FIG. 20 shows a program execution section in the program method of FIG. 19 in more detail.
FIG. 21 shows an embodiment of a program method for stacks of memory blocks of FIG. 18 , and FIG. 22 shows a program execution section in the program method of FIG. 21 in more detail.
FIG. 23 shows an embodiment of a program method for stacks of memory blocks of FIG. 18 , and FIG. 24 shows a program execution section in the program method of FIG. 23 in more detail.
FIG. 25 shows an embodiment of a program method for stacks of memory blocks of FIG. 18 , and FIG. 26 shows a program execution section in the program method of FIG. 25 in more detail.
27 is a cross-sectional view illustrating a memory block divided into three sub-blocks according to example embodiments.
FIG. 28 illustrates an embodiment of a programming method for sub-blocks of the memory block of FIG. 27 .
FIG. 29 illustrates an embodiment of a programming method for sub-blocks of the memory block of FIG. 27 .
30 schematically shows a non-volatile memory device according to embodiments of the present invention.
31 is a cross-sectional view illustrating a nonvolatile memory device according to example embodiments.
32 is a block diagram illustrating an electronic system including a semiconductor device according to example embodiments.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in more detail. The same reference numerals are used for the same components in the drawings, and redundant descriptions of the same components are omitted.

1 is a flowchart illustrating a method of programming a non-volatile memory device according to example embodiments.

1 , a nonvolatile memory device including at least one memory block including a plurality of cell strings in which a string select transistor, a plurality of memory cells, and a ground select transistor are arranged in series between a bit line and a source line in a vertical direction. The program method of is shown. According to example embodiments, the nonvolatile memory device may include a 3D NAND flash memory device or a vertical NAND flash memory device.

Referring to FIG. 1 , the plurality of cell strings are divided into a plurality of stacks (S110). Each of the plurality of stacks may include at least one dummy word line disposed at or adjacent to a boundary of the plurality of stacks.

Channels of the plurality of cell strings are precharged with a first voltage in the bit line setup period of the program loop (S150).

In general, in a bit line setup period, channels of cell strings may be precharged with a setup voltage of the bit line through string select transistors. However, in order to reduce program disturbance, when memory cells are programmed first as they are located at the top, if at least one memory cell among the programmed memory cells is programmed from the erase state to the program state, the channel of the cell string It can no longer be initialized, that is, precharged through the string select transistor. Therefore, according to embodiments of the present invention, in an operation in which memory cells are programmed first as they are located at the top, the channel of the cell string may be precharged through the ground select transistor.

A 3D NAND flash device is vulnerable to program disturb as the size of a channel hole or a critical dimension (CD) of the hole is small. In the case of MLC (Multi Level Cell), the number of states programmed into one memory cell increases. In this case, the number of program loops increases, and performance degradation due to program disturb increases as the number of program loops increases. Therefore, programming can be performed in a direction in which the size of the channel hole decreases. As such, when programming is performed in a direction in which the size of the channel hole decreases, a bias voltage is applied to the ground selection line and USIP (unselect string initial precharge) is performed using the voltage of the source line.

At least one upper part of the plurality of stacks disposed vertically higher than a selection stack to which the selection word line belongs among the plurality of stacks while applying a program voltage to a selected word line of the plurality of cell strings in a program execution period of the program loop. The level of the dummy voltage applied to the at least one dummy word line of the stack is reduced in the program execution period (S200).

In the program recovery section of the program loop, the selected word line and non-selected word lines of the plurality of cell strings are recovered (S300).

After recovering the selected word lines and the non-selected word lines to the negative voltage, they may be recovered to the second voltage. When the selected word lines and unselected word lines are recovered with a negative voltage and then recovered with a second voltage, after the channel of the cell strings is lowered to the ground voltage level, the voltage before precharge in the verify read period after the program recovery period can be reliably recovered. In this case, it is possible to prevent soft erase that may occur in unselected cell strings and hot carrier injection that may occur in selected cell strings.

2 is a timing diagram illustrating a method of programming a nonvolatile memory device according to example embodiments.

2 illustrates a bit line setup period PBLS, a program execution period PGME, a program recovery period PGMRC, and a verify read period VFRD of one program loop among a plurality of program loops. The viewpoints T1 to T8 indicate the boundary of each section.

Referring to FIG. 2 , during the bit line setup period PBLS, the ground voltage VSS is applied to the string selection line SSL_SEL and the ground selection line GSL_SEL of the selected cell string from the time point T1 to the time point T2. , the first turn-on voltage VON1 is applied from the time point T2 to the time point T4. The ground voltage VSS is applied to the string selection line SSL_UNS and the ground selection line GSL_UNS of the non-selected cell string from time point T1 to time point T2, and from time point T2 to time point T3 1 turn-on voltage VON1 is applied, and voltage VSS is applied from time point T3 to time point T4.

In an embodiment, voltage levels applied to the string selection line SSL_UNS and the ground selection line GSL_UNS of the unselected cell string may vary according to the position of the unselected cell string.

A second voltage V2 having a higher level than the ground voltage is applied to the selected word line WL_SEL and the unselected word line WL_UNS from time T1 to time T4. Accordingly, the channel CH of each of the cell strings is precharged with the first voltage V1 from the ground voltage VSS. That is, by performing unselect string initial precharge (hereinafter referred to as 'USIP'), each channel of the cell strings is precharged with the first voltage V1.

The USIP may be performed using gate induced drain leakage (GIDL). As the name suggests, GIDL is a phenomenon in which leakage occurs in the drain of a transistor by the gate of the transistor. For example, in a state where 0V or a negative voltage level is applied to the gate and a sufficiently high positive voltage level is applied to the drain, an oxide near the drain becomes high in gate energy and low in drain. At this time, too much band bending is applied to the silicon (Si) itself, resulting in tunneling of electrons from the valence band of the silicon surface to the conduction band of the bulk of the silicon. (band-to-band tunneling) takes place.

The tunneled electrons are attracted to the drain electrode, and eventually the drain current increases. At this time, since the substrate is usually biased to ground, the hole is drawn to the side of the substrate that is relatively low compared to the drain. In general, the negative gate voltage means that the transistor is turned off, but the drain current is increased by GIDL so that the transistor operates as if turned on. In this GIDL phenomenon, the GIDL current increases as the gate voltage becomes more negative and the drain voltage becomes more positive.

Channels of each cell string may be precharged using such GIDL. To generate GIDL, a string select transistor of a cell string, a ground select transistor, or a GIDL transistor may be used, which will be described later with reference to FIGS. 8B to 8D.

At the start point T1 of the bit line setup period PBLS, the program inhibit voltage VINH or the program allow voltage VPER may be applied to the bit line BL according to the value of the write data.

During the program execution period PGME from the time point T4 to the time point T5 subsequent to the bit line setup period PBLS, the string selection line SSL_SEL and the ground selection line GSL_SEL of the selected cell string have a first turn -On voltage VON1 is applied, ground voltage VSS is applied to the string selection line SSL_UNS and ground selection line GSL_UNS of the unselected cell string, and program voltage VPGM is applied to the selected word line WL_SEL. is applied, and the program pass voltage VPPASS is applied to the unselected word line WL_UNS. Accordingly, the potential of the channel CH of each of the cell strings rises to the third voltage V3. In the program execution period PGME, the bit line BL maintains the program inhibit voltage VINH or the program allow voltage VPER according to the value of the write data.

During the program recovery period PGMRC from the time point T5 to the time point T7 subsequent to the program execution period PGME, the string selection line SSL_SEL and the ground selection line GSL_SEL of the selected cell string have a first turn- The turn-on voltage VON1 is applied, and a second turn-on voltage VON2 lower than the first turn-on voltage VON1 is applied to the string select line SSL_UNS and the ground select line GSL_UNS of the unselected cell string. this is authorized In addition, after the first negative voltage VNEG1 is applied to the selected word line WL_SEL and the non-selected word line WL_UNS from time T5 to time T6, the second voltage from time T6 to time T7 is applied. (V2) is applied.

That is, the selected word line WL_SEL and the unselected word line WL_UNS are recovered to the first negative voltage VNEG1 and then to the second voltage V2. At this time, the first turn-on voltage VON1 is applied to the string selection line SSL_SEL and the ground selection line GSL_SEL of the selected cell string, and the string selection line SSL_UNS and the ground selection line ( GSL_UNS) is applied with the second turn-on voltage VON2, which is lower than the first turn-on voltage VON1, so that the selected cell string and the non-selected cell string are open. The potential drops to a level near the ground voltage VSS and is maintained. In the program recovery period PGMRC, the voltage of the bit line BL converges to the program allowable voltage VPER.

During the verification read period VFRD from the time point T7 to the time point T8 consecutive to the program recovery period PGMRC, the string selection line SSL_SEL and the ground selection line GSL_SEL of the selected cell string have a verification pass voltage ( VVPASS) is applied, and the ground voltage VSS is applied to the string selection line SSL_UNS and the ground selection line GSL_UNS of the unselected cell string. In addition, the verify read voltage VPV is applied to the selected word line WL_SEL, and the verify pass voltage VVPASS is applied to the unselected word line WL_UNS. Accordingly, the potential of the channel of the selected cell string STR_SEL is maintained at a level near the ground voltage VSS, and the potential of the channel of the unselected cell string STR_UNS rises to the level of the fourth voltage V4. The fourth voltage V4 may be lower than the third voltage V3 and higher than the first voltage V1. Accordingly, it is possible to prevent soft erase that may occur in the unselected cell string STR_UNS and hot carrier injection (HCI) that may occur at the edge of the selected cell string STR_SEL.

Assume that the potential of the channel CH that has not dropped during the program recovery period PGMRC has the same first level as the precharged voltage. When the verification read voltage is applied to the selected word line (WL_SEL) and the verification pass voltage is applied to the unselected word line (WL_UNS) in the verification read period (VFRD), the potential of the channel of the unselected cell string reaches the first level and the verification pass voltage. It has a high level corresponding to the level of the voltage. Accordingly, soft erase may occur in memory cells of the unselected cell string due to a high-level potential of a channel of the unselected cell string. In addition, since the potential of the channel of the selected cell string rapidly changes from the first level to the ground voltage (VSS) level, the leakage current entering the bit line or the common source line rapidly changes due to the potential of the channel that changes rapidly. By injecting HCI into the transistor, the threshold voltage of the string select transistor or the ground select transistor may increase.

Although not shown, the voltages of all bit lines may be initialized to the same precharge voltage during the bit line precharge period before the verification read period VFRD. In the verification read period VFRD, the voltage of the bit line BL is developed as a voltage corresponding to data '1' or '0' according to the threshold voltage state of the selected memory cell. The value of data stored in the selected memory cell may be determined by sensing the voltage development of the bit line BL.

FIG. 3 is a flowchart illustrating in detail a step of decreasing the level of a dummy voltage in the program execution period in the method of FIG. 1 according to embodiments of the present invention, and FIG. 4 is a timing diagram illustrating the method of FIG. 3 .

3 and 4, in order to decrease the level of the dummy voltage in the program execution period (S200), the at least one upper stack ( A first dummy voltage VDUM1 is applied to the at least one dummy word line DWL of ST_UP (S210). During the first sub-period T4 to T41, the program forcing voltage may be applied to the bit line BL, so that the program forcing voltage may reach the channel of the selection stack ST_SEL.

During the second sub-periods T41 to T42 of the program execution period PGME, the first dummy voltage VDUM1 is reduced to the second dummy voltage VDUM2 (S220). The first pass voltage VPASS1 is applied to the word lines WL_UP of the at least one upper stack ST_UP during the first sub-period T4 to T41 and the second sub-period T41 to T42 ( S230).

The second dummy voltage VDUM2 is applied to the at least one dummy word line DWL of the at least one upper stack ST_UP during the third sub-period T42 to T5 of the program execution period PGME2 ( S240). In the third sub-period T42 to T5, a second pass voltage VPASS2 lower than the first pass voltage VPASS1 is applied to the word lines WL_UP of the upper stack ST_UP (S250).

During the program execution period PGME, the program voltage VPGM is applied to the selected word line WL_SEL of the selected stack ST_SEL.

Therefore, in the third subperiod T42 to T5, the dummy memory cells connected to the at least one dummy word line DWL are turned off by applying the second dummy voltage VDUM2 to the at least one dummy word line DWL. Thus, path disturb that the word lines WL_UP of the upper stack ST_UP can receive from the selection stack ST_SEL in the third sub-period T42 to T5 can be blocked.

The first subintervals T4 to T41, the second subintervals T41 to T42, and the third subintervals T42 to T5 may be consecutive.

5 is a block diagram illustrating a configuration of a memory system according to example embodiments.

Referring to FIG. 5 , the memory system 10 may include a memory controller 50 and at least one nonvolatile memory device 100 .

In an embodiment, each of the memory controller 50 and the nonvolatile memory device 100 may be provided as one chip, one package, or one module. Alternatively, the memory controller 50 and the nonvolatile memory device 100 may be mounted based on various packages and provided as a storage device such as a memory card.

The nonvolatile memory device 100 may perform an erase, write, or read operation under the control of the memory controller 50 . To this end, the nonvolatile memory device 100 receives a command CMD, an address ADDR, and data DATA through an input/output line. Also, the nonvolatile memory device 100 may receive a control signal CTRL through a control line. Also, the nonvolatile memory device 100 may receive power PWR from the memory controller 50 .

6 is a block diagram illustrating a nonvolatile memory device in the memory system of FIG. 5 according to example embodiments.

Referring to FIG. 6 , the nonvolatile memory device 100 includes a memory cell array 200, an address decoder 430, a page buffer circuit 410, a data input/output circuit 420, a control circuit 450, and a voltage generator ( 500) may be included.

The memory cell array 200 may be connected to the address decoder 430 through a string select line SSL, a plurality of word lines WLs, and a ground select line GSL. Also, the memory cell array 200 may be connected to the page buffer circuit 410 through a plurality of bit lines BLs. The memory cell array 100 may include a plurality of non-volatile memory cells connected to a plurality of word lines WLs and a plurality of bit lines BLs.

In an embodiment, the memory cell array 200 may be a three-dimensional memory cell array formed in a three-dimensional structure (or vertical structure) on a substrate. In this case, the memory cell array 200 may include vertical memory cell strings including a plurality of memory cells stacked on each other.

The control circuit 450 receives the command signal CMD and the address signal ADDR from the memory controller 50, and erases the nonvolatile memory device 100 based on the command signal CMD and the address signal ADDR. Loops, program loops and read operations can be controlled. Here, the program loop may include a program operation and a program verify operation, and the erase loop may include an erase operation and an erase verify operation.

For example, the control circuit 450 provides control signals CTLs for controlling the voltage generator 500 and a control signal PCTL for controlling the page buffer circuit 410 based on the command signal CMD. and generate a row address R_ADDR and a column address C_ADDR based on the address signal ADDR. The control circuit 450 may provide the row address R_ADDR to the address decoder 430 and the column address C_ADDR to the data input/output circuit 420 .

The address decoder 430 may be connected to the memory cell array 200 through a string select line SSL, a plurality of word lines WLs, and a ground select line GSL. During a program operation or a read operation, the address decoder 430 determines one of a plurality of word lines WLs as a selected word line based on the row address R_ADDR provided from the control circuit 450, and Word lines other than the selected word line among the lines WLs may be determined as non-selected word lines.

The voltage generator 500 may generate word line voltages VWLs necessary for the operation of the nonvolatile memory device 100 based on the control signals CTLs provided from the control circuit 450 . The word line voltages VWLs generated by the voltage generator 500 may be applied to the plurality of word lines WLs through the address decoder 430 .

For example, during an erase operation, the voltage generator 500 may apply an erase voltage to a well of a memory block and a ground voltage to all word lines of the memory block. During the erase verify operation, the voltage generator 500 may apply the erase verify voltage to all word lines of one memory block or may apply the erase verify voltage in units of word lines.

For example, during a program operation, the voltage generator 500 may apply a program voltage to selected word lines and a program pass voltage to non-selected word lines. Also, during the program verify operation, the voltage generator 500 may apply a program verify voltage to selected word lines and apply a verify pass voltage to non-selected word lines. Also, during a read operation, the voltage generator 500 may apply a read voltage to a selected word line and apply a read pass voltage to unselected word lines.

The page buffer circuit 410 may be connected to the memory cell array 300 through a plurality of bit lines BLs. The page buffer circuit 410 may include a plurality of page buffers. The page buffer circuit 410 may temporarily store data to be programmed in a selected page during a program operation, and may temporarily store data read from the selected page during a read operation.

The data input/output circuit 420 may be connected to the page buffer circuit 410 through a plurality of data lines DLs. During a program operation, the data input/output circuit 420 receives program data DATA from the memory controller 50 and transfers the program data DATA to the page buffer based on the column address C_ADDR provided from the control circuit 450. circuit 410. During a read operation, the data input/output circuit 420 provides the read data DATA stored in the page buffer circuit 410 to the memory controller 50 based on the column address C_ADDR provided from the control circuit 450. can

FIG. 7 is a block diagram illustrating an example of a memory cell array in the nonvolatile memory device of FIG. 6 .

Referring to FIG. 7 , the memory cell array 200 includes a plurality of memory blocks (BLK1 to BLKz, where z is a natural number greater than or equal to 3) disposed along a plurality of directions HD1 , HD2 , and VD. In an embodiment, the memory blocks are selected by the address decoder 430 shown in FIG. 5 . For example, the address decoder 430 may select a memory block BLK corresponding to a block address from among the memory blocks BLK1 to BLKz.

Hereinafter, a direction substantially perpendicular to the top surface of the substrate is defined as a vertical direction VD, and two directions parallel to and crossing each other are defined as a first horizontal direction HD1 and a second horizontal direction HD2, respectively. For example, the first horizontal direction HD1 and the second horizontal direction HD2 may substantially perpendicularly cross each other. The definition of the foregoing direction is the same in all drawings hereinafter.

FIG. 8A is a circuit diagram illustrating one BLKi of the memory blocks BLK1 to BLKz of FIG. 7 .

The memory block BLKi shown in FIG. 8A represents a three-dimensional memory block formed in a three-dimensional structure on a substrate. For example, a plurality of memory cell strings included in the memory block BLKi may be formed in a direction perpendicular to the substrate.

Referring to FIG. 8A , the memory block BLKi may include a plurality of memory cell strings NS11 to NS33 connected between the bit lines BL1 , BL2 , and BL3 and the common source line CSL.

Each of the plurality of memory cell strings (or cell strings, NS11 to NS33) may include a string select transistor (SST), a plurality of memory cells (MC1, MC2, ..., MC8), and a ground select transistor (GST). can The string select transistor SST may be connected to corresponding string select lines SSL1 , SSL2 , and SSL3 .

The plurality of memory cells MC1 , MC2 , ..., MC8 may be connected to corresponding word lines WL1 , WL2 , ..., WL8 , respectively. The ground select transistor GST may be connected to corresponding ground select lines GSL1 , GSL2 , and GSL3 . The string select transistor SST may be connected to corresponding bit lines BL1 , BL2 , and BL3 , and the ground select transistor GST may be connected to the common source line CSL. Word lines (eg, WL1) having the same height may be commonly connected, and ground select lines GSL1, GSL2, and GSL3 and string select lines SSL1, SSL2, and SSL3 may be separated from each other.

8B to 8D each show one of the cell strings of FIG. 8A according to embodiments of the present invention.

Referring to FIG. 8B , the cell string NS11a includes a ground select transistor GST connected between the common source line CSL and the bit line BL1, memory cells MC1, MC2, ..., MC8, and a string selector. A transistor SST and a GIDL string select transistor GDT1 may be included. The GIDL string select transistor GDT1 may be connected to the GIDL string select line GDSSL1. In this case, a GIDL drain voltage having a voltage level higher than a voltage difference obtained by subtracting the GIDL on voltage from the GIDL threshold voltage is applied to all or some of the plurality of bit lines in the bit line setup period (PBLS) to generate a unidirectional signal in each of the cell strings. Channel precharge can be performed. The GIDL on voltage represents a voltage capable of turning on the GIDL string select transistor GDT1. Each of the cell strings NS11 to NS33 of FIG. 8A may be implemented as the cell string NS11a of FIG. 8B.

Referring to FIG. 8C , the cell string NS11b includes a GIDL ground select transistor GDT2, a ground select transistor GST, and memory cells MC1, MC2, . .., MC8) and a string select transistor (SST). The GIDL ground select transistor GDT2 may be connected to the GIDL ground select line GDGSL2. In this case, unidirectional channel precharging may be performed in each of the cell strings by applying the GIDL drain voltage to the common source line CSL during the bit line setup period PBLS. Each of the cell strings NS11 to NS33 of FIG. 8A may be implemented as a cell string NS11b of FIG. 8C.

Referring to FIG. 8D , the cell string NS11b includes a GIDL ground select transistor GDT2, a ground select transistor GST, and memory cells MC1, MC2, . .., MC8), a string select transistor SST, and a GIDL string select transistor GDT1. The GIDL ground select transistor GDT2 may be connected to the GIDL ground select line GDGSL2, and the GIDL string select transistor GDT1 may be connected to the GIDL string select line GDSSL1. In this case, bidirectional channel precharging may be performed in each of the cell strings by applying the GIDL drain voltage to at least some of the bit lines and the common source line CSL during the bit line setup period PBLS. Each of the cell strings NS11 to NS33 of FIG. 6A may be implemented as a cell string NS11c of FIG. 8D.

FIG. 9 is a block diagram illustrating a configuration of a control circuit in the nonvolatile memory device of FIG. 6 according to example embodiments.

Referring to FIG. 9 , the control circuit 450 may include a command decoder 460 , an address buffer 470 and a control signal generator 480 .

The command decoder 460 may decode the command signal CMD and provide the decoded command D_CMD to the control signal generator 480 .

The address buffer 470 receives the address signal ADDR, provides the row address R_ADDR of the address signal ADDR to the address decoder 430 and provides the column address C_ADDR to the data input/output circuit 420. can

The control signal generator 530 receives the decoded command D_CMD, generates control signals CTLs based on an operation indicated by the decoded command D_CMD, provides them to the voltage generator 500, and provides them to the page buffer. A control signal PCTL may be generated and provided to the page buffer circuit 410 .

10 is a block diagram illustrating a configuration of a voltage generator in the nonvolatile memory device of FIG. 6 according to example embodiments.

Referring to FIG. 10 , the voltage generator 500 may include a high voltage generator 510 and a low voltage generator 520 . In an embodiment, the voltage generator 500 may further include a negative voltage generator 530 .

The high voltage generator 510 generates a program voltage VPGM, a program pass voltage VPPASS, a verify pass voltage VVPASS, and a read pass voltage according to an operation indicated by the command CMD in response to the first control signal CTL1. VRPASS), dummy voltage VDUM, and erase voltage VRES. The dummy voltage VDUM may include the first dummy voltage VDUM1 and the second dummy voltage VDUM2 of FIG. 4 .

The program voltage VPGM is applied to selected word lines, the program pass voltage VPPASS, program verify pass voltage VVPASS, and read pass voltage VRPASS are applied to unselected word lines, and the dummy voltage VDUM The dummy word line disposed adjacent to the boundary of the stacks may be applied, and the erase voltage VRES may be applied to a well of the memory block. The first control signal CTL1 may include a plurality of bits to indicate an operation indicated by the decoded command D_CMD.

The low voltage generator 520 generates a program verification voltage VPV, a read voltage VRD, an erase verification voltage VEV according to an operation indicated by the command CMD in response to the second control signal CTL2, and a first turn- A turn-on voltage VON1 , a second turn-on voltage VON2 , a first voltage V1 and a second voltage V2 may be generated.

The program verification voltage VPV, the read voltage VRD, and the erase verification voltage VEV may be applied to the selected word line according to an operation. The first turn-on voltage VON1 and the second turn-on voltage VON2 may be applied to the string select transistor and the ground select transistor of the selected cell string and the non-selected cell string, and the second voltage V2 is It can be applied to word lines and unselected word lines. The second control signal CTL2 may include a plurality of bits to indicate an operation indicated by the decoded command D_CMD.

The negative voltage generator 530 generates a first negative voltage VNEG1 and a second negative voltage VNEG2 having negative levels according to an operation indicated by the command CMD in response to the third control signal CTL3. can The third control signal CTL3 may include a plurality of bits to indicate an operation indicated by the decoded command D_CMD. The first negative voltage VNEG1 may be applied to the selected word line and the unselected word line in the program recovery period, and the second negative voltage VNEG2 may be applied to the unselected word line in the bit line setup period.

11 is a diagram illustrating operation sections included in each of a plurality of program loops.

Referring to FIG. 11 , each program loop LOOP(i) includes a program period PROGRAM for applying program voltages VPGM1, VPGM2, VPGM3, ... to a selected word line in order to program selected memory cells and a program A verification section VERIFY for applying the verification read voltage VPV to the selected word line may be included to verify whether the operation is successful.

The program period PROGRAM may include a bit line setup period PBLS, a program execution period PGME, and a program recovery period PGMRC. The verification period VERIFY may include a bit line precharge period PBLP, a verify read period VFRD, and a read recovery period RDCR. The bit line setup period PBLS, program execution period PGME, program recovery period PGMRC, and verification read period VFRD have been described with reference to FIG. 2 .

FIG. 12 is a diagram illustrating an example of a structure of one cell string according to embodiments of the present invention, and FIG. 13 is a diagram illustrating an example of a structure of one memory cell included in the cell string of FIG. 12 .

Referring to FIGS. 12 and 13 , in order to form a cell string NS, a pillar PL may be provided on the substrate SUB to extend in a direction perpendicular to the substrate and contact the substrate SUB. The ground select line GSL, word lines WLs, and string select lines SSL shown in FIG. 12 may be formed of conductive materials parallel to the substrate SUB, for example, metal materials. there is. The pillar PL may contact the substrate SUB by passing through conductive materials forming the ground select line GSL, the word lines WLs, and the string select lines SSL. Also, the word lines WLs may include dummy word lines not used for data storage. A dummy word line can be used for a variety of purposes.

FIG. 13 shows a cross-sectional view taken along the line A-A' in FIG. 12 . As an example, a cross-sectional view of a memory cell MC corresponding to one word line may be shown. The pillar PL may include a cylindrical body BD. An air gap AG may be provided inside the body BD. The body BD may include P-type silicon and may be a region in which a channel is formed.

The pillar PL may further include a cylindrical tunnel insulating layer TI surrounding the body BD and a cylindrical charge trapping layer CT surrounding the tunnel insulating layer TI. A blocking insulating layer BI may be provided between one word line and the pillar PL. A body (BD), a tunnel insulating film (TI), a charge trapping film (CT), a blocking insulating film (BI), and one word line form a substrate (SUB) or a charge trap formed in a direction perpendicular to the upper surface of the substrate (SUB). type transistor. The string select transistor SST, the ground select transistor GST, and other memory cells may have the same structure as the memory cell MC.

Exemplarily, in the manufacturing process of the cell string NS, the width of the pillar PL or the cross-sectional area parallel to the top surface of the substrate SUB may be formed smaller as the distance to the substrate SUB decreases.

Therefore, the same voltage is applied to the bodies of the ground select transistor GST, the memory cells MCs, and the string select transistors SSTs, and the ground select line GSL, word lines WL, and string select lines When the same voltage is applied to SSL, the electric field formed in the memory cell adjacent to the substrate SUB or the ground select transistor GST is the electric field formed in the memory cell or string select transistor SST far from the substrate SUB. bigger than These characteristics affect program disturb that occurs while a program operation is being performed. However, the width of the pillar PL or the cross-sectional area parallel to the upper surface of the substrate SUB is not limited thereto. The width of the pillar PL or the cross-sectional area parallel to the upper surface of the substrate SUB may be formed differently according to the distance from the substrate SUB according to the etching process.

14A is a circuit diagram illustrating a structure of a memory block according to example embodiments, and FIG. 14B is a perspective view illustrating a memory block corresponding to the structure of FIG. 14A.

Although FIG. 14A shows NAND strings or cell strings STR1 to STRm connected to one bit line BL and one common source line CSL among the cell strings of the memory block for convenience, the memory block It may have a three-dimensional structure as described with reference to FIGS. 7 and 8 .

Referring to FIGS. 14A and 14B , a memory block may include a plurality of cell strings STR1 to STRm connected between the same bit line BL and common source line CSL. Each of the cell strings STR1 to STRm includes string select transistors SST1 to SSTm controlled by string select lines SSL1 to SSLm, memory cells controlled by word lines WL, and a dummy word line. dummy memory cells DMC11 to DMC1m controlled by DWL and ground select transistors GST1 to GSTm controlled by ground select line GSL. Memory cells connected to at least one word line positioned at both ends of the first and second stacks ST1 and ST2 in the vertical direction VD may be dummy cells. Valid data may not be stored in the dummy cells. Meanwhile, the dummy cells may be configured to store data of a smaller number of bits than other memory cells.

The dummy memory cells DMC11 to DMC1m may be included in the second stack ST2.

14A and 14B show an embodiment in which ground select transistors are connected to the same ground select line GSL, but a certain number of ground select transistors may be connected to each of a plurality of ground select lines.

In one embodiment, as shown in FIG. 14A , the boundary layer BND may include one gate line. The one gate line corresponds to the dummy word line DWL and can simultaneously control the dummy memory cells DMC11 to DMC1m connected thereto.

In one embodiment, as shown in FIG. 14B , the boundary layer BND may include two gate lines, and the two gate lines may correspond to dummy word lines DWL11 and DWL12. The dummy word line DWL11 may be included in the first stack ST1, and the dummy word line DWL12 may be included in the second stack ST2.

15 is a cross-sectional view illustrating an example of a boundary layer included in a nonvolatile memory device according to example embodiments.

Referring to FIG. 15 , each channel hole constituting each cell string may include a first sub-channel hole 610 and a second sub-channel hole 630 . The first sub-channel hole 610 may include a channel layer 611 , an internal material 612 , and an insulating layer 613 . The second sub-channel hole 630 may include a channel layer 631 , an internal material 632 , and an insulating layer 633 . The channel film 611 of the first sub-channel hole 610 may be connected to the channel film 631 of the second sub-channel hole 630 through a P-type silicon pad (SIP).

The plurality of sub-channel holes 610 and 630 may be formed using a stopper line GTL5 having an appropriate etch selectivity. For example, in order to realize the appropriate etching selectivity, the stopper line GTL5 may be formed of polysilicon and the remaining gate lines GTL1 to GTL4 and GTL6 to GTL8 may be formed of a metal such as tungsten. Although there is a difference depending on the doping concentration of polysilicon, the resistance value of the stopper line GTL5 is about 6 times greater than the respective resistance values of the remaining gate lines GTL1 to GTL4 and GTL6 to GTL8.

The boundary layer between the aforementioned stacks may correspond to a stopper line GTL5 for forming a plurality of sub-channel holes constituting the channel hole of the cell string step by step. Cells of the stopper line may not be suitable for storing data, and such a stopper line may be used as a boundary layer for forming dummy memory cells according to embodiments of the present invention. Also, one or more gate line layers vertically adjacent to the stopper line GTL5 may be further included in the boundary layer.

Dummy memory cells formed on the boundary layer may be implemented as a cell type or as a transistor type. Here, the cell type refers to a case including a floating gate like a flash memory cell, and the transistor type refers to a case in which the floating gate is omitted.

16 is a diagram illustrating a program operation according to embodiments of the present invention.

16 illustrates memory connected to 12 word lines WL1 to WL12 between a string select transistor SST connected to a string select line SSL and a ground select transistor GST connected to a ground select line GSL. One cell string including cells MC1 to MC12 and a dummy memory cell DMC connected to a dummy word line DWL and its state are shown. The cell string is connected to the bit line BL and the source line CSL. In addition, FIG. 16 illustrates the state of the threshold voltage (Vth) of a triple-level cell storing 3 bits as an example.

Referring to FIG. 16 , according to an operating scenario of a nonvolatile memory device, a program operation of sequentially programming from a lowest word line to an upper direction may be performed.

The memory cells MC1 to MC7 of the programmed word line of the selection stack ST1 are in the erased state E0 or each programmed state P1, P2, P3, P4, P5, P6, P7 according to the stored data. , and all of the word lines and memory cells MC8 to MC12 of the upper stack ST2 disposed above the selection stack ST1 may have an erase state E0. The dummy word line DWL may be included in the upper stack ST2.

FIG. 17 is a timing diagram illustrating an embodiment of a programming method for a first stack according to the program operation of FIG. 16 .

17 shows a program operation when the selected word line WL_SEL corresponding to the program address is included in the first stack ST1. That is, the first stack ST1 corresponds to a selection stack to be programmed, and the second stack ST2 corresponds to an upper stack disposed above the selection stack.

The time period T21 to T22 is the precharge period (PPC), the time period T22 to T23 is the boosting period (PBS), and the time period T23 to T26 is the program execution period in which the program voltage (VPGM) is applied to the selected word line (WL_SEL). (PGME), and the time intervals T26 to T27 are program recovery intervals (PGMRC). Hereinafter, voltages having levels at which corresponding transistors can be turned on and turned off may be referred to as turn-on voltages and turn-off voltages, respectively.

When the bit line BL is a program inhibit bit line, the program inhibit voltage VINH may be applied, and when the bit line BL is a program allow bit line, the program enable voltage VPER may be applied.

During the precharge period PPC, the turn-off voltage VSOFF is applied to the select string select line SSL_SEL and the non-select string select line SSL_UNS, and the turn-on voltage DWON is applied to the dummy word line DWL. , the turn-on voltage VGON is applied to the ground selection line GSL. Accordingly, since the ground selection transistor and the dummy memory cell are turned on, the precharge voltage of the source line CSL is applied to the channels of the first and second stacks ST1 and ST2.

As such, before performing the boosting operation of the boosting period PBST, the precharge voltage VPC may be applied to the channels of the first stack ST1 and the second stack ST2 using the source line CSL. . During the precharge period PPC, the initial voltage Vo is applied to the selected word line WL_SEL and the unselected word lines WL_UNS. The initial voltage Vo has a voltage level at which erased memory cells can be turned on.

In the boosting period PBST, the turn-on voltage VSON is applied to the select string select line SSL_SEL and the turn-off voltage VOFF is applied to the dummy word line DWL, thereby forming the first stack ST1 and the second stack ST1. The channels of the stack ST2 are electrically disconnected from each other. In the state in which the dummy memory cells are turned off, the word lines WL_UNS(ST1) and WL_SEL(ST2) of the first stack ST1 corresponding to the selected stack maintain the initial voltage Vo, and the upper stack ( The word lines WL_UNS(ST2) of ST2 also maintain the initial voltage Vo. A program allowable voltage VPER is applied to a channel of the first stack ST1 of the selected cell string or has a voltage (not shown) corresponding to the program inhibit voltage VINH according to the bit line BL.

During the program operation, the turn-off voltage VGOFF is applied to the ground selection line GSL, and an electrical connection between the cell strings and the common source line may be cut off.

In the program execution period PGME, the bit line BL to which the program voltage VPGM is applied to the selected word line WL_SEL(ST1) of the first stack ST1 corresponding to the selected stack and the program allowable voltage VPER is applied ), the corresponding memory cell connected to is programmed. Also, in the program execution period PGME, the first pass voltage VPASS1 is applied to the unselected word line WL_UNS(ST1) of the first stack ST1.

In the program execution period PGME, the turn-on voltage VSON is applied to the selected string select line SSL_SEL, and the turn-off voltage VSOFF is applied to the non-select string select line SSL_UNS.

During the first sub-period T23 to T24 of the program execution period PGME, the first dummy voltage VDUM1 is applied to the dummy word line DWL of the second stack ST2 corresponding to the upper stack.

During the second sub-period T24 to T25 of the program execution period PGME, the first dummy voltage VDUM1 is reduced to the second dummy voltage VDUM2.

The first pass voltage VPASS1 is applied to the word lines WL_UNS(ST2) of the second stack ST2 during the first sub-period T23 to T24 and the second sub-period T24 to T25.

The second dummy voltage VDUM2 is applied to the dummy word line DWL of the second stack ST2 during the third sub-period T25 to T26 of the program execution period PGME. A second pass voltage VPASS2 lower than the first pass voltage VPASS1 is applied to the word lines WL_UNS(ST2) of the second stack ST2 in the third subperiod T25 to T26.

In the program recovery period PGMRC, recovery is performed with the initialization voltage Vo of the first stack ST1, and at the same time, the voltage of the word lines of the second stack ST2 is changed from the second pass voltage VPASS2 to the initialization voltage Vo. Decrease.

18 is a cross-sectional view illustrating a memory block divided into three stacks according to example embodiments.

Referring to FIG. 18 , the aforementioned boundary layer includes a lower boundary layer BNDL and an upper boundary layer BNDU. The memory block MBa includes a first stack ST1 positioned under the lower boundary layer BNDL, a second stack ST2 positioned between the lower boundary layer BNDL and the upper boundary layer BNDU, and an upper boundary layer. A third stack ST3 positioned above the layer BNDU is included.

The first dummy word line DWL1 is included in the second stack ST2 adjacent to the lower boundary layer BNDL, and first dummy memory cells may be connected to the first dummy word line DWL1. The second dummy word line DWL2 is included in the third stack ST3 adjacent to the upper boundary layer BNDU, and second dummy memory cells may be connected to the second dummy word line DWL2.

FIG. 19 shows an embodiment of a program method for stacks of memory blocks of FIG. 18 , and FIG. 20 shows a program execution section in the program method of FIG. 19 in more detail. A description overlapping with that of FIG. 17 will be omitted.

19 illustrates voltages in the aforementioned precharge period (PPC), boosting period (PBST), program execution period (PGME), and program recovery period (PGMRC).

19 shows a case of performing a program for the first stack ST1. In this case, the first stack ST1 corresponds to the selected stack, and the second and third stacks ST2 and ST2 correspond to the aforementioned upper stack.

During the precharge period PPC, the turn-off voltage VSOFF is applied to the string select line SSL, the turn-on voltage DWON is applied to the dummy word lines DWL1 and DWL2, and the ground select line GSL A turn-on voltage (VGON) is applied to . Accordingly, since the ground select transistor and the dummy memory cells are turned on, the precharge voltage of the source line CSL is applied to the channels of the first stack ST1, the second stack ST2, and the third stack ST3.

In the boosting period PBST, the turn-on voltage VSON is applied to the string select line SSL, and the turn-off voltage VOFF is applied to the dummy word lines DWL1 and DWL2, thereby forming the first stack ST1, Channels of the second stack ST2 and the third stack ST3 are electrically disconnected from each other. In such a state in which the dummy memory cells are turned off, the word lines of the first stack ST1 corresponding to the selected stack maintain the initial voltage Vo, and the word lines of the upper stacks ST2 and ST2 also have the initial voltage ( hold Vo). A program allowable voltage VPER is applied to a channel of the first stack ST1 of the selected cell string or has a voltage (not shown) corresponding to the program inhibit voltage VINH according to the bit line BL.

19 and 20, the program inhibit voltage VINH or the program allow voltage VPER may be applied to the bit line BL in the program execution period PGME, and the turn-off voltage VPER may be applied to the string select line SSL. The on voltage VSON is applied, the program voltage VPGM is applied to the selected word line WL_SEL(ST1) of the first stack ST1, and the unselected word lines WL_UNS of the first stack ST1 A first pass voltage VPASS1 is applied to .

During the first sub-period T31 to T32 of the program execution period PGME, the first dummy voltage DUM1 is applied to the dummy word lines DWL1 and DWL2, and the second sub-period T32 to T33 is applied with the first dummy voltage DUM1. 1 dummy voltage DUM1 is lowered to the second dummy voltage DUM2, and the second dummy voltage VDUM2 is applied to the dummy word lines DWL1 and DWL2 during the third sub-period T33 to T34. During the first sub-periods T31 to T32, the program forcing voltage may be applied to the bit line BL, so that the program forcing voltage may reach the channel of the selection stack ST1.

Word lines of the second stack ST2 and the third stack ST3 corresponding to the upper stack during the first sub-period T31 to T32 and the second sub-period T32 to T33 of the program execution period PGME. The first pass voltage VPASS1 is applied to (WL_UNS(ST2, ST3)), and the second stack ST2 and the third stack ST3 are applied during the third sub-period T33 to T34 of the program execution period PGME. The second pass voltage VPASS2 having a lower level than the first pass voltage VPASS1 is applied to the word lines WL_UNS(ST2, ST3) of ).

In the program recovery period PGMRC, the turn-off voltage VSOFF is applied to the string select line SSL and the turn-off voltages VOFF are applied to the dummy word lines DWL1 and DWL2, respectively, and the other voltages in FIG. 17 As described above with reference to.

As such, by applying the second dummy voltage VDUM2 to the dummy word lines DWL1 and DWL2 during the third sub-period T33 to T34, the second stack ST2 and the third stack corresponding to the upper stack ( Path disturb that the word lines of ST3 can receive from the selection stack ST1 in the third sub-period T33 to T34 can be prevented.

FIG. 21 shows an embodiment of a program method for stacks of memory blocks of FIG. 18, and FIG. 22 shows a program execution section in the program method of FIG. 21 in more detail. A description overlapping with that of FIG. 17 will be omitted.

21 illustrates voltages in the aforementioned precharge period (PPC), boosting period (PBST), program execution period (PGME), and program recovery period (PGMRC).

21 shows a case of executing a program for the second stack ST2. In this case, the second stack ST2 corresponds to the selected stack, corresponds to the lower stack in the first stack ST1, and the third stack ST2 corresponds to the aforementioned upper stack.

Operations of the precharge period (PPC) and the boosting period (PBST) are the same as those of FIG. 19, so detailed descriptions are omitted.

21 and 22, in the program execution period PGME, the program inhibit voltage VINH or the program allow voltage VPER may be applied to the bit line BL, and the turn- The on voltage VSON is applied, the program voltage VPGM is applied to the selected word line WL_SEL(ST2) of the second stack ST2, and the unselected word lines WL_UNS( The second pass voltage VPASS1 is applied to ST2), and the first dummy voltage DUM1 is applied to the dummy word line DWL1 of the second stack ST2.

During the first sub-period T51 to T52 of the program execution period PGME, the first dummy voltage DUM1 is applied to the dummy word line DWL2, and the first dummy voltage is applied to the second sub-period T52 to T53. DUM1 is dropped to the second dummy voltage DUM2, and the second dummy voltage VDUM2 is applied to the dummy word line DWL2 during the third sub-period T53 to T54.

During the first sub-periods T51 to T52 and the second sub-periods T52 to T53 of the program execution period PGME, the word lines WL_UNS(ST3) of the third stack ST3 corresponding to the upper stack are The first pass voltage VPASS1 is applied, and during the third sub-period T53 to T54 of the program execution period PGME, the first pass voltage is applied to the word lines WL_UNS(ST3) of the third stack ST3. The second pass voltage VPASS2 having a lower level than (VPASS1) is applied.

During the program execution period PGME, the first pass voltage VPASS1 is applied to the word lines WL_UNS(ST1) of the first stack ST1 corresponding to the lower stack.

In the program recovery period PGMRC2, the turn-off voltage VSOFF is applied to the string select line SSL and the turn-off voltages VOFF are applied to the dummy word lines DWL1 and DWL2, respectively, and the other voltages in FIG. 17 As described above with reference to.

As such, by applying the second dummy voltage VDUM2 to the dummy word line DWL2 during the third sub-period T53 to T54, the word lines of the third stack ST3 corresponding to the upper stack are connected to the third sub-period. In (T53 to T54), path disturb that can be received from the second stack ST2 can be prevented.

FIG. 23 shows an embodiment of a program method for stacks of memory blocks of FIG. 18 , and FIG. 24 shows a program execution section in the program method of FIG. 23 in more detail. A description overlapping with that of FIG. 17 will be omitted.

23 shows a case of performing a program for the first stack ST1. In this case, the first stack ST1 corresponds to the selected stack, and the second and third stacks ST2 and ST2 correspond to the aforementioned upper stack.

Operations in the precharge period (PPC) and the boosting period (PBST) are the same as those in FIG. 19, so detailed descriptions are omitted.

23 and 24, the program inhibit voltage VINH or the program allow voltage VPER may be applied to the bit line BL in the program execution period PGME, and the turn-off voltage VPER may be applied to the string select line SSL. The on voltage VSON is applied, the program voltage VPGM is applied to the selected word line WL_SEL(ST1) of the first stack ST1, and the unselected word lines WL_UNS of the first stack ST1 A first pass voltage VPASS1 is applied to .

During the first sub-period T61 to T62 of the program execution period PGME, the first dummy voltage DUM1 is applied to the dummy word lines DWL1 and DWL2, and the second sub-period T62 to T63 is applied to the dummy word lines DWL1 and DWL2. 1 dummy voltage DUM1 is lowered to the second dummy voltage DUM2, and the second dummy voltage VDUM2 is applied to the dummy word lines DWL1 and DWL2 during the third sub-period T63 to T64.

Word lines WL_UNS(ST2, The first pass voltage VPASS1 is applied to ST3), and during the third sub-periods T33 to T34 of the program execution period PGME, word lines of the second and third stacks ST2 and ST3 are applied. The second pass voltage VPASS2 having a lower level than the first pass voltage VPASS1 is applied to (WL_UNS(ST2, ST3)), and the dummy word lines of the second and third stacks ST2 and ST3 are applied. The third pass voltage VPASS3 having a lower level than the second pass voltage VPASS2 is applied to the boundary word lines WL_BDR(ST2, ST3) adjacent to each of (DWL1 and DWL2).

In the program recovery period PGMRC, the turn-off voltage VSOFF is applied to the string select line SSL and the turn-off voltages VOFF are applied to the dummy word lines DWL1 and DWL2, respectively, and the other voltages in FIG. 17 As described above with reference to.

As such, during the third sub-period T33 to T34, the second dummy voltage VDUM2 is applied to the dummy word lines DWL1 and DWL2, and the second pass is applied to the boundary word lines WL_BDR (ST2 and ST3). By applying the third pass voltage VPASS3 having a lower level than the voltage VPASS2, the word lines of the second and third stacks ST2 and ST3 corresponding to the upper stack are connected to the third sub-period T33 to T34. ), path disturb that can be received from the first stack ST1 can be prevented.

FIG. 25 shows an embodiment of a program method for stacks of memory blocks of FIG. 18, and FIG. 26 shows a program execution section in the program method of FIG. 25 in more detail. A description overlapping with that of FIG. 17 will be omitted.

25 illustrates voltages in the aforementioned precharge period (PPC), boosting period (PBST), program execution period (PGME), and program recovery period (PGMRC).

25 shows a case of executing a program for the second stack ST2. In this case, the second stack ST2 corresponds to the selected stack, the first stack ST1 corresponds to the lower stack, and the third stack ST3 corresponds to the aforementioned upper stack.

Operations in the precharge period (PPC) and the boosting period (PBST) are the same as those in FIG. 19, so detailed descriptions are omitted.

During the first sub-period T71 to T72 of the program execution period PGME, the first dummy voltage DUM1 is applied to the dummy word line DWL2, and the first dummy voltage is applied to the second sub-period T72 to T73. DUM1 is dropped to the second dummy voltage DUM2, and the second dummy voltage VDUM2 is applied to the dummy word line DWL2 during the third sub-period T73 to T74.

During the first sub-periods T71 to T72 and the second sub-periods T72 to T73 of the program execution period PGME, the word lines WL_UNS(ST3) of the third stack ST3 corresponding to the upper stack are The first pass voltage VPASS1 is applied, and during the third sub-period T73 to T74 of the program execution period PGME, the first pass voltage is applied to the word lines WL_UNS(ST3) of the third stack ST3. The second pass voltage VPASS2 having a lower level than VPASS1 is applied, and the second pass voltage VPASS2 is applied to the boundary word line WL_BDR(ST3) adjacent to the dummy word line DWL2 of the third stack ST3. ), the third pass voltage VPASS3 having a lower level is applied.

During the program execution period PGME, the first pass voltage VPASS1 is applied to the word lines WL_UNS(ST1) of the first stack ST1 corresponding to the lower stack.

In the program recovery period PGMRC2, the turn-off voltage VSOFF is applied to the string select line SSL and the turn-off voltages VOFF are applied to the dummy word lines DWL1 and DWL2, respectively, and the other voltages in FIG. 17 As described above with reference to.

As such, during the third sub-periods T73 to T74, the second dummy voltage VDUM2 is applied to the dummy word line DWL2, and a lower voltage than the second pass voltage VPASS2 is applied to the boundary word line WL_BDR(ST3). By applying the third pass voltage VPASS3 having a level, word lines of the third stack ST3 corresponding to the upper stack can receive a pass from the second stack ST2 in the third sub-period T73 to T74. Disturb can be prevented.

27 is a cross-sectional view illustrating a memory block divided into three sub-blocks according to example embodiments.

Referring to FIG. 27 , the memory block MBb may include a first sub-block SB1, a second sub-block SB2, and a third sub-block SB3 including a plurality of word lines, respectively. The second sub-block SB2 may include a boundary word line BWL1 adjacent to the first sub-block SB1, and the third sub-block SB3 may include a boundary word line BWL2 adjacent to the third sub-block SB3. ) may be included.

Each of the first sub-block SB1, the second sub-block SB2, and the third sub-block SB3 is smaller than the physical block, and the first sub-block SB1, the second sub-block SB2, and the third sub-block (SB3) An erase operation may be performed for each.

Word lines other than the boundary word lines BWL1 and BWL2 in each of the second sub-block SB2 and the third sub-block SB3 may be referred to as internal word lines.

In FIG. 27 , each of the memory cells connected to the boundary word lines BWL1 and BWL2 may store fewer bits than each of the memory cells connected to each of the internal word lines.

FIG. 28 illustrates an embodiment of a programming method for sub-blocks of the memory block of FIG. 27 .

28 , the first sub-block SB1 includes memory cells MC1 to MC4, the second sub-block SB2 includes memory cells MC5 to MC8, and the third sub-block SB3 includes memory cells MC5 to MC8. Cells MC9 to MC12 may be included. The memory cell MC5 may be connected to the boundary word line BWL1 , and the memory cell MC9 may be connected to the boundary word line BWL2 .

28 illustrates voltages in the aforementioned precharge period (PPC), boosting period (PBST), program execution period (PGME), and program recovery period (PGMRC).

28 shows a case of performing a program for the first sub-block SB1. In this case, the first sub-block SB1 corresponds to the selection sub-block, and the second and third sub-blocks SB2 and SB3 correspond to the upper sub-blocks.

During the precharge period PPC, the turn-off voltage VSOFF is applied to the string select line SSL, the turn-on voltage BVON is applied to the boundary word lines BWL1 and BWL2, and the ground select line GSL A turn-on voltage (VGON) is applied to . Accordingly, since the memory cells connected to the ground select transistor and the boundary word lines BWL1 and BWL2 are turned on, the precharge voltage of the source line CSL is applied to the first sub-block SB1 and the second sub-sub-block SB2. and applied to the channel of the third sub block SB3.

In the boosting period PBST, the turn-on voltage VSON is applied to the string select line SSL, and the turn-off voltage VOFF is applied to the boundary word lines BWL1 and BWL2, thereby forming the first sub-block SB1. , channels of the second sub-block SB2 and the third sub-block SB3 are electrically disconnected from each other. In this way, in a state in which the memory cells connected to the boundary word lines BWL1 and BWL2 are turned off, the word lines of the first sub-block SB1 corresponding to the selected sub-block maintain the initial voltage Vo, and the upper sub-block Word lines of the second and second sub-blocks SB2 and SB3 corresponding to also maintain the initial voltage Vo.

In the program execution period PGME, the program inhibit voltage VINH or the program allow voltage VPER may be applied to the bit line BL, and the turn-on voltage VSON may be applied to the string select line SSL. there is. In addition, the program voltage VPGM is applied to the selected word line of the first sub-block SB1, and the first pass voltage VPASS1 is applied to the unselected word lines of the first sub-block SB2.

During the first sub-period of the program execution period PGME, the first dummy voltage DUM1 is applied to the boundary word lines BWL1 and BWL2, and the first dummy voltage DUM1 is applied to the second dummy voltage DUM1 during the second sub-period. The second dummy voltage VDUM2 is applied to the boundary word lines BWL1 and BWL2 during the third subperiod. During the first sub-period, the program forcing voltage may be applied to the bit line BL, so that the program forcing voltage may reach the channel of the selection sub-block SB1.

Boundary word lines and word lines BWL1 of the second sub-block SB2 and the third sub-block SB3 corresponding to the upper sub-block during the first and second sub-periods of the program execution period PGME; BWL2), the first pass voltage VPASS1 is applied to internal word lines, and during the third sub-period of the program execution period PGME, the second sub-block SB2 and the third sub-block SB3 generate internal words. A second pass voltage VPASS2 having a lower level than the first pass voltage VPASS1 is applied to the lines.

In the program recovery period PGMRC, the turn-off voltage VSOFF is applied to the string select line SSL and the turn-off voltage VOFF is applied to the boundary word lines BWL1 and BWL2, respectively, and the other voltages are as shown in FIG. 17 . As described above with reference.

As such, by applying the second dummy voltage VDUM2 to the boundary word lines BWL1 and BWL2 during the third sub-period, the second sub-block SB2 and the third sub-block SB3 corresponding to the upper sub-block are formed. It is possible to prevent path disturb that internal word lines of can receive from the first sub block SB1 during the third sub period.

FIG. 29 illustrates an embodiment of a programming method for sub-blocks of the memory block of FIG. 27 .

29 , the first sub-block SB1 includes memory cells MC1 to MC4, the second sub-block SB2 includes memory cells MC5 to MC8, and the third sub-block SB3 includes memory cells MC5 to MC8. Cells MC9 to MC12 may be included. The memory cell MC5 may be connected to the boundary word line BWL1 , and the memory cell MC9 may be connected to the boundary word line BWL2 .

29 illustrates voltages in the aforementioned precharge period (PPC), boosting period (PBST), program execution period (PGME), and program recovery period (PGMRC).

29 shows a case of performing a program for the second sub-block SB1. In this case, the second sub-block SB2 corresponds to the selected sub-block, the third sub-block SB3 corresponds to the upper sub-block, and the first sub-block SB1 corresponds to the lower sub-block.

Operations in the precharge period (PPC) and the boosting period (PBST) are the same as those of FIG. 28, so detailed descriptions are omitted.

In the program execution period PGME, the program inhibit voltage VINH or the program allow voltage VPER may be applied to the bit line BL, and the turn-on voltage VSON may be applied to the string select line SSL. there is. In addition, the program voltage VPGM is applied to the selected word line of the second sub-block SB2, the first pass voltage VPASS1 is applied to the unselected word lines of the second sub-block SB2, and the boundary word line A first dummy voltage VDUM1 may be applied to BWL1, and a first pass voltage VPASS1 may be applied to word lines of the first sub-block SB1 corresponding to a lower sub-block.

During the first sub-period of the program execution period PGME, the first dummy voltage DUM1 is applied to the boundary word line BWL2, and the first dummy voltage DUM1 is applied to the second dummy voltage DUM2 during the second sub-period. ), and the second dummy voltage VDUM2 is applied to the boundary word line BWL2 during the third subperiod.

During the first sub-period and the second sub-period of the program execution period PGME, internal word lines excluding the boundary word line word lines BWL2 of the third sub-block SB3 corresponding to the upper sub-block have first and second sub-blocks. The pass voltage VPASS1 is applied, and during the third sub-period of the program execution period PGME, the second pass voltage having a lower level than the first pass voltage VPASS1 is applied to word lines inside the third sub-block SB3. (VPASS2) is applied.

In the program recovery period PGMRC, the turn-off voltage VSOFF is applied to the string select line SSL and the turn-off voltage VOFF is applied to the boundary word lines BWL1 and BWL2, respectively, and the other voltages are as shown in FIG. 17 . As described above with reference.

As such, by applying the second dummy voltage VDUM2 to the boundary word line BWL2 during the third sub-period, the internal word lines of the third sub-block SB3 corresponding to the upper sub-block are in the third sub-period. Path disturb that can be received from the 2nd sub-block (SB2) can be prevented.

30 schematically shows a non-volatile memory device according to embodiments of the present invention.

Referring to FIG. 30 , the nonvolatile memory device 1000 may include a first semiconductor layer L1 and a second semiconductor layer L2, and the first semiconductor layer L1 is a second semiconductor layer L2. may be stacked in a vertical direction (VD) with respect to Specifically, the second semiconductor layer L2 may be disposed below the first semiconductor layer L1 in a vertical direction VD, and thus, the second semiconductor layer L2 may be disposed close to the substrate. there is.

In an embodiment, the memory cell array 200 of FIG. 6 may be formed on the first semiconductor layer L1, and may include the address decoder 430, the page buffer circuit 410, and the data input/output circuit 420 of FIG. , a control circuit 450 and a peripheral circuit including the voltage generator 500 may be formed on the second semiconductor layer L2. Accordingly, the memory device 1000 may have a structure in which the memory cell array 200 is disposed on top of a peripheral circuit, that is, a COP (Cell Over Periphery) structure. The COP structure can effectively reduce an area in a horizontal direction and improve the degree of integration of the nonvolatile memory device 1000 .

31 is a cross-sectional view illustrating a nonvolatile memory device according to example embodiments.

Referring to FIG. 31 , the nonvolatile memory device 2000 may have a chip to chip (C2C) structure. The C2C structure fabricates an upper chip (first chip) including a cell region (CELL) on a first wafer, and a lower chip (first chip) including a peripheral circuit region (PERI) on a second wafer different from the first wafer. 2), and then connecting the upper chip and the lower chip by a bonding method. For example, the bonding method may refer to a method of electrically connecting the bonding metal formed on the uppermost metal layer of the upper chip and the bonding metal formed on the uppermost metal layer of the lower chip to each other. For example, when the bonding metal is formed of copper (Cu), the bonding method may be a Cu-to-Cu bonding method, and the bonding metal may also be formed of aluminum (Al) or tungsten (W).

Each of the peripheral circuit area PERI and the cell area CELL of the nonvolatile memory device 2000 may include an external pad bonding area PA, a word line bonding area WLBA, and a bit line bonding area BLBA. there is.

The peripheral circuit region PERI includes a first substrate 2210, an interlayer insulating layer 2215, a plurality of circuit elements 2220a, 2220b, and 2220c formed on the first substrate 2210, and a plurality of circuit elements 2220a. , 2220b, 2220c) to include first metal layers 2230a, 2230b, and 2230c connected to each other, and second metal layers 2240a, 2240b, and 2240c formed on the first metal layers 2230a, 2230b, and 2230c. can In an embodiment, the first metal layers 2230a, 2230b, and 2230c may be formed of tungsten having a relatively high electrical resistivity, and the second metal layers 2240a, 2240b, and 2240c may be made of copper having a relatively low electrical resistivity. can be formed

In this specification, only the first metal layers 2230a, 2230b, and 2230c and the second metal layers 2240a, 2240b, and 2240c are shown and described, but are not limited thereto, and the second metal layers 2240a, 2240b, and 2240c At least one or more metal layers may be further formed. At least some of the one or more metal layers formed on the second metal layers 2240a, 2240b, and 2240c are made of aluminum having a lower electrical resistivity than copper forming the second metal layers 2240a, 2240b, and 2240c. can be formed

The interlayer insulating layer 2215 covers the plurality of circuit elements 2220a, 2220b, and 2220c, the first metal layers 2230a, 2230b, and 2230c, and the second metal layers 2240a, 2240b, and 2240c on the first substrate. 2210, and may include an insulating material such as silicon oxide, silicon nitride, or the like.

Lower bonding metals 2271b and 2272b may be formed on the second metal layer 2240b of the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 2271b and 2272b of the peripheral circuit area PERI may be electrically connected to the upper bonding metals 2371b and 2372b of the cell area CELL by a bonding method. , The lower bonding metals 2271b and 2272b and the upper bonding metals 2371b and 2372b may be formed of aluminum, copper, or tungsten.

The cell area CELL may provide at least one memory block. The cell region CELL may include a second substrate 2310 and a common source line 2320 . On the second substrate 2310, a plurality of word lines 2331, 2332, 2333, 2334, 2335, 2336, 2337, 2338, and 2330 are provided along the third direction VD perpendicular to the upper surface of the second substrate 2310. ) can be stacked. String select lines and a ground select line may be disposed on upper and lower portions of the word lines 2330 , and a plurality of word lines 2330 may be disposed between the string select lines and the ground select line.

In the bit line bonding area BLBA, the channel structure CH extends in a direction VD perpendicular to the upper surface of the second substrate 2310 to form word lines 2330, string select lines, and ground select lines. can penetrate The channel structure CH may include a data storage layer, a channel layer, and a buried insulating layer, and the channel layer may be electrically connected to the first metal layer 2350c and the second metal layer 2360c. For example, the first metal layer 2350c may be a bit line contact, and the second metal layer 2360c may be a bit line. In one embodiment, the bit line 2360c may extend along the second horizontal direction HD2 parallel to the upper surface of the second substrate 2310 .

In the example of FIG. 31 , a region where the channel structure CH and the bit line 2360c are disposed may be defined as a bit line bonding region BLBA. The bit line 2360c may be electrically connected to the circuit elements 2220c providing the page buffer 2393 in the peripheral circuit area PERI in the bit line bonding area BLBA. For example, the bit line 2360c is connected to upper bonding metals 2371c and 2372c in the peripheral circuit area PERI, and the upper bonding metals 2371c and 2372c are connected to circuit elements 2220c of the page buffer 2393. It may be connected to the connected lower bonding metals 2271c and 2272c.

In the word line bonding area WLBA, the word lines 2330 may extend along a second horizontal direction HD2 perpendicular to the first horizontal direction HD1 and parallel to the upper surface of the second substrate 310. , may be connected to a plurality of cell contact plugs 2341, 2342, 2343, 2344, 2345, 2346, 3347; 3340. The word lines 2330 and the cell contact plugs 2340 may be connected to each other at pads provided by extending different lengths from at least some of the word lines 2330 along the first horizontal direction HD1. . A first metal layer 2350b and a second metal layer 2360b may be sequentially connected to upper portions of the cell contact plugs 2340 connected to the word lines 2330 . The cell contact plugs 2340 are connected to peripheral circuits in the word line bonding area WLBA through the upper bonding metals 2371b and 2372b of the cell area CELL and the lower bonding metals 2271b and 2272b of the peripheral circuit area PERI. It may be connected to the area PERI.

The cell contact plugs 2340 may be electrically connected to circuit elements 2220b forming the address decoder or row decoder 2394 in the peripheral circuit area PERI. In one embodiment, the operating voltage of the circuit elements 2220b forming the row decoder 2394 may be different from the operating voltage of the circuit elements 2220c forming the page buffer 2393. For example, the operating voltage of the circuit elements 2220c forming the page buffer 2393 may be higher than the operating voltage of the circuit elements 2220b forming the row decoder 2394 .

A common source line contact plug 2380 may be disposed in the external pad bonding area PA. The common source line contact plug 2380 is formed of a conductive material such as metal, metal compound, or polysilicon, and may be electrically connected to the common source line 2320 . A first metal layer 2350a and a second metal layer 2360a may be sequentially stacked on the common source line contact plug 2380 . For example, an area where the common source line contact plug 2380, the first metal layer 2350a, and the second metal layer 2360a are disposed may be defined as an external pad bonding area PA.

Meanwhile, input/output pads 2205 and 2305 may be disposed in the external pad bonding area PA. A lower insulating film 2201 covering a lower surface of the first substrate 2210 may be formed under the first substrate 2210, and a first input/output pad 2205 may be formed on the lower insulating film 2201. The first input/output pad 2205 is connected to at least one of the plurality of circuit elements 2220a, 2220b, and 2220c arranged in the peripheral circuit area PERI through the first input/output contact plug 2203, and the lower insulating layer 2201 ) may be separated from the first substrate 2210. In addition, a side insulating layer may be disposed between the first input/output contact plug 2203 and the first substrate 2210 to electrically separate the first input/output contact plug 2203 from the first substrate 2210 .

An upper insulating layer 2301 covering the upper surface of the second substrate 2310 may be formed on the second substrate 2310, and second input/output pads 2305 may be disposed on the upper insulating layer 2301. The second input/output pad 2305 may be connected to at least one of the plurality of circuit elements 2220a, 2220b, and 2220c disposed in the peripheral circuit area PERI through the second input/output contact plug 2303. In one embodiment, the second input/output pad 2305 may be electrically connected to the circuit element 2220a.

Depending on the embodiment, the second substrate 2310 and the common source line 2320 may not be disposed in the region where the second input/output contact plug 2303 is disposed. Also, the second input/output pad 2305 may not overlap the word lines 2380 in the third direction D3. The second input/output contact plug 2303 is separated from the second substrate 2310 in a direction parallel to the top surface of the second substrate 2310, and penetrates the interlayer insulating layer 2315 of the cell region CELL to form the second input/output contact plug. It can be connected to pad 2305.

According to embodiments, the first input/output pad 2205 and the second input/output pad 2305 may be selectively formed. For example, the non-volatile memory device 2000 includes only the first input/output pad 2205 disposed on the first substrate 2201, or the second input/output pad 2205 disposed on the second substrate 2301 ( 2305) may be included. Alternatively, the memory device 2000 may include both the first input/output pad 2205 and the second input/output pad 2305 .

In each of the external pad bonding area PA and the bit line bonding area BLBA included in the cell area CELL and the peripheral circuit area PERI, the metal pattern of the uppermost metal layer exists in a dummy pattern, or The top metal layer may be empty.

In the nonvolatile memory device 2000, in the external pad bonding area PA, the cell area is formed on the uppermost metal layer of the peripheral circuit area PERI corresponding to the upper metal pattern 2372a formed on the uppermost metal layer of the cell area CELL. A lower metal pattern 2273a having the same shape as the upper metal pattern 2372a of the cell may be formed. The lower metal pattern 2273a formed on the uppermost metal layer of the peripheral circuit area PERI may not be connected to a separate contact in the peripheral circuit area PERI. Similarly, in the external pad bonding area PA, the upper metal layer of the cell area CELL corresponds to the lower metal pattern 2273a formed on the uppermost metal layer of the peripheral circuit area PERI. An upper metal pattern 2372a having the same shape as the lower metal pattern 2273a may be formed.

Lower bonding metals 2271b and 2272b may be formed on the second metal layer 2240b of the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 2271b and 2272b of the peripheral circuit area PERI may be electrically connected to the upper bonding metals 2371b and 2372b of the cell area CELL by a bonding method. .

In addition, in the bit line bonding area BLBA, the uppermost metal layer of the cell area CELL corresponds to the lower metal pattern 2252 formed on the uppermost metal layer of the peripheral circuit area PERI. An upper metal pattern 2392 having the same shape as the metal pattern 2252 may be formed. A contact may not be formed on the upper metal pattern 2392 formed on the uppermost metal layer of the cell region CELL.

The aforementioned word line voltages are applied to at least one memory block of the cell area CELL through the lower bonding metals 2271b and 2272b of the peripheral circuit area PERI and the upper bonding metals 2371b and 2372b of the cell area CELL. can be provided.

32 is a block diagram illustrating an electronic system including a semiconductor device according to example embodiments.

Referring to FIG. 32 , the electronic system 3000 may include a semiconductor device 3100 and a controller 3200 electrically connected to the semiconductor device 3100 . The electronic system 3000 may be a storage device including one or a plurality of semiconductor devices 3100 or an electronic device including the storage device. For example, the electronic system 3000 may be a solid state drive (SSD) device including one or a plurality of semiconductor devices 3100, a universal serial bus (USB), a computing system, a medical device, or a communication device. may be a device.

The semiconductor device 3100 may be a non-volatile memory device, and may be, for example, the non-volatile memory device described above with reference to FIGS. 15 to 15, 18, and 27 . The semiconductor device 3100 may include a first structure 3100F and a second structure 3100S on the first structure 3100F. The first structure 3100F may be a peripheral circuit structure including a decoder circuit 3110 , a page buffer circuit 3120 , and a logic circuit 3130 . The second structure 3100S includes a bit line BL, a common source line CSL, word lines WL, first and second gate upper lines UL1 and UL2, and first and second gate lower lines. LL1 and LL2, and memory NAND strings CSTR between the bit line BL and the common source line CSL.

In the second structure 3100S, each of the memory NAND strings CSTR includes lower transistors LT1 and LT2 adjacent to the common source line CSL and upper transistors UT1 adjacent to the bit line BL. UT2), and a plurality of memory cell transistors MCT disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of lower transistors LT1 and LT2 and the number of upper transistors UT1 and UT2 may be variously modified according to embodiments.

In example embodiments, the upper transistors UT1 and UT2 may include string select transistors, and the lower transistors LT1 and LT2 may include ground select transistors. The lower gate lines LL1 and LL2 may be gate electrodes of the lower transistors LT1 and LT2, respectively. The word lines WL may be gate electrodes of the memory cell transistors MCT, and the upper gate lines UL1 and UL2 may be gate electrodes of the upper transistors UT1 and UT2, respectively.

In example embodiments, the lower transistors LT1 and LT2 may include a lower erase control transistor LT1 and a ground select transistor LT2 connected in series. The upper transistors UT1 and UT2 may include a string select transistor UT1 and an upper erase control transistor UT2 connected in series. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT1 may be used for an erase operation of erasing data stored in the memory cell transistors MCT by using the GIDL phenomenon.

The common source line CSL, the first and second lower gate lines LL1 and LL2, the word lines WL, and the first and second upper gate lines UL1 and UL2 have a first structure ( 3100F) may be electrically connected to the decoder circuit 3110 through first connection wires 3115 extending to the second structure 3100S. The bit lines BL may be electrically connected to the page buffer circuit 3120 through second connection lines 3125 extending from the first structure 3100F to the second structure 3100S.

In the first structure 3100F, the decoder circuit 1110 and the page buffer circuit 3120 may execute a control operation on at least one selected memory cell transistor among the plurality of memory cell transistors MCT. The decoder circuit 3110 and the page buffer circuit 3120 may be controlled by the logic circuit 3130 . The semiconductor device 3000 may communicate with the controller 3200 through the input/output pad 3101 electrically connected to the logic circuit 3130 . The input/output pad 3101 may be electrically connected to the logic circuit 3130 through an input/output connection wire 3135 extending from the first structure 3100F to the second structure 3100S.

The controller 3200 may include a processor 3210 , a NAND controller 3220 , and a host interface 1230 . According to example embodiments, the electronic system 3000 may include a plurality of semiconductor devices 3100 , and in this case, the controller 3200 may control the plurality of semiconductor devices 3000 .

The processor 3210 may control the overall operation of the electronic system 3000 including the controller 3200 . The processor 3210 may operate according to predetermined firmware and access the semiconductor device 3100 by controlling the NAND controller 3220 . The NAND controller 3220 may include a NAND interface 3221 that processes communication with the semiconductor device 3100 . Through the NAND interface 3221, a command for controlling the semiconductor device 3100, data to be written to the memory cell transistors MCT of the semiconductor device 1100, and memory cell transistors MCT of the semiconductor device 3100 ), data to be read from can be transmitted. The host interface 3230 may provide a communication function between the electronic system 1000 and an external host. When a control command is received from an external host through the host interface 3230, the processor 1210 may control the semiconductor device 1100 in response to the control command.

A nonvolatile memory device or storage device according to an embodiment of the present invention may be mounted using various types of packages.

As described above, although it has been described with reference to the preferred embodiments of the present invention, those skilled in the art can make the present invention various without departing from the spirit and scope of the present invention described in the claims below. It will be understood that it can be modified and changed accordingly.

Claims (20)

a plurality of cell strings in which a string select transistor, a plurality of memory cells, and a ground select transistor are disposed in series in a vertical direction between a bit line and a source line, and are divided into a plurality of stacks disposed in the vertical direction; Each of the plurality of stacks includes at least one memory block including at least one dummy word line disposed adjacent to a boundary of the plurality of stacks; and
While applying a program voltage to a selected word line of the plurality of cell strings in a program execution period, the at least one upper stack disposed vertically higher than the selected stack to which the selected word line belongs among the plurality of stacks and a control circuit that controls a program operation such that a level of a dummy voltage applied to at least one dummy word line is reduced during the program execution period. According to claim 1,
a voltage generator for generating word line voltages based on the control signal; and
an address decoder providing the word line voltages to the at least one memory block based on a row address;
The control circuit controls the voltage generator and the address decoder based on a command and the row address. According to claim 2,
The control circuit controls the voltage generator and the address decoder to
applying a first dummy voltage to the at least one dummy word line of the at least one upper stack during a first sub-period of the program execution period;
reducing the first dummy voltage to a second dummy voltage in a second sub-period of the program execution period;
Applying a first pass voltage to word lines of the at least one upper stack during the first sub-period and the second sub-period;
and applying the second dummy voltage to the at least one dummy word line of the at least one upper stack during a third sub-period of the program execution period. 4. The method of claim 3, wherein the control circuit controls the voltage generator and the address decoder,
During the third subperiod, a second pass voltage having a level lower than the first pass voltage is applied to the word lines of the at least one upper stack, and the second pass voltage has a level higher than the ground voltage. volatile memory device. 4. The method of claim 3, wherein the control circuit controls the voltage generator and the address decoder,
During the third sub-interval
applying a second pass voltage having a level lower than the first pass voltage to second word lines other than a first word line adjacent to the at least one dummy word line among the word lines of the at least one upper stack; , A third pass voltage having a lower level than the second pass voltage is applied to the first word line, and the level of the second pass voltage is higher than a ground voltage. According to claim 3,
The control circuit controls the voltage generator and the address decoder,
and applying the first pass voltage to unselected word lines of the selected stack during the program execution period. According to claim 3,
Dummy memory cells connected to the at least one dummy word line are turned on in response to the first dummy voltage;
A nonvolatile memory device in which dummy memory cells connected to the at least one dummy word line are turned off in response to the second dummy voltage. According to claim 3,
The first dummy voltage has a level higher than the ground voltage;
The second dummy voltage has a level greater than or equal to the ground voltage and lower than the first dummy voltage. According to claim 2,
The plurality of stacks further include at least one lower stack disposed above a selection stack to which the selected word line belongs among the plurality of stacks in the vertical direction,
The control circuit controls the voltage generator and the address decoder to
applying a first dummy voltage to the at least one dummy word line of the at least one upper stack during a first sub-period of the program execution period;
reducing the first dummy voltage to a second dummy voltage during a second sub-period of the program execution period;
Applying a first pass voltage to word lines of the at least one upper stack during the first sub-period and the second sub-period;
and applying the second dummy voltage to the at least one dummy word line of the at least one upper stack during a third sub-period of the program execution period. 10. The method of claim 9, wherein the control circuit controls the voltage generator and the address decoder,
Applying a second pass voltage having a lower level than the first pass voltage to the word lines of the at least one upper stack during the third subperiod;
Applying the first pass voltage to word lines of the at least one lower stack during the program execution period;
A level of the second pass voltage is higher than a ground voltage. 10. The method of claim 9, wherein the control circuit controls the voltage generator and the address decoder,
During the third sub-interval
applying a second pass voltage having a level lower than the first pass voltage to second word lines other than a first word line adjacent to the at least one dummy word line among the word lines of the at least one upper stack; , a third pass voltage having a level lower than that of the second pass voltage is applied to the first word line,
Applying the first pass voltage to word lines of the at least one lower stack during the program execution period;
A level of the second pass voltage is higher than a ground voltage. According to claim 9,
The control circuit controls the voltage generator and the address decoder,
Applying the first pass voltage to unselected word lines of the selected stack during the program execution period;
and applying the first pass voltage to word lines of the at least one lower stack during the program execution period. According to claim 9,
The control circuit controls the voltage generator and the address decoder,
and applying the first dummy voltage to the at least one dummy word line of the selection stack during the program execution period. According to claim 1,
Dummy memory cells connected to the at least one dummy word line do not store valid data or store single-bit data. According to claim 1,
a memory cell region including the at least one memory block and a first metal pad; and
a peripheral circuit region including the control circuit and a second metal pad and connected to the memory cell region through the second metal pad and the first metal pad;
The peripheral circuit area is
a voltage generator for generating word line voltages based on the control signal; and
an address decoder providing the word line voltages to the at least one memory block based on a row address;
The address decoder applies the program voltage, the dummy voltage, the first voltage, and the negative voltage to the at least one memory block through the second metal pad and the first metal pad. According to claim 1,
a voltage generator for generating word line voltages based on the control signal; and
an address decoder providing the word line voltages to the at least one memory block based on a row address;
the at least one memory block is disposed on a first semiconductor layer;
the control circuit, the voltage generator and the address decoder are disposed on a second semiconductor layer;
The first semiconductor layer and the second semiconductor layer are disposed in the vertical direction of the non-volatile memory device. Dividing at least one memory block including a plurality of cell strings in which a string select transistor, a plurality of memory cells, and a ground select transistor are respectively arranged in series between a bit line and a source line in a vertical direction into a plurality of stacks ( each of the plurality of stacks includes at least one dummy word line disposed adjacent to a boundary of the plurality of stacks);
applying a program voltage to selected word lines of the plurality of cell strings in a program execution period; and
The level of the dummy voltage applied to the at least one dummy word line of at least one upper stack disposed vertically higher than the selected stack to which the selected word line belongs among the plurality of stacks is reduced during the program execution period. A method of programming a non-volatile memory device comprising the step of doing. According to claim 17,
The step of decreasing the level of the dummy voltage in the program execution period
applying a first dummy voltage to the at least one dummy word line of the at least one upper stack during a first sub-period of the program execution period;
reducing the first dummy voltage to a second dummy voltage in a second sub-period of the program execution period;
applying a first pass voltage to word lines of the at least one upper stack during the first sub-period and the second sub-period; and
and applying the second dummy voltage to the at least one dummy word line of the at least one upper stack during a third sub-period of the program execution period. A plurality of cell strings in which a string select transistor, a plurality of memory cells, and a ground select transistor are disposed in series in a vertical direction between a bit line and a source line, respectively, and a plurality of sub blocks smaller than the physical blocks disposed in the vertical direction At least one memory block divided into sub-blocks, each of which includes at least one boundary word line adjacent to another sub-block and internal word lines excluding the at least one boundary word line; and
At least one upper sub block disposed above a selected sub block to which the selected word line belongs among the plurality of sub blocks in the vertical direction while applying a program voltage to a selected word line of the plurality of cell strings in a program execution period. and a control circuit that controls a program operation such that a level of a dummy voltage applied to the at least one boundary word line of a block is reduced during the program execution period. According to claim 19,
a voltage generator for generating word line voltages based on the control signal; and
an address decoder providing the word line voltages to the at least one memory block based on a row address;
The control circuit controls the voltage generator and the address decoder based on a command and the row address to
applying a first dummy voltage to the at least one boundary word line of the at least one upper sub-block during a first sub-period of the program execution period;
reducing the first dummy voltage to a second dummy voltage in a second sub-period of the program execution period;
Applying a first pass voltage to internal word lines of the at least one upper sub-block during the first sub-period and the second sub-period;
and applying the second dummy voltage to the at least one boundary word line of the at least one upper stack during a third sub-period of the program execution period.

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