KR20230088529A - Display device - Google Patents

Abstract

The present invention relates to a display device capable of solving the lack of a space for arranging fan-out wires due to a reduction in an area of a non-display region. The display device according to one embodiment is provided with a plurality of first data wires extending in a second direction intersecting a first direction, a plurality of second data wires extending in the second direction and disposed apart from the plurality of first data wires, a plurality of data connection wires each connected to the plurality of first data wires, a plurality of vertical dummy patterns disposed apart from the plurality of data connection wires and extending in the second direction, and a plurality of horizontal power wires disposed in a display region, extending in the first direction, and having a power supply voltage applied. A first space unit, in which one data connection wire among the plurality of data connection wires and one vertical dummy pattern among the plurality of vertical dummy patterns are arranged apart from each other, overlaps one horizontal power wire among the plurality of horizontal power wires. According to the present invention, even if the area of the non-display region on a lower side of the display panel is reduced, the space for arranging the fan-out wires may not be insufficient.

Description

Display device {DISPLAY DEVICE}

The present invention relates to a display device.

As the information society develops, demands for display devices for displaying images are increasing in various forms. For example, display devices are applied to various electronic devices such as smart phones, digital cameras, notebook computers, navigation devices, and smart televisions.

A display device includes pixels emitting a predetermined light, scan wires for driving the pixels, data wires, power supply wires, a scan driver outputting scan signals to the scan wires, and data voltages to the data wires. A display driving unit for outputting may be further included.

The display device includes a display area including pixels to display an image and a non-display area disposed around the display area. Recently, the area of the non-display area has been minimized in display devices, but due to this, there may be insufficient space in the non-display area for disposing fan-out lines connecting the display driver and data lines.

An object to be solved by the present invention is to provide a display device capable of resolving a lack of arrangement space for fan-out wires due to a decrease in the area of a non-display area.

The tasks of the present invention are not limited to the tasks mentioned above, and other technical tasks not mentioned will be clearly understood by those skilled in the art from the following description.

A display device according to an exemplary embodiment for solving the above problems includes a plurality of first data wires extending in a second direction crossing the first direction, a plurality of first data wires extending in the second direction, and the plurality of first data wires extending in the second direction. a plurality of second data wires disposed apart from the plurality of data wires, a plurality of data connection wires respectively connected to the plurality of first data wires, disposed apart from the plurality of data connection wires and extending in the second direction; and a plurality of vertical dummy patterns disposed in the display area, extending in the first direction, and receiving a power voltage. A first spacer portion in which one data connection wire among the plurality of data connection wires and one vertical dummy pattern among the plurality of vertical dummy patterns is spaced apart overlaps one horizontal power supply wire among the plurality of horizontal power supply wires. do.

A second spaced portion in which another data connection wire among the plurality of data connection wires and another vertical dummy pattern among the plurality of vertical dummy patterns are spaced apart may not overlap the plurality of horizontal power supply wires.

Each of the another data connection wire and the another vertical dummy pattern may include a first wire part having a first width and a second wire part having a second width greater than the first width.

The first separation part may be defined as a gap between the first wiring part of the data connection wire and the first wiring part of the vertical dummy pattern.

The second spacer may be a gap between the first wiring part of the another data connection wire and the second wiring part of the another vertical dummy pattern or the second wiring part of the another data connection wire and the another vertical dummy pattern. It may be defined as a gap between the first wiring parts of

The second separation part may be defined as a gap between the second wiring part of the another data connection wire and the second wiring part of the another vertical dummy pattern.

Each of the plurality of data connection wires may include a first data connection wire extending in the second direction and a second data connection wire extending in the first direction.

The plurality of first data lines, the plurality of second data lines, the plurality of vertical dummy patterns, and the first data connection line may be made of the same material and disposed on the same layer.

The plurality of horizontal power lines and the second data connection line may be made of the same material and disposed on the same layer.

A display device according to an exemplary embodiment for solving the above problems includes a plurality of first horizontal power wires extending in the first direction and to which a first power supply voltage is applied, extending in the first direction, and applying the first power supply voltage. A plurality of second horizontal power lines to which a second power supply voltage higher than the voltage is applied, a plurality of first data lines extending in a second direction crossing the first direction, and extending in the second direction, A plurality of second data wires disposed apart from the first data wires of, a plurality of data connection wires respectively connected to the plurality of first data wires, and disposed apart from the plurality of data connection wires, and a plurality of vertical dummy patterns extending in the second direction. Any one of the plurality of first horizontal power lines is connected to any one of the plurality of vertical dummy patterns.

a plurality of horizontal dummy patterns extending in the first direction, and a plurality of vertical power supply lines extending in the second direction and to which the first power supply voltage is applied, wherein any one of the plurality of vertical power supply lines is provided. One vertical power wire may be connected to any one horizontal dummy pattern among the plurality of horizontal dummy patterns.

A first spacer in which one of the plurality of data connection wires and one of the plurality of vertical dummy patterns are spaced apart from one another of the plurality of second horizontal power supply wires. May overlap with power wiring.

A second spacer portion in which one of the plurality of data connection wires and one of the plurality of vertical dummy patterns is spaced apart may not overlap the plurality of second horizontal power supply wires. .

A display device according to an embodiment for solving the above problems includes a first display area including a first sub display area and a second sub display area, a second display area adjacent to the first display area in a first direction; a plurality of first data lines disposed in the first sub-display area and extending in a second direction crossing the first direction; a plurality of first data lines disposed in the second sub-display area and extending in the second direction first data connection lines, a plurality of second data connection wires disposed in the first sub display area and the second sub display area and extending in the first direction, and the plurality of second data connection lines in the second sub display area and a plurality of first connection holes respectively connecting the first data connection wires of and the plurality of first data connection wires. In the second sub-display area, the plurality of first connection holes are arranged in a first diagonal direction between the first direction and the second direction.

The plurality of first data connection wires and a plurality of second connection holes respectively connected to the plurality of first data wires in the first sub display area are further provided, and the plurality of second connection holes are connected in the first sub display area. The two connection holes may be arranged in a second diagonal direction crossing the first diagonal direction.

The display device may further include a plurality of second data wires disposed in the second sub-display area, extending in the plurality of second directions, and disposed apart from the plurality of first data connection wires.

a third display area adjacent to the first display area in the second direction and including a third sub display area and a fourth sub display area, disposed in the third sub display area and the fourth sub display area; A plurality of first horizontal power lines extending in the first direction and to which a first power voltage is applied, and a plurality of first horizontal power lines extending in the second direction and disposed in the second sub display area and the fourth sub display area. Vertical dummy patterns of may be further provided.

a plurality of first power holes to which the plurality of first horizontal power lines and the plurality of vertical dummy patterns are respectively connected in the fourth sub display area;

In the fourth sub-display area, the plurality of first power holes are arranged in a first diagonal direction between the first direction and the second direction.

A plurality of vertical power lines disposed in the third sub-display area and extending in the second direction, and the plurality of first horizontal power lines and the plurality of vertical power lines in the third sub-display area, respectively. A plurality of second power holes may be further provided, and in the third sub-display area, the plurality of second power holes may be arranged in a second diagonal direction crossing the first diagonal direction.

and a plurality of horizontal dummy patterns disposed in the first sub-display area and the second sub-display area and extending in the first direction, wherein the vertical power lines extend in the second direction in the first sub-display area. and a plurality of third power holes to which the plurality of horizontal dummy patterns and the vertical power wires are respectively connected in the first sub-display area, and wherein the plurality of third power holes are connected in the first sub-display area. Power holes may be arranged in the second diagonal direction.

Other embodiment specifics are included in the detailed description and drawings.

According to the display device according to the exemplary embodiments, a plurality of first data wires disposed on the left and right sides of the display panel are connected to the first fan-out wires through the data connection wires. As a result, the first fan-out wires do not need to be disposed in the lower non-display area of the display panel to be connected to the plurality of first data wires disposed adjacent to the left and right sides of the display area. Therefore, even if the area of the non-display area at the lower side of the display panel is reduced, space for arranging fan-out wires may not be insufficient.

According to the display device according to the exemplary embodiments, the first spacer between the data connection wire and the vertical dummy pattern is disposed to overlap the second horizontal power supply wire, or the second spacer between the data connection wire and the vertical dummy pattern is disposed to overlap the second horizontal power supply wire. By arranging the pixel electrode so that it does not overlap with the power wiring, it is possible to prevent a user from seeing a pattern due to a step in the pixel electrode.

According to the display device according to the embodiments, the second spacer may be formed between the second wiring part having the second width of the first data connection line and the first wiring part having the first width of the vertical dummy pattern, or A spacer is formed between the second wiring part having the first width of the first data connection line and the second wiring part having the second width of the vertical dummy pattern. Alternatively, the second spacer is formed between the second wiring part having the second width of the first data connection line and the second wiring part having the second width of the vertical dummy pattern. Due to this, it is possible to prevent over-etching than originally intended during the etching process.

Effects according to the embodiments are not limited by the contents exemplified above, and more various effects are included in this specification.

1 is a perspective view illustrating a display device according to an exemplary embodiment.
2 is a plan view illustrating a display device according to an exemplary embodiment.
3 is a side view illustrating a display device according to an exemplary embodiment.
FIG. 4 is a layout diagram showing area A of FIG. 2 in detail.
5 is a circuit diagram illustrating a sub-pixel according to an exemplary embodiment.
6 is a circuit diagram illustrating a sub-pixel according to another exemplary embodiment.
FIG. 7 is a layout diagram illustrating an example of the first display area of FIG. 2 .
8 is a layout diagram showing a part of the first sub display area of FIG. 7 in detail.
FIG. 9 is a layout diagram showing a part of the second sub display area of FIG. 7 in detail.
FIG. 10 is an enlarged layout diagram illustrating an example of the first spacer of FIG. 9 in detail.
FIG. 11 is an enlarged layout diagram showing an example of the second spacer of FIG. 9 in detail.
FIG. 12 is an enlarged layout diagram showing still another example of the second spacer of FIG. 9 in detail.
13 is a cross-sectional view illustrating an example of a display panel taken along line AA′ of FIG. 10 .
14 is a cross-sectional view showing a first comparative example of a display panel.
15 is a cross-sectional view showing a second comparative example of a display panel.
16 is a cross-sectional view illustrating an example of a display panel taken along line BB′ of FIG. 10 .
17 is a layout diagram showing an example of the second display area of FIG. 2 in detail.
FIG. 18 is a layout diagram showing a part of the second display area of FIG. 17 in detail.
19 is a layout diagram illustrating an example of the third display area of FIG. 2 .
FIG. 20 is a layout diagram showing a part of the third sub display area of FIG. 19 in detail.
21 is a layout diagram showing a part of the fourth sub display area of FIG. 19 in detail.
22 is a layout diagram showing an example of the sixth display area of FIG. 2 in detail.
23 is a layout diagram showing a part of the sixth display area of FIG. 22 in detail.
24 is a layout diagram showing an example of region B of FIG. 9 in detail.
25 is an enlarged layout diagram showing an example of region B of FIG. 9 in detail.
26 is a cross-sectional view illustrating an example of a display panel taken along line C-C′ of FIGS. 24 and 25 .
27 is a cross-sectional view illustrating an example of a display panel taken along line DD′ of FIG. 25 .
FIG. 28 is a cross-sectional view illustrating an example of a display panel taken along line E-E′ of FIG. 25 .
FIG. 29 is a cross-sectional view illustrating an example of a display panel taken along line F-F′ of FIG. 25 .
30 is a cross-sectional view illustrating an example of a first fan-out wiring, a first bending wiring, and a first pad wiring according to an exemplary embodiment.
31 is a cross-sectional view illustrating an example of a second fan-out wiring, a second bending wiring, and a second pad wiring according to an exemplary embodiment.

Advantages and features of the present invention, and methods of achieving them, will become clear with reference to the detailed description of the following embodiments taken in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, only these embodiments make the disclosure of the present invention complete, and common knowledge in the art to which the present invention belongs. It is provided to fully inform the holder of the scope of the invention, and the present invention is only defined by the scope of the claims.

When an element or layer is referred to as being "on" another element or layer, it includes all cases where another element or layer is directly on top of another element or another layer or other element intervenes therebetween. Like reference numbers designate like elements throughout the specification. The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments are illustrative, and the present invention is not limited thereto.

Although first, second, etc. are used to describe various components, these components are not limited by these terms, of course. These terms are only used to distinguish one component from another. Accordingly, it goes without saying that the first element mentioned below may also be the second element within the technical spirit of the present invention.

Each feature of the various embodiments of the present invention can be partially or entirely combined or combined with each other, technically various interlocking and driving are possible, and each embodiment can be implemented independently of each other or can be implemented together in a related relationship. may be

Hereinafter, specific embodiments will be described with reference to the accompanying drawings.

1 is a perspective view illustrating a display device according to an exemplary embodiment.

Referring to FIG. 1 , a display device 10 is a device that displays moving images or still images, and includes a mobile phone, a smart phone, a tablet personal computer (PC), and a smart watch. ), watch phones, mobile communication terminals, electronic notebooks, electronic books, PMP (portable multimedia player), navigation, UMPC (Ultra Mobile PC), as well as portable electronic devices such as televisions, laptops, monitors, billboards, It can be used as a display screen for various products such as the Internet of Things (IoT).

The display device 10 includes an organic light emitting display using an organic light emitting diode, a quantum dot light emitting display including a quantum dot light emitting layer, an inorganic light emitting display including an inorganic semiconductor, and a micro or nano light emitting diode (micro LED). or nano LED)) may be a light emitting display device such as a subminiature light emitting display device. Hereinafter, the display device 10 has been mainly described as an organic light emitting display device, but the present invention is not limited thereto.

The display device 10 includes a display panel 100 , a display driving circuit 200 , and a circuit board 300 .

The display panel 100 may be formed in a flat rectangular shape having a short side in the first direction DR1 and a long side in the second direction DR2 crossing the first direction DR1 . A corner where the short side of the first direction DR1 and the long side of the second direction DR2 meet may be formed round to have a predetermined curvature or formed at a right angle. The planar shape of the display panel 100 is not limited to a quadrangle and may be formed in a polygonal shape, a circular shape, or an elliptical shape. The display panel 100 may be formed flat, but is not limited thereto. For example, the display panel 100 may include curved portions formed at left and right ends and having a constant curvature or a changing curvature. In addition, the display panel 100 may be formed to be flexible so as to be bent, bent, bent, folded, or rolled.

The substrate SUB of the display panel 100 may include a main area MA and a sub area SBA.

The main area MA may include a display area DA displaying an image and a non-display area NDA that is a peripheral area of the display area DA. The display area DA may include sub-pixels (SPX in FIG. 5 ) displaying an image. The sub area SBA may protrude in the second direction DR2 from one side of the main area MA.

In FIG. 1 , the sub area SBA is unfolded, but the sub area SBA may be bent, and in this case, it may be disposed on the lower surface of the display panel 100 . When the sub area SBA is bent, it may overlap the main area MA in the thickness direction DR3 of the substrate SUB. The display driving circuit 200 may be disposed in the sub area SBA.

The display driving circuit 200 may generate signals and voltages for driving the display panel 100 . The display driving circuit 200 may be formed of an integrated circuit (IC) and attached to the display panel 100 using a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic bonding method. , but not limited thereto. For example, the display driving circuit 200 may be attached on the circuit board 300 using a chip on film (COF) method.

The circuit board 300 may be attached to one end of the sub area SBA of the display panel 100 . Accordingly, the circuit board 300 may be electrically connected to the display panel 100 and the display driving circuit 200 . The display panel 100 and the display driving circuit 200 may receive digital video data, timing signals, and driving voltages through the circuit board 300 . The circuit board 300 may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

2 is a plan view illustrating a display device according to an exemplary embodiment. 3 is a side view illustrating a display device according to an exemplary embodiment.

2 illustrates that the sub area SBA is unfolded without being bent. 3 illustrates that the sub area SBA is bent to the lower surface of the display device 10 .

Referring to FIGS. 2 and 3 , the display panel 100 may include a main area MA and a sub area SBA.

The main area MA may include a display area DA displaying an image and a non-display area NDA that is a peripheral area of the display area DA. The display area DA may occupy most of the main area MA. The display area DA may be disposed at the center of the main area MA.

The display area DA may include first to sixth display areas DA1 , DA2 , DA3 , DA4 , DA5 , and DA6 . Each of the first display area DA1 and the fourth display area DA4 is an area where first data lines connected to data fan-out lines through data connection lines are disposed. The second display area DA2 and the sixth display area DA6 may be areas in which second data lines directly connected to the data fan-out lines are disposed. The third display area DA3 and the fifth display area DA5 may be areas in which first horizontal power lines extending in the first direction DR1 and power holes connecting the first vertical power lines are disposed.

The first display area DA1 and the third display area DA3 are disposed on the left side of the display area DA, and the fourth display area DA4 and the fifth display area DA5 are disposed on the right side of the display area DA. can be placed in The first display area DA1 may be disposed below the third display area DA3, and the fourth display area DA4 may be disposed below the fifth display area DA5. The second display area DA2 may be disposed between the first display area DA1 and the fourth display area DA4. The sixth display area DA6 may be disposed between the third and fifth display areas DA3 and DA5.

The length of the first display area DA1 in the first direction DR1 may be substantially the same as the length of the third display area DA3 in the first direction DR1. Also, the length of the first display area DA1 in the second direction DR2 may be shorter than the length of the third display area DA3 in the second direction DR2.

The length of the first display area DA1 in the first direction DR1 may be longer than the length of the second display area DA2 in the first direction DR1. The length of the first display area DA1 in the second direction DR2 may be substantially the same as the length of the second display area DA2 in the second direction DR2 .

The length of the third display area DA3 in the first direction DR1 may be longer than the length of the second display area DA2 in the first direction DR1. The length of the third display area DA3 in the second direction DR2 may be longer than the length of the second display area DA2 in the second direction DR2.

The length of the fourth display area DA4 in the first direction DR1 may be substantially the same as the length of the fifth display area DA5 in the first direction DR1. Also, the length of the fourth display area DA4 in the second direction DR2 may be shorter than the length of the fifth display area DA5 in the second direction DR2.

The length of the fourth display area DA4 in the first direction DR1 may be longer than the length of the second display area DA2 in the first direction DR1. The length of the fourth display area DA4 in the second direction DR2 may be substantially the same as the length of the second display area DA2 in the second direction DR2 .

The length of the fifth display area DA5 in the first direction DR1 may be greater than the length of the sixth display area DA6 in the first direction DR1. The length of the fifth display area DA5 in the second direction DR2 may be substantially the same as the length of the sixth display area DA6 in the second direction DR2.

The length of the first display area DA1 in the first direction DR1 may be substantially the same as the length of the fourth display area DA4 in the first direction DR1. Also, the length of the second direction DR2 of the first display area DA1 may be substantially the same as that of the second direction DR2 of the fourth display area DA4 .

The length of the second display area DA2 in the first direction DR1 may be substantially the same as the length of the sixth display area DA6 in the first direction DR1. Also, the length of the second display area DA2 in the second direction DR2 may be smaller than the length of the sixth display area DA6 in the second direction DR2.

The length of the third display area DA3 in the first direction DR1 may be substantially the same as the length of the fifth display area DA5 in the first direction DR1. Also, the length of the third display area DA3 in the second direction DR2 may be substantially the same as the length of the fifth display area DA5 in the second direction DR2.

For example, when the display area DA includes 1080×2340 pixels, the first display area DA1 and the third display area DA3 include 488×2340 pixels, and the second display area ( DA2) may include 104×2340 pixels, and the fourth display area DA4 and the fifth display area DA5 may include 488×2340 pixels.

A detailed description of the first display area DA1 will be described later with reference to FIG. 7 , a detailed description of the second display area DA2 will be described later with reference to FIG. 17 , and a detailed description of the third display area DA3 will be described later. A description will be given later with reference to FIG. 19 .

The non-display area NDA may be disposed adjacent to the display area DA. The non-display area NDA may be an area outside the display area DA. The non-display area NDA may be disposed to surround the display area DA. The non-display area NDA may be an edge area of the display panel 100 .

The sub area SBA may protrude in the second direction DR2 from one side of the main area MA. The length of the second direction DR2 of the sub area SBA may be smaller than the length of the second direction DR2 of the main area MA. The length of the sub area SBA in the first direction DR1 is smaller than the length of the main area MA in the first direction DR1 or substantially equal to the length of the main area MA in the first direction DR1. can do. The sub area SBA may be bent and may be disposed under the display panel 100 . In this case, the sub area SBA may overlap the main area MA in the third direction DR3 .

The sub area SBA may include a connection area CA, a pad area PA, and a bending area BA.

The connection area CA is an area protruding in the second direction DR2 from one side of the main area MA. The connection area CA may be disposed between the non-display area NDA and the bending area BA of the main area MA in the second direction DR2 .

The pad area PA is an area where the pads PD and the display driving circuit 200 are disposed. The display driving circuit 200 may be attached to the driving pads of the pad area PA using a conductive adhesive such as an anisotropic conductive film. The circuit board 300 may be attached to the pads PD of the pad area PA using a conductive adhesive member such as an anisotropic conductive film.

The bending area BA is a bending area. When the bending area BA is bent, the pad area PA may be disposed under the connection area CA and under the main area MA. The bending area BA may be disposed between the connection area CA and the pad area PA in the second direction DR2 .

As shown in FIG. 3 , the display panel 100 may include a thin film transistor layer (TFTL), a light emitting element layer (EML), an encapsulation layer (TFEL), and a touch sensing unit (TDU).

The substrate SUB may be made of an insulating material such as a polymer resin. For example, the substrate SUB may be made of polyimide. The substrate SUB may be a flexible substrate capable of being bent, folded, or rolled.

A thin film transistor layer TFTL may be disposed on the substrate SUB. The thin film transistor layer TFTL may be disposed in the main area MA and the sub area SBA. The thin film transistor layer TFTL includes thin film transistors.

The light emitting element layer EML may be disposed on the thin film transistor layer TFTL. The light emitting element layer EML may be disposed in the display area DA of the main area MA. The light emitting element layer EML includes light emitting elements disposed in the light emitting units.

The encapsulation layer TFEL may be disposed on the light emitting element layer EML. The encapsulation layer TFEL may be disposed in the display area DA and the non-display area NDA of the main area MA. The encapsulation layer TFEL includes at least one inorganic layer and at least one organic layer for encapsulating the light emitting element layer.

The touch sensing unit TDU may be disposed on the encapsulation layer TFEL. The touch sensing unit TDU may be disposed in the display area DA and the non-display area NDA of the main area MA. The touch sensing unit TDU may sense a touch of a person or object using touch electrodes.

A cover window for protecting an upper portion of the display panel 100 may be disposed on the touch sensing unit TDU. The cover window may be attached on the touch sensing unit TDU by a transparent adhesive member such as an optically clear adhesive (OCA) film or an optically clear resin (OCR). The cover window may be an inorganic material such as glass or an organic material such as plastic or polymer material.

In addition, in order to prevent deterioration in visibility of an image displayed by the display panel 100 due to external light being reflected by the display panel 100, an anti-reflection member is additionally disposed between the touch sensing unit TDU and the cover window. It can be. The antireflection member may be a polarizing film. Alternatively, the anti-reflection member may include a light-blocking organic layer such as a black matrix and a color filter, or may include a light-blocking organic layer such as a black matrix and an anti-reflection organic layer.

The touch driving circuit 400 may be disposed on the circuit board 300 . The touch driving circuit 400 may be formed as an integrated circuit (IC) and attached to the circuit board 300 .

The touch driving circuit 400 may be electrically connected to a plurality of driving electrodes and a plurality of sensing electrodes of the touch sensing unit TDU. The touch driving circuit 400 applies a touch driving signal to a plurality of driving electrodes, and detects a touch sensing signal of each of a plurality of touch nodes, for example, a charge change amount of mutual capacitance, through a plurality of sensing electrodes. The touch driving circuit 400 may determine whether or not a user touches and whether or not the touch is approached according to a touch detection signal of each of a plurality of touch nodes. The user's touch refers to direct contact of a user's finger or an object such as a pen with the front surface of the display device 10 disposed on the touch sensing unit TDU. Proximity of the user refers to an object such as a user's finger or a pen being positioned apart from the front surface of the display device 10, such as hovering.

FIG. 4 is a layout diagram showing area A of FIG. 2 in detail. 4 illustrates the first display area DA1, the second display area DA2, the fourth display area DA4, the non-display area NDA, and the sub area SBA in detail.

Referring to FIG. 4 , a plurality of first data lines DL1, a plurality of second data lines DL2, a plurality of data connection lines DCL, and a plurality of first vertical power lines VPL1 are It may be disposed in the first display area DA1.

The plurality of first data lines DL1 may extend in the second direction DR2 and be disposed in the first direction DR1. The plurality of second data lines DL2 may extend in the second direction DR2 and may be disposed in the first direction DR1. The plurality of data connection lines DCL may include a first data connection line DCL1 and a second data connection line DCL2 . The plurality of first vertical power lines VPL1 may extend in the second direction DR2 and be disposed in the first direction DR1.

The first data connection line DCL1 may extend in the second direction DR2 and be connected to the first fan-out line FL1 through the third connection hole CH3. The second data connection line DCL2 may extend in the first direction DR1 and be connected to the first data connection line DCL1 through the first connection hole CH1.

Each of the plurality of first data lines DL1 may be connected to the second data connection line DCL2 through the second connection hole CH2. Each of the plurality of second data lines DL2 may be connected to the second fan-out line FL2 through the fourth connection hole CH4. Each of the plurality of first vertical power lines VPL1 may be connected to the first power line PL1.

A plurality of second data lines DL2 and a plurality of first vertical power lines VPL1 may be disposed in the second display area DA2.

The first fan-out lines FL1 , the second fan-out lines FL2 , the first power lines PL1 , and the second power lines PL2 may be disposed in the non-display area NDA. Each of the first fan-out lines FL1 may be connected to the first data connection line DCL1 through the third connection hole CH3. Each of the second fan-out lines FL2 may be connected to the second data line DL2 through the fourth connection hole CH4.

Among the first power lines PL1 , the first power line PL1 disposed in the center may be connected to the plurality of first vertical power lines VPL1 . Among the first power wires PL1 , the first power wires PL1 disposed on the left and right sides may be disposed to surround the second power wires PL2 . The second power lines PL2 may be arranged to surround the display area DA. A first power supply voltage may be applied to each of the first power supply wires PL1 , and a second power supply voltage higher than the first power supply voltage may be applied to each of the second power supply wires PL2 .

First bending lines BL1 , second bending lines BL2 , third bending lines BL3 , and fourth bending lines BL4 may be disposed in the bending area BA. Each of the first bending lines BL1 may have a fifth connection hole CH5 connected to the first fan-out line FL1. Each of the second bending lines BL2 may be connected to the second fan-out line FL2 through the sixth connection hole CH6. Each of the third bending lines BL3 may be connected to the first power line PL1 , and each of the fourth bending lines BL4 may be connected to the second power line PL2 .

The first pad lines PDL1 , the second pad lines PDL2 , the first power pad lines PPL1 , and the second power pad lines PPL2 may be disposed in the pad area PA. Each of the first pad lines PDL1 may be connected to the first bending line BL1 through the seventh connection hole CH7 . Each of the second pad lines PDL2 may be connected to the second bending line BL2 through the eighth connection hole CH8 . The first power pad lines PPL1 may be connected to the third bending lines BL3, and the second power pad lines PPL2 may be connected to the fourth bending lines BL4.

The first pad wires PDL1 and the second pad wires PDL2 may be electrically connected to the display driving circuit 200 . The first power pad wires PPL1 and the second power pad wires PPL2 may be directly connected to the pads PD. The display driving circuit 200 may be connected to the pads PD through the third pad wires PDL3 .

As shown in FIG. 4 , the plurality of first data lines DL1 disposed on the left and right sides of the display panel 100 are connected to the first fan-out lines FL1 through the data connection lines DCL. As a result, the first fan-out lines FL1 are connected to the plurality of first data lines DL1 disposed adjacent to the left and right sides of the display area DA, so that the lower side of the display panel 100 is not displayed. It does not need to be placed in the area NDA. Therefore, even if the area of the non-display area NDA on the lower side of the display panel 100 is reduced, the space for disposing the fan-out lines FL1 and FL2 may not be insufficient.

5 is a circuit diagram illustrating sub-pixels of a display layer according to an exemplary embodiment.

Referring to FIG. 5 , the sub-pixel SPX may be connected to at least one of scan lines GWL, GIL, GCL, and GBL, one of light emitting lines EL, and one of data lines. . For example, the sub-pixel SPX includes a write scan line GWL, an initialization scan line GIL, a control scan line GCL, a bias scan line GBL, a light emitting line EL, and a data line DL. can be connected to.

The sub-pixel SPX includes a light emitting element LE and a pixel driver PDU. The pixel driver PDU includes a driving transistor DT, switch elements, and a capacitor C1. The switch elements include first to sixth transistors ST1 , ST2 , ST3 , ST4 , ST5 , and ST6 .

The driving transistor DT includes a gate electrode, a first electrode, and a second electrode. The driving transistor DT controls a drain-to-source current (Ids, hereinafter referred to as “driving current”) flowing between the first electrode and the second electrode according to the data voltage applied to the gate electrode.

The light emitting element LEL emits light according to the driving current Ids. The amount of light emitted from the light emitting element LEL may be proportional to the driving current Ids.

The light emitting element LEL may be an organic light emitting diode including an anode electrode, a cathode electrode, and an organic light emitting layer disposed between the anode electrode and the cathode electrode. Alternatively, the light emitting element LEL may be an inorganic light emitting element including an anode electrode, a cathode electrode, and an inorganic semiconductor disposed between the anode electrode and the cathode electrode. Alternatively, the light emitting element LEL may be a quantum dot light emitting element including an anode electrode, a cathode electrode, and a quantum dot light emitting layer disposed between the anode electrode and the cathode electrode. Alternatively, the light emitting element LEL may be a micro light emitting diode.

The anode electrode of the light emitting element LEL may be connected to the first electrode of the fourth transistor ST4 and the second electrode of the sixth transistor ST6, and the cathode electrode may be connected to the low potential line VSL. A parasitic capacitance Cel may be formed between the anode electrode and the cathode electrode of the light emitting element LEL.

The capacitor C1 is formed between the second electrode of the driving transistor DT and the high potential line VSL. One electrode of the capacitor C1 may be connected to the second electrode of the driving transistor DT, and the other electrode may be connected to the high potential wire VSL.

As shown in FIG. 5 , the first to sixth transistors ST1 , ST2 , ST3 , ST4 , ST5 , and ST6 and the driving transistor DT may all be formed of P-type MOSFETs. An active layer of each of the first to sixth transistors ST1 , ST2 , ST3 , ST4 , ST5 , and ST6 and the driving transistor DT may be formed of polysilicon or an oxide semiconductor.

A gate electrode of the second transistor ST2 may be connected to the write scan line GWL, and a gate electrode of the first transistor ST1 may be connected to the control scan line GCL. A gate electrode of the third transistor ST3 may be connected to the initialization scan line GIL, and a gate electrode of the fourth transistor ST4 may be connected to the bias scan line GBL. Since the first to sixth transistors ST1 , ST2 , ST3 , ST4 , ST5 , and ST6 are formed of P-type MOSFETs, the control scan line GCL, the initial scan line GIL, the write scan line GWL, and the bias When the scan signal and the light emitting signal of the gate low voltage are applied to the scan line GBL and the light emitting line EL, respectively, they may be turned on.

One electrode of the third transistor ST3 is connected to the first initialization voltage line VIL, while one electrode of the fourth transistor ST4 is connected to the second initialization voltage line VAIL. The first initialization voltage applied to the first initialization voltage line VIL and the second initialization voltage applied to the second initialization voltage line VAIL may be different voltages.

Alternatively, as shown in FIG. 6, the driving transistor DT, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 are formed of P-type MOSFETs, and the first The transistor ST1 and the third transistor ST3 may be formed of N-type MOSFETs. An active layer of each of the driving transistor DT, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 formed of a P-type MOSFET is formed of polysilicon. , An active layer of each of the first transistor ST1 and the third transistor ST3 formed of an N-type MOSFET may be formed of an oxide semiconductor. In this case, since the transistors formed of polysilicon and the transistors formed of oxide semiconductor may be disposed on different layers, the arrangement area of each transistor in the pixel PX may be reduced.

Since the first transistor ST1 and the third transistor ST3 are formed of N-type MOSFETs, the first transistor ST1 is turned on when the control scan signal of the gate high voltage is applied to the control scan line GCL. , the third transistor ST3 may be turned on when an initialization scan signal is applied to the initialization scan line GIL. In contrast, since the second transistor ST2 , the fourth transistor ST4 , the fifth transistor ST5 , and the sixth transistor ST6 are formed of P-type MOSFETs, the write scan wire GWL and the light emitting wire EL ) may be turned on when a scan signal and a light emitting signal of the gate low voltage are applied to each of the gate low voltages.

Alternatively, in FIG. 6 , the fourth transistor ST4 may be formed of an N-type MOSFET. In this case, the active layer of each of the fourth transistors ST4 may be formed of an oxide semiconductor. When the fourth transistor ST4 is formed of an N-type MOSFET, it may be turned on when a bias scan signal having a gate high voltage is applied to the bias scan line GBL.

Alternatively, although not shown in FIGS. 5 and 6 , the first to sixth transistors ST1 , ST2 , ST3 , ST4 , ST5 , and ST6 and the driving transistor DT may all be formed of N-type MOSFETs.

FIG. 7 is a layout diagram illustrating an example of the first display area of FIG. 2 . 8 is a layout diagram showing a part of the first sub display area of FIG. 7 in detail. FIG. 9 is a layout diagram showing a part of the second sub display area of FIG. 7 in detail.

7 to 9 , the first display area DA1 includes a first sub display area SDA1 and a second sub display area SDA2. The first sub display area SDA1 is an area in which first connection holes CH1 to which the first data connection lines DCL1 and the second data connection lines DCL2 are respectively connected are disposed, and the second sub display area ( SDA2 is an area where second connection holes CH2 to which the second data connection lines DCL2 and the first data lines DL1 are respectively connected are disposed.

A plurality of first data lines DL1 and a plurality of first vertical power lines VPL1 are disposed in the first sub display area SDA1, and a plurality of second data lines DL2 and a first data connection line DCL1 and a plurality of vertical dummy patterns VDP may be disposed in the second sub display area SDA2. Also, the second data connection lines DCL2 and the plurality of horizontal dummy patterns HDP may be disposed in the first sub display area SDA1 and the second sub display area SDA2.

In the first sub-display area SDA1, the plurality of first data lines DL1 and the plurality of first vertical power lines VPL1 may be alternately disposed in the first direction DR1. That is, the first vertical power line VPL1 is disposed between the first data lines DL1 adjacent to each other in the first direction DR1, and the first vertical power lines VPL1 are adjacent to each other in the first direction DR1. A first data line DL1 may be disposed between VPL1 ).

In the second sub display area SDA2 , the plurality of second data lines DL2 and the first data connection lines DCL1 may be alternately disposed in the first direction DR1 . That is, the first data connection lines DCL1 are disposed between the second data lines DL2 adjacent to each other in the first direction DR1, and the first data connection lines (DL2) adjacent to each other in the first direction DR1 ( A second data line DL2 may be disposed between DCL1 ).

Also, in the second sub-display area SDA2, the plurality of second data lines DL2 and the plurality of vertical dummy patterns VDP may be alternately disposed in the first direction DR1. That is, the vertical dummy patterns VDP are disposed between second data lines DL2 adjacent to each other in the first direction DR1, and between the vertical dummy patterns VDP adjacent to each other in the first direction DR1. A second data line DL2 may be disposed on .

Each of the first data line DL1 , the first vertical power line VPL1 , the second data line DL2 , and the first data connection line DCL1 is smaller than the first wiring parts having the first width and the first width. Second wiring parts having a large second width may be included. The first wire parts and the second wire parts may be alternately disposed in the second direction DR2 . Some of the second wiring parts may overlap the second data connection line DCL2 or the horizontal dummy pattern HDP, and others may not overlap the second data connection line DCL2 or the horizontal dummy pattern HDP.

The plurality of second horizontal power lines HPL2 may extend in the first direction DR1 and may be disposed in the second direction DR2. A second power voltage higher than the first power voltage may be applied to the plurality of second horizontal power lines HPL2 . The first power supply voltage may be a low potential voltage, and the second power supply voltage may be a high potential voltage.

The plurality of second data connection lines DCL2 may extend in the first direction DR1 and may be disposed in the second direction DR2. In the first display area DA1, the plurality of second horizontal power lines HPL2 and the plurality of second data connection lines DCL2 may be alternately disposed in the second direction DR2. That is, the second data connection wires DCL2 are disposed between the second horizontal power lines HPL2 adjacent to each other in the second direction DR2, and the second data connection wires adjacent to each other in the second direction DR2. A second horizontal power line HPL2 may be disposed between DCL2 .

The plurality of horizontal dummy patterns HDP may extend in the first direction DR1 and may be disposed in the second direction DR2. In the first display area DA1, the plurality of second horizontal power lines HPL2 and the plurality of horizontal dummy patterns HDP may be alternately disposed in the second direction DR2. That is, the horizontal dummy patterns HDP are disposed between the second horizontal power lines HPL2 adjacent to each other in the second direction DR2, and the horizontal dummy patterns HDP are adjacent to each other in the second direction DR2. A second horizontal power line HPL2 may be disposed between them.

Each of the second data connection line DCL2 and the horizontal dummy pattern HDP may include third wiring parts having a third width and fourth wiring parts having a fourth width greater than the third width. The third wire parts and the fourth wire parts may be alternately disposed in the first direction DR1 . Each of the fourth wiring parts may overlap the first data line DL1 , the first vertical power line VPL1 , the second data line DL2 , or the first data connection line DCL1 .

Each of the first data connection lines DCL1 may be respectively connected to the second data connection lines DCL2 through the first connection hole CH1. Each of the plurality of first data lines DL1 may be connected to the second data connection line DCL2 through the second connection hole CH2. The first connection holes CH1 may be arranged in the first diagonal direction DD1 in the second sub display area SDA2 . The second connection holes CH2 may be arranged in the second diagonal direction DD2 in the first sub display area SDA1.

Each of the plurality of first vertical power lines VPL1 may be connected to the horizontal dummy pattern HDP through the first power hole PH1. For this reason, the first power voltage may be applied to each of the plurality of horizontal dummy patterns HDP. The first power holes PH1 may be arranged in the second diagonal direction DD2 in the first sub display area SDA1.

One of the first data connection lines DCL1 and a vertical dummy pattern VDP adjacent thereto may be spaced apart from each other. The first spacer SU1 between the first data connection line DCL1 and the vertical dummy pattern VDP adjacent thereto may overlap the second horizontal power supply line HPL2. A description of the first spacer unit SU1 will be described later with reference to FIG. 10 .

Also, among the first data connection lines DCL1 , another first data connection line DCL1 and a vertical dummy pattern VDP adjacent thereto may be spaced apart from each other. The second spacer SU2 between the another first data connection line DCL1 and the vertical dummy pattern VDP adjacent thereto may not overlap the second horizontal power supply line HPL2. A description of the second spacer unit SU2 will be described later with reference to FIGS. 11 and 12 .

Also, the second data connection line DCL2 and the horizontal dummy pattern HDP adjacent thereto may be spaced apart from each other. The third spacer SU3 between the second data connection line DCL2 and the horizontal dummy pattern HDP adjacent thereto is disposed between the adjacent first data line DL1 and the first vertical power supply line VPL1. or disposed between the second data line DL2 and the first data connection line DCL1 adjacent to each other.

Meanwhile, since the fourth display area DA4 is symmetrical to the first display area DA1 with respect to the second display area DA2, a detailed description of the fourth display area DA4 is omitted.

FIG. 10 is an enlarged layout diagram illustrating an example of the first spacer of FIG. 9 in detail.

Referring to FIG. 10 , the first spacer SU1 is disposed between the first data connection line DCL1 and the vertical dummy pattern VDP adjacent thereto, and forms a gap overlapping the second horizontal power supply line HPL2. point The first spacer SU1 includes a first wiring part WP1 having a first width Wwp1 of the first data connection line DCL1 and a first width Wwp1 of the vertical dummy pattern VDP. It may be a gap between the wiring parts WP1.

The length Lsu1 of the first spacer SU1 in the second direction DR2 may be smaller than the width WWhpl2 of the second horizontal power line HPL2. The width Whpl2 of the second horizontal power line HPL2 may be the length of the second horizontal power line HPL2 in the second direction DR2.

FIG. 11 is an enlarged layout diagram showing an example of the second spacer of FIG. 9 in detail.

Referring to FIG. 11 , the second spacer SU2 is disposed between the first data connection line DCL1 and the vertical dummy pattern VDP adjacent thereto, and has a gap that does not overlap the second horizontal power supply line HPL2. points to The second spacer SU2 includes a first wiring part WP1 having a first width Wwp1 of the first data connection line DCL1 and a second width Wwp2 of the vertical dummy pattern VDP. It may be a gap between the wiring parts WP2, but the embodiment of the present specification is not limited thereto. The second spacer SU2 includes a second wiring part WP2 having the second width Wwp2 of the first data connection line DCL1 and a first width Wwp1 of the vertical dummy pattern VDP. It may be a gap between the wiring parts WP2.

The second spacer SU2 may be formed by removing a pattern connecting the first data connection line DCL1 and the vertical dummy pattern VDP through an etching process. At this time, since the second wire part WP2 of the first data connection wire DCL1 has a thicker width than the first wire part WP1, the second spacer SU2 is used as the width of the first data connection wire DCL1. In the case of forming the gap between the first wiring part WP1 and the second wiring part WP2 of the vertical dummy pattern VDP, it is possible to prevent over-etching during the etching process. In addition, since the second wiring part WP2 of the vertical dummy pattern VDP also has a wider width than the first wiring part WP1, the second spacer SU2 is used as the second wiring part of the first data connection line DCL1. In the case of forming the gap between the wiring part WP2 and the first wiring part WP1 of the vertical dummy pattern VDP, it is possible to prevent over-etching during the etching process.

FIG. 12 is an enlarged layout diagram showing still another example of the second spacer of FIG. 9 in detail.

The second spacer SU2 shown in FIG. 12 includes the second wiring part WP2 having the second width Wwp2 of the first data connection line DCL1 and the second width Wwp2 of the vertical dummy pattern VDP. ) is different from the embodiment of FIG. 11 in that it is a gap between the second wire parts WP2.

The second spacer SU2 may be formed by removing a pattern connecting the first data connection line DCL1 and the vertical dummy pattern VDP through an etching process. At this time, the second wire part WP2 of the first data connection wire DCL1 has a wider width than the first wire part WP1, and the second wire part WP2 of the vertical dummy pattern VDP also has a first wire part. Since it has a wider width than the part WP1, the second spacer SU2 is connected to the first wiring part WP1 of the first data connection line DCL1 and the second wiring part WP2 of the vertical dummy pattern VDP. In the case of forming a gap therebetween, it may be easier to prevent over-etching than originally intended during an etching process.

13 is a cross-sectional view illustrating an example of a display panel taken along line AA′ of FIG. 10 . 14 is a cross-sectional view showing a first comparative example of a display panel. 15 is a cross-sectional view showing a second comparative example of a display panel. 16 is a cross-sectional view illustrating an example of a display panel taken along line BB′ of FIG. 10 .

13 to 15 , the thin film transistor layer TFTL is disposed on the substrate SUB, the first planarization layer 160 is disposed on the thin film transistor layer TFTL, and the first planarization layer 160 ), the second horizontal power line HPL2 may be disposed on. A second planarization layer 161 may be disposed on the second horizontal power line HPL2 , and a first data connection line DCL1 and a vertical dummy pattern VDP may be disposed on the second planarization layer 161 . . A third planarization layer 162 may be disposed on the first data connection line DCL1 and the vertical dummy pattern VDP, and a pixel electrode 171 may be disposed on the third planarization layer 162 .

In this case, the flatness of the third planarization layer 162 may be affected by a step difference between the second horizontal power line HPL2 and a step difference between the first data connection line DCL1 and the vertical dummy pattern VDP. For this reason, the pixel electrode 171 disposed on the first spacer SU1 may also have a step.

As shown in FIG. 13 , when the second horizontal power line HPL2 overlaps the first spacer SU1 , the pixel electrode 171 may have a first level difference h1 . In contrast, as shown in FIG. 14 , when the second horizontal power line HPL2 partially overlaps the first spacer SU1, the pixel electrode 171 has a second level difference h2 greater than the first level difference h1. can have In addition, as shown in FIG. 15 , when the second horizontal power line HPL2 does not overlap the first spacer SU1 but is disposed adjacent to the first spacer SU1, the pixel electrode 171 is disposed adjacent to the second spacer SU1. It may have a third level difference h3 greater than the level difference h2.

As shown in FIG. 16 , when the second horizontal power line HPL2 does not overlap the first spacer SU1, the pixel electrode 171 may have a fourth step h4. The fourth level difference h4 may be smaller than the second level difference h2 or the third level difference h3.

As the level difference between the pixel electrodes 171 increases, when external light is reflected from the display panel 100 , a pattern caused by the level difference between the pixel electrodes 171 may be recognized by a user. As shown in FIG. 13, the first spacer SU1 is disposed to overlap the second horizontal power line HPL2, or as shown in FIG. 16, the second spacer SU2 is not overlapped with the second horizontal power line HPL2. By arranging the pixel electrode 171, it is possible to prevent a pattern due to a level difference from being visually recognized by a user.

17 is a layout diagram showing an example of the second display area of FIG. 2 in detail. FIG. 18 is a layout diagram showing a part of the second display area of FIG. 17 in detail.

17 and 18 , the second display area DA2 is an area where the first vertical power lines VPL1 are connected to the horizontal dummy patterns HDP through the second power holes PH2.

The second data lines DL2 and the first vertical power lines VPL1 may be alternately disposed in the first direction DR1 . That is, the first vertical power line VPL1 is disposed between the second data lines DL2 adjacent to each other in the first direction DR1, and the first vertical power lines VPL1 are adjacent to each other in the first direction DR1. A second data line DL2 may be disposed between VPL1 ).

Each of the second data line DL2 and the first vertical power line VPL1 includes first wiring parts having a first width W1 and second wiring parts having a second width W2 greater than the first width. can do. The first wire parts and the second wire parts may be alternately disposed in the second direction DR2 . Some of the second wiring parts may overlap the horizontal dummy pattern HDP, and others may not overlap the horizontal dummy pattern HDP.

The plurality of second horizontal power lines HPL2 may extend in the first direction DR1 and may be disposed in the second direction DR2. A second power voltage may be applied to the plurality of second horizontal power lines HPL2 .

The plurality of horizontal dummy patterns HDP may extend in the first direction DR1 and may be disposed in the second direction DR2. In the first display area DA1, the plurality of second horizontal power lines HPL2 and the plurality of horizontal dummy patterns HDP may be alternately disposed in the second direction DR2. That is, the horizontal dummy patterns HDP are disposed between the second horizontal power lines HPL2 adjacent to each other in the second direction DR2, and the horizontal dummy patterns HDP are adjacent to each other in the second direction DR2. A second horizontal power line HPL2 may be disposed between them.

The horizontal dummy pattern HDP may include third wire parts having a third width and fourth wire parts having a fourth width greater than the third width. The third width may be substantially equal to the first width Wwp1 , and the fourth width may be substantially equal to the second width Wwp2 . The third wire parts and the fourth wire parts may be alternately disposed in the first direction DR1 . Each of the fourth wiring parts may overlap the second data line DL2 or the first vertical power line VPL1.

Each of the plurality of first vertical power lines VPL1 may be connected to the horizontal dummy pattern HDP through the second power hole PH2. Although FIG. 17 illustrates that the second power supply holes PH2 are arranged in the first diagonal direction DD1 , the exemplary embodiment of the present specification is not limited thereto. For example, the second power holes PH2 may be arranged in the second diagonal direction DD2. Alternatively, the second power supply holes PH2 may be arranged in the first diagonal direction DD1 and then in the second diagonal direction DD2. That is, the second power holes PH2 may be arranged in a “>” shape. Alternatively, the second power holes PH2 may be arranged in the second diagonal direction DD2 and then in the first diagonal direction DD1. That is, the second power holes PH2 may be arranged in a “<” shape. Alternatively, the second power holes PH2 may be arranged in a repeated pattern other than “>” and “<”.

19 is a layout diagram illustrating an example of the third display area of FIG. 2 . FIG. 20 is a layout diagram showing a part of the third sub display area of FIG. 19 in detail. 21 is a layout diagram showing a part of the fourth sub display area of FIG. 19 in detail.

19 to 21 , the third display area DA3 includes a third sub display area SDA3 and a fourth sub display area SDA4. The third sub display area SDA3 is an area where the fourth power holes PH4 to which the first horizontal power lines HPL1 and the first vertical power lines VPL1 are respectively connected are disposed, and the fourth sub display area ( SDA4) is an area where fifth power holes PH5 to which the first horizontal power lines HPL1 and the vertical dummy patterns VDP are respectively connected are disposed.

The plurality of first data lines DL1 and the plurality of first vertical power lines VPL1 are disposed in the third sub display area SDA3, and the plurality of second data lines DL2 and the plurality of vertical dummy patterns (VDP) may be arranged in the fourth sub display area SDA4.

In the third sub-display area SDA3 , the plurality of first data lines DL1 and the plurality of first vertical power lines VPL1 may be alternately disposed in the first direction DR1 . That is, the first vertical power line VPL1 is disposed between the first data lines DL1 adjacent to each other in the first direction DR1, and the first vertical power lines VPL1 are adjacent to each other in the first direction DR1. A first data line DL1 may be disposed between VPL1 ).

In the fourth sub display area SDA4 , a plurality of second data lines DL2 and a plurality of vertical dummy patterns VDP may be alternately disposed in the first direction DR1 . That is, the vertical dummy patterns VDP are disposed between second data lines DL2 adjacent to each other in the first direction DR1, and between the vertical dummy patterns VDP adjacent to each other in the first direction DR1. A second data line DL2 may be disposed on .

Each of the first data line DL1, the first vertical power line VPL1, and the second data line DL2 includes first wiring parts having a first width W1 and a second width W2 greater than the first width. It may include second wiring parts having a. The first wire parts and the second wire parts may be alternately disposed in the second direction DR2 . Some of the second wiring parts may overlap the first horizontal power line HPL1, and others may not overlap the first horizontal power line HPL1.

The plurality of second horizontal power lines HPL2 may extend in the first direction DR1 and may be disposed in the second direction DR2. A second power voltage may be applied to the plurality of second horizontal power lines HPL2 .

The first horizontal power line HPL1 may include third wiring parts having a third width W3 and fourth wiring parts having a fourth width W4 greater than the third width. The third wire parts and the fourth wire parts may be alternately disposed in the first direction DR1 . Each of the fourth wiring parts may overlap the first data line DL1 , the first vertical power supply line VPL1 , or the second data line DL2 .

Each of the first vertical power lines VPL1 may be respectively connected to the first horizontal power lines HPL1 through the fourth power hole PH4. Each of the vertical dummy patterns VDP may be respectively connected to the first horizontal power lines HPL1 through the fifth power hole PH5.

In FIG. 19 , the fourth power holes PH4 are arranged in the second diagonal direction DD2 and the fifth power holes PH5 are arranged in the first diagonal direction DD1, so that the fourth power holes PH4 and It is exemplified that the fifth power supply holes PH5 are repeatedly arranged in a “∨” shape. However, the embodiments of the present specification are not limited thereto. For example, the fourth power holes PH4 are arranged in a first diagonal direction DD1 and the fifth power holes PH5 are arranged in a second diagonal direction DD2, so that the fourth power holes PH4 and the fifth power hole PH5 may be repeatedly arranged in a “∧” shape. Alternatively, the fourth power supply holes PH4 and the fifth power supply holes PH5 may be arranged in a repeated pattern other than “∨” and “∧”.

Meanwhile, since the fifth display area DA5 is symmetrical to the third display area DA3 with respect to the sixth display area DA6, a detailed description of the fifth display area DA5 will be omitted.

22 is a layout diagram showing an example of the sixth display area of FIG. 2 in detail. 23 is a layout diagram showing a part of the sixth display area of FIG. 22 in detail.

22 and 23 , the sixth display area DA6 is an area where the first vertical power lines VPL1 are connected to the first horizontal power lines HPL1 through the sixth power holes PH6.

The second data lines DL2 and the first vertical power lines VPL1 may be alternately disposed in the first direction DR1 . That is, the first vertical power line VPL1 is disposed between the second data lines DL2 adjacent to each other in the first direction DR1, and the first vertical power lines VPL1 are adjacent to each other in the first direction DR1. A second data line DL2 may be disposed between VPL1 ).

Each of the second data line DL2 and the first vertical power line VPL1 includes first wiring parts having a first width W1 and second wiring parts having a second width W2 greater than the first width. can do. The first wire parts and the second wire parts may be alternately disposed in the second direction DR2 . Some of the second wiring parts may overlap the first vertical power line VPL1, and others may not overlap the first vertical power line VPL1.

The plurality of second horizontal power lines HPL2 may extend in the first direction DR1 and may be disposed in the second direction DR2. A second power voltage may be applied to the plurality of second horizontal power lines HPL2 .

The plurality of first vertical power lines VPL1 may extend in the first direction DR1 and may be disposed in the second direction DR2. In the first display area DA1 , the plurality of second horizontal power lines HPL2 and the plurality of first vertical power lines VPL1 may be alternately disposed in the second direction DR2 . That is, the first vertical power lines VPL1 are disposed between the second horizontal power lines HPL2 adjacent to each other in the second direction DR2, and the first vertical power lines HPL2 adjacent to each other in the second direction DR2. A second horizontal power line HPL2 may be disposed between the VPL1s.

The first vertical power line VPL1 may include third wiring parts having a third width W3 and fourth wiring parts having a fourth width W4 greater than the third width. The third wire parts and the fourth wire parts may be alternately disposed in the first direction DR1 . Each of the fourth wiring parts may overlap the second data line DL2 or the first vertical power line VPL1.

Each of the plurality of first vertical power lines VPL1 may be connected to the first horizontal power line HPL1 through the sixth power hole PH6. Although FIG. 22 illustrates that the sixth power holes PH6 are arranged in the first diagonal direction DD1, the exemplary embodiment of the present specification is not limited thereto. For example, the sixth power holes PH6 may be arranged in the second diagonal direction DD2. Alternatively, the sixth power holes PH6 may be arranged in the first diagonal direction DD1 and then in the second diagonal direction DD2. That is, the sixth power holes PH6 may be arranged in a “>” shape. Alternatively, the sixth power holes PH6 may be arranged in the second diagonal direction DD2 and then in the first diagonal direction DD1. That is, the sixth power holes PH6 may be arranged in a “<” shape. Alternatively, the sixth power holes PH6 may be arranged in a repeated pattern other than ">" and "<".

24 is a layout diagram showing an example of region B of FIG. 9 in detail. 25 is an enlarged layout diagram showing an example of region B of FIG. 9 in detail.

24 shows a first active layer, a first gate layer, a second gate layer, and a first source-drain layer of the pixel driving unit PDU, and FIG. 25 shows the first active layer and the second gate layer of the pixel driving unit PDU. A first gate layer, a second gate layer, a first source drain layer, a second source drain layer, and a third source drain layer are shown.

24 and 25 , scan write lines GWL, scan initialization lines GIL, scan bias lines GBL, and light emitting lines EL may extend in a first direction DR1. there is. In addition, the first horizontal initialization lines HVIL, the second horizontal initialization lines HVAIL, the second horizontal power line HPL2, the horizontal driving voltage lines HVDL, and the second data connection lines DCL2 It may extend in the first direction DR1.

The first vertical initialization lines VVIL, the second vertical initialization lines VVAIL, and the vertical driving voltage lines VVDL may extend in the second direction DR2 . Also, the second data lines DL, the first data connection lines DCL1 , and the vertical dummy patterns VDP may extend in the second direction DR2 .

The pixel driving unit PDU may include a driving transistor DT, first to sixth transistors ST1 to ST6, a capacitor CST, and connection electrodes CE1 to CE6. The first transistor ST1 may include a 1-1st transistor ST1-1 and a 1-2th transistor ST1-2. The third transistor ST3 may include a 3-1st transistor ST3-1 and a 3-2nd transistor ST3-2.

The driving transistor DT may include a channel layer DTCH, a gate electrode DTG, a first electrode DTS, and a second electrode DTD. The channel layer DTCH of the driving transistor DT may overlap the gate electrode DTG of the driving transistor DT. The gate electrode DTG of the driving transistor DT may be disposed on the channel layer DTCH of the driving transistor DT.

The gate electrode DTG of the driving transistor DT may be connected to the first connection electrode CE1 through the first contact hole CT1. The first connection electrode BE1 may be connected to the second electrode D2 of the first-second transistor ST1-2 through the second contact hole CT2. The first connection electrode CE1 may cross the kth scan control line GCLk.

The first electrode DTS of the driving transistor DT may be connected to the second electrode D2 of the second transistor ST2 and the second electrode D5 of the fifth transistor ST5.

The second electrode DTD of the driving transistor DT may be connected to the first electrode S1-1 of the 1-1st transistor ST1-1 and the first electrode S6 of the sixth transistor ST6. .

The 1-1st transistor ST1-1 may include a channel layer CH1-1, a gate electrode G1-1, a first electrode S1-1, and a second electrode D1-1. . The channel layer CH1-1 of the 1-1st transistor ST1-1 may overlap the gate electrode G1-1 of the 1-1st transistor ST1-1. The gate electrode G1-1 of the 1-1st transistor ST1-1 may be integrally formed with the scan write line GWL. The gate electrode G1 - 1 of the 1-1st transistor ST1 - 1 may be a part of the scan write line GWL. The first electrode S1 - 1 of the 1-1st transistor ST1 - 1 may be connected to the second electrode DTD of the driving transistor DT. The second electrode D1-1 of the 1-1st transistor ST1-1 may be connected to the first electrode S1-2 of the 1-2th transistor ST1-2.

The first-second transistor ST1-2 may include a channel layer CH1-2, a gate electrode G1-2, a first electrode S1-2, and a second electrode D1-2. . The channel layer CH1 - 2 of the first and second transistor ST1 - 2 may overlap the gate electrode G1 - 2 of the first and second transistor ST1 - 2 . The gate electrode G1 - 2 of the first-second transistor ST1 - 2 may be integrally formed with the scan write line GWL. The gate electrode G1 - 2 of the first-second transistor ST1 - 2 may protrude from the scan write line GWL in the second direction DR2 . The first electrode S1-2 of the 1-2nd transistor ST1-2 may be connected to the second electrode D1-1 of the 1-1st transistor ST1-1. The second electrode D1 - 2 of the 1 - 2 transistor ST1 - 2 may be connected to the first connection electrode CE1 .

The second transistor ST2 may include a channel layer CH2, a gate electrode G2, a first electrode S2, and a second electrode D2. The channel layer CH2 of the second transistor ST2 may overlap the gate electrode G2 of the second transistor ST2. The gate electrode G2 of the second transistor ST2 may be integrally formed with the scan write line GWL. The gate electrode G2 of the second transistor ST2 may be a part of the scan write line GWL. The first electrode S1 of the second transistor ST2 may be connected to the second connection electrode BE2 through the fourth contact hole CT4. The second electrode D2 of the second transistor ST2 may be connected to the first electrode DTS of the driving transistor DT.

The 3-1st transistor ST3-1 may include a channel layer CH3-1, a gate electrode G3-1, a first electrode S3-1, and a second electrode D3-1. . The channel layer CH3-1 of the 3-1 transistor ST3-1 may overlap the gate electrode G3-1 of the 3-1 transistor ST3-1. The gate electrode G3 - 1 of the 3-1st transistor ST3 - 1 may be integrally formed with the scan initialization line GIL. The gate electrode G3 - 1 of the 3-1st transistor ST3 - 1 may be a part of the scan initialization line GIL. The first electrode S3 - 1 of the 3-1 transistor ST3 - 1 may be connected to the first connection electrode CE1 . The second electrode D3-1 of the 3-1st transistor ST3-1 may be connected to the first electrode S3-2 of the 3-2nd transistor ST3-2.

The 3-2nd transistor ST3-2 may include a channel layer CH3-2, a gate electrode G3-2, a first electrode S3-2, and a second electrode D3-2. . The channel layer CH3-2 of the 3-2nd transistor ST3-2 may overlap the gate electrode G3-2 of the 3-2nd transistor ST3-2. The gate electrode G3 - 2 of the 3 - 2nd transistor ST3 - 2 may be integrally formed with the scan initialization line GIL. The gate electrode G3 - 2 of the 3-2nd transistor ST3 - 2 may be a part of the scan initialization line GIL. The first electrode S3-2 of the 3-2 transistor ST3-2 may be connected to the second electrode D3-1 of the 3-1 transistor ST3-1. The second electrode D3 - 2 of the 3 - 2nd transistor ST3 - 2 may be connected to the first vertical initialization line VVIL through the second initialization contact hole VICH2 .

The fourth transistor ST4 may include a channel layer CH4 , a gate electrode G4 , a first electrode S4 , and a second electrode D4 . The channel layer CH4 of the fourth transistor ST4 may overlap the gate electrode G4 of the fourth transistor ST4. The gate electrode G4 of the fourth transistor ST4 may be integrally formed with the scan bias line GBL. The gate electrode G4 of the fourth transistor ST4 may be a part of the scan bias line GBL. The kth scan bias wire may be a k+1th scan initialization wire. The first electrode S4 of the fourth transistor ST4 may be connected to the third connection electrode CE3 through the seventh contact hole CH7. The second electrode D4 of the fourth transistor ST4 may be connected to the second vertical initialization line VVAIL through the fourth initialization contact hole VACH2.

The fifth transistor ST5 may include a channel layer CH5, a gate electrode G5, a first electrode S5, and a second electrode D5. The channel layer CH5 of the fifth transistor ST5 may overlap the gate electrode G5 of the fifth transistor ST5. The gate electrode G5 of the fifth transistor ST5 may be integrally formed with the light emitting line EML. The gate electrode G5 of the fifth transistor ST5 may be a part of the light emitting line EML. The first electrode S5 of the fifth transistor ST5 may be connected to the vertical driving voltage line VVDL through the sixth contact hole CT6. The second electrode D5 of the fifth transistor ST5 may be connected to the first electrode DTS of the driving transistor DT.

The sixth transistor ST6 may include a channel layer CH6, a gate electrode G6, a first electrode S6, and a second electrode D6. The channel layer CH6 of the sixth transistor ST6 may overlap the gate electrode G6 of the sixth transistor ST6. The gate electrode G6 of the sixth transistor ST6 may be integrally formed with the light emitting line EML. The gate electrode G6 of the sixth transistor ST6 may be a part of the light emitting wiring. The first electrode S6 of the sixth transistor ST6 may be connected to the second electrode DTD of the driving transistor DT. The second electrode D6 of the sixth transistor ST6 may be connected to the third connection electrode CE3 through the seventh contact hole CH7.

The first electrode CAE1 of the capacitor CST may be integrally formed with the gate electrode DTG of the driving transistor DT. The first electrode CAE1 of the capacitor CST may be a part of the gate electrode DTG of the driving transistor DT. The second electrode CAE2 of the capacitor CST may be integrally formed with the horizontal driving voltage line HVDL. The second electrode CAE2 of the capacitor CST may be part of the horizontal driving voltage line HVDL. The second electrode CAE2 of the capacitor CST may overlap the first electrode CAE1 of the capacitor CST. The horizontal driving voltage line HVDL may be connected to the vertical driving voltage line VVDL through the fifth contact hole CT5 .

The first connection electrode CE1 is connected to the gate electrode DTG of the driving transistor DT through the first contact hole CT1 and is connected to the first and second transistors ST1-2 through the second contact hole CT2. ) and the first electrode S3-1 of the 3-1 transistor ST3-1. The first connection electrode CE1 may extend in the second direction DR2. The first connection electrode CE1 may overlap the scan write line GWL and the horizontal driving voltage line HVDL.

The second connection electrode CE2 may be connected to the first electrode S2 of the second transistor ST2 through the fourth contact hole CT4. The fourth connection electrode CE4 may be connected to the second connection electrode CE2 through the tenth contact hole CT10. The second data line DL2 may be connected to the fourth connection electrode CE4 through the eleventh contact hole CT11.

The third connection electrode CE3 may be connected to the second electrode D6 of the sixth transistor ST6 through the seventh contact hole CT7. The fifth connection electrode CE5 may be connected to the third connection electrode CE3 through the eighth contact hole CT8. The sixth connection electrode CE6 may be connected to the fifth connection electrode CE5 through the ninth contact hole CT9.

The shielding electrode SHE may be connected to the vertical driving voltage line VVDL through the third contact hole CT3. The shielding electrode SHE may overlap the second electrode D1-2 of the 1-1st transistor ST1-1 and the first electrode S1-2 of the 1-2nd transistor ST1-2. . Also, the shielding electrode SHE may overlap the first electrode S3 - 1 of the 3-1st transistor ST3 - 1 .

The first horizontal initialization wire HVIL and the second horizontal initialization wire HVAIL may extend in the first direction DR1 . The first horizontal initialization wire HVIL and the second horizontal initialization wire HVAIL may be alternately disposed in the second direction DR2 .

The first vertical initialization wire VVIL and the second vertical initialization wire VVAIL may extend in the second direction DR2 . The first vertical initialization wire VVIL and the second vertical initialization wire VVAIL may be alternately disposed in the second direction DR2 .

The first vertical initialization wire VVIL may be connected to the first horizontal initialization wire HVIL through the first initialization contact hole VICH1. The first vertical initialization line VVIL may be connected to the second electrode D3 - 2 of the third transistor ST3 - 2 through the second initialization contact hole VICH2 .

The second vertical initialization wire VVAIL may be connected to the second horizontal initialization wire HVAIL through the third initialization contact hole VACH1. The second vertical initialization line VVAIL may be connected to the second electrode D4 of the fourth transistor ST4 through the fourth initialization contact hole VICH4.

A first initialization voltage is applied to the first horizontal initialization line HVIL and the first vertical initialization line VVIL, and a second initialization voltage is applied to the second horizontal initialization line HVAIL and the second vertical initialization line VVAIL. It can be.

The first data connection line DCL1 may be connected to the second data connection line DCL2 through the first connection hole CH1.

The first spacer SU1 is disposed between the first data connection line DCL1 and the vertical dummy pattern VDP, and may overlap the second horizontal power supply line HPL2. Also, the first spacer SU1 may overlap the horizontal driving voltage line HVDL and the second electrode DTD of the driving transistor DT.

26 is a cross-sectional view illustrating an example of a display panel taken along line C-C′ of FIGS. 24 and 25 . 27 is a cross-sectional view illustrating an example of a display panel taken along line DD′ of FIG. 25 . FIG. 28 is a cross-sectional view illustrating an example of a display panel taken along line E-E′ of FIG. 25 . FIG. 29 is a cross-sectional view illustrating an example of a display panel taken along line F-F′ of FIG. 25 .

Referring to FIGS. 26 to 28 , a thin film transistor layer TFTL may be disposed on the substrate SUB. The thin film transistor layer TFTL may be a layer on which the driving transistor DT of each of the pixel driving units PDU1 to PDU4, the first to sixth transistors ST1 to ST6, and the capacitor CST are formed.

The display panel 100 includes a substrate SUB, an active layer ACT, a first gate layer GTL1 , a second gate layer GTL2 , a first data metal layer DTL1 , a second data metal layer DTL2 , and A third data metal layer DTL3 is included. In addition, the display panel 100 includes a buffer layer BF, a gate insulating layer 130 , a first interlayer insulating layer 141 , a second interlayer insulating layer 142 , a first planarization layer 160 , and a second planarization layer 161 . ), and a third planarization layer 162 .

A buffer layer BF may be disposed on one surface of the substrate SUB. The buffer film BF may be formed on one surface of the substrate SUB to protect the thin film transistors and the organic light emitting layer 172 of the light emitting element layer EML from moisture penetrating through the substrate SUB, which is vulnerable to moisture permeation. there is. The buffer layer BF may include a plurality of inorganic layers alternately stacked. For example, the buffer layer BF may be formed of a multilayer in which at least one inorganic layer of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer is alternately stacked. The buffer layer BF may be omitted.

An active layer ACT may be disposed on the buffer layer BF. The active layer ACT may include a silicon semiconductor such as polycrystalline silicon, single crystal silicon, low-temperature polycrystalline silicon, and amorphous silicon.

The active layer ACT may include the channel layer DTCH of the driving transistor DT, the first electrode DTS, and the second electrode DTD. The channel layer DTCH of the driving transistor DT may overlap the gate electrode DTG of the driving transistor DT in the third direction DR3 , which is the thickness direction of the substrate SUB. The first electrode DTS of the driving transistor DT may be disposed on one side of the channel layer DTCH, and the second electrode DTD may be disposed on the other side of the channel layer DTCH. The first electrode DTS and the second electrode DTD of the driving transistor DT may be an area that does not overlap with the gate electrode DTG in the third direction DR3 . The first electrode DTS and the second electrode DTD of the driving transistor DT may be conductive regions by doping silicon semiconductor with ions or impurities.

In addition, the active layer ACT includes channel layers CH1 and CH4 to CH6 of the first and fourth to sixth transistors ST1 and ST4 to ST6, first electrodes S1 and S4 to S6, and Second electrodes D1 and D4 to D6 may be further included. Each of the channel layers CH1 and CH4 to CH6 of the first to sixth transistors ST1 and ST4 to ST6 has a corresponding gate electrode among the gate electrodes G1 and G4 to G6 in the third direction DR3. can overlap with The first electrodes S1 and S4 to S6 and the second electrodes D1 and D4 to D6 of the first to sixth transistors ST1 to ST6 are conductive regions by doping silicon semiconductors with ions or impurities. can be

A gate insulating layer 130 may be disposed on the active layer ACT. The gate insulating layer 130 may be formed of an inorganic layer, such as a silicon nitride layer, a silicon oxy nitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

A first gate layer GTL1 may be disposed on the gate insulating layer 130 . The first gate layer GTL1 may include the gate electrode DTG of the driving transistor DT. In addition, the first gate layer GTL1 includes the gate electrodes G1 to G6 of the first to sixth transistors ST1 to ST6, the first capacitor electrode CAE1, scan write lines GWL, and scan initialization. It may further include lines GIL, scan bias lines GBL, and light emitting lines EL. The first gate layer GTL1 may include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Or it may be formed of a single layer or multiple layers made of alloys thereof.

A first interlayer insulating layer 141 may be disposed on the first gate layer GTL1. The first interlayer insulating layer 141 may be formed of an inorganic layer, such as a silicon nitride layer, a silicon oxy nitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

A second gate layer GTL2 may be disposed on the first interlayer insulating layer 141 . The second gate layer GTL2 includes a second capacitor electrode CAE2, a shielding electrode SHE, a horizontal driving voltage line HVDL, a first horizontal initialization line HVIL, and a second horizontal initialization line HVAIL. can do. The second gate layer GTL2 may include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Or it may be formed of a single layer or multiple layers made of alloys thereof.

A second interlayer insulating layer 142 may be disposed on the second gate layer GTL2 . The second interlayer insulating layer 142 may be formed of an inorganic layer, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

First to third connection electrodes CE1 , CE2 , CE3 , a vertical driving voltage line VVDL, a first vertical initialization line VVIL, and a second vertical initialization line VVAIL are formed on the second interlayer insulating layer 142 . A first data metal layer DTL1 including may be disposed. The first data metal layer DTL1 may include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Or it may be formed of a single layer or multiple layers made of alloys thereof.

The first connection electrode CE1 may be connected to the gate electrode DTG of the driving transistor DT through the first contact hole CT1 penetrating the first interlayer insulating film 141 and the second interlayer insulating film 142 . . The first connection electrode CE1 is connected to the first and second transistors ST1- through the second contact hole CT2 penetrating the gate insulating layer 130 , the first interlayer insulating layer 141 , and the second interlayer insulating layer 142 . 2) may be connected to the second electrode D1-2 and the first electrode S3-1 of the 3-1 transistor ST3-1. The second connection electrode CE2 is connected to the first electrode S2 of the second transistor ST2 through the fourth contact hole CT4 penetrating the first interlayer insulating film 141 and the second interlayer insulating film 142 . can The third connection electrode CE3 is connected to the sixth transistor ST6 through the seventh contact hole CT7 penetrating the gate insulating layer 130 , the first interlayer insulating layer 141 , and the second interlayer insulating layer 142 . It may be connected to the second electrode D6.

The vertical driving voltage line VVIL may be connected to the shielding electrode SHE through the third contact hole CT3 penetrating the second interlayer insulating layer 142 . The vertical driving voltage line VVIL may be connected to the horizontal driving voltage line HVIL through the fifth contact hole CT5 penetrating the second interlayer insulating layer 142 . The vertical driving voltage line VVIL is formed through the sixth contact hole CT6 penetrating the gate insulating layer 130 , the first interlayer insulating layer 141 , and the second interlayer insulating layer 142 to form the fifth transistor ST5 . 1 may be connected to the electrode S5. Accordingly, the second power supply voltage may be applied to the shielding electrode SHE, the horizontal driving voltage line HVIL, and the first electrode S5 of the fifth transistor ST5.

On the first data metal layer DTL1, a first planarization layer for flattening a level difference caused by the active layer ACT, the first gate layer GTL1, the second gate layer GTL2, and the first data metal layer DTL1 is formed. (160) may be formed. The first planarization layer 160 is formed of an organic layer such as acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. It can be.

A second data metal layer DTL2 may be formed on the first planarization layer 160 . The second data metal layer DTL2 may include a fourth connection electrode CE4 , a fifth connection electrode CE5 , second data connection lines DCL2 , and second horizontal power lines HPL2 . Also, the second data metal layer DTL2 may further include first horizontal power lines HPL1 and horizontal dummy patterns HDP. The second data metal layer DTL2 may include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Or it may be formed of a single layer or multiple layers made of alloys thereof.

The fourth connection electrode CE4 may be connected to the second connection electrode CE2 through the tenth contact hole CT10 penetrating the first planarization layer 160 . The fifth connection electrode CE5 may be connected to the third connection electrode CE3 through the eighth contact hole CT8 penetrating the first planarization layer 160 . The first horizontal power line HPL1 may be connected to the vertical driving voltage line VVDL through the twelfth contact hole CT12 penetrating the first planarization layer 160 .

A second planarization layer 161 may be formed on the second data metal layer DTL2 to flatten the level difference. The second planarization layer 161 is formed of an organic layer such as acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. It can be.

A third data metal layer DTL3 may be formed on the second planarization layer 161 . The third data metal layer DTL3 may include a sixth connection electrode CE6 , second data lines DL2 , first data connection lines DCL1 , and vertical dummy patterns VDP. Also, the third data metal layer DTL3 may further include first data lines DL1 and first vertical power lines VPL1. The third data metal layer DTL3 may include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Or it may be formed of a single layer or multiple layers made of alloys thereof.

The sixth connection electrode CE6 may be connected to the fifth connection electrode CE5 through the ninth contact hole CT9 penetrating the second planarization layer 161 . The second data line DL2 may be connected to the fourth connection electrode CE4 through the eleventh contact hole CT11 penetrating the second planarization layer 161 .

The first data connection line DCL1 may be connected to the second data connection line DCL2 through the first connection hole CH1 penetrating the second planarization layer 161 . The first data line DL1 may be connected to the second data connection line DCL2 through the second connection hole CH2 penetrating the second planarization layer 161 . The first vertical power line VPL1 forms the horizontal dummy pattern HDP through the first power hole PH1, the second power hole PH2, or the third power hole PH3 penetrating the second planarization layer 161. can be connected to The first vertical power line VPL1 may be connected to the first horizontal power line HPL1 through the fourth power hole PH4 or the sixth power hole PH6 penetrating the second planarization layer 161 . The vertical dummy pattern VDP may be connected to the first horizontal power line HPL1 through the fifth power hole PH5 penetrating the second planarization layer 161 .

A third planarization layer 162 may be formed on the third data metal layer DTL3 to flatten the level difference. The third planarization layer 162 is formed of an organic layer such as acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. It can be.

Light emitting devices 170 and a bank 180 may be disposed on the third planarization layer 162 . Each of the light emitting elements 170 may include a pixel electrode 171 , an organic light emitting layer 172 , and a common electrode 173 . The light emitting elements LE may share a common electrode 173 .

The pixel electrode 171 of each of the light emitting elements 170 may be formed on the third planarization layer 162 . The pixel electrode 171 of each of the light emitting elements LE may be connected to the sixth connection electrode CE6 through the pixel contact hole ANCT penetrating the third planarization layer 162 . The pixel electrode 171 of each of the light emitting elements 170 may include a stacked structure of aluminum and titanium (Ti/Al/Ti), a stacked structure of aluminum and ITO (ITO/Al/ITO), an APC alloy, or an APC alloy and ITO. It may be formed of a metal material having high reflectivity, such as a stacked structure (ITO/APC/ITO). An APC alloy is an alloy of silver (Ag), palladium (Pd), and copper (Cu).

The bank 180 may be a pixel defining layer or a light emitting portion defining layer defining the light emitting units EA. The bank 180 may partition the light emitting units EA. In each of the light emitting units EA, a pixel electrode 171, an organic light emitting layer 172, and a common electrode 173 are sequentially stacked so that holes from the pixel electrode 171 and electrons from the common electrode 173 are organically This indicates a region that is recombinated in the light emitting layer 172 and emits light.

The bank 180 may be formed to cover an edge of the pixel electrode 171 of each of the light emitting elements 170 . The bank 180 may be formed of an organic layer such as acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. .

An organic light emitting layer 172 is formed on the pixel electrode 171 of each of the light emitting elements 170 . The organic emission layer 172 may emit light of a predetermined color by including an organic material. For example, the organic emission layer 172 may include a hole transporting layer, an organic material layer, and an electron transporting layer.

The common electrode 173 may be disposed on the organic emission layer 172 and the bank 180 . The common electrode 173 may be formed to cover the organic emission layer 172 . The common electrode 173 may be formed in common with the light emitting units EA. A capping layer may be formed on the common electrode 173 .

In the top emission structure, the common electrode 173 is formed of a transparent conductive material (TCO) capable of transmitting light, such as ITO or IZO, or magnesium (Mg), silver (Ag), or magnesium (Mg) and silver. It may be formed of a semi-transmissive conductive material such as an alloy of (Ag). When the common electrode 173 is formed of a transflective metal material, light emission efficiency of each of the light emitting units ELU1 , ELU2 , ELU3 , and ELU4 may be increased by a micro cavity.

An encapsulation layer TFE may be formed on the light emitting elements 170 . The encapsulation layer TFE may include at least one inorganic layer to prevent penetration of oxygen or moisture into the light emitting element layer EML. Also, the encapsulation layer TFE may include at least one organic layer to protect the light emitting element layer EML from foreign substances such as dust.

Meanwhile, in the exemplary embodiments of FIGS. 24 to 29 , the display panel 100 includes the third data metal layer DTL3, but the third data metal layer DTL3 may be omitted from the display panel 100. . In this case, the second data connection lines DCL2 and the second horizontal power line HPL2 are formed to be included in the first data metal layer DTL1, and the first data lines DL1 and the second data line DL2 ), first data connection lines DCL1 , vertical dummy patterns VDP, and first vertical power lines VPL1 may be formed to be included in the second data metal layer DTL2 .

30 is a cross-sectional view illustrating an example of a first fan-out wiring, a first bending wiring, and a first pad wiring according to an exemplary embodiment. 31 is a cross-sectional view illustrating an example of a second fan-out wiring, a second bending wiring, and a second pad wiring according to an exemplary embodiment.

30 and 31 , the first gate metal layer GTL1 further includes first fan-out lines FL1 and first pad lines PDL1, and the second gate metal layer GTL2 includes a second fan. Out wires FL2 and second pad wires PDL2 may be further included. The first fan-out wires FL1 and the second fan-out wires FL2 may be alternately disposed in the first direction DR1. The first pad wires PDL1 and the second pad wires PDL2 may be alternately disposed in the first direction DR1 .

The second power line PL2 may include a first sub power line SPL1 and a second sub power line SPL2. The second sub power line SPL2 may cover the first sub power line SPL1. The second sub power line SPL2 may contact an upper surface of the first sub power line SPL1.

The pad electrode PDE may include a first pad electrode PDE1 and a second pad electrode PDE2. The second pad electrode PDE2 may cover the first pad electrode PDE1. The second pad electrode PDE2 may contact the upper surface of the first pad electrode PDE1.

The first data metal layer DTL1 includes a first sub power supply line SPL1, a bending connection electrode BCE, and a first pad electrode PDE1, and the second data metal layer DTL2 includes a second sub power supply line ( SPL2 ), a first bending line BL1 , a second bending line BL2 , and a second pad electrode PDE2 .

The bending connection electrode BCE is connected to the first fan-out wire FL1 through a contact hole penetrating the first interlayer insulating film 141 and the second interlayer insulating film 142 or penetrates the second interlayer insulating film 142. may be connected to the second fan-out wire FL2 through a contact hole formed thereon. The first bending line BL1 may be connected to the bending connection electrode BCE connected to the first fan-out line FL1 through the fifth connection hole CH5. The first bending line BL1 may be connected to the bending connection electrode BCE connected to the first pad line PDL1 through the seventh connection hole CH7 . The second bending line BL2 may be connected to the bending connection electrode BCE connected to the second fan-out line FL2 through the sixth connection hole CH6 . The second bending line BL2 may be connected to the bending connection electrode BCE connected to the second pad line PDL2 through the eighth connection hole CH8 .

The first pad electrode PDE is connected to the first pad line PDL1 through a contact hole penetrating the first interlayer insulating film 141 and the second interlayer insulating film 142 or penetrates the second interlayer insulating film 142 . may be connected to the second pad line PDL2 through a contact hole formed thereon. The second pad electrode PDE2 may be connected to the bump BMP of the display driving circuit 200 through a conductive adhesive member ACF such as an anisotropic conductive film. The conductive adhesive member ACF may include a conductive ball CB.

Although the embodiments of the present invention have been described with reference to the accompanying drawings, those skilled in the art to which the present invention pertains can be implemented in other specific forms without changing the technical spirit or essential features of the present invention. you will be able to understand Therefore, the embodiments described above should be understood as illustrative in all respects and not limiting.

10: display device 100: display panel
200: display driving circuit 300: circuit board

Claims (20)

a plurality of first data lines extending in a second direction crossing the first direction;
a plurality of second data wires extending in the second direction and disposed apart from the plurality of first data wires;
a plurality of data connection wires respectively connected to the plurality of first data wires;
a plurality of vertical dummy patterns disposed apart from the plurality of data connection lines and extending in the second direction; and
a plurality of horizontal power lines disposed in the display area, extending in the first direction, and receiving a power voltage;
A first spacer portion in which one data connection wire among the plurality of data connection wires and one vertical dummy pattern among the plurality of vertical dummy patterns is spaced apart overlaps one horizontal power supply wire among the plurality of horizontal power supply wires. display device. According to claim 1,
A second spacer portion in which another data connection wire among the plurality of data connection wires and another vertical dummy pattern among the plurality of vertical dummy patterns are spaced apart does not overlap with the plurality of horizontal power supply wires. According to claim 2,
Each of the another data connection wire and the another vertical dummy pattern,
a first wiring portion having a first width; and
A display device comprising a second wiring part having a second width greater than the first width. According to claim 3,
The first separation part is defined as a gap between the first wiring part of the data connection line and the first wiring part of the vertical dummy pattern. According to claim 3,
The second spacer may be a gap between the first wiring part of the another data connection wire and the second wiring part of the another vertical dummy pattern or the second wiring part of the another data connection wire and the another vertical dummy pattern. A display device defined as a gap between the first wiring parts of According to claim 3,
The second separation part is defined as a gap between the second wiring part of the another data connection wire and the second wiring part of the another vertical dummy pattern. According to claim 1,
Each of the plurality of data connection wires,
a first data connection wire extending in the second direction; and
A display device comprising a second data connection wire extending in the first direction. According to claim 7,
The plurality of first data lines, the plurality of second data lines, the plurality of vertical dummy patterns, and the first data connection line are made of the same material and disposed on the same layer. According to claim 7,
The plurality of horizontal power lines and the second data connection line are made of the same material and disposed on the same layer. a plurality of first horizontal power lines extending in a first direction and to which a first power voltage is applied;
a plurality of second horizontal power supply wires extending in the first direction and to which a second power supply voltage higher than the first power supply voltage is applied;
a plurality of first data wires extending in a second direction crossing the first direction;
a plurality of second data wires extending in the second direction and disposed apart from the plurality of first data wires;
a plurality of data connection wires respectively connected to the plurality of first data wires; and
a plurality of vertical dummy patterns disposed apart from the plurality of data connection wires and extending in the second direction;
wherein one of the plurality of first horizontal power wires is connected to one of the plurality of vertical dummy patterns. According to claim 10,
a plurality of horizontal dummy patterns extending in the first direction; and
Further comprising a plurality of vertical power lines extending in the second direction and to which the first power voltage is applied;
wherein one of the plurality of vertical power wires is connected to one of the plurality of horizontal dummy patterns. According to claim 10,
A first spacer in which one of the plurality of data connection wires and one of the plurality of vertical dummy patterns are spaced apart from one another of the plurality of second horizontal power supply wires. Display device overlapping power wiring. According to claim 10,
A second spacer portion in which one of the plurality of data connection wires and one of the plurality of vertical dummy patterns is separated from each other is a display device that does not overlap with the plurality of second horizontal power supply wires. . a first display area including a first sub display area and a second sub display area;
a second display area adjacent to the first display area in a first direction;
a plurality of first data wires disposed in the first sub-display area and extending in a second direction crossing the first direction;
a plurality of first data connection wires disposed in the second sub-display area and extending in the second direction;
a plurality of second data connection lines disposed in the first sub-display area and the second sub-display area and extending in the first direction; and
a plurality of first connection holes respectively connecting the plurality of first data connection wires and the plurality of first data connection wires in the second sub display area;
The plurality of first connection holes in the second sub-display area are arranged in a first diagonal direction between the first direction and the second direction. According to claim 14,
a plurality of second connection holes through which the plurality of first data connection lines and the plurality of first data lines are respectively connected in the first sub display area;
In the first sub-display area, the plurality of second connection holes are arranged in a second diagonal direction crossing the first diagonal direction. According to claim 15,
and a plurality of second data wires disposed in the second sub-display area, extending in the plurality of second directions, and disposed apart from the plurality of first data connection wires. According to claim 15,
a third display area adjacent to the first display area in the second direction and including a third sub display area and a fourth sub display area;
a plurality of first horizontal power lines disposed in the third sub display area and the fourth sub display area, extending in the first direction, and to which a first power voltage is applied; and
and a plurality of vertical dummy patterns disposed in the second sub-display area and the fourth sub-display area and extending in the second direction. According to claim 17,
a plurality of first power holes to which the plurality of first horizontal power lines and the plurality of vertical dummy patterns are respectively connected in the fourth sub display area;
In the fourth sub-display area, the plurality of first power holes are arranged in a first diagonal direction between the first direction and the second direction. According to claim 18,
a plurality of vertical power wires disposed in the third sub-display area and extending in the second direction; and
a plurality of second power holes to which the plurality of first horizontal power wires and the plurality of vertical power wires are respectively connected in the third sub display area;
In the third sub-display area, the plurality of second power holes are arranged in a second diagonal direction crossing the first diagonal direction. According to claim 19,
a plurality of horizontal dummy patterns disposed in the first sub display area and the second sub display area and extending in the first direction;
The vertical power wires extend in the second direction in the first sub display area;
a plurality of third power supply holes through which the plurality of horizontal dummy patterns and the vertical power lines are respectively connected in the first sub display area;
The plurality of third power supply holes are arranged in the second diagonal direction in the first sub-display area.

Images