CN220274185U

CN220274185U - Display device

Info

Publication number: CN220274185U
Application number: CN202321332675.7U
Authority: CN
Inventors: 曹永振; 文重守; 方正勳; 李民哲; 金京勳
Original assignee: Samsung Display Co Ltd
Current assignee: Samsung Display Co Ltd
Priority date: 2022-06-03
Filing date: 2023-05-29
Publication date: 2023-12-29
Anticipated expiration: 2033-05-29
Also published as: CN117177624A

Abstract

A display device is provided. The display device includes: a display region in which a plurality of sub-pixels arranged in a first direction and a second direction crossing the first direction are arranged; a plurality of data wires arranged in the display area and extending along the second direction; a first data connection wiring disposed in the display region, extending in the second direction, and spaced apart from the data wiring in the first direction in the sub-pixel; and second data connection wirings disposed in the display region, extending in the first direction, and connected to at least one of the first data connection wirings, wherein the sub-pixel includes a first connection electrode connected to a first electrode of the driving transistor, the first connection electrode being disposed between the first data connection wiring and the data wiring in a non-overlapping manner with the first data connection wiring, so that a wiring arrangement structure or a pattern structure that does not affect an emission amount of light even if an electric signal is applied to other wirings when the sub-pixel emits light may be provided.

Description

Display device

Technical Field

The present utility model relates to a display device.

Background

With the development of the information society, the demand for display devices for displaying images is increasing in various forms. For example, display devices are being applied to various electronic apparatuses such as smart phones, digital cameras, notebook computers, navigators, and smart televisions. The display device may be a flat panel display device such as a liquid crystal display device (Liquid Crystal Display Device), a field emission display device (Field Emission Display Device), an organic light emitting display device (Organic Light Emitting Display Device), or the like. In such a flat panel display device, the light emitting display device includes a light emitting element capable of causing each of the pixels of the display panel to emit light autonomously, so that an image can be displayed even without a backlight unit that supplies light to the display panel.

The display device may further include a pixel emitting a predetermined light, a scan wiring for driving the pixel, a data wiring, a power supply wiring, a scan driving part outputting a scan signal to the scan wiring, and a display driving part outputting a data voltage to the data wiring.

The display device includes a display area including pixels and displaying an image and a non-display area disposed around the display area. Recently, although the area of a non-display region in a display device is being minimized, thus a space for disposing fan-out wirings (fan out lines) connecting a display driving part and data wirings in the non-display region may be insufficient.

Disclosure of Invention

The utility model provides a display device capable of removing the marks on the display surface caused by fan-out wiring due to the reduction of the area of a non-display area.

The technical problems of the present utility model are not limited to the above-mentioned technical problems, and other technical problems not mentioned can be clearly understood by those skilled in the art to which the present utility model pertains through the following description.

In order to solve the above technical problem, a display device according to an embodiment includes: a display region in which a plurality of sub-pixels arranged in a first direction and a second direction crossing the first direction are arranged; a plurality of data wires arranged in the display area and extending along the second direction; a first data connection wiring disposed in the display region, extending in the second direction, and spaced apart from the data wiring in the first direction in the sub-pixel; and second data connection wirings disposed in the display region, extending in the first direction, and connected to at least any one of the first data connection wirings, wherein the sub-pixel includes a first connection electrode connected to a first electrode of a driving transistor, the first connection electrode being disposed between the first data connection wiring and the data wiring in a non-overlapping manner with the first data connection wiring.

The first connection electrode is arranged so as not to overlap the data wiring, and a portion of the first data connection wiring overlaps the first electrode of the driving transistor.

The display device further includes: and an initialization voltage wiring extending in the first direction and including a protrusion adjacent to the first connection electrode and protruding toward the second direction, the protrusion of the initialization voltage wiring overlapping the first data connection wiring, a width of the protrusion of the initialization voltage wiring being greater than a width of the first data connection wiring.

The display device further includes: and a plurality of first vertical wirings extending in the second direction and spaced apart from the first data connection wirings and the data wirings in the first direction, a space between the first vertical wirings and the data wirings being smaller than a space between the first vertical wirings and the first data connection wirings.

The display device further includes: and a voltage connection electrode disposed at the subpixel and connected to the first vertical wire, at least a portion of the voltage connection electrode overlapping the first data connection wire, the voltage connection electrode overlapping the first electrode of the driving transistor, and a maximum line width of the voltage connection electrode being greater than a width of the first data connection wire.

The display device further includes: bias voltage wiring extending along the first direction; and a first transistor connected to the bias voltage wiring, wherein the first transistor is connected to the first connection electrode.

The display device is characterized in that the display area includes: a first display area; and a second display area adjacent to the first display area in the first direction, the data wiring including: a first data wire disposed in the first display region and connected to the second data connection wire; and a second data wiring disposed in the second display region and not connected to the second data connection wiring, wherein at least a portion of the plurality of first data connection wirings is electrically connected to the first data wiring through the second data connection wiring.

The display device further includes: a first fan-out wiring line arranged in a non-display area surrounding the display area and connected to the first data connection wiring line; a second fan-out wiring disposed in the non-display area and connected to the second data connection wiring; a plurality of vertical dummy patterns arranged in the second display region, spaced apart from the first data connection wiring lines along the second direction; a plurality of horizontal dummy patterns spaced apart from the second data connection wiring line in the first direction; a horizontal power supply wiring extending in the first direction in the display area and spaced apart from the second data connection wiring in the second direction; and a vertical power supply wiring line extending in the second direction in the first display region and spaced apart from the first data wiring line.

In order to solve the above technical problem, a display device according to an embodiment includes: a first subpixel and a second subpixel including a driving transistor and a first connection electrode connected to a first electrode of the driving transistor and adjacent to each other in a first direction; a plurality of first data connection wirings disposed at each of the first and second sub-pixels, spaced apart from each other along the first direction, and extending along a second direction crossing the first direction; a plurality of data wirings spaced apart from each other in the first direction through the plurality of first data connection wirings and extending in the second direction; a second data connection wiring extending in the second direction and arranged in the first subpixel and the second subpixel, connected to any one of the first data connection wirings; and a plurality of first vertical wirings extending in the second direction and spaced apart from the data wirings in the first direction, wherein the first connection electrode is disposed between any one of the plurality of first data connection wirings and any one of the plurality of data wirings.

In order to solve the above technical problems, a display device according to an embodiment includes; a display region in which a plurality of sub-pixels arranged in a first direction and a second direction crossing the first direction are arranged; a plurality of data wires arranged in the display area and extending along the second direction; a first data connection wiring disposed in the display region, extending in the second direction, and spaced apart from the data wiring in the first direction in the sub-pixel; and second data connection wirings disposed in the display region, extending in the first direction, and connected to at least any one of the first data connection wirings, wherein the sub-pixel includes a first connection electrode connected to a first electrode of a driving transistor, the first connection electrode does not overlap with the first data connection wiring, and the first connection electrode includes: a first portion extending in a diagonal direction intersecting the first direction and the second direction; and a second portion connected to the first portion and extending in the second direction.

In order to solve the above technical problem, a display device according to an embodiment includes: a display region in which a plurality of sub-pixels arranged in a first direction and a second direction intersecting the first direction are arranged, and a non-display region surrounding the display region; a plurality of data wires arranged in the display area and extending along the second direction; a first data connection wiring disposed in the display region, extending in the second direction, and spaced apart from the data wiring in the first direction in the sub-pixel; and second data connection wirings disposed in the display region, extending in the first direction, and connected to at least one of the first data connection wirings, wherein the sub-pixel includes a first connection electrode connected to a first electrode of a driving transistor, the first connection electrode being disposed between the first data connection wiring and the data wiring in a non-overlapping manner with the first data connection wiring.

The first connection electrode is disposed not to overlap the data wiring, and a portion of the first data connection wiring may overlap the first electrode of the driving transistor.

The display device further includes: and an initialization voltage wiring extending in the first direction and including a protrusion adjacent to the first connection electrode and protruding toward the second direction, the protrusion of the initialization voltage wiring may overlap the first data connection wiring.

The width of the protruding portion of the initialization voltage wiring may be greater than the width of the first data connection wiring.

The display device further includes: and a plurality of first vertical wirings extending in the second direction and spaced apart from the first data connection wirings and the data wirings in the first direction, and a space between the first vertical wirings and the data wirings may be smaller than a space between the first vertical wirings and the first data connection wirings.

The display device further includes: and a voltage connection electrode disposed at the subpixel and connected to the first vertical wiring, at least a portion of the voltage connection electrode may overlap the first data connection wiring.

The voltage connection electrode may overlap the first electrode of the driving transistor.

The maximum line width of the voltage connection electrode may be greater than the width of the first data connection wiring.

The display device further includes: bias voltage wiring extending along the first direction; and a first transistor connected to the bias voltage wiring, wherein the first transistor may be connected to the first connection electrode.

The display area includes: a first display area; and a second display area adjacent to the first display area in the first direction, the data wiring may include: a first data wire disposed in the first display region and connected to the second data connection wire; and a second data wiring disposed in the second display region and not connected to the second data connection wiring.

At least a part of the plurality of first data connection wirings may be electrically connected to the first data wiring through the second data connection wiring.

The display device may further include: a first fan-out wiring disposed in the non-display area and connected to the first data connection wiring; and a second fan-out wiring disposed in the non-display area and connected to the second data connection wiring.

The display device may further include: a plurality of vertical dummy patterns arranged in the second display region, spaced apart from the first data connection wiring lines along the second direction; and a plurality of horizontal dummy patterns spaced apart from the second data connection wiring line in the first direction.

The display device may further include: a horizontal power supply wiring extending in the first direction in the display area and spaced apart from the second data connection wiring in the second direction; and a vertical power supply wiring line extending in the second direction in the first display region and spaced apart from the first data wiring line.

The first connection electrode is disposed to partially overlap the data wiring, and a portion of the first data connection wiring may overlap the first electrode of the driving transistor.

In order to solve the technical problem, a display device according to an embodiment includes: a first subpixel and a second subpixel including a driving transistor and a first connection electrode connected to a first electrode of the driving transistor and adjacent to each other in a first direction; a plurality of first data connection wirings disposed at each of the first and second sub-pixels, spaced apart from each other along the first direction, and extending along a second direction crossing the first direction; a plurality of data wirings spaced apart from each other in the first direction through the plurality of first data connection wirings and extending in the second direction; a second data connection wiring extending in the second direction and disposed between the first subpixel and the second subpixel, and connected to any one of the first data connection wirings; and a plurality of first vertical wirings extending in the second direction and spaced apart from the data wirings in the first direction, wherein the first connection electrode is disposed between any one of the plurality of first data connection wirings and any one of the plurality of data wirings.

An interval between the first data connection wiring of the first subpixel and the first data connection wiring of the second subpixel may be smaller than an interval between the data wiring of the first subpixel and the data wiring of the second subpixel.

The first data connection wiring of the first subpixel and the first data connection wiring of the second subpixel may be disposed between the first connection electrodes of the first subpixel and the second subpixel, respectively.

Each of the first data connection wirings does not overlap the first connection electrode, but may overlap the first electrode of the driving transistor.

The display device further includes: an initialization voltage wiring extending in the first direction and disposed at the first and second sub-pixels, wherein the initialization voltage wiring is disposed between the first connection electrodes of the first and second sub-pixels, respectively, and may include a protrusion protruding toward the second direction.

The protruding portion is arranged to overlap the first data connection wiring of each of the first and second sub-pixels, and a width of the protruding portion may be greater than a width of the first data connection wiring of each of the first and second sub-pixels.

The width of the protrusion may be greater than the interval between the first data connection wiring of the first subpixel and the first data connection wiring of the second subpixel.

The display device further includes: and a voltage connection electrode connected to the first vertical wiring and disposed between the first connection electrodes of the first and second sub-pixels, respectively, wherein the voltage connection electrode may be disposed to overlap the first data connection wiring of the first and second sub-pixels, respectively.

The voltage connection electrode may be arranged to overlap the first electrode of the driving transistor of the first subpixel and the first electrode of the driving transistor of the second subpixel, respectively.

The minimum line width of the voltage connection electrode may be greater than the interval between the first data connection wirings of the first and second sub-pixels, respectively.

The maximum line width of the voltage connection electrode may be greater than a sum of a space between the first data connection wirings and a width of the first data connection wirings of the first and second sub-pixels, respectively.

The display device may further include: a first sub-initialization voltage wiring extending along the first direction and connected to the second sub-pixel; and a second sub-initialization voltage wiring extending along the first direction and connected to the first sub-pixel.

The display device may further include: and a second connection electrode disposed at the same layer as the second sub-initialization voltage wiring and disposed at the second sub-pixel to be connected to the first sub-initialization voltage wiring.

An interval between the first data connection wiring of the first subpixel and the first data connection wiring of the second subpixel may be the same as an interval between the data wiring of the first subpixel and the data wiring of the second subpixel.

The data wiring of the first subpixel and the data wiring of the second subpixel may overlap the first connection electrode, respectively.

In order to solve the technical problem, a display device according to an embodiment includes; a display region in which a plurality of sub-pixels arranged in a first direction and a second direction intersecting the first direction are arranged, and a non-display region surrounding the display region; a plurality of data wires arranged in the display area and extending along the second direction; a first data connection wiring disposed in the display region, extending in the second direction, and spaced apart from the data wiring in the first direction in the sub-pixel; and second data connection wirings disposed in the display region, extending in the first direction, and connected to at least one of the first data connection wirings, wherein the sub-pixel includes a first connection electrode connected to a first electrode of a driving transistor, the first connection electrode does not overlap with the first data connection wiring, and the first connection electrode includes: a first portion extending in a diagonal direction intersecting the first direction and the second direction; and a second portion connected to the first portion and extending in the second direction.

The first connection electrode includes: a first contact portion in which an electrode contact hole is arranged; and a second contact portion in which a first contact hole is arranged, wherein each side of the first contact portion may be non-parallel to the first data connection wiring.

The first contact part may include a first side, a space between a first fulcrum in both end portions of the first side and the first data connection wire is smaller than a space between a second fulcrum in both end portions of the first side and the first data connection wire, wherein the first fulcrum is adjacent to the first data connection wire, and the second fulcrum is an opposite side end portion of the first fulcrum.

At least a portion of each side of the second contact portion may be parallel to the first data connection wiring.

The maximum width of the electrode contact hole measured in the second direction may be different from the maximum width of the first contact hole measured in the second direction.

The direction in which the long axis of the electrode contact hole extends may be different from the direction in which the long axis of the first contact hole extends.

An angle between a direction in which the first portion of the first connection electrode extends and a direction in which the second portion extends may have a range of 30 degrees to 60 degrees.

The first connection electrode is disposed with at least a portion overlapping the data wiring, and a portion of the first data connection wiring may overlap the first electrode of the driving transistor.

The display device may further include: and an initialization voltage wiring extending in the first direction and including a protrusion adjacent to the first connection electrode and protruding toward the second direction, the protrusion of the initialization voltage wiring overlapping the first data connection wiring.

The display device may further include: and a voltage connection electrode disposed at the subpixel overlapping the first data connection wiring, the voltage connection electrode overlapping the first electrode of the driving transistor.

At least a portion of the voltage connection electrodes may have a shape recessed corresponding to the first portion of the first connection electrode.

A width of a portion of the voltage connection electrode adjacent to the first portion of the first connection electrode is greater than a width of a portion of the voltage connection electrode adjacent to the second portion of the first connection electrode.

Specific details of other embodiments are included in the detailed description and the accompanying drawings.

The display device according to an embodiment may have a wiring arrangement structure or a pattern structure that does not affect the light emission amount even if an electric signal is applied to other wirings when the sub-pixel emits light. Accordingly, even if the display device includes a wiring to which different signals are applied according to positions in the display region, it is possible to prevent the identification of the mark from the outside by the change in the amount of light emission.

Effects according to the embodiments are not limited to the above-exemplified contents, and more various effects are included in the present specification.

Drawings

Fig. 1 is a perspective view of a display device according to an embodiment.

Fig. 2 is a side view illustrating a display device according to an embodiment.

Fig. 3 is a plan view of a display device according to an embodiment.

Fig. 4 is a plan view showing the region a of fig. 3 in detail.

Fig. 5 is a pixel circuit diagram of a sub-pixel according to an embodiment.

Fig. 6 is a pixel circuit diagram of a sub-pixel according to another embodiment.

Fig. 7 is a plan view illustrating wirings disposed at a first display region and a second display region of a display device according to an embodiment.

Fig. 8 is a plan view illustrating wirings disposed at a third display region and a fourth display region of a display device according to an embodiment.

Fig. 9 and 10 are layout diagrams illustrating adjacent two sub-pixels of a display device according to an embodiment.

Fig. 11 is a cross-sectional view taken along line N1-N1' of fig. 9 and 10.

Fig. 12 is a schematic diagram showing data connection wirings and electrical connection of the data wirings of a display device according to an embodiment.

Fig. 13 is a plan view showing a portion B of fig. 9 and 10.

Fig. 14 is a cross-sectional view taken along line N2-N2' of fig. 13.

Fig. 15 is a plan view showing pixel electrodes arranged at a plurality of sub-pixels of a display device according to an embodiment.

Fig. 16 is a plan view showing a part of a display device according to another embodiment.

Fig. 17 is a cross-sectional view taken along line N3-N3' of fig. 16.

Fig. 18 is a plan view showing a part of a display device according to another embodiment.

Fig. 19 is a cross-sectional view taken along line N4-N4' of fig. 18.

Fig. 20 is a cross-sectional view taken along line N5-N5' of fig. 18.

Fig. 21 is a layout diagram showing adjacent two sub-pixels of a display device according to another embodiment.

Fig. 22 is a pixel circuit diagram of the first sub-pixel of fig. 21.

Fig. 23 is a pixel circuit diagram of the second sub-pixel of fig. 21.

Fig. 24 is a plan view showing a part of a display device according to another embodiment.

Fig. 25 is a schematic view showing data connection wirings of a display device according to another embodiment and electrical connection of the data wirings.

Fig. 26 is a plan view illustrating a portion of the display device of fig. 25.

Fig. 27 is a cross-sectional view taken along line N6-N6' of fig. 26.

Fig. 28 is a plan view showing pixel electrodes arranged at a plurality of sub-pixels of the display device of fig. 25.

Fig. 29 is a plan view showing a part of a display device according to another embodiment.

Fig. 30 is a cross-sectional view taken along line N7-N7' of fig. 29.

Fig. 31 is a plan view showing a part of a display device according to another embodiment.

Fig. 32 is a plan view illustrating the first connection electrode of fig. 31.

Fig. 33 is a plan view showing an arrangement of the first connection electrode and the first data connection wiring of fig. 31.

Fig. 34 is a cross-sectional view taken along line N8-N8' of fig. 31.

Fig. 35 is a cross-sectional view taken along line N9-N9' of fig. 31.

Fig. 36 is a plan view showing a part of a display device according to still another embodiment.

Fig. 37 is a plan view showing an arrangement of the first connection electrode and the first data connection wiring of fig. 36.

Fig. 38 is a cross-sectional view taken along line N10-N10' of fig. 36.

Description of the reference numerals

10: display device

100: display panel

Detailed Description

The advantages and features of the present utility model and methods for achieving the same will be apparent with reference to the embodiments described in detail below in conjunction with the accompanying drawings. However, the present utility model is not limited to the embodiments disclosed below, which may be implemented in various forms different from each other, and the embodiments are provided only for the purpose of fully completing the disclosure of the present utility model and for fully informing a person having ordinary skill in the art to which the present utility model pertains, the present utility model being defined by the scope of the claims.

References to an element or layer being "on" another element or layer include both the case of immediately above the other element or the case of sandwiching the other layer or other element. In the same manner, when referring to the cases of "lower", "Left" and "Right", both cases where other elements are immediately adjacent to each other or where other layers or other elements are interposed therebetween are included. Like reference numerals refer to like elements throughout the specification.

Although the terms first, second, etc. are used to describe various elements, these elements are obviously not limited by these terms. These terms are only used to distinguish one element from another. Therefore, the first component mentioned below may be the second component within the technical idea of the present utility model.

Hereinafter, embodiments will be described with reference to the drawings.

Fig. 1 is a perspective view illustrating a display device according to an embodiment.

Referring to fig. 1, a display device 10, which is a device that displays a moving image or a still image, may be used not only as a display screen of a portable electronic apparatus such as a Mobile Phone (Mobile Phone), a Smart Phone (Smart Phone), a Tablet PC (Tablet PC), and a Smart Watch (Smart Watch), a Watch Phone (Watch Phone), a Mobile communication terminal, an electronic notepad, an electronic book, a portable multimedia player (PMP: portable Multimedia Player), a navigator, an Ultra Mobile personal computer (UMPC: ultra Mobile PC), and the like, but also as a display screen of various products such as a television, a notebook computer, a monitor, an advertisement board, and an internet of things (IOT: internet of Things) device.

The display device 10 may be a light emitting display device such as an organic light emitting display device using an organic light emitting diode, a quantum dot light emitting display device including a quantum dot light emitting layer, an inorganic light emitting display device including an inorganic semiconductor, and a microminiature light emitting display device using a microminiature light emitting diode (a microminiature light emitting diode or a nanolight emitting diode (a microminiature LED or a nanoled)) (micro or nano light emitting diode (micro LED or nano LED)). Hereinafter, the description will be given centering on the case where the display device 10 is an organic light emitting display device, but the present utility model is not limited thereto.

The display device 10 includes a display panel 100, a display driving circuit 200, and a circuit board 300.

The display panel 100 may be formed in a rectangular-shaped plane having a short side in the first direction DR1 and a long side in the second direction DR2 intersecting the first direction DR 1. The corners (corner) where the short sides in the first direction DR1 meet the long sides in the second direction DR2 may be smoothly formed or formed as right angles in such a manner as to have a predetermined curvature. The planar shape of the display panel 100 is not limited to a rectangle, and may be formed in other polygons, circles, or ovals. The display panel 100 may be formed flat, but is not limited thereto. For example, the display panel 100 may include curved surface portions formed at left and right side ends and having a predetermined curvature or a varying curvature. Further, the display panel 100 may be flexibly formed to be able to be bent, meandered, curved, folded, or rolled.

The substrate SUB of the display panel 100 may include a main region MA and a SUB-region SBA. The main area MA may include a display area DA that displays an image and a non-display area NDA that is a surrounding area of the display area DA. The display area DA may include subpixels SPX (SPX of fig. 5) that display an image.

The sub-area SBA may protrude from one side of the main area MA in the opposite direction of the second direction DR 2. Although fig. 1 illustrates a case where the sub-area SBA is unfolded, the sub-area SBA may be folded, in which case the sub-area SBA may be disposed on the lower surface of the display panel 100. In the case where the SUB-region SBA is folded, it may overlap with the main region MA in the thickness direction DR3 of the substrate SUB. A display driving circuit 200 may be disposed in the sub-region SBA.

The display driving circuit 200 may generate signals and voltages for driving the display panel 100. The display driving circuit 200 may be formed as an integrated circuit (IC: integrated circuit) and attached to the display panel 100 in a Chip On Glass (COG) manner, a Chip On Plastic (COP) manner, or an ultrasonic bonding manner, but is not limited thereto. For example, the display driving circuit 200 may be attached to the circuit board 300 in a Chip On Film (COF) manner.

The circuit board 300 may be attached to one end of the sub-area SBA of the display panel 100. Accordingly, the circuit board 300 may be electrically connected with the display panel 100 and the display driving circuit 200. The display panel 100 and the display driving circuit 200 may receive digital image data and timing signals and driving voltages through the circuit board 300. The circuit board 300 may be a flexible film such as a flexible printed circuit board (flexible printed circuit board), a printed circuit board (printed circuit board), or a chip on film (chip on film).

Fig. 2 is a side view illustrating a display device according to an embodiment. Fig. 2 illustrates a case where the sub-area SBA of the display device 10 is bent toward the lower side of the display device 10.

Referring to fig. 2, the display panel 100 may include a substrate SUB, a thin film transistor layer TFEL, a light emitting element layer EL, an encapsulation layer TFEL, and a touch sensing layer TDU.

The substrate SUB may be made of an insulating material such as a polymer resin. For example, the substrate SUB may be formed using polyimide (polyimide). The substrate SUB may be a flexible substrate that can be bent (bonding), folded (folding), rolled (rolling), or the like.

The thin film transistor layer TFTL may be disposed on the substrate SUB. The thin film transistor layer TFTL may be disposed at the main region MA and the sub-region SBA. The thin film transistor layer TFTL includes a plurality of thin film transistors.

The light emitting element layer EL may be disposed on the thin film transistor layer TFTL. The light emitting element layer EL may be disposed at the display area DA of the main area MA. The light emitting element layer EL includes light emitting elements arranged in a light emitting portion.

The encapsulation layer TFEL may be disposed on the light emitting element layer EL. The encapsulation layer TFEL may be disposed at the display area DA and the non-display area NDA of the main area MA. The encapsulation layer TFEL includes at least one inorganic film and at least one organic film for encapsulating the light emitting element layer EL.

The touch sensing layer TDU may be disposed on the encapsulation layer TFEL. The touch sensing layer TDU may be disposed at the display area DA and the non-display area NDA of the main area MA. The touch sensing layer TDU may sense a touch of a person or object using the touch electrode.

A cover window for protecting an upper portion of the display panel 100 may be disposed on the touch sensing layer TDU. The cover window may be attached to the touch sensing layer TDU by means of a transparent adhesive member such as an optically transparent adhesive (OCA: optically clear adhesive) film or an optically transparent resin (OCR: optically clear resin). The cover window may be inorganic such as glass or organic such as plastic or polymer material.

In addition, in order to prevent degradation of the visibility of the image displayed by the display panel 100 due to reflection of external light from the display panel 100, an anti-reflection member may be additionally disposed between the touch sensing layer TDU and the cover window. The anti-reflection member may be a polarizing film. Alternatively, the anti-reflection member may include a light blocking organic film such as a black matrix and a color filter, or may include a light blocking organic film such as a black matrix and an anti-reflection organic film.

The touch driving circuit 400 may be disposed on the circuit board 300. The touch driving circuit 400 may be formed as an Integrated Circuit (IC) and attached to the circuit board 300.

The touch driving circuit 400 may be electrically connected to a plurality of driving electrodes and a plurality of sensing electrodes of the touch sensing layer TDU. The touch driving circuit 400 applies a touch driving signal to the plurality of driving electrodes, and senses a touch sensing signal (e.g., a charge (charge) variation amount of a mutual capacitance) of each of the plurality of touch nodes through the plurality of sensing electrodes. The touch driving circuit 400 may determine whether a user touches, approaches the user, and the like based on the touch sensing signal of each of the plurality of touch nodes. The touch of the user refers to a case where an object such as a finger or a pen of the user is in direct contact with the front surface of the display device 10 disposed on the touch sensing layer TDU. The proximity of the user refers to a case where an object such as a user's finger or pen is located at a position (such as hovering) separated from the front surface of the display device 10.

Fig. 3 is a plan view of a display device according to an embodiment. Fig. 3 illustrates a state in which the sub-region SBA of the display device 10 is unfolded without bending.

Referring to fig. 3, the display panel 100 may include a main area MA and a sub-area SBA.

The main area MA may include a display area DA that displays an image and a non-display area NDA that is a surrounding area of the display area DA. The display area DA may occupy a large area of the main area MA. The display area DA may be disposed at the center of the main area MA.

The display area DA may include a first display area DA1, a second display area DA2, a third display area DA3, and a fourth display area DA4. The first display area DA1 and the second display area DA2 may be disposed adjacent to the sub-area SBA of the display panel 100, and the third display area DA3 and the fourth display area DA4 may be disposed at one side of the first display area DA1 and the second display area DA2 in the second direction DR2, respectively. The first display area DA1 and the third display area DA3 may be disposed at one side in the first direction DR1 and the other side in the first direction DR1, respectively, with respect to the center of the display area DA, and the second display area DA2 and the fourth display area DA4 may be disposed at the center of the display area DA, respectively. The first display areas DA1 may be disposed at both sides in the first direction DR1 at lower sides of the display areas DA, respectively, and the second display areas DA2 may be disposed therebetween. The third display area DA3 may be disposed at both sides in the first direction DR1 at an upper side of the display area DA, respectively, and the fourth display area DA4 may be disposed therebetween.

The first display area DA1 and the third display area DA3 are areas where first data wirings connected to the data fan-out wirings through data connection wirings are arranged, respectively. The second display area DA2 and the fourth display area DA4 may be areas where second data wirings directly connected to the data fan-out wirings are arranged. A data connection hole in which the data connection wiring and the data wiring are connected to each other may be disposed at the first display area DA1 and the second display area DA 2. A power hole connecting a horizontal power wiring extending in the first direction DR1 and a vertical power wiring extending in the second direction DR2 may be disposed at the third display area DA3 and the fourth display area DA 4.

The length of the first display area DA1 in the first direction DR1 may be longer than the length of the second display area DA2 in the first direction DR 1. The length of the first display area DA1 in the second direction DR2 may be substantially the same as the length of the second display area DA2 in the second direction DR 2.

The length of the first display area DA1 in the first direction DR1 may be substantially the same as the length of the third display area DA3 in the first direction DR 1. The length of the first display area DA1 in the second direction DR2 may be smaller than the length of the third display area DA3 in the second direction DR 2. Similarly, the length of the second display area DA2 in the first direction DR1 may be substantially the same as the length of the fourth display area DA4 in the first direction DR 1. The length of the second display area DA2 in the second direction DR2 may be smaller than the length of the fourth display area DA4 in the second direction DR 2.

For example, in the case where the display area DA includes 1080×2340 pixels, 484 pixels may be arranged in the first direction DR1 in each of the first display area DA1 and the third display area DA3, and 112 pixels may be arranged in the first direction DR1 in each of the second display area DA2 and the fourth display area DA 4. The description of the wirings disposed in the first to fourth display areas DA1 to DA4 will be described later with reference to other drawings.

The non-display area NDA may be disposed adjacent to the display area DA. The non-display area NDA may be an outer area of the display area DA. The non-display area NDA may be arranged to surround the display area DA. The non-display area NDA may be an edge area of the display panel 100.

The sub-area SBA may protrude from one side of the main area MA in the opposite direction of the second direction DR 2. The length in the second direction DR2 of the sub-area SBA may be smaller than the length in the second direction DR2 of the main area MA. The length of the sub-area SBA in the first direction DR1 may be smaller than or substantially equal to the length of the main area MA in the first direction DR 1. The sub-region SBA may be bent and may be disposed at a lower portion of the display panel 100. In this case, the sub-area SBA may overlap with the main area MA in the third direction DR 3.

The sub-area SBA may include a connection area CA, a pad area PA, and a bending area BA.

The connection area CA is an area protruding from one side of the main area MA toward the opposite direction of the second direction DR 2. The connection region CA may be disposed between the non-display region NDA of the main region MA and the curved region BA in the second direction DR 2.

The pad area PA is an area where the pad PD and the display driving circuit 200 are arranged. The display driving circuit 200 may be attached to the driving pad of the pad area PA using a conductive adhesive member such as an anisotropic conductive film (anisotropic conductive film). The circuit board 300 may be attached to the pad PD of the pad area PA using a conductive adhesive member such as an anisotropic conductive film.

The bending area BA is a bending area. In the case where the bending area BA is bent, the pad area PA may be disposed at a lower portion of the connection area CA and a lower portion of the main area MA. The bending area BA may be disposed between the connection area CA and the pad area PA in the second direction DR 2.

Fig. 4 is a plan view showing the region a of fig. 3 in detail.

Fig. 4 schematically illustrates wirings arranged in the first display area DA1, the second display area DA2, the non-display area NDA, and the sub-area SBA of fig. 3.

Referring to fig. 4, a plurality of first data wirings DL1, a plurality of second data wirings DL2, a plurality of data connection wirings DCL, and a plurality of first vertical power supply wirings VPL1 may be disposed at the first display area DA1 and the second display area DA2. Although not illustrated in fig. 4, a plurality of horizontal power supply wirings, vertical dummy wirings, and horizontal dummy wirings may be disposed at the first display area DA1 and the second display area DA2.

The first and second data wirings DL1 and DL2 may extend in the second direction DR2, respectively, and are aligned with each other in the first direction DR 1. The first data wiring DL1 may be disposed at the first display area DA1 and spaced apart from another adjacent first data wiring DL1 in the first direction DR 1. The second data wiring DL2 may be disposed at the second display area DA2 and spaced apart from another adjacent second data wiring DL2 in the first direction DR 1.

The plurality of data connection wirings DCL may be disposed at the first display area DA1 and the second display area DA2. The plurality of data connection wirings DCL may include a first data connection wiring DCL1 and a second data connection wiring DCL2. The first data connection wirings DCL1 may extend in the second direction DR2 and be arranged in the first direction DR 1. The second data connection wirings DCL2 may extend in the first direction DR1 and be arranged in the second direction DR 2. The first data connection wiring DCL1 may be spaced apart from another adjacent first data connection wiring DCL1 in the first direction DR1, and the second data connection wiring DCL2 may be spaced apart from another adjacent second data connection wiring DCL2 in the second direction DR 2.

The first data connection wiring DCL1 may be connected to the first fan-out wiring FL1 through a first connection hole COH 1. The second data connection wiring DCL2 may be connected to the first data connection wiring DCL1 through the first data connection hole DCH 1. Each of the plurality of first data wirings DL1 may be connected to the second data connection wiring DCL2 through the second data connection hole DCH 2. Each of the plurality of second data wirings DL2 may be connected to the second fan-out wiring FL2 through a second connection hole COH 2.

In the first and second display areas DA1 and DA2, the first data connection hole DCH1 connecting the first and second data connection wirings DCL1 and DCL2 and the second data connection hole DCH2 connecting the second and first data connection wirings DCL2 and DL1 may be arranged in a v shape. Alternatively, the first data connection hole DCH1 and the second data connection hole DCH2 may be repeatedly arranged in a "Λ" shape, or may be arranged in other patterns other than the "v" and the "Λ".

The first data wiring DL1 disposed at the first display area DA1 may be a data wiring electrically connected to the first fan-out wiring FL1 through a data connection wiring DCL. The second data wiring DL2 disposed at the second display area DA2 may be a data wiring directly connected to the second fan-out wiring FL2.

Each of the plurality of first vertical power supply wirings VPL1 may be disposed at the first display area DA1 and the second display area DA2. Each of the plurality of first vertical power supply wirings VPL1 may extend in the second direction DR2 and be arranged in the first direction DR 1. The first vertical power supply line VPL1 disposed at the first display area DA1 may extend in the second direction DR2 from the first power supply line PL1 disposed at the left and right sides of the non-display area NDA. The first vertical power supply line VPL1 disposed at the second display area DA2 may be connected to the first power supply line PL1 at the center of the non-display area NDA.

The first fan-out wiring FL1, the second fan-out wiring FL2, the first power supply wiring PL1, and the second power supply wiring PL2 may be disposed in the non-display area NDA. Each of the first fan-out wirings FL1 may be connected to the first data connection wiring DCL1 through a first connection hole COH 1. Each of the second fan-out wirings FL2 may be connected to the second data wiring DL2 through a second connection hole COH 2.

Among the first power supply wirings PL1, the first power supply wiring PL1 disposed at the center of the display panel 100 may be connected to a plurality of first vertical power supply wirings VPL 1. Among the first power supply lines PL1, the first power supply lines PL1 disposed at the left and right sides of the display panel 100 may be disposed to surround the second power supply line PL2. The second power supply wiring PL2 may be arranged to surround the display area DA. Each of the first power supply wirings PL1 may be applied with a first power supply voltage, and each of the second power supply wirings PL2 may be applied with a second power supply voltage higher than the first power supply voltage.

The first, second, third, and fourth curved wirings BL1, BL2, BL3, and BL4 may be disposed at the curved region BA. Each of the first bent wirings BL1 may be connected to the first fan-out wiring FL1 through a third connection hole COH 3. Each of the second bent wirings BL2 may be connected to the second fan-out wiring FL2 through a fourth connection hole COH 4. Each of the third curved wirings BL3 may be connected to the first power supply wiring PL1, and each of the fourth curved wirings BL4 may be connected to the second power supply wiring PL2.

The first pad wiring PDL1, the second pad wiring PDL2, the first power pad wiring PPL1, and the second power pad wiring PPL2 may be arranged in the pad area PA. Each of the first pad wirings PDL1 may be connected to the first curved wiring BL1 through a fifth connection hole COH 5. Each of the second pad wirings PDL2 may be connected to the second curved wiring BL2 through a sixth connection hole COH 6. The first power pad wiring PPL1 may be connected to the third curved wiring BL3, and the second power pad wiring PPL2 may be connected to the fourth curved wiring BL4.

The first pad wiring PDL1 and the second pad wiring PDL2 may be electrically connected to the display driving circuit 200. The first power pad wiring PPL1 and the second power pad wiring PPL2 may be directly connected to the pad PD. The display driving circuit 200 may be connected to the pad PD through a third pad wiring.

The plurality of first data wirings DL1 disposed at the left and right sides of the display panel 100 may be connected to the first fan-out wiring FL1 through the data connection wiring DCL. The first fan-out wiring FL1 is not required to be arranged at the non-display area NDA of the lower side of the display panel 100 in order to be connected to the plurality of first data wirings DL1 arranged adjacent to the left and right sides of the display area DA. Therefore, even if the area of the non-display area NDA on the lower side of the display panel 100 is reduced, the arrangement space of the fan-out wirings FL1, FL2 may not be insufficient.

Fig. 5 is a pixel circuit diagram of a sub-pixel according to an embodiment.

Referring to fig. 5, the sub-pixel SPX may be connected to at least one of the scan lines GWL, GIL, GCL, GBL, any one of the light emitting lines EML, and any one of the data lines DL. For example, the sub-pixel SPX may be connected to the write scan line GWL, the initialization scan line GIL, the control scan line GCL, the bias scan line GBL, the emission line EML, and the data line DL.

The sub-pixel SPX includes a light emitting element ED and a pixel driving section PDU. The pixel driving section PDU includes a driving transistor (transistor) DT, a switching element, and a capacitor C1. The switching elements include a first transistor ST1, a second transistor ST2, a third transistor ST3, a fourth transistor ST4, a fifth transistor ST5, a sixth transistor ST6, and a seventh transistor ST7.

The driving transistor DT includes a gate electrode, a first electrode, and a second electrode. The driving transistor DT controls a drain-source current (hereinafter, referred to as a "driving current") flowing between the first electrode and the second electrode according to a data voltage applied to the gate electrode.

The light emitting element ED emits light according to the driving current. The light emission amount of the light emitting element ED may be proportional to the driving current.

The light emitting element ED may be an organic light emitting diode including an anode electrode, a cathode electrode, and an organic light emitting layer disposed between the anode electrode and the cathode electrode. Alternatively, the light emitting element ED may be an inorganic light emitting element including an anode electrode, a cathode electrode, and an inorganic semiconductor arranged between the anode electrode and the cathode electrode. Alternatively, the light emitting element ED may be a quantum dot light emitting element including an anode electrode, a cathode electrode, and a quantum dot light emitting layer arranged between the anode electrode and the cathode electrode. Alternatively, the light emitting element ED may be a micro light emitting diode (micro light emitting diode).

An anode electrode of the light emitting element ED may be connected to one electrode of the sixth transistor ST6 and one electrode of the seventh transistor ST7, and a cathode electrode may be connected to the second voltage wiring VSS. A parasitic capacitance Cel may be formed between the anode electrode and the cathode electrode of the light emitting element ED.

The capacitor C1 is formed between the gate electrode of the driving transistor DT and the first voltage wiring VDD. One electrode of the capacitor C1 may be connected to the gate electrode of the driving transistor DT, and the other electrode may be connected to the first voltage wiring VDD.

The gate electrode of the first transistor ST1 and the gate electrode of the seventh transistor ST7 may be connected to the bias scan wiring GBL, and the gate electrode of the second transistor ST2 may be connected to the write scan wiring GWL. A gate electrode of the third transistor ST3 may be connected to the control scan line GCL, and a gate electrode of the fourth transistor ST4 may be connected to the initialization scan line GIL. An electrode of the first transistor ST1 may be connected to the bias voltage wiring VOBS, and an electrode of the second transistor ST2 may be connected to the data wiring DL. One electrode of the third transistor ST3 may be connected to the second electrode of the driving transistor DT, and the other electrode of the third transistor ST3 may be connected to the one electrode of the capacitor C1. One electrode of the fourth transistor ST4 may be connected to the first initialization voltage wiring VIL, and the other electrode of the seventh transistor ST7 may be connected to the second initialization voltage wiring fail. The first initialization voltage applied to the first initialization voltage wiring VIL and the second initialization voltage applied to the second initialization voltage wiring VAIL may be voltages different from each other.

In the display device 10 according to an embodiment, the driving transistor DT, the first transistor ST1, the second transistor ST2, the fifth transistor ST5, the sixth transistor ST6, and the seventh transistor ST7 of one sub-pixel SPX may be formed as P-type metal-oxide semiconductor field effect transistors (MOSFETs), and the third transistor ST3 and the fourth transistor ST4 may be formed as N-type MOSFETs. The active layers of the driving transistor DT, the first transistor ST1, the second transistor ST2, the fifth transistor ST5, the sixth transistor ST6, and the seventh transistor ST7, which are formed as P-type MOSFETs, are formed using polysilicon, and the active layers of the third transistor ST3 and the fourth transistor ST4, which are formed as N-type MOSFETs, may be formed using oxide semiconductors. In this case, the transistor formed using polysilicon and the transistor formed using an oxide semiconductor can be arranged in layers different from each other, and thus the arrangement area of the transistors of each of the sub-pixels SPX can be reduced. Alternatively, in fig. 6, the seventh transistor ST7 may be formed as an N-type MOSFET. In this case, the active layer of each seventh transistor ST7 may also be formed using an oxide semiconductor.

The third transistor ST3 and the fourth transistor ST4 are formed as N-type MOSFETs, and thus the third transistor ST3 and the fourth transistor ST4 may be turned on in a case where a scan signal of a gate high voltage is applied to the control scan wiring GCL and the initialization scan wiring GIL. In contrast, since the first transistor ST1, the second transistor ST2, the fifth transistor ST5, the sixth transistor ST6, and the seventh transistor ST7 are formed as P-type MOSFETs, the first transistor ST1, the second transistor ST2, the fifth transistor ST5, the sixth transistor ST6, and the seventh transistor ST7 are turned on when a scanning signal and a light-emitting signal of a gate low voltage are applied to the bias scanning wiring GBL, the write scanning wiring GWL, and the light-emitting wiring EML, respectively.

Referring to fig. 6, in the display device 10 according to an embodiment, the first to seventh transistors ST1 to ST7 and the driving transistor DT of one sub-pixel SPX may be all formed as P-type MOSFETs. The active layer of each of the first to seventh transistors ST1 to ST7 and the driving transistor DT may be formed using polysilicon or an oxide semiconductor. Since the first to seventh transistors ST1 to ST7 are formed as P-type MOSFETs, the first to seventh transistors ST1 to ST7 are turned on in the case where a scan signal and a light emitting signal of a gate low voltage are applied to the control scan wiring GCL, the initialization scan wiring GIL, the write scan wiring GWL, the bias scan wiring GBL, and the light emitting wiring EML, respectively.

Alternatively, although not illustrated in fig. 5 and 6, the first to seventh transistors ST1 to ST7 and the driving transistor DT may be all formed as N-type MOSFETs.

Fig. 7 is a plan view illustrating wirings disposed at a first display region and a second display region of a display device according to an embodiment. Fig. 7 illustrates an arrangement of the data wirings DL1, DL2, the data connection wirings DCL1, DCL2, the first vertical power supply wiring VPL1, and the second horizontal power supply wiring HPL2 arranged in the first and second display areas DA1 and DA 2.

Referring to fig. 7, the plurality of first data wirings DL1 and the plurality of first vertical power supply wirings VPL1 may be disposed at the first display area DA1, and the plurality of second data wirings DL2 and the plurality of first data connection wirings DCL1 may be disposed at the second display area DA2. Each of the first data wiring DL1, the second data wiring DL2, the first data connection wiring DCL1, and the first vertical power supply wiring VPL1 may extend in the second direction DR2 and be spaced apart from each other in the first direction DR 1. In the first display area DA1, the first data wiring DL1 and the first vertical power supply wiring VPL1 may be arranged to be spaced apart from each other along the first direction DR1, and in the second display area DA2, the second data wiring DL2 and the first data connection wiring DCL1 may be arranged to be spaced apart from each other along the first direction DR 1.

In the first display area DA1, a pair of first data wirings DL1 and a pair of first vertical power supply wirings VPL1 may be alternately arranged with each other. For example, a pair of first vertical power supply wirings VPL1 adjacent in the first direction DR1 and a pair of first data wirings DL1 adjacent in the first direction DR1 may be spaced apart from each other in the first direction DR 1. The first data wiring DL1 different from the pair of first vertical power supply wirings VPL1 may be arranged along the first direction DR1 with reference to any one of the first data wirings DL1. A pair of first vertical power supply wirings VPL1 may be disposed between two first data wirings DL1 different from each other. In an embodiment, the interval between the pair of first data wirings DL1 adjacent to each other may be greater than the interval between the pair of first vertical power wirings VPL1 adjacent to each other, and the interval between the first data wirings DL1 and the first vertical power wirings VPL1 may be the same as the interval between the pair of first vertical power wirings VPL1 adjacent to each other.

In the second display area DA2, a pair of second data wirings DL2 and a pair of first data connection wirings DCL1 may be alternately arranged with each other. For example, a pair of first data connection wirings DCL1 adjacent in the first direction DR1 and a pair of second data wirings DL2 adjacent in the first direction DR1 may be spaced apart from each other in the first direction DR 1. The second data wiring DL2 different from the pair of first data connection wirings DCL1 may be arranged in the first direction DR1 with reference to any one of the second data wirings DL2. A pair of first data connection wirings DCL1 may be disposed between two second data wirings DL2 different from each other. In an embodiment, the interval between the pair of second data wirings DL2 adjacent to each other may be greater than the interval between the pair of first data connection wirings DCL1 adjacent to each other, and the interval between the second data wirings DL2 and the first data connection wirings DCL1 may be the same as the interval between the pair of first data connection wirings DCL1 adjacent to each other.

As will be described later, in the display device 10 according to an embodiment, the wirings and patterns connected to two sub-pixels SPX adjacent in the first direction DR1 may be arranged to have a symmetrical structure or Flip (Flip) structure with each other, and accordingly, the data wirings DL1, DL2 and the first data connection wiring DCL1 and the first vertical power supply wiring VPL1 may have an arrangement as shown in fig. 7. One first vertical power supply wiring VPL1 and one first data wiring DL1 adjacent to each other or one first data connection wiring DCL1 and one second data wiring DL2 adjacent to each other may be connected to a certain sub-pixel SPX (e.g., a first sub-pixel), and wirings spaced apart therefrom in the first direction DR1 and arranged in a symmetrical structure may be connected to another sub-pixel SPX (e.g., a second sub-pixel).

The arrangement of the first data wiring DL1 in the first display area DA1 may be substantially the same as the arrangement of the second data wiring DL2 in the second display area DA2, and the arrangement of the first vertical power supply wiring VPL1 in the first display area DA1 may be very similar to the arrangement of the first data connection wiring DCL1 in the second display area DA 2. For the arrangement of the wirings in the display area DA, the first data wiring DL1 and the second data wiring DL2 are substantially the same wirings, and the first vertical power supply wiring VPL1 and the first data connection wiring DCL1 may be wirings which are similar in overall arrangement form and are divided based on the connection relationship with the second data connection wiring DCL2 and the arranged positions.

The plurality of second data connection wirings DCL2 and the second horizontal power supply wiring HPL2 may be disposed across the first display area DA1 and the second display area DA 2. Each of the second data connection wiring DCL2 and the second horizontal power supply wiring HPL2 may extend in the first direction DR1 and be aligned in the second direction DR 2. For example, the second data connection wirings DCL2 and the second horizontal power supply wirings HPL2 may be alternately arranged in the second direction DR 2. One second data connection wire DCL2 may be disposed between two second horizontal power supply wires HPL2 adjacent in the second direction DR2, and one second horizontal power supply wire HPL2 may be disposed between two second data connection wires DCL2 adjacent in the second direction DR 2.

The plurality of first vertical dummy patterns VDP1 may be disposed at the second display area DA2. The first vertical dummy patterns VDP1 may extend in the second direction DR2 similarly to the first data connection wiring DCL1 and be arranged spaced apart from each other in the first direction DR 1. Each of the first vertical dummy patterns VDP1 may be disposed in the second display area DA2 corresponding to the first data connection wiring DCL1 and may be spaced apart from each of the first data connection wiring DCL1 in the second direction DR 2.

The plurality of first horizontal dummy patterns HDP1 may be disposed at the first display area DA1 and the second display area DA2. The first horizontal dummy pattern HDP1 may extend in the first direction DR1 similarly to the second data connection wiring DCL2 and be arranged spaced apart from each other in the second direction DR 2. The first horizontal dummy patterns HDP1 and the second horizontal power supply wirings HPL2 may be alternately arranged with each other along the second direction DR 2. Each of the first horizontal dummy patterns HDP1 may be arranged corresponding to the second data connection wiring DCL2, and may be spaced apart from each of the second data connection wirings DCL2 along the first direction DR 1.

A spacer where the first data connection wiring DCL1 and the first vertical dummy pattern VDP1 are spaced apart from each other may overlap the second horizontal power supply wiring HPL 2. However, without being limited thereto, the spacer may not overlap the second horizontal power supply wiring HPL 2.

The spacer portion of the second data connection wiring DCL2 spaced apart from the first horizontal dummy pattern HDP1 may be disposed between the first data wiring DL1 and the first vertical power supply wiring VPL1, or may be disposed between the second data wiring DL2 and the first data connection wiring DCL 1. However, the spacer may overlap the data wirings DL1 and DL2, the first data connection wiring DCL1, or the first vertical power supply wiring VPL 1.

The first data connection wiring DCL1 may be electrically connected to the second data connection wiring DCL2 in the second display area DA 2. For example, the first data connection wiring DCL1 may be connected to any one of the second data connection wirings DCL2 through the first data connection hole DCH 1. The second display area DA2 may be an area where a plurality of first data connection holes DCH1 are arranged.

The second data connection wiring DCL2 may be electrically connected to the first data wiring DL1 in the first display area DA 1. For example, the second data connection wiring DCL2 may be connected to any one of the first data wirings DL1 through the second data connection hole DCH 2. The first display area DA1 may be an area where a plurality of second data connection holes DCH2 are arranged.

The first data connection holes DCH1 may be aligned in the first diagonal direction in the second display area DA 2. The second data connection holes DCH2 may be aligned in the second diagonal direction in the first display area DA 1.

The first and second data connection wirings DCL1 and DL2 of the second display area DA2 may be connected to the fan-out wirings (FL 1 and FL2 of fig. 4) and respectively applied with data signals. The first data connection wiring DCL1 may be electrically connected to the second data connection wiring DCL2, and the first data wiring DL1 of the first display area DA1 may be electrically connected to the second data connection wiring DCL2 to be applied with a data signal. The first vertical power supply line VPL1 of the first display area DA1 has a similar arrangement to the first data connection line DCL1, and is connected to the first power supply line PL1 to be applied with a first power supply voltage. The second horizontal power supply line HPL2 may be connected to the first power supply line PL1 to apply the first power supply voltage.

Fig. 8 is a plan view illustrating wirings disposed at a third display region and a fourth display region of a display device according to an embodiment. Fig. 8 illustrates an arrangement of the data wirings DL1, DL2, the first vertical power supply wiring VPL1, the first horizontal power supply wiring HPL1, and the second horizontal power supply wiring HPL2 arranged in the third display area DA3 and the fourth display area DA4.

Referring to fig. 8, the plurality of first data wirings DL1 and the plurality of first vertical power supply wirings VPL1 may be disposed at the third display area DA3, and the plurality of second data wirings DL2 and the plurality of first vertical dummy patterns VDP1 may be disposed at the fourth display area DA4. The description of their arrangement is substantially the same as that described hereinabove with reference to fig. 7.

The plurality of first and second horizontal power supply wirings HPL1 and HPL2 may be disposed across the third and fourth display areas DA3 and DA 4. The first and second horizontal power supply wirings HPL1 and HPL2 may extend in the first direction DR1 and be aligned in the second direction DR2, respectively. For example, the first and second horizontal power supply wirings HPL1 and HPL2 may be alternately arranged in the second direction DR 2. One first horizontal power supply line HPL1 may be disposed between two second horizontal power supply lines HPL2 adjacent in the second direction DR2, and one second horizontal power supply line HPL2 may be disposed between two first horizontal power supply lines HPL1 adjacent in the second direction DR 2.

The first horizontal power supply wiring HPL1 may be electrically connected to the first vertical power supply wiring VPL1 in the third display area DA 3. For example, the first horizontal power supply wiring HPL1 may be connected to any one of the first vertical power supply wirings VPL1 through the second power supply hole PH 2. The third display area DA3 may be an area where a plurality of second power holes PH2 are arranged.

The first horizontal power supply line HPL1 may be electrically connected to the first vertical dummy pattern VDP1 in the fourth display area DA 4. For example, the first horizontal power supply wiring HPL1 may be connected to any one of the first vertical dummy patterns VDP1 through the first power supply hole PH 1. The fourth display area DA4 may be an area where a plurality of first power holes PH1 are arranged. The first horizontal power supply line HPL1 may be electrically connected to the first power supply line PL1 to be applied with a first power supply voltage.

The first power holes PH1 may be arranged in the first diagonal direction in the fourth display area DA 4. The second power holes PH2 may be arranged in the second diagonal direction in the third display area DA 3.

The first and second display areas DA1 and DA2 and the third and fourth display areas DA3 and DA4 may be areas divided from each other according to whether the data connection wirings DCL1 and DCL2 are arranged or not. In the display area DA, the arrangement structure of the wirings may be similar regardless of the position, but the kinds of electric signals applied to the wirings may be different from each other. Accordingly, in a part of the display area DA, a mark identifiable from the outside may be generated as a signal different from that of other areas is applied.

For example, the conductive layers disposed at the sub-pixels SPX disposed at the display area DA may have the same arrangement structure as each other regardless of the positions of the sub-pixels SPX. However, the wiring adjacent to the conductive layer may be applied with a different electric signal based on the position in the display area DA, and may also cause generation of spots due to such a difference in the applied signal. The display device 10 according to an embodiment may include wirings to which different signals are applied based on the position in the display area DA, and may have a structure capable of preventing generation of a mark caused by the wirings. The structure of the subpixel SPX is described in detail below with reference to other drawings.

Fig. 9 and 10 are layout diagrams illustrating adjacent two sub-pixels of a display device according to an embodiment. Fig. 11 is a cross-sectional view taken along line N1-N1' of fig. 9 and 10.

Fig. 9 and 10 are layout diagrams of a plurality of semiconductor layers and a plurality of conductive layers, which show a plurality of wirings and electrodes of the pixel driving section PDU arranged at two sub-pixels SPX1, SPX2 adjacent to each other in the first direction DR 1. Fig. 9 illustrates wirings and electrodes of the lower metal layer CAS, the first semiconductor layer, the first gate conductive layer, the second gate conductive layer, and the first source drain layer, and fig. 10 illustrates wirings and electrodes of the first semiconductor layer, the second semiconductor layer, the third gate conductive layer, the first source drain layer, and the second source drain layer. Fig. 11 illustrates a section across the driving transistor DT and the sixth transistor ST6 of the first subpixel SPX 1.

Referring to fig. 9 to 11, the display device 10 may include a plurality of sub-pixels SPX, and two sub-pixels SPX1, SPX2 adjacent in the first direction DR1 may include wirings and electrodes symmetrically arranged with each other. For example, in the first and second sub-pixels SPX1 and SPX2, wirings connected to them, respectively, and semiconductor layers of transistors may be arranged in a specific pattern, and the pattern of the first sub-pixel SPX1 and the pattern of the second sub-pixel SPX2 may have a symmetrical structure to each other. As shown in fig. 9 and 10, the pattern of the wirings and electrodes arranged at the first subpixel SPX1 and the pattern of the wirings and electrodes arranged at the second subpixel SPX2 may have a symmetrical structure or a flip-chip structure with respect to each other with respect to the dummy line extending in the second direction DR 2. In the display device 10, the pattern of the wirings and the electrodes may be repeatedly arranged with reference to a pair of sub-pixels SPX1, SPX2 instead of reference to one sub-pixel SPX. Although not illustrated in the drawings, the same pattern as the wirings and electrodes of the first and second sub-pixels SPX1 and SPX2 may be repeatedly arranged in the first direction DR1 or the second direction DR2 in the sub-pixels SPX adjacent to the first and second sub-pixels SPX1 and SPX 2.

For the description of the plurality of layers disposed at the SUB-pixels SPX of the display device 10, the display device 10 may include a substrate SUB and a plurality of semiconductor layers, a plurality of conductive layers, and a plurality of insulating layers disposed on the substrate SUB. The semiconductor layer, the conductive layer, and the insulating layer may constitute elements of the pixel driving section PDU of the sub-pixel SPX or wirings connected to the sub-pixel SPX, respectively.

The substrate SUB may be a base substrate or a base member. The substrate SUB may be a Flexible (Flexible) substrate capable of Bending (Folding), folding (Rolling), rolling, or the like. For example, the substrate SUB may include a polymer resin such as Polyimide (PI), but is not limited thereto. In another embodiment, the substrate SUB may comprise a glass material or a metal material.

The first buffer layer BF1 may be disposed on the substrate SUB. The first buffer layer BF1 can protect the organic light emitting layer 172 of the thin film transistor and the light emitting element ED from moisture permeated through the substrate SUB which is easily permeable to moisture. The first buffer layer BF1 may be constituted by using a plurality of inorganic films alternately stacked. For example, the first buffer layer BF1 may be formed using a multilayer film in which one or more inorganic films of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked. The first buffer layer BF1 may be omitted.

The lower metal layer CAS may be disposed on the first buffer layer BF 1. The lower metal layer CAS may be disposed on the entire surface of the display panel 100 and may be disposed to overlap a portion of the first semiconductor layer. The lower metal layer CAS may be disposed to extend substantially in the first direction DR1 and the second direction DR2, and may be disposed in a Mesh (drain) form over the entire surface of the display area DA. An extension portion having a relatively wide width may be disposed at a portion of the lower metal layer CAS where portions extending in the first and second directions DR1 and DR2 intersect, and may overlap with an active layer of the driving transistor DT in the first semiconductor layer in the third direction DR3 as a thickness direction.

The lower metal layer CAS may include a material blocking light to prevent light from being incident to the active layer of the driving transistor DT, or may be electrically connected to the active layer of the driving transistor DT to perform a function of stabilizing the electrical characteristics of the driving transistor DT. In an exemplary embodiment, the lower metal layer CAS may be formed as a single layer or a plurality of layers using any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof. In some embodiments, the lower metal layer CAS may be omitted.

The second buffer layer BF2 may be disposed on the lower metal layer CAS. The second buffer layer BF2 may protect the organic light emitting layer 172 of the thin film transistor and the light emitting element ED from moisture permeated through the substrate SUB which is easily permeable to moisture, similarly to the first buffer layer BF 1.

The first semiconductor layer may be disposed on the second buffer layer BF 2. The first semiconductor layer may include polycrystalline silicon or monocrystalline silicon. However, it is not limited thereto.

The first semiconductor layer may include active layers of the driving transistor DT, the first transistor ST1, the second transistor ST2, the fifth transistor ST5, the sixth transistor ST6, and the seventh transistor ST 7. As will be described later, the active layers of the third transistor ST3 and the fourth transistor ST4 may be disposed at the second semiconductor layer.

In an embodiment in which two sub-pixels SPX adjacent in the first direction DR1 have a symmetrical structure, the first semiconductor layer of the first sub-pixel SPX1 and the first semiconductor layer of the second sub-pixel SPX2 may have structures connected to each other. The shapes of the first semiconductor layer patterns disposed at the respective sub-pixels SPX may have a symmetrical structure with each other based on the boundary of the first sub-pixel SPX1 and the second sub-pixel SPX 2. The portion where the first semiconductor layer of the first subpixel SPX1 is connected to the first semiconductor layer of the second subpixel SPX2 may be a first electrode S5 of a fifth transistor ST5 described later.

The active layer of the driving transistor DT may include a channel layer DTCH, a first electrode DTs, and a second electrode DTD. The channel layer DTCH of the driving transistor DT may overlap with the gate electrode GDT of the first gate conductive layer and the extension of the lower metal layer CAS. The first electrode DTs of the driving transistor DT may be connected to the second electrode D2 of the second transistor ST2 and the second electrode D5 of the fifth transistor ST 5. The second electrode DTD of the driving transistor DT may be connected to the first electrode S3 of the third transistor ST3 and the first electrode S6 of the sixth transistor ST 6.

The active layer of the first transistor ST1 may include a channel layer CH1, a first electrode S1, and a second electrode D1. The channel layer CH1 of the first transistor ST1 may overlap the bias scan wiring GBL of the first gate conductive layer. A part of the bias scan wiring GBL may function as the gate electrode G1 of the first transistor ST 1. The first electrode S1 of the first transistor ST1 may be electrically connected to the first electrode DTs of the driving transistor DT. The second electrode D1 of the first transistor ST1 may be electrically connected to the bias voltage wiring VOBS. The first electrode S1 of the first transistor ST1 is electrically connected to the first electrode DTs of the driving transistor DT through the first connection electrode BE1 of the first source-drain layer, and the second electrode D1 of the first transistor ST1 may BE electrically connected to the bias voltage wiring VOBS through the second connection electrode BE2 of the first source-drain layer.

The active layer of the second transistor ST2 may include a channel layer CH2, a first electrode S2, and a second electrode D2. The channel layer CH2 of the second transistor ST2 may overlap the write scan wiring GWL of the first gate conductive layer. A part of the write scan wiring GWL may function as the gate electrode G2 of the second transistor ST 2. The first electrode S2 of the second transistor ST2 may be electrically connected to the data wiring DL. The second electrode D2 of the second transistor ST2 may be connected to the first electrode DTs of the driving transistor DT. The first electrode S2 of the second transistor ST2 may BE in contact with the third connection electrode BE3 of the first source-drain layer and may BE electrically connected with the data wiring DL of the second source-drain layer through the third connection electrode BE 3.

The active layer of the fifth transistor ST5 may include a channel layer CH5, a first electrode S5, and a second electrode D5. The channel layer CH5 of the fifth transistor ST5 may overlap the light emitting wiring EML of the first gate conductive layer. A part of the light emitting wiring EML may function as the gate electrode G5 of the fifth transistor ST 5. The first electrode S5 of the fifth transistor ST5 may be electrically connected to the first vertical wiring vdd_v. The second electrode D5 of the fifth transistor ST5 may be connected to the first electrode DTs of the driving transistor DT. The first electrode S5 of the fifth transistor ST5 may be electrically connected to the first vertical wiring vdd_v of the second source-drain layer through the voltage connection electrode VBE of the first source-drain layer.

The active layer of the sixth transistor ST6 may include a channel layer CH6, a first electrode S6, and a second electrode D6. The channel layer CH6 of the sixth transistor ST6 may overlap the light emitting wiring EML of the first gate conductive layer. A part of the light emitting wiring EML may function as the gate electrode G6 of the sixth transistor ST 6. The first electrode S6 of the sixth transistor ST6 may be connected to the second electrode DTD of the driving transistor DT. The second electrode D6 of the sixth transistor ST6 may be electrically connected to the second electrode D7 of the seventh transistor ST7 and the pixel electrode 171 of the light emitting element ED. The second electrode D6 of the sixth transistor ST6 may BE electrically connected to the pixel electrode 171 through the seventh connection electrode BE7 of the first source-drain layer and the ninth connection electrode BE9 of the second source-drain layer.

The active layer of the seventh transistor ST7 may include a channel layer CH7, a first electrode S7, and a second electrode D7. The channel layer CH7 of the seventh transistor ST7 may overlap the bias scan wiring GBL of the first gate conductive layer. A part of the bias scan wiring GBL may function as the gate electrode G7 of the seventh transistor ST 7. The first electrode S7 of the seventh transistor ST7 may be electrically connected to the second initialization voltage wiring valid. The second electrode D7 of the seventh transistor ST7 may be electrically connected to the second electrode D6 of the sixth transistor ST6 and the pixel electrode 171 of the light emitting element ED. The first electrode S7 of the seventh transistor ST7 may BE electrically connected to the second initialization voltage wiring fail of the third gate conductive layer through the eighth connection electrode BE8 of the first source-drain layer.

The active layers of the driving transistor DT, the second transistor ST2, the fifth transistor ST5, the sixth transistor ST6, and the seventh transistor ST7 are formed in one pattern connected to each other in the first semiconductor layer, and the active layer of the first transistor ST1 may be formed in a pattern separated from the active layers of the other transistors or an Island (Island) pattern. The first transistor ST1 may be electrically connected to other transistors through a connection electrode of the first source-drain layer. Although the active layers of the third transistor ST3 and the fourth transistor ST4, which will be described later, may be arranged at a second semiconductor layer arranged at a different layer from the first semiconductor layer, differently from the other transistors. The third transistor ST3 and the fourth transistor ST4 may be electrically connected to other transistors through a connection electrode of the first source-drain layer.

The first gate insulating layer GI1 may be disposed on the first semiconductor layer and the second buffer layer BF 2. The first gate insulating layer GI1 may function as a gate insulating film of a transistor.

The first gate conductive layer may be disposed on the first gate insulating layer GI 1. The first gate conductive layer may include a first initialization voltage wiring VIL, a write scan wiring GWL, a gate electrode GDT of the driving transistor DT, a light emitting wiring EML, and a bias scan wiring GBL.

The gate electrode GDT of the driving transistor DT may be disposed to overlap the channel layer DTCH of the driving transistor DT in the first semiconductor layer. In addition, the gate electrode GDT of the driving transistor DT may overlap with the extension of the lower metal layer CAS. The gate electrodes GDT of the plurality of driving transistors DT may be arranged to be spaced apart in the first and second directions DR1 and DR2 across the entire surface of the display area DA. The gate electrode GDT of the driving transistor DT may be formed integrally with the first capacitance electrode of the capacitor C1. The first capacitance electrode of the capacitor C1 may be a part of the gate electrode GDT of the driving transistor DT.

The first initialization voltage wiring VIL may extend in the first direction DR 1. The first initialization voltage wiring VIL may be disposed at an upper side of each sub-pixel SPX as one side in the second direction DR 2. The first initialization voltage wiring VIL may be electrically connected to the first electrode S4 of the fourth transistor ST 4. The first initialization voltage wiring VIL may BE electrically connected to the first electrode S4 of the fourth transistor ST4 through the sixth connection electrode BE6 of the first source-drain layer.

The write scan wiring GWL may extend in the first direction DR 1. The write scan wiring GWL is spaced apart from the first initialization voltage wiring VIL in the second direction DR2, and may be disposed at a lower side of the first initialization voltage wiring VIL as the other side in the second direction DR 2. The write scan wiring GWL may be disposed to overlap the channel layer CH2 of the second transistor ST2, and a portion of the write scan wiring GWL may be the gate electrode G2 of the second transistor ST 2.

The light emitting wiring EML may extend in the first direction DR 1. The light emitting wiring EML may be spaced apart from the gate electrode GDT of the driving transistor DT in the second direction DR2 in the subpixel SPX, and may be disposed at a lower side of the gate electrode GDT. The light emitting wiring EML may be arranged to overlap the channel layers CH5, CH6 of the fifth and sixth transistors ST5, ST6, and a portion of the light emitting wiring EML may be the gate electrodes G5, G6 of the fifth and sixth transistors ST5, ST 6.

The bias scan wiring GBL may extend in the first direction DR 1. The bias scan wiring GBL may be spaced apart from the light emitting wiring EML in the second direction DR2 and disposed at a lower side of the light emitting wiring EML. The bias scan wiring GBL may be arranged to overlap the channel layers CH1, CH7 of the first and seventh transistors ST1, ST7, and a portion of the bias scan wiring GBL may be the gate electrodes G1, G7 of the first and seventh transistors ST1, ST 7.

The second gate insulating layer GI2 may be disposed on the first gate conductive layer. The second gate insulating layer GI2 may perform a function of an insulating film between the first gate conductive layer and other layers disposed thereon, and may protect the first gate conductive layer.

The second gate conductive layer may be disposed on the second gate insulating layer GI 2. The second gate conductive layer may include a first initialization scan wiring GIL1, a first control scan wiring GCL1, and a second horizontal wiring vdd_h.

The first initialization scan wiring GIL1 may extend in the first direction DR 1. The first initialization scan wiring GIL1 may be disposed at an upper side of each sub-pixel SPX. The first initialization scan wiring GIL1 may be arranged to overlap the channel layer CH4 of the fourth transistor ST 4. A portion of the first initialization scan wiring GIL1 may be the gate electrode G4 of the fourth transistor ST 4.

The first control scan line GCL1 may extend in the first direction DR 1. The first control scan line GCL1 may be spaced apart from the first initialization scan line GIL1 in the second direction DR2 and disposed at a lower side of the first initialization scan line GIL 1. The first control scan wiring GCL1 may be arranged to overlap the channel layer CH3 of the third transistor ST 3. A part of the first control scan line GCL1 may be a gate electrode G3 of the third transistor ST 3.

The second horizontal wiring vdd_h may extend in the first direction DR 1. The second horizontal wiring vdd_h may be spaced apart from the first control scan wiring GCL1 in the second direction DR2 and disposed at a lower side of the first control scan wiring GCL 1. The second horizontal wiring vdd_h may be connected to the first power supply wiring PL1 in the non-display region NDA, and may be disposed to overlap the gate electrode GDT of the first gate conductive layer within the subpixel SPX, and may function as a second capacitance electrode of the capacitor C1.

The first interlayer insulating layer IL1 may be disposed on the second gate conductive layer. The first interlayer insulating layer IL1 performs the function of an insulating film between the second gate conductive layer and other layers disposed thereon, and can protect the second gate conductive layer.

The second semiconductor layer may be disposed on the first interlayer insulating layer IL 1. The second semiconductor layer may include an oxide semiconductor layer. The second semiconductor layer may include active layers of the third transistor ST3 and the fourth transistor ST 4.

The active layer of the third transistor ST3 may include a channel layer CH3, a first electrode S3, and a second electrode D3. The channel layer CH3 of the third transistor ST3 may overlap the first control scan line GCL1 of the second gate conductive layer and the second control scan line GCL2 of the third gate conductive layer. A portion of each of the first control scan wiring GCL1 and the second control scan wiring GCL2 may function as the gate electrode G3 of the third transistor ST 3. The third transistor ST3 may have a structure in which gate electrodes are disposed at upper and lower portions of the active layer, respectively.

The first electrode S3 of the third transistor ST3 may be electrically connected to the second electrode DTD of the driving transistor DT. The second electrode D3 of the third transistor ST3 may be connected to the first capacitive electrode of the capacitor C1 and the first electrode S4 of the fourth transistor ST 4. The second electrode D3 of the third transistor ST3 may BE electrically connected to the first capacitive electrode of the capacitor C1 and the gate electrode GDT of the driving transistor DT through the fifth connection electrode BE5 of the first source-drain layer. The first electrode S3 of the third transistor ST3 may BE electrically connected to the second electrode DTD of the driving transistor DT through the fourth connection electrode BE4 of the first source-drain layer.

The active layer of the fourth transistor ST4 may include a channel layer CH4, a first electrode S4, and a second electrode D4. The channel layer CH4 of the fourth transistor ST4 may overlap the first initializing scan wiring GIL1 of the second gate conductive layer and the second initializing scan wiring GIL2 of the third gate conductive layer. A portion of each of the first and second initialization scan wirings GIL1 and GIL2 may function as a gate electrode G4 of the fourth transistor ST 4. Similar to the third transistor ST3, the fourth transistor ST4 may have a structure in which gate electrodes are disposed at upper and lower portions of the active layer, respectively.

The first electrode S4 of the fourth transistor ST4 may be connected to the second electrode D3 of the third transistor ST 3. The second electrode D4 of the fourth transistor ST4 may be electrically connected to the first initialization voltage wiring VIL. The second electrode D4 of the fourth transistor ST4 may BE electrically connected to the first initialization voltage wiring VIL through the sixth connection electrode BE6 of the first source-drain layer.

The third gate insulating layer GI3 may be disposed on the second semiconductor layer. The third gate insulating layer GI3 may function as a gate insulating film of the transistor.

The third gate conductive layer may be disposed on the third gate insulating layer GI 3. The third gate conductive layer may include a second initialization scan wiring GIL2, a second control scan wiring GCL2, a bias voltage wiring VOBS, and a second initialization voltage wiring fail.

The second initialization scan wiring GIL2 may extend in the first direction DR 1. The second initialization scan wiring GIL2 may be disposed at an upper side of each sub-pixel SPX. The second initialization scan wiring GIL2 may be arranged to overlap the channel layer CH4 of the fourth transistor ST 4. The second initialization scan wiring GIL2 may overlap the first initialization scan wiring GIL1 of the second gate conductive layer in the thickness direction, and both may extend in the same direction. In some embodiments, the first and second initialization scan wirings GIL1 and GIL2 may have substantially the same pattern shape in a plan view.

The second control scan line GCL2 may extend in the first direction DR 1. The second control scan line GCL2 may be spaced apart from the second initialization scan line GIL2 in the second direction DR2 and disposed at a lower side of the second initialization scan line GIL 2. The second control scan line GCL2 may be arranged to overlap the channel layer CH3 of the third transistor ST 3. The second control scan line GCL2 may overlap the first control scan line GCL1 of the second gate conductive layer in the thickness direction, and both may extend in the same direction. In some embodiments, the first and second control scan wirings GCL1 and GCL2 may have substantially the same pattern shape in a plan view.

The second initialization voltage wiring valid may extend in the first direction DR 1. The second initialization voltage wiring valid may be disposed at the lower side of the sub-pixel SPX. The second initialization voltage wiring valid may overlap the light emitting wiring EML of the first gate conductive layer in the thickness direction, and both may extend in the same direction. The second initialization voltage wiring valid may be electrically connected to the first electrode S7 of the seventh transistor ST 7. The second initialization voltage wiring VAIL may BE electrically connected to the first electrode S7 of the seventh transistor ST7 through the eighth connection electrode BE8 of the first source-drain layer.

The offset voltage wiring VOBS may extend in the first direction DR 1. The bias voltage wiring VOBS may be disposed at a lower side of the second initialization voltage wiring VAIL. The bias voltage wiring VOBS may be arranged to overlap the bias scan wiring GBL of the first gate conductive layer. The bias voltage wiring VOBS may be electrically connected to the first electrode S1 of the first transistor ST 1. The bias voltage wiring VOBS may BE connected to the first electrode S1 of the first transistor ST1 through the first connection electrode BE1 of the first source-drain layer.

The second interlayer insulating layer IL2 may be disposed on the third gate conductive layer. The second interlayer insulating layer IL2 performs the function of an insulating film between the third gate conductive layer and other layers disposed thereon, and can protect the third gate conductive layer.

The first source drain layer may be disposed on the second interlayer insulating layer IL 2. The first source-drain layer may include a second data connection wiring DCL2 and a plurality of connection electrodes BE1, BE2, BE3, BE4, BE5, BE6, BE7, BE8. The plurality of connection electrodes BE1, BE2, BE3, BE4, BE5, BE6, BE7, BE8 may BE connected to wiring or semiconductor layers arranged at different layers from each other, respectively, and electrically connect them to each other.

The second data connection wiring DCL2 may extend in the first direction DR1 and be disposed at an upper side of the sub-pixel SPX. As described with reference to fig. 7 and 8, the electrical connection of the second data connection wiring DCL2 with different wirings may be different according to the display areas DA1, DA2, DA3, DA4 in which the corresponding sub-pixels SPX are arranged. For example, the second data connection wiring DCL2 of the sub-pixel SPX disposed in the first display area DA1 or the second display area DA2 may be a wiring electrically connected to the first data connection wiring DCL1 and the first data wiring DL 1. Alternatively, the second data connection wiring DCL2 may be the first horizontal dummy pattern HDP1 which is not connected to the first data connection wiring DCL1 and the first data wiring DL 1. The second data connection wiring DCL2 of the sub-pixel SPX arranged in the third display area DA3 or the fourth display area DA4 may also be the first horizontal power supply wiring HPL1.

The second data connection wiring DCL2 illustrated in fig. 9 and 10 illustrates the first data wiring DL1 and wirings not connected to the first data connection wiring DCL 1. In this case, the second data connection wiring DCL2 may be the first horizontal dummy pattern HDP1 or the first horizontal power supply wiring HPL1. As will BE described later, in the case where the second data connection wiring DCL2 is connected to the first data wiring DL1 and the first data connection wiring DCL1, it may BE integrated with any one of the third connection electrodes BE3 arranged on the lower side of the second data connection wiring DCL 2. The second data connection wiring DCL2 may BE electrically connected to the first data connection wiring DCL1 or the first data wiring DL1 through the third connection electrode BE 3.

The first to eighth connection electrodes BE1 to BE8 may BE connected to a layer disposed at a lower portion with respect to the first source-drain layer through contact holes CNT1, CNT2 penetrating the insulating layer at the lower portion. For example, the first connection electrode BE1 may BE connected to the first semiconductor layer through a first contact hole CNT1 penetrating the first gate insulating layer GI1, the second gate insulating layer GI2, the third gate insulating layer GI3, the first interlayer insulating layer IL1, and the second interlayer insulating layer IL 2. The first connection electrode BE1 may BE connected to the second electrode D1 of the first transistor ST1 and the first electrode DTs of the driving transistor DT, respectively.

The second connection electrode BE2 may BE connected to the first electrode S1 of the first transistor ST1 in the first semiconductor layer through the first contact hole CNT 1. The second connection electrode BE2 may BE connected to the bias voltage wiring VOBS through the first contact hole CNT1 penetrating the second interlayer insulating layer IL 2.

The third connection electrode BE3 may BE disposed at a lower side of the second data connection wiring DCL 2. The third connection electrode BE3 may BE connected to the first data connection wiring DCL1 or the data wiring DL of the second data conductive layer through a second contact hole CNT2 penetrating the first VIA layer VIA1 and the first protection layer PV1, which will BE described later. In some embodiments, any one of the third connection electrodes BE3 may also BE integrated with the second data connection wiring DCL 2.

The fourth connection electrode BE4 may BE connected to the second electrode DTD of the driving transistor DT of the first semiconductor layer through the first contact hole CNT1 and may BE connected to the first electrode S3 of the third transistor ST3 of the second semiconductor layer through the second contact hole CNT 2. The fifth connection electrode BE5 may BE connected to the gate electrode GDT of the first gate conductive layer through the first contact hole CNT1, and may BE connected to the second electrode D3 of the third transistor ST3 through the second contact hole CNT 2. The sixth connection electrode BE6 may BE connected to the first initialization voltage wiring VIL through the first contact hole CNT1 and may BE connected to the second electrode D4 of the fourth transistor ST4 of the second semiconductor layer through the second contact hole CNT 2.

The seventh connection electrode BE7 may BE connected to the second electrode D6 of the sixth transistor ST6 through the first contact hole CNT1, and may BE connected to the ninth connection electrode BE9 through the second contact hole CNT 2. The eighth connection electrode BE8 may BE connected to the first electrode S7 of the seventh transistor ST7 through the first contact hole CNT1 and may BE connected to the second initialization voltage wiring VAIL through the second contact hole CNT 2.

The voltage connection electrode VBE may be connected to the first semiconductor layer and the first vertical wiring vdd_v, respectively. The voltage connection electrode VBE may be connected to the second electrode D6 of the sixth transistor ST6 of the first semiconductor layer through the first contact hole CNT1 and may be connected to the first vertical wiring vdd_v through the second contact hole CNT 2.

The first protection layer PV1 may be disposed on the first source-drain layer. The first protection layer PV1 may perform a function of an insulating film between the first source-drain layer and other layers disposed thereon, and may protect the first source-drain layer.

The first VIA layer VIA1 may be disposed on the first protection layer PV 1. The first VIA layer VIA1 may planarize a step formed by the lower layer while protecting the lower layer thereof.

The second source drain layer may be disposed on the first VIA layer VIA 1. The second source-drain layer may include a plurality of first data connection wirings DCL1, a plurality of data wirings DL, a first vertical wiring vdd_v, and a plurality of ninth connection electrodes BE9.

The plurality of first data connection wirings DCL1 and DL may extend in the second direction DR 2. One first data connection wiring DCL1 and one data wiring DL may be arranged in each of two sub-pixels SPX adjacent to each other (for example, in the first sub-pixel SPX1 and the second sub-pixel SPX 2). As described with reference to fig. 7 and 8, in the display device 10 according to an embodiment, a pair of first data connection wirings DCL1 are arranged adjacent to each other, and two data wirings DL different from each other may be arranged with the pair of first data connection wirings DCL1 interposed therebetween. The interval between the first data connection wiring DCL1 of the first subpixel SPX1 and the first data connection wiring DCL1 of the second subpixel SPX2 may be smaller than the interval between the first data wiring DL1 of the first subpixel SPX1 and the first data wiring DL1 of the second subpixel SPX 2. The first data connection wiring DCL1 of the first subpixel SPX1 and the second subpixel SPX2 illustrated in fig. 9 and 10 is disposed adjacent to a boundary therebetween, the data wiring DL of the first subpixel SPX1 may be disposed at a left side of the first data connection wiring DCL1, and the data wiring DL of the second subpixel SPX2 may be disposed at a right side of the first data connection wiring DCL 1.

Although not shown in the drawings, for an nth sub-pixel adjacent to the first sub-pixel SPX1 or the second sub-pixel SPX2 of fig. 9 and 10 in the first direction DR1, the data wiring DL and the first data connection wiring DCL1 of the nth sub-pixel may be spaced apart from a boundary that meets the first sub-pixel SPX1 or the second sub-pixel SPX 2. In other words, in the display device 10, the pattern shapes of the wirings, the semiconductor layers, and the electrodes illustrated in fig. 9 and 10 may be repeatedly arranged in the first direction DR1 and the second direction DR2 across the entire surface of the display area DA. In the display device 10, the first data connection wirings DCL1 may be disposed adjacent to each other on both sides of a boundary of two sub-pixels SPX adjacent in the first direction DR1, respectively, and the data wirings DL may be disposed apart from each other on both sides of the boundary, respectively (refer to fig. 12).

As described with reference to fig. 7 and 8, according to the display areas DA1, DA2, DA3, DA4 in which the corresponding sub-pixels SPX are arranged, the electrical connection between the first data connection wiring DCL1 and other wirings may be different, and the data wiring DL may be divided into data wirings different from each other.

For example, the first data connection wiring DCL1 of the sub-pixel SPX arranged in the first display area DA1 or the third display area DA3 may be the first vertical power supply wiring VPL1. The first data connection wiring DCL1 disposed at the sub-pixel SPX of the second display area DA2 or the fourth display area DA4 may be a wiring electrically connected to the second data connection wiring DCL2, or may be the first vertical dummy pattern VDP1. The data wiring DL disposed in the first display area DA1 or the third display area DA3 may be a first data wiring DL1 connected to the second data connection wiring DCL2, and the data wiring DL disposed in the second display area DA2 or the fourth display area DA4 may be a second data wiring DL2.

The first data connection wiring DCL1 illustrated in fig. 9 and 10 includes wiring not connected to the second data connection wiring DCL 2. In this case, the first data connection wiring DCL1 may be the first vertical power supply wiring VPL1 or the first vertical dummy pattern VDP1, otherwise, the first data connection wiring DCL1 may be a wiring connected to the second data connection wiring DCL2 at another position. The data wiring DL illustrated in fig. 9 and 10 may be a first data wiring DL1 or a second data wiring DL2.

The plurality of first data connection wirings DCL1 and DL may BE connected to the third connection electrode BE3 of the first source-drain layer through the second contact hole CNT2, respectively. The kinds and electrical connections of the first data connection wiring DCL1 and the data wiring DL may BE different according to the connection between the third connection electrode BE3 and the second data connection wiring DCL2, in which case the second contact hole CNT2 may BE divided into the data connection holes DCH1, DCH2 or the power supply holes PH1, PH2 of fig. 7 and 8. The detailed description about the arrangement between the data wiring DL and the first data connection wiring DCL1 will be described later with reference to other drawings.

The first vertical wiring vdd_v may extend in the second direction DR2 and be spaced apart from the data wiring DL in the first direction DR 1. The width of the first vertical wire vdd_v in the first direction DR1 may be relatively larger than the widths of the first data connection wire DCL1 and the data wire DL in the first direction DR 1. The first data connection wirings DCL1 of the adjacent two sub-pixels SPX may be respectively arranged between the two data wirings DL different from each other, and the first vertical wiring vdd_v may also be arranged between the two data wirings DL different from each other. The first data connection wiring DCL1 may be disposed between two data wirings DL disposed relatively adjacently, and the first vertical wiring vdd_v may be disposed between two data wirings DL spaced relatively far apart. Accordingly, the interval between the first vertical wiring vdd_v and the data wiring DL may be smaller than the interval between the first vertical wiring vdd_v and the first data connection wiring DCL 1. Such arrangement may be realized based on an arrangement relationship of a pair of first data connection wirings DCL1 and a pair of data wirings DL adjacent to each other.

The first vertical wiring vdd_v may be connected to the first power supply wiring PL1 in the non-display area NDA, and may be applied with a first power supply voltage. The first vertical wiring vdd_v may be connected to the voltage connection electrode VBE through the second contact hole CNT2 and may be electrically connected to the fifth transistor ST5 through the voltage connection electrode VBE.

The second VIA layer VIA2 may be disposed on the second source drain layer. The second VIA layer VIA2 may planarize a step formed by the lower layer while protecting the lower layer thereof.

In an exemplary embodiment, the first to third gate conductive layers, the first data conductive layer, and the second data conductive layer described above may be formed as a single layer or a plurality of layers composed of any one of (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. The first to third gate insulating layers GI1 to GI3, the first and second interlayer insulating layers IL1 and IL2, and the first protective layer PV1 may be formed by alternately stacking a plurality of inorganic layers. For example, the first to third gate insulating layers GI1 to GI3, the first and second interlayer insulating layers IL1 and IL2, and the first protective layer PV1 may be formed to include silicon oxide (SiO _x : silicon Oxide), silicon nitride (SiN _x : silicon Nitride), silicon oxynitride (SiO _x N _y : silicon Oxynitride) of a metal layerLayers or layers in which they are alternately stacked. However, it is not limited thereto. In some embodiments, the first and second interlayer insulating layers IL1 and IL2 may also be formed using an organic insulating substance such as Polyimide (PI).

The light emitting element ED and the pixel defining film PDL may be disposed on the second VIA layer VIA 2. The light emitting element ED may include a pixel electrode 171, an organic light emitting layer 172, and a common electrode 173. The light emitting elements ED arranged at the plurality of sub-pixels SPX may share the common electrode 173 with each other.

The pixel electrode 171 of the light emitting element ED may be disposed on the second VIA layer VIA 2. The pixel electrode 171 of the light emitting element ED may BE connected to the ninth connection electrode BE9 through the third contact hole CNT3 penetrating the second VIA layer VIA 2. The pixel electrode 171 may be formed using a metal substance having high reflectivity, and may be formed, for example, as a stacked structure of aluminum and titanium (Ti/Al/Ti), a stacked structure of aluminum and ITO (ITO/Al/ITO), an APC alloy, and a stacked structure of APC alloy and ITO (ITO/APC/ITO). The APC alloy is an alloy of silver (Ag), palladium (Pd), and copper (Cu).

The pixel defining film PDL may be disposed on the second VIA layer VIA2 and on a portion of the pixel electrode 171. The pixel defining film PDL may include an opening portion exposing a portion of the pixel electrode 171, and the organic light emitting layer 172 of the light emitting element ED may be disposed at the opening portion of the pixel defining film PDL. A light emitting portion of the light emitting element ED in which the pixel electrode 171, the organic light emitting layer 172, and the common electrode 173 are sequentially stacked so that holes from the pixel electrode 171 and electrons from the common electrode 173 can be recombined in the organic light emitting layer 172 to emit light may be defined as an opening portion of the pixel defining film PDL. The pixel defining film PDL may be formed using an organic film such as an acrylic resin (acryl resin), an epoxy resin (epoxy resin), a phenolic resin (phenol resin), a polyamide resin (polyamide resin), or a polyimide resin (polyimide resin).

The spacer SPC may be disposed on the pixel defining film PDL. In the manufacturing process of the display panel 100, a mask (mask) may be mounted on the spacers SPC. The spacer SPC may be formed using an organic film such as an acrylic resin (acryl resin), an epoxy resin (epoxy resin), a phenolic resin (phenolic resin), a polyamide resin (polyamide resin), a polyimide resin (polyimide resin), or the like.

The organic light emitting layer 172 may be disposed on the pixel electrode 171 of the light emitting element ED. The organic light emitting layer 172 may include an organic substance to emit light of a predetermined color. For example, the organic light emitting layer 172 may include a hole transport layer (hole transporting layer), an organic substance layer, and an electron transport layer (electron transporting layer).

The common electrode 173 may be disposed on the organic light emitting layer 172 and the pixel defining film PDL. The common electrode 173 may be formed to cover the organic light emitting layer 172. The common electrode 173 may be commonly formed at the light emitting part. A capping layer may be formed on the common electrode 173.

In the upper light emitting structure, the common electrode 173 may be formed using a transparent metal substance (TCO: transparent Conductive Material) such as ITO or IZO or a Semi-transmissive metal substance (Semi-transmissive Conductive Material) such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). In the case where the common electrode 173 is formed using a semi-transmissive metal substance, the light emitting efficiency of each light emitting portion can be improved by a micro cavity (micro cavity).

The thin film encapsulation layer TFE may be arranged on the light emitting element ED. The thin film encapsulation layer TFE may comprise at least one inorganic film to prevent permeation of the light emitting element ED by oxygen or moisture. Further, the thin film encapsulation layer TFE may include at least one organic film to protect the light emitting element ED from foreign matter such as dust. In the drawings, the case where the thin film encapsulation layer TFE has a single layer structure is exemplified, but not limited thereto. In some embodiments, the thin film encapsulation layer TFE may also have a structure in which inorganic insulating layers and organic insulating layers are alternately arranged with each other, or a structure including two inorganic insulating layers different from each other and an organic insulating layer arranged therebetween.

Fig. 12 is a schematic diagram showing data connection wirings and electrical connection of the data wirings of a display device according to an embodiment. Fig. 12 illustrates the arrangement of the data connection wirings DCL1, DCL2 and the data wirings DL1, DL2 of the sub-pixel SPX arranged in the first display area DA1 and the sub-pixel SPX arranged in the second display area DA 2. In fig. 12, the connection electrode of the first source-drain layer is omitted, and a part of wiring and wiring of the second source-drain layer are schematically illustrated.

Referring to fig. 12, the data wiring of the sub-pixel SPX disposed in the first display area DA1 may be the first data wiring DL1, and the data wiring of the sub-pixel SPX disposed in the second display area DA2 may be the second data wiring DL2. The first data connection wiring DCL1 disposed at the first display area DA1 may be a first vertical power supply wiring VPL1, and the first data connection wiring DCL1 disposed at the second display area DA2 may be a wiring connected to the second data connection wiring DCL 2.

The first data wiring DL1, the second data wiring DL2, and the first data connection wiring DCL1 disposed in each of the first and second display areas DA1 and DA2 may BE connected to the third connection electrode BE3 through the second contact hole CNT 2. In the plurality of third connection electrodes BE3, a part is integrated with the second data connection wiring DCL2 to constitute an electrical connection, and the other part is separated from the second data connection wiring DCL2 or remains in an Island (Island) pattern.

For example, among the third connection electrodes BE3 disposed at the second display area DA2, the third connection electrode BE3 connected to the first data connection wiring DCL1 may BE integrated with the second data connection wiring DCL 2. Among the third connection electrodes BE3 disposed in the first display area DA1, the third connection electrodes BE3 connected to the first data wiring DL1 may also BE integrated with the second data connection wiring DCL 2. Accordingly, the first data connection wiring DCL1, the second data connection wiring DCL2, and the first data wiring DL1 disposed in the first display area DA1 may be electrically connected to each other. By using such an electrical connection structure of the data connection wirings DCL1 and DCL2 and the data wirings DL1 and DL2, the area of the non-display area NDA required for the lower side of the first display area DA1 can be reduced.

In addition, as described above, the pattern shapes of the wirings and the electrodes arranged at the respective sub-pixels SPX may be substantially the same, and their electrical connections may be different from each other, depending on the position of the display area DA. For example, the positions and shapes at which the wirings disposed between the first data wirings DL1 of the first display area DA1 and the wirings disposed between the second data wirings DL2 of the second display area DA2 are respectively disposed may be substantially the same. However, the wiring of the first display area DA1 may be the first vertical power supply wiring VPL1 electrically connected to the first power supply wiring PL1, and the wiring disposed in the second display area DA2 may be the first data connection wiring DCL1.

The first data connection wiring DCL1 is applied with a different signal in the other display area DA except the second display area DA2, and the first data connection wiring DCL1 in the second display area DA2 may be applied with a data signal transferred to the first data wiring DL 1. Accordingly, the kind of signal applied to the corresponding wiring and the timing of applying the signal may be different from those of the wirings of the other display area DA. In particular, the first data connection wiring DCL1 may have an influence on an electric signal applied between adjacent other wirings or electrodes, which may have an influence on the light emission amount of the corresponding sub-pixel SPX, and may also cause generation of a speckle identifiable from the outside. The display device 10 according to an embodiment may have an arrangement structure of wirings as follows: even if a wiring in which the applied signal differs depending on the position of the display area DA is included, the light emission characteristics of the sub-pixel SPX are not affected by the wiring.

Fig. 13 is a plan view showing a portion B of fig. 9 and 10. Fig. 14 is a cross-sectional view taken along line N2-N2' of fig. 13.

Fig. 13 illustrates, as part B of fig. 9 and 10, areas where the first connection electrode BE1 and the first data connection wiring DCL1 and the data wiring DL of each sub-pixel SPX are arranged. Fig. 13 illustrates the relative arrangement of the first semiconductor layer, the first gate conductive layer, the third gate conductive layer, the first source drain layer, and the second source drain layer. The sub-pixels SPX illustrated in fig. 13 may be sub-pixels SPX respectively arranged in the second display area DA2, and the data wiring DL may be the second data wiring DL2.

According to an embodiment, the display device 10 may BE arranged such that the first data connection wiring DCL1 to which the data signal is applied and the data wiring DL do not overlap the first connection electrode BE1 connected to one electrode of the driving transistor DT and the first transistor ST 1. The first data connection wiring DCL1 extending in the second direction DR2 may BE arranged to BE spaced apart from the first connection electrode BE1 in the first direction DR1 in plan view, and not overlap with them in the third direction DR3 as the thickness direction, respectively. The data wiring DL extending in the second direction DR2 may BE arranged to BE spaced apart from the first connection electrode BE1 in the first direction DR1 in plan view, and not overlap with them in the third direction DR3 as the thickness direction, respectively.

Referring to fig. 9 and 13, the first connection electrode BE1 may BE connected to the first electrode DTs of the driving transistor DT and the second electrode D1 of the first transistor ST1, respectively. In the case where the subpixel SPX illustrated in fig. 13 is the subpixel SPX disposed at the first display area DA1, the first data connection wire DCL1 may be electrically connected to the first data wire DL1 disposed at the first display area DA1 and may be applied with a data signal applied to other subpixels SPX except for the subpixel SPX disposed with the first data connection wire DCL 1. Each of the data wirings DL of fig. 13 may be a second data wiring DL2 of the second display area DA 2.

If a data signal is applied to the first data connection wiring DCL1 while the sub-pixel SPX emits light, parasitic capacitance may also BE formed between the first connection electrodes BE1 arranged at different layers from each other. The parasitic capacitance formed between the first data connection wiring DCL1 and the first connection electrode BE1 may raise the potential of the first electrode DTs of the driving transistor DT. Meanwhile, if the second transistor ST2 is turned on by applying a scan signal through the write scan line GWL, the potential of the first electrode DTs of the driving transistor DT may further rise, and if the third transistor ST3 is turned on by applying a scan signal through the control scan lines GCL1, GCL2, the potential of the gate electrode GDT of the driving transistor DT may also rise.

The parasitic capacitance formed between the first data connection wiring DCL1 and the first connection electrode BE1 may generate a change in the potential of the source electrode (or the first electrode DTs) and the gate electrode of the driving transistor DT, which affects the light emission amount of the corresponding sub-pixel SPX. In the display area DA, the sub-pixel SPX formed with the parasitic capacitance may appear relatively dark, and a speckle identifiable from the outside may be generated due to an insufficient amount of light emitted from the plurality of sub-pixels SPX.

In order to prevent such a mark from being generated as the first data connection wiring DCL1 is arranged, the display device 10 according to an embodiment may have a structure that minimizes parasitic capacitance that may BE generated between the first data connection wiring DCL1 and the first connection electrode BE 1. For example, the first data connection wiring DCL1 may BE designed to avoid an arrangement structure of the first connection electrode BE1 connected to the first electrode DTs of the driving transistor DT.

As described above, the first data connection wiring DCL1 and the data wiring DL adjacent to their boundaries may be arranged at two sub-pixels (the first sub-pixel SPX1 and the second sub-pixel SPX2 of fig. 9 and 10) adjacent to each other in the first direction DR 1. Since the first semiconductor layer of the two sub-pixels SPX also has a symmetrical structure with respect to the boundary of the two sub-pixels SPX, the first connection electrode BE1 may also BE disposed adjacent to the boundary.

In a structure in which the first data connection wiring DCL1 arranged at the boundary of two sub-pixels SPX adjacent to each other in the first direction DR1 is arranged between the data wirings DL adjacent to each other, the first connection electrode BE1 may BE arranged at a region not overlapping with the first data connection wiring DCL1 and the data wiring DL. The first connection electrodes BE1 may BE disposed between one first data connection wiring DCL1 and one data wiring DL, respectively.

For example, the first connection electrode BE1 of the sub-pixel SPX disposed at the left side of fig. 13 is disposed between the data wiring DL and the first data connection wiring DCL1, and may BE disposed at the right side of the data wiring DL and the left side of the first data connection wiring DCL 1. The sub-pixel SPX of the right side of fig. 13 may have an arrangement structure of wirings and electrodes having a symmetrical structure with the sub-pixel SPX of the left side, and the first connection electrode BE1 of the sub-pixel SPX arranged on the right side may BE arranged between the first data connection wiring DCL1 and the data wiring DL and may BE arranged on the left side of the data wiring DL and the right side of the first data connection wiring DCL 1.

The first data connection wiring DCL1 may BE disposed to extend in the second direction DR2 regardless of the position, and conversely, the data wiring DL may have a shape that is bent toward the first direction DR1 by detouring the first connection electrode BE1 after extending in the second direction DR 2. The interval between the first data connection wiring DCL1 and the data wiring DL may BE different according to positions, and the maximum interval therebetween may have a width of such an extent that the first connection electrode BE1 can BE disposed.

Since the first data connection wiring DCL1 is arranged so as not to overlap the first connection electrode BE1 in the thickness direction, parasitic capacitance formed between the first connection electrode BE1 of the first source-drain layer and the first data connection wiring DCL1 of the second source-drain layer can BE minimized. As the data wiring DL is also arranged not to overlap the first connection electrode BE1, parasitic capacitance formed therebetween can also BE minimized. If parasitic capacitance between the first connection electrodes BE1 is hardly formed when a data signal is applied to the first data connection wiring DCL1, it is possible to reduce a potential variation of the first electrode DTs of the driving transistor DT and reduce an influence on the light emission amount of the corresponding sub-pixel SPX. Accordingly, the display device 10 can prevent the generation of the mark in the display area DA due to the arrangement of the first data connection wiring DCL 1.

However, in the display device 10, when the data signal is applied to the first data connection wiring DCL1, parasitic capacitance may not BE formed between the first connection electrodes BE1, and thus, the first connection electrodes BE1 and the data wiring DL do not necessarily overlap. The display device 10 may have a structure in which the bent portion of the data line DL is reduced to increase the straightness, and the data line DL and the first connection electrode BE1 may BE overlapped in the thickness direction according to circumstances. The explanation will be described later with reference to other embodiments.

In addition, the voltage connection electrode VBE may BE disposed between two first connection electrodes BE1 adjacent to each other. A portion of the voltage connection electrode VBE may overlap the first data connection wiring DCL1 in the thickness direction. The voltage connection electrode VBE serves as an electrode connected to the first vertical wiring vdd_v to which the first power supply voltage is applied, and may be applied when the sub-pixel SPX emits light. In fig. 13, a case where the voltage connection electrode VBE is hardly overlapped with the first data connection wiring DCL1 or only a partial region is overlapped is illustrated, but not limited thereto.

In some embodiments, the voltage connection electrode VBE may have a shape in which a region overlapping the first data connection wiring DCL1 is large, and parasitic capacitance may BE prevented from being formed between the first connection electrode BE1 and the first data connection wiring DCL 1. In addition, the second initialization voltage wiring VAIL of the third gate conductive layer may also prevent parasitic capacitance from being formed between the first connection electrode BE1 and the first data connection wiring DCL1 while overlapping the first data connection wiring DCL1 and the first semiconductor layer ACT in the thickness direction. The explanation will be described later with reference to other embodiments.

Fig. 15 is a plan view showing a pixel electrode arranged at a sub-pixel of a display device according to an embodiment. Fig. 15 illustrates a relative planar arrangement of the pixel electrode 171, the first data connection wiring DCL1, and the data wiring DL.

Referring to fig. 15, according to an embodiment, the first data connection wiring DCL1 and the data wiring DL of the sub-pixel SPX may be arranged to overlap the pixel electrode 171 of the light emitting element ED. The first data connection wiring DCL1 and the data wiring DL are arranged to BE spaced apart from each other, and the interval between them and the first data connection wiring DCL1 may BE different according to positions as the data wiring DL detours the first connection electrode BE 1.

For example, the first data connection wiring DCL1 and the data wiring DL may be spaced apart from each other by a distance W2 in a portion overlapping the pixel electrode 171, which is greater than a distance W3 in a portion not overlapping the pixel electrode 171. The interval W3 at which the first data connection wiring DCL1 and the data wiring DL are spaced apart from each other in a portion not overlapping the pixel electrode 171 may be substantially the same as the interval W1 between the first data connection wirings DCL 1. In each sub-pixel SPX, the first connection electrode BE1 may BE arranged in a manner overlapping the pixel electrode 171, and in a portion where the data wiring DL extends to detour the first connection electrode BE1, an interval with the first data connection wiring DCL1 may BE different. As illustrated in fig. 13 and 15, for the interval between the first data connection wiring DCL1 and the data wiring DL, the interval W2 of the portion spaced apart with the first connection electrode BE1 interposed therebetween may BE larger than the interval W3 in other portions than that.

However, the interval W2 at which the first data connection wiring DCL1 and the data wiring DL are spaced apart from each other in the portion overlapping the pixel electrode 171 may be substantially constant at least in the lower portion of the pixel electrode 171. That is, a portion of the data wiring DL extending in the second direction DR2 and partially bent may be disposed adjacent to an outer boundary of the pixel electrode 171. Even if the display device 10 has a structure in which the first data connection wirings DCL1 adjacent to each other are arranged between the data wirings DL, in a portion overlapping with the pixel electrode 171, a variation in the interval between two wirings different from each other can be small. Accordingly, according to the arrangement structure of the data wiring DL and the first data connection wiring DCL1, little influence is exerted on the pixel electrode 171 of each sub-pixel SPX, and the variation in the light emission amount of the light emitting element ED can be small.

Hereinafter, other embodiments of the display device 10 will be described with reference to other drawings.

Fig. 16 is a plan view showing a part of a display device according to another embodiment. Fig. 17 is a cross-sectional view taken along line N3-N3' of fig. 16.

Referring to fig. 16 and 17, in the display device 10_1 according to an embodiment, the second initialization voltage wiring line vail_1 may extend in the first direction DR1 and include a protrusion PE1 protruding toward the second direction DR2, and the protrusion PE1 of the second initialization voltage wiring line vail_1 may BE arranged to overlap the first data connection wiring line DCL1 in a thickness direction between two adjacent first connection electrodes BE1 in a plan view. The protruding portion PE1 of the second initialization voltage wiring line_1 may be arranged to overlap the first electrode DTs of the driving transistor DT in the thickness direction, so that parasitic capacitance may be prevented from being formed between the first electrode DTs of the driving transistor DT and the first data connection wiring line DCL 1.

The protrusion PE1 of the second initialization voltage wiring valid_1 may be disposed at a boundary between two adjacent sub-pixels SPX. The protruding portion PE1 may BE disposed between the first connection electrodes BE1 while overlapping the first data connection wirings DCL1 of the two sub-pixels SPX, respectively. The width WP of the protrusion PE1 in the first direction DR1 may be greater than the widths WC of the two first data connection wirings DCL1 spaced apart from each other, and may be greater than the sum of the widths WC of the two first data connection wirings DCL1 different from each other and the interval W1 therebetween. Accordingly, the protruding portion PE1 may be arranged so as to be able to cover the entire first data connection wiring DCL1 in the width direction of the first direction DR 1.

The protruding portion PE1 of the second initialization voltage wiring valid_1 may overlap the first electrode DTs of the driving transistor DT in the first semiconductor layer ACT. The first data connection wiring DCL1 of the second source-drain layer may partially overlap the first electrode DTs of the driving transistor DT. However, the second initialization voltage wiring line valid_1, which is the third gate conductive layer of the intermediate layer therebetween, includes the protrusion PE1, so that parasitic capacitance can be prevented from being formed between the first data connection wiring line DCL1 and the first electrode DTs of the driving transistor DT.

Fig. 18 is a plan view showing a part of a display device according to another embodiment. Fig. 19 is a cross-sectional view taken along line N4-N4' of fig. 18. Fig. 20 is a cross-sectional view taken along line N5-N5' of fig. 18.

Referring to fig. 18 to 20, in the display device 10_2 according to an embodiment, the voltage connection electrode vbe_2 may BE arranged to overlap the first data connection wiring DCL1 in the thickness direction between two adjacent first connection electrodes BE1 in a plan view. The voltage connection electrode vbe_2 is disposed at the first source-drain layer as an intermediate layer between the first data connection wiring DCL1 and the first electrode DTs of the driving transistor DT, and may prevent parasitic capacitance from being formed between the first data connection wiring DCL1 and the first electrode DTs of the driving transistor DT. Further, the voltage connection electrode vbe_2 may BE disposed at the same layer as the first connection electrode BE1, thereby also preventing parasitic capacitance from being formed between the side portion of the first connection electrode BE1 and the first data connection wiring DCL 1.

The voltage connection electrode vbe_2 may be disposed at a boundary between two adjacent sub-pixels SPX. The voltage connection electrode vbe_2 may partially overlap each of the adjacent two first data connection wirings DCL1, and may BE disposed between the first connection electrodes BE1 disposed at the same layer.

The widths WV1, WV2 of the voltage connection electrode vbe_2 in the first direction DR1 may be different according to positions. The voltage connection electrode vbe_2, which is an electrode disposed at the same first source-drain layer as the first connection electrode BE1, may have a width spaced apart from the first connection electrode BE1 and a portion capable of overlapping the first data connection wiring DCL1. For example, the voltage connection electrode vbe_2 may have a relatively small minimum line width WV1 between the first connection electrode BE1 and the portion where the first electrode DTs of the driving transistor DT is connected. However, the minimum line width WV1 of the voltage connection electrode vbe_2 may BE greater than the interval W1 between the first data connection wirings DCL1 such that the voltage connection electrode vbe_2 overlaps the first data connection wirings DCL1 at least between the first connection electrodes BE 1.

In contrast, the voltage connection electrode vbe_2 may have a relatively large maximum line width WV2 between portions where the first connection electrode BE1 and the second electrode D1 of the first transistor ST1 overlap. The maximum line width WV2 of the voltage connection electrode vbe_2 may be greater than the widths WC of the two first data connection wirings DCL1 spaced apart from each other and greater than the sum of the widths WC of the two first data connection wirings DCL1 different from each other and the interval W1 therebetween. Accordingly, the voltage connection electrode vbe_2 may be arranged to be able to cover the entire first data connection wiring DCL1 in the portion having the maximum line width WV2.

Fig. 21 is a layout diagram showing adjacent two sub-pixels of a display device according to another embodiment. Fig. 22 is a pixel circuit diagram of the first sub-pixel of fig. 21. Fig. 23 is a pixel circuit diagram of the second sub-pixel of fig. 21.

Referring to fig. 21 to 23, the display device 10_3 according to an embodiment may include a plurality of sub-initialization voltage wirings VAIL1, VAIL2 in which the second initialization voltage wiring vail_3 is arranged at different layers from each other. For example, the second initialization voltage wiring vail_3 may include a first sub-initialization voltage wiring VAIL1 disposed at the third gate conductive layer and a second sub-initialization voltage wiring VAIL2 disposed at the first source drain layer as an upper layer thereof as shown in the embodiments of fig. 9 and 10. The first sub-initialization voltage wiring VAIL1 may be connected to the second sub-pixel SPX2 of fig. 21, and the second sub-initialization voltage wiring VAIL2 may be connected to the first sub-pixel SPX1 of fig. 21. In the display device 10_3, the second initialization voltage wirings valid_3 connected to the sub-pixels SPX1, SPX2 different from each other may be wirings of different layers from each other.

The arrangement and electrical connection relationship of the first sub-initialization voltage wiring VAIL1 are substantially the same as those described above with reference to fig. 9 and 10. However, the first sub-initialization voltage wiring VAIL1 is not connected to the first sub-pixel SPX1 of fig. 21, and thus, the eighth connection electrode BE8 connecting the first sub-initialization voltage wiring VAIL1 and the first electrode S7 of the seventh transistor ST7 may not BE disposed at the first sub-pixel SPX1.

The second sub-initialization voltage wiring VAIL2 may be disposed at the first source-drain layer and extend substantially along the first direction DR 1. Compared to the case where the first sub-initialization voltage wiring VAIL1 extends in the first direction DR1 to have a linear shape, the second sub-initialization voltage wiring VAIL2 may be locally bent to include a shape having a Recess (return) portion.

In an embodiment, the second sub-initialization voltage wiring line VAIL2 may BE disposed at the same layer as the second connection electrode BE2, and the first sub-initialization voltage wiring line VAIL1 may BE connected to the second connection electrode BE2 disposed at the second sub-pixel SPX 2.

For example, the second sub-initialization voltage wiring VAIL2 extends in the first direction DR1 from the upper side of the first sub-initialization voltage wiring VAIL1 in a plan view, and is bent in the second direction DR2 toward a portion of the first semiconductor layer where the first electrode S7 of the seventh transistor ST7 is located. The second sub-initialization voltage wiring VAIL2 may be directly connected to the first electrode S7 of the seventh transistor ST7 in the first sub-pixel SPX1 and bent again in the first direction DR 1. In the second subpixel SPX2, the eighth connection electrode BE8 is located on the first electrode S7 of the seventh transistor ST7, and thus, in order to detour the eighth connection electrode BE8, the second sub-initialization voltage wiring line VAIL2 may BE bent in the second direction DR2 and then bent and extended in the first direction DR 1.

The sub-pixels SPX different from each other may emit light of colors different from each other, respectively, and characteristics of voltages applied to the respective sub-pixels SPX may be different according to colors of light emitted from the respective sub-pixels SPX. To accommodate this, the display device 10_3 may include sub-initialization voltage wirings VAIL1, VAIL2 different from each other so that initialization voltages different from each other are applied to the pixel electrodes 171 of the sub-pixels SPX different from each other.

Referring to fig. 24, in the display device 10_4 according to an embodiment, the second initialization voltage wiring VAIL may include sub-initialization voltage wirings VAIL1, VAIL2 different from each other. Among them, the first sub-initialization voltage wiring line vat 1 disposed at the third gate conductive layer may include a protrusion PE1 and overlap with the first data connection wiring line DCL1 in the thickness direction. The description thereof is the same as that described above with reference to fig. 16, and thus a detailed description thereof is omitted.

Fig. 25 is a schematic view showing data connection wirings and electrical connections of the data wirings of a display device according to another embodiment. Fig. 26 is a plan view illustrating a portion of the display device of fig. 25. Fig. 27 is a cross-sectional view taken along line N6-N6' of fig. 26.

Referring to fig. 25 to 27, in the display device 10_4 according to an embodiment, the first connection electrode BE1 may BE disposed not to overlap the first data connection wiring DCL1 but to partially overlap the data wiring DL. The first connection electrode BE1 of the sub-pixel SPX disposed at the left side of fig. 26 may BE disposed at the left side of the first data connection wiring DCL 1. The sub-pixel SPX on the right side may have an arrangement structure of wirings and electrodes having a symmetrical structure with the sub-pixel SPX on the left side, and the first connection electrode BE1 of the sub-pixel SPX arranged on the right side may BE arranged on the right side of the first data connection wiring DCL 1. In the left sub-pixel SPX and the right sub-pixel SPX, the first connection electrode BE1 may overlap the data wiring DL in the thickness direction, respectively. The present embodiment is different from the embodiment of fig. 12 to 15 in that the shape of the data wiring DL is different.

The first data connection wiring DCL1 may be disposed to extend in the second direction DR2 regardless of the position, and the data wiring DL may have a shape partially bent at a portion where the second data connection hole DCH2 is disposed after extending in the second direction DR 2. Similar to the first data connection wiring DCL1, the data wiring DL may have a shape extending in the second direction DR2 except for a portion where the second data connection hole DCH2 is arranged. Accordingly, the first data connection wiring DCL1 may not overlap the first connection electrode BE1, and the data wiring DL may overlap the first connection electrode BE 1.

As described above, in the display device 10_4, when the data signal is applied to the first data connection wiring DCL1, parasitic capacitance may not BE formed between the first connection electrodes BE1, and therefore, the first connection electrodes BE1 and the data wiring DL may not overlap.

Fig. 28 is a plan view illustrating pixel electrodes of a plurality of sub-pixels arranged in the display device of fig. 25. Fig. 28 illustrates a relative planar arrangement of the pixel electrode 171 and the first data connection wiring DCL1 and the data wiring DL in the display device 10_4 of fig. 25.

Referring to fig. 28, the first data connection wiring DCL1 and the data wiring DL of the sub-pixel SPX may be arranged to overlap the pixel electrode 171 of the light emitting element ED. The first data connection wirings DCL1 and DL are arranged to be spaced apart from each other, and since the data wirings DL have substantially a linear shape extending in the second direction DR2, the interval with the first data connection wirings DCL1 can be almost constant regardless of the position.

For example, the interval W2 at which the first data connection wiring DCL1 and the data wiring DL are spaced apart from each other in a portion overlapping the pixel electrode 171 may be substantially the same as the interval W3 at which they are spaced apart from each other in a portion not overlapping the pixel electrode 171. The interval W3 at which the first data connection wiring DCL1 and the data wiring DL are spaced apart from each other in a portion not overlapping the pixel electrode 171 may be substantially the same as the interval W1 between the first data connection wirings DCL 1. In each sub-pixel SPX, the first connection electrode BE1 may BE arranged to overlap the pixel electrode 171, and unlike the embodiment of fig. 15, the interval with the first data connection wiring DCL1 may also BE constantly maintained in the portion where the data wiring DL overlaps the first connection electrode BE 1. As shown in fig. 26 and 27, the interval between the first data connection wiring DCL1 and the data wiring DL may BE constant regardless of the arrangement of the first connection electrode BE 1.

Fig. 29 is a plan view showing a part of a display device according to another embodiment. Fig. 30 is a cross-sectional view taken along line N7-N7' of fig. 29.

Referring to fig. 29 and 30, the display device 10_5 according to an embodiment is arranged like the display device 10_4 of fig. 25 to 28 such that the data wiring DL has a substantially linear shape and overlaps the first connection electrode BE1, and the second initialization voltage wiring vail_5 extends in the first direction DR1 and includes a protrusion PE1 protruding toward the second direction DR2, and the voltage connection electrode vbe_5 may BE arranged to overlap the first data connection wiring DCL1 in a thickness direction between two adjacent first connection electrodes BE1 in a plan view. The present embodiment may have a structure combining the embodiments of fig. 25 to 28 with the embodiments of fig. 16 and 18. The data wiring DL of the display device 10_5 has a linear shape and overlaps the first connection electrode BE1 and has the protrusion PE1 of the second initialization voltage wiring vail_5, so that parasitic capacitance can BE prevented from being formed between the first electrode DTs of the driving transistor DT and the first data connection wiring DCL 1. Further, since the voltage connection electrode vbe_5 is disposed between the first connection electrodes BE1, it is also possible to prevent parasitic capacitance from being formed between the side portions of the first connection electrodes BE1 and the first data connection wiring DCL 1. The description of these structures is the same as that described above, and thus a detailed description thereof is omitted.

As described above, in order to prevent parasitic capacitance from being formed between the first connection electrode BE1 and the first data connection wiring DCL1, the display device 10_5 according to an embodiment may have various wiring and electrode arrangement structures. The above-described embodiment may have a structure of reducing parasitic capacitance by an arrangement structure of the first data connection wiring DCL1 or a shielding structure between the first data connection wiring DCL1 and the first connection electrode BE 1. However, it is not limited thereto. The display device 10_5 may also reduce parasitic capacitance by changing the structure of the first connection electrode BE1 by the shielding structure between the first data connection wiring DCL1 and the first connection electrode BE 1.

Fig. 31 is a plan view showing a part of a display device according to another embodiment. Fig. 32 is a plan view illustrating the first connection electrode of fig. 31.

Referring to fig. 31 and 32, in the display device 10_6 according to an embodiment, the planar structure and the contact hole structure of the first connection electrode BE1 and the portion contacting the first electrode DTs of the driving transistor DT and the portion contacting the second electrode D1 of the first transistor ST1 may BE different. The first connection electrode BE1 of the display device 10_6 may include a first portion P1 extending in a diagonal or diagonal direction and a second portion P2 connected to the first portion P1 and parallel to a perpendicular or second direction DR 2. The first portion P1 of the first connection electrode BE1 may BE in contact with the first electrode DTs of the driving transistor DT, and the second portion P2 may BE in contact with the second electrode D1 of the first transistor ST 1. In the first connection electrode BE1, the portion of the first portion P1 where the electrode contact hole CNTA is formed may BE closer to the first data connection wiring DCL1 than the portion of the second portion P2 where the first contact hole CNT1 is formed. The first portion P1 of the first connection electrode BE1 may form a parasitic capacitance with the first data connection wiring DCL1, but the first portion P1 may have a shape that minimizes the parasitic capacitance.

The angle between the direction in which the first portion P1 extends and the direction in which the second portion P2 extends may have a range of 30 degrees to 60 degrees.

For example, the contact portions CP1, CP2 of the first connection electrode BE1, in which the electrode contact hole CNTA and the first contact hole CNT1 are formed, respectively, of the first portion P1 and the second portion P2 may have a shape having a width greater than that of the other portions or an area greater than that of the other portions in a plan view. As shown in the drawing, the first contact portion CP1 of the first portion P1 of the first connection electrode BE1, in which the electrode contact hole CNTA is formed, and the second contact portion CP2 of the second portion P2, in which the first contact hole CNT1 is formed, may have a larger width than other portions, respectively, and may have a rectangular shape in a plan view. This may BE a structure for ensuring a space in which the electrode contact hole CNTA and the first contact hole CNT1 can BE formed in the first connection electrode BE 1.

In the first portion P1 of the first connection electrode BE1, each side of the first contact portion CP1 where the electrode contact hole CNTA is formed may BE non-parallel to the first data connection wiring DCL 1. For example, the first portion P1 of the first connection electrode BE1 may have a shape extending in a diagonal direction or a diagonal direction crossing the first direction DR1 and the second direction DR 2. Each side of the first contact portion CP1 in the first portion P1 may also extend in a diagonal direction crossing the first direction DR1 and the second direction DR 2. In an exemplary embodiment, the inclination of the first portion P1 with respect to the first direction DR1 as a horizontal direction or the second direction DR2 as a vertical direction may have a range of about 30 ° to 60 ° or about 45 °.

In contrast, in the second portion P2 of the first connection electrode BE1, each side of the second contact portion CP2 where the first contact hole CNT1 is formed may BE parallel to the first data connection wiring DCL 1. For example, the second portion P2 of the first connection electrode BE1 may have a shape extending in the second direction DR 2. A portion of each side of the second contact portion CP2 in the second portion P2 may extend in the second direction DR 2. In an embodiment in which the first data connection wiring DCL1 is arranged to extend in the second direction DR2, respective sides of the first portion P1 of the first connection electrode BE1 may not BE parallel to the first data connection wiring DCL1, and respective sides of the second portion P2 may BE parallel to the first data connection wiring DCL 1.

According to an embodiment, the first portion P1 of the first connection electrode BE1 may have a shape different from the interval between the first data connection wirings DCL1 according to the position in the first contact portion CP1 where the electrode contact hole CNTA is formed. The first connection electrode BE1 may BE disposed adjacent to the first data connection wiring DCL1 to form a parasitic capacitance, but since an interval between the first connection electrode BE1 and the first data connection wiring DCL1 is different according to a position, a size of the parasitic capacitance may BE reduced.

Fig. 33 is a plan view showing an arrangement of the first connection electrode and the first data connection wiring of fig. 31. Fig. 34 is a cross-sectional view taken along line N8-N8' of fig. 31. Fig. 35 is a cross-sectional view taken along line N9-N9' of fig. 31. Fig. 34 illustrates a section crossing the center of the electrode contact hole CNTA in the first portion P1 of the first connection electrode BE1, and fig. 35 illustrates a section crossing the topmost portion in the second direction DR2 in the first portion P1 of the first connection electrode BE 1.

With further reference to fig. 33 to 35 on the basis of fig. 31 and 32, since the first connection electrode BE1 has a shape in which the first portion P1 extends in the diagonal direction, the side edge of the first contact portion CP1 in which the electrode contact hole CNTA is arranged may also extend in the diagonal direction, and the interval between the edge of the first contact portion CP1 in the first portion P1 and the first data connection wiring DCL1 may BE different from each other. For example, the first contact portion CP1 of the first portion P1 may include a first side PS toward the first data connection wiring DCL1, and intervals DS1, DS2 between both end portions ps_1, ps_2 of the first side PS and the first data connection wiring DCL1 may be different from each other. In the first portion P1, a first fulcrum ps_1 adjacent to the first data connection wiring DCL1 in both end portions of the first side PS is closer to the first data connection wiring DCL1 than a second fulcrum ps_2 on the opposite side of the first fulcrum ps_1 in both end portions of the first side PS. The first interval DS1 between the first pivot ps_1 of the first portion P1 and the first data connection wiring DCL1 may be smaller than the second interval DS2 between the second pivot ps_2 of the first portion P1 and the first data connection wiring DCL1. Fig. 34 may be a section through the first pivot ps_1 of the first portion P1, and fig. 35 may be a section through the second pivot ps_2 of the first portion P1.

In the first portion P1 of the first connection electrode BE1, the first contact portion CP1 and the first data connection wiring DCL1 may BE disposed adjacent to each other, so that parasitic capacitance may BE formed therebetween. However, since the first portion P1 has a shape extending in the diagonal direction, parasitic capacitance with the first data connection wiring DCL1 is maximized at the first pivot ps_1 of the first contact portion CP1, in contrast to this, in other portions, the magnitude of parasitic capacitance may become small due to a long distance from the first data connection wiring DCL 1.

In the manufacturing process of the display device 10_6, the patterning process of forming the first connection electrode BE1 may also generate a deviation at the position of the first connection electrode BE1 according to the process deviation. The process deviation may change the intervals DS1, DS2 between the first connection electrode BE1 and the first data connection wiring DCL1, which may also affect the formation of parasitic capacitance between the first connection electrode BE1 and the first data connection wiring DCL 1. In order to prevent the formation of unintended parasitic capacitance due to such process deviation, the display device 10_6 according to an embodiment includes the first portion P1 in which the first connection electrode BE1 extends in the diagonal direction, thereby changing the intervals DS1, DS2 with the first data connection wiring DCL1 and may reduce the size of the parasitic capacitance formed therebetween. In particular, since the intervals DS1, DS2 between the first portion P1 of the first connection electrode BE1 and the first data connection wiring DCL1 are different depending on the positions thereof, the variation in the magnitude of parasitic capacitance formed therebetween can BE small even if the first connection electrode BE1 is disposed adjacent to the first data connection wiring DCL1 according to the process variation.

The first connection electrode BE1 includes a first portion P1 extending in a diagonal direction and a second portion P2 extending in a second direction DR2 or a vertical direction, and an electrode contact hole CNTA and a first contact hole CNT1 may BE formed at their respective contact portions CP1, CP 2. The electrode contact hole CNTA and the first contact hole CNT1 may penetrate the first to third gate insulating layers GI1 to GI3 and the first and second interlayer insulating layers IL1 and IL2, respectively. However, the shapes of the electrode contact hole CNTA and the first contact hole CNT1 in a plan view may also BE different according to the extending directions of the first and second portions P1 and P2 of the first connection electrode BE 1.

According to an embodiment, the display device 10_6 may include the electrode contact hole CNTA formed obliquely at a predetermined angle with respect to the first contact hole CNT1. The maximum width H1 of the first contact hole CNT1 measured in the second direction DR2 may be smaller than the maximum width H2 of the electrode contact hole CNTA measured in the second direction DR 2. Since the first contact hole CNT1 and the electrode contact hole CNTA penetrate the same layer, respectively, the maximum diameters thereof may be the same as each other. However, the electrode contact hole CNTA may be formed in a state of being inclined with respect to the first contact hole CNT1 by an angle corresponding to an angle by which the first portion P1 is inclined with respect to the second portion P2. Accordingly, the width H1 of the first contact hole CNT1 and the width H2 of the electrode contact hole CNTA measured in the same direction may be different from each other. In the drawings, it is illustrated that the first contact hole CNT1 and the electrode contact hole CNTA have rectangular shapes in plan view, respectively. The first width H1 measured in the second direction DR2 of the first contact hole CNT1 may have the same size as the length of one side of the first contact hole CNT1, and the second width H2 measured in the second direction DR2 of the electrode contact hole CNTA may have a size greater than the length of one side of the electrode contact hole CNTA.

However, it is not limited thereto. In some embodiments, the first contact hole CNT1 and the electrode contact hole CNTA may have a shape that is nearly circular in plan view. However, since the electrode contact hole CNTA is formed to be inclined at a predetermined angle with respect to the first contact hole CNT1, widths measured in the second direction DR2 through centers of the electrode contact hole CNTA and the first contact hole CNT1 may be different from each other.

Alternatively, in an embodiment, the direction in which the long axis of the electrode contact hole CNTA extends may be different from the direction in which the long axis of the first contact hole CNT1 extends. In an embodiment in which the electrode contact hole CNTA and the first contact hole CNT1 have an elliptical shape close to a circle, directions in which the long axes of the electrode contact hole CNTA and the first contact hole CNT1 extend may BE different from each other, and an angle between directions in which the long axes extend may BE the same as an angle between directions in which the first and second portions P1 and P2 of the first connection electrode BE1 extend.

According to an embodiment, the first data connection wiring DCL1 is arranged not to overlap the first connection electrode BE1 in the thickness direction, and the first connection electrode BE1 also includes the first portion P1 extending in the diagonal direction in the pattern shape in a plan view, and thus, the formation of parasitic capacitance between the first connection electrode BE1 of the first source drain layer and the first data connection wiring DCL1 of the second source drain layer can BE minimized. When a data signal is applied to the first data connection wiring DCL1, if parasitic capacitance is hardly formed between the first connection electrodes BE1, it is possible to reduce the potential variation of the first electrode DTs of the driving transistor DT and reduce the influence on the light emission amount of the corresponding sub-pixel SPX. Accordingly, the display device 10_6 can prevent the generation of the mark in the display area DA due to the arrangement of the first data connection wiring DCL 1.

Fig. 36 is a plan view showing a part of a display device according to still another embodiment. Fig. 37 is a plan view showing an arrangement of the first connection electrode and the first data connection wiring of fig. 36. Fig. 38 is a cross-sectional view taken along line N10-N10' of fig. 36.

Referring to fig. 36 to 38, the display device 10_7 according to an embodiment includes a first portion P1 in which a first connection electrode BE1 extends in a diagonal direction, and similar to the display devices 10_1, 10_2 of fig. 16 and 18, the second initialization voltage wiring line vail_7 may include a protrusion PE1 extending in the first direction DR1 and protruding toward the second direction DR2, and the voltage connection electrode vbe_7 is arranged to overlap the first data connection wiring line DCL1 in a thickness direction between two adjacent first connection electrodes BE1 in a plan view. The present embodiment may have a structure combining the embodiments of fig. 31 to 35 with the embodiments of fig. 16 and 18. The display device 10_7 includes the first portion P1 in which the first connection electrode BE1 extends in the diagonal direction, and has a structure in which the distance between the first data connection wiring DCL1 and the first connection electrode BE1 is different depending on the position, and parasitic capacitance can BE prevented from being formed between the first electrode DTs of the driving transistor DT and the first data connection wiring DCL1 by the protrusion PE1 having the second initialization voltage wiring vail_7.

Further, since the voltage connection electrode vbe_7 is disposed between the first connection electrodes BE1, it is also possible to prevent parasitic capacitance from being formed between the side portions of the first connection electrodes BE1 and the first data connection wiring DCL 1. However, the present embodiment is different from the embodiment of fig. 18 in that the voltage connection electrode vbe_7 may have a pattern shape partially recessed corresponding to the shape of the first connection electrode BE1 extending in the diagonal direction. Since the first connection electrode BE1 and the voltage connection electrode vbe_7 are disposed at the same conductive layer as each other, interference with the voltage connection electrode vbe_7 may occur according to the pattern shape of the first connection electrode BE 1. To prevent this, the voltage connection electrode vbe_7 may BE disposed between the first connection electrodes BE1, and may BE partially recessed corresponding to the shape of the first contact portion CP1 in the first portion P1 of the first connection electrode BE 1. In an embodiment, the width of the portion vbe_p1 of the voltage connection electrode vbe_7 disposed between the first portions P1 of the first connection electrode BE1 may BE smaller than the width of the portion vbe_p2 disposed between the second portions P2. Alternatively, the width of the portion of the voltage connection electrode vbe_7 adjacent to the first portion P1 of the first connection electrode BE1 may BE smaller than the width of the portion adjacent to the second portion P2 of the first connection electrode BE 1. The voltage connection electrode vbe_7 may have a structure that prevents parasitic capacitance from being formed at the sides of the first connection electrode BE1 and the first data connection wiring DCL1 while preventing physical interference with the first connection electrode BE 1. Note that, the description of the configuration of the protruding portion PE1 and the voltage connection electrode vbe_7 of the second initialization voltage wiring line valid_7 is the same as that described above, and therefore, a detailed description thereof is omitted.

While the embodiments of the present utility model have been described above with reference to the drawings, those skilled in the art to which the present utility model pertains will appreciate that the present utility model may be embodied in other specific forms without changing the technical idea or essential features of the present utility model. Accordingly, it should be understood that the above-described embodiments are illustrative in all respects, rather than restrictive.

Claims

1. A display device, comprising:

a display region in which a plurality of sub-pixels arranged in a first direction and a second direction crossing the first direction are arranged;

a plurality of data wires arranged in the display area and extending along the second direction;

a first data connection wiring disposed in the display region, extending in the second direction, and spaced apart from the data wiring in the first direction in the sub-pixel; and

a second data connection wiring disposed in the display area, extending in the first direction, and connected to at least one of the first data connection wirings,

wherein the sub-pixel comprises a first connection electrode connected to a first electrode of the drive transistor,

The first connection electrode is disposed between the first data connection wiring and the data wiring in a non-overlapping manner with the first data connection wiring.

2. The display device of claim 1, wherein,

the first connection electrode is disposed so as not to overlap the data wiring,

a portion of the first data connection wiring overlaps the first electrode of the driving transistor.

3. The display device according to claim 1, further comprising:

an initialization voltage wiring extending in the first direction and including a protruding portion adjacent to the first connection electrode and protruding toward the second direction,

the protruding portion of the initialization voltage wiring overlaps the first data connection wiring,

the width of the protruding portion of the initialization voltage wiring is greater than the width of the first data connection wiring.

4. The display device according to claim 1, further comprising:

a plurality of first vertical wirings extending in the second direction and spaced apart from the first data connection wirings and the data wirings in the first direction,

an interval between the first vertical wiring and the data wiring is smaller than an interval between the first vertical wiring and the first data connection wiring.

5. The display device according to claim 4, further comprising:

a voltage connection electrode disposed at the sub-pixel, connected to the first vertical wiring,

at least a portion of the voltage connection electrode overlaps the first data connection wiring,

the voltage connection electrode overlaps the first electrode of the driving transistor,

the maximum line width of the voltage connection electrode is greater than the width of the first data connection wiring.

6. The display device according to claim 1, further comprising:

bias voltage wiring extending along the first direction; and

a first transistor connected to the bias voltage wiring,

wherein the first transistor is connected with the first connection electrode.

7. The display device of claim 1, wherein,

the display area includes:

a first display area; and

a second display area adjacent to the first display area along the first direction,

the data wiring includes:

a first data wire disposed in the first display region and connected to the second data connection wire; and

a second data wiring disposed in the second display region without being connected to the second data connection wiring,

Wherein at least a part of the plurality of first data connection wirings is electrically connected to the first data wiring through the second data connection wiring.

8. The display device according to claim 7, further comprising:

a first fan-out wiring line arranged in a non-display area surrounding the display area and connected to the first data connection wiring line;

a second fan-out wiring disposed in the non-display area and connected to the second data connection wiring;

a plurality of vertical dummy patterns arranged in the second display region, spaced apart from the first data connection wiring lines along the second direction;

a plurality of horizontal dummy patterns spaced apart from the second data connection wiring line in the first direction;

a horizontal power supply wiring extending in the first direction in the display area and spaced apart from the second data connection wiring in the second direction; and

and a vertical power supply wiring line extending in the second direction in the first display region and spaced apart from the first data wiring line.

9. A display device, comprising:

a first subpixel and a second subpixel including a driving transistor and a first connection electrode connected to a first electrode of the driving transistor and adjacent to each other in a first direction;

A plurality of first data connection wirings disposed at each of the first and second sub-pixels, spaced apart from each other along the first direction, and extending along a second direction crossing the first direction;

a plurality of data wirings spaced apart from each other in the first direction through the plurality of first data connection wirings and extending in the second direction;

a second data connection wiring extending in the second direction and arranged in the first subpixel and the second subpixel, connected to any one of the first data connection wirings; and

a plurality of first vertical wirings extending in the second direction and spaced apart from the data wirings in the first direction,

wherein the first connection electrode is disposed between any one of the plurality of first data connection wirings and any one of the plurality of data wirings.

10. A display device, comprising;

the first connection electrode does not overlap the first data connection wiring, and the first connection electrode includes: a first portion extending in a diagonal direction intersecting the first direction and the second direction; and a second portion connected to the first portion and extending in the second direction.