KR20230083959A - Near field communication device, terminal device having the same, and operation method of the near field communication device - Google Patents

Abstract

An NFC device according to an embodiment of the present invention receives a reference clock signal, detects a phase of the reference clock signal, outputs a generated clock signal synchronized in frequency with the reference clock signal, and outputs phase information of the generated clock signal. A phase detector for storing as a first digital code, calculating a delta value by comparing the phase of the generated clock signal applied from the phase detector with a reference phase during an active load modulation (ALM) operation, It may include a phase delay calculator that stores the delta value as a second digital code, and a transmission clock generator that outputs a transmission clock signal by reflecting the phase information stored as the first digital code and the second digital code. Accordingly, the phase of the transmission clock signal applied to the antenna of the reader device may be controlled to have an optimal load modulation amplitude (LMA) using the NFC device according to an embodiment of the present invention.

Description

NFC device, terminal device including NFC device, and operating method of NFC device

The present invention relates to an NFC device, a terminal device including the NFC device, and a method of operating the NFC device.

Near Field Communication (NFC) technology, one of Radio Frequency Identification (RFID) technologies that wirelessly recognizes information stored in tags using radio waves, provides non-contact data communication between devices placed in a short distance. do. An NFC device that wirelessly transmits and receives data in both directions using NFC technology uses a frequency of 13.56 MHz band and is based on the ISO14443 standard. The data transmission speed of the NFC device is about 105 kbps to about 848 kbps, and fast transmission is possible because a pairing procedure between two terminals is not required. On the other hand, the NFC device may load modulate and output data in response to a request from an external device, and the NFC device may use active load modulation (ALM) and / or separate Passive Load Modulation (PLM), which performs load modulation without power, can be performed.

One of the problems to be achieved by the technical idea of the present invention is to detect the phase delay when the transmission clock signal is input again as a reference clock signal and use it to control the phase of the transmission clock signal, thereby optimizing the load modulation amplitude (Load It is intended to provide an NFC device capable of transmitting a transmission clock signal having Modulation Amplitude (LMA) to a reader device.

An NFC device according to an embodiment of the present invention receives a reference clock signal, detects a phase of the reference clock signal, outputs a generated clock signal synchronized in frequency with the reference clock signal, and outputs a phase of the generated clock signal. A phase detector that stores information as a first digital code, a delta value is calculated by comparing the phase of the generated clock signal applied from the phase detector with a reference phase during an active load modulation (ALM) operation, , a phase delay calculator that stores the delta value as a second digital code, and a transmission clock generator that outputs a transmission clock signal by reflecting the phase information stored as the first digital code and the second digital code.

An NFC device according to an embodiment of the present invention detects the phase of a first reference clock signal input in a first period, outputs a first generated clock signal synchronized in frequency with the first reference clock signal, and A phase detector for storing a phase of a first generated clock signal and a phase of a second generated clock signal output based on a second reference clock signal input in a second interval after the first interval as a first digital code; In section 2, a phase delay calculator for calculating a delta value by comparing the phase of the second generated clock signal applied from the phase detector with a reference phase, and storing the delta value as a second digital code, and the first digital code and a transmission clock generator for outputting a transmission clock signal by reflecting the phase information stored as the code and the second digital code.

A terminal device according to an embodiment of the present invention includes an antenna for receiving a signal from an approaching reader device, a matching network for outputting a reference clock signal by performing impedance matching on a signal received through the antenna, and the reference clock signal. A phase detector for receiving a signal and a feedback signal and storing path delay information of the reference clock signal and the feedback signal as a first digital code, and a phase delay calculator for storing additional delay information as a second digital code based on the feedback signal , and inputting the feedback signal to the phase detector by reflecting the phase information stored as the first digital code, or reflecting the phase information stored as the first digital code and the second digital code to transmit a clock signal to the reader device. It includes an NFC device including a transmission clock generator that delivers.

An operating method of an NFC device according to an embodiment of the present invention includes the steps of a reader device approaching an antenna, detecting a phase of a reference clock signal based on a signal received from the reader device, and generating a frequency of the reference clock signal. Synchronizing with a clock signal, converting phase delay information of the generated clock signal into a digital code, compensating by reflecting the phase delay information to a transmission clock signal using the digital code, converting the transmission clock signal to a reader Sending to the device.

An operating method of an NFC device according to an embodiment of the present invention includes the steps of a reader device approaching an antenna, detecting a phase of a first reference clock signal based on a signal received from the reader device, and the first reference clock signal. Synchronizing a frequency of a first generated clock signal, outputting a first transfer clock signal based on the first generated clock signal, and inputting the first transfer clock signal as a second reference clock signal; 2 converting phase delay information of the reference clock signal into a digital code, calculating a delta value corresponding to a difference between a reference phase and a phase of a second generated clock signal frequency-synchronized with the second reference clock signal, the phase and transmitting a second transmission clock signal compensated for by reflecting delay information and the delta value to the reader device.

An NFC device according to an embodiment of the present invention detects a phase delay along a path and uses it to control the phase of a transmission clock signal, thereby controlling a signal having an optimal phase modulation amplitude for an antenna of a reader device regardless of external conditions. can deliver.

Various advantageous advantages and effects of the present invention are not limited to the above description, and will be more easily understood in the process of describing specific embodiments of the present invention.

1 is a block diagram simply illustrating an NFC device according to an embodiment of the present invention.
Figure 2 is a flow chart for explaining the basic operation of the NFC device according to an embodiment of the present invention.
3 is a flow chart for explaining a delta calculation operation of an NFC device according to an embodiment of the present invention.
4 is a waveform diagram of a clock signal according to an operation of an NFC device according to an embodiment of the present invention.
5 to 8 are block diagrams for explaining the operation of the NFC device according to an embodiment of the present invention from a structural point of view.
9 is a diagram for explaining phase compensation of a transmission clock signal in the NFC device shown in FIG. 7 .
10 is a diagram for explaining phase compensation of a transmission clock signal in an NFC device according to an embodiment of the present invention shown in FIG. 8 .
11 and 12 are views for explaining the effect of the NFC device according to an embodiment of the present invention.
13 is a timing diagram for explaining an operation of an NFC device according to an embodiment of the present invention.
14 is a block diagram for explaining the detailed configuration of an NFC device according to an embodiment of the present invention.
15 is a simple block diagram for explaining an electronic system including an NFC device according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a block diagram simply illustrating an NFC device according to an embodiment of the present invention.

Referring to FIG. 1 , an NFC device 100 according to an embodiment of the present invention may be included in a terminal device 10 together with a terminal antenna 11 and a matching network 12 . The terminal device 10 including the NFC device 100 may transmit response data using a load modulation technique to modulate impedance in the process of receiving data from another terminal device and/or a reader device. .

The terminal device 10 may convert a received RF signal, for example, a reference clock signal into a received digital signal. Meanwhile, the terminal device 10 may generate a transmission digital signal based on the received digital signal and output an RF signal to be transmitted, for example, a transmission clock signal. The terminal device 10 may transmit the output transmission clock signal to another terminal device and/or a reader device by using inductive coupling in the terminal antenna 11 .

The terminal device 10 including the NFC device 100 according to an embodiment of the present invention may transmit data to a reader device based on an active load modulation (ALM) method in an NFC card mode. Depending on the active load modulation scheme, the terminal device 10 may include its own power source.

The NFC device 100 according to an embodiment of the present invention may determine a phase of a transmission clock signal transmitted in an active load modulation scheme in an NFC card mode and control a phase delay. Meanwhile, the NFC device 100 may control the phase of the transmission clock signal in consideration of the path delay until the transmission clock signal is received again. Accordingly, the NFC device 100 may transmit a signal having an optimal load modulation amplitude to the reader device regardless of a phase change caused by an external environment.

The NFC device 100 according to an embodiment of the present invention may include a phase detector 110, a phase delay calculator 120, and a transmission clock generator 130. For example, the terminal antenna 11 included in the terminal device 10 together with the NFC device 100 can inductively receive a signal from an approaching reader device, and the matching network 12 is connected to the terminal antenna 11 A reference clock signal may be output by performing impedance matching on a signal received through.

While the NFC device 100 does not transmit data to the reader device, the phase detector 110 receives a reference clock signal, detects the phase of the reference clock signal, and generates a clock signal synchronized in frequency with the reference clock signal. can output In this case, the reference clock signal may be defined as the first reference clock signal, and the generated clock signal may be defined as the first generated clock signal. The phase detector 110 may store phase information of the generated clock signal as a first digital code.

The transmission clock generator 130 may input a feedback signal to the phase detector 110 by reflecting the phase information stored as the first digital code. At this time, the signal output from the transfer clock generator 130 may be defined as the first transfer clock signal, and the signal input to the phase detector 110 may be defined as the second reference clock signal. That is, the phase information stored as the first digital code may be reflected in the first transmission clock signal.

Meanwhile, while the NFC device 100 transmits data to the reader device in an active load modulation scheme, the phase detector 110 may receive a feedback signal. For example, the phase detector 110 may output a second generated clock signal based on the second reference clock signal. The phase detector 110 may store path delay information of the feedback signal as a first digital code.

The phase delay calculator 120 may store additional delay information as a second digital code based on the feedback signal. At this time, the additional delay information may be defined as a delta value. For example, the additional delay information may include delay information according to a matching network, impedance distribution of the NFC device 100, and coupling between the NFC device 100 and the reader device. However, this is merely an example and may not be limited. The delta value may be calculated by comparing the phase of the second generated clock signal applied from the phase detector 110 with an internally determined reference phase.

The transmission clock generator 130 may output a second transmission clock signal by reflecting the phase delay information stored as the first digital code and the second digital code. That is, phase information stored as the first digital code and the second digital code may be reflected in the second transmission clock signal. The NFC device 100 may transfer the second transmission clock signal to the reader device. According to the above process, the transmission clock generator 130 may output a transmission clock signal by reflecting the phase delay information according to the path delay in real time.

However, the configuration of the NFC device 100 may not be limited to the above. For example, the NFC device 100 according to an embodiment of the present invention may further include a transmit clock amplifier 140 that amplifies and outputs a transmit clock signal applied from the transmit clock generator 130 . In addition, although not shown in FIG. 1, the transmission clock generator 130 includes a digital-time converter capable of converting the first digital code and the second digital code into a time domain, and an output oscillation frequency based on the input generated clock signal. It may include a voltage controlled oscillator for controlling.

Figure 2 is a flow chart for explaining the basic operation of the NFC device according to an embodiment of the present invention.

Referring to FIG. 2 , the NFC device 100 may control the phase of the transmission clock signal by reflecting the phase delay to the transmission clock signal. First, the operation of the NFC device 100 may start when the reader device approaches the terminal antenna 11 (S110). For example, when a reader device including a reader antenna approaches the terminal antenna 11, coupling may occur between the two antennas, and the derived reference clock signal may be input to the NFC device 100.

The phase detector 110 included in the NFC device 100 may detect the phase of the reference clock signal inductively input based on the signal received from the reader device. Meanwhile, the phase detector 110 may output a generated clock signal synchronized with the frequency of the reference clock signal (S120).

The phase detector 110 may convert phase information of the generated clock signal synchronized with the frequency of the reference clock signal into a digital code (S130). At this time, if the phase of the generated clock signal is delayed by the path delay (S140), the transmission clock generator 130 may compensate by reflecting the phase delay according to the path delay to the transmission clock signal using the stored digital code ( S150), the compensated transmission clock signal may be transmitted to the reader device (S160).

Meanwhile, when the phase of the generated clock signal is not delayed by the path delay (S140), the transmission clock generator 130 may transmit the transmission clock signal to the reader device without additional compensation for the transmission clock signal (S160). According to the above process, the NFC device 100 may reflect the phase delay due to the path delay until the transmission clock signal is received again to the transmission clock signal.

3 is a flow chart for explaining a delta calculation operation of an NFC device according to an embodiment of the present invention.

Referring to FIG. 3, the NFC device 100 according to an embodiment of the present invention determines the phase of the transmission clock signal in consideration of additional phase delay factors as well as the phase delay due to the path delay until the transmission clock signal is received again. You can control it.

First, similar to the operation method of FIG. 2 , the operation of the NFC device 100 may be initiated by the reader device approaching the terminal antenna 11 (S210). For example, when a reader device including a reader antenna approaches the terminal antenna 11, coupling may occur between the two antennas, and the derived first reference clock signal may be input to the NFC device 100. .

Also, the phase detector 110 included in the NFC device 100 may detect the phase of the first reference clock signal received from the reader device. Meanwhile, the phase detector 110 may output a first generated clock signal synchronized with the frequency of the reference clock signal (S220).

According to the above-described steps S130 to S150 in the description of FIG. 2 , the transfer clock generator 130 may output a first transfer clock signal based on the first generated clock signal. At this time, the first transfer clock signal may not be transmitted to the reader device and may be input again to the phase detector 110 as a second reference clock signal that is a feedback signal (S230).

The phase detector 110 may convert and store the phase information of the input second reference clock signal into a first digital code (S240), and the phase delay calculator 120 receiving the second generated clock signal from the phase detector 110 ) may calculate a delta value corresponding to a difference between the phase of the second generated clock signal frequency-synchronized with the second reference clock signal and the internally determined reference phase. The calculated delta value may be converted into a second digital code and stored (S250).

At this time, when the phase of the second generated clock signal is delayed by the path delay and/or additional delay (S260), the transmission clock generator 130 uses the stored first digital code and/or second digital code to generate the second digital code. It is possible to compensate by reflecting the phase delay to the transmission clock signal (S270). That is, the NFC device 100 according to an embodiment of the present invention reflects the phase delay information by the path delay until the transmission clock signal is received again and the additional phase delay information by the additional delay elements to transmit the second transmission clock signal. signal can be compensated. The compensated second transmission clock signal may be transmitted to the reader device (S280).

Meanwhile, when the phase of the second generation clock signal is not delayed by the path delay (S260), the transmission clock generator 130 may transmit the second transmission clock signal to the reader device without additional compensation of the transmission clock signal. . According to the above process, the NFC device 100 according to an embodiment of the present invention may transmit the second transmission clock signal to the reader device by controlling the phase of the second transmission clock signal to have an optimal load modulation amplitude.

4 is a waveform diagram of a clock signal according to an operation of an NFC device according to an embodiment of the present invention. 5 to 8 are block diagrams for explaining the operation of the NFC device according to an embodiment of the present invention from a structural point of view.

Referring to FIG. 4 , signals in the NFC device 100 according to an embodiment of the present invention may be transmitted in the form of a clock signal. The first waveform diagram REF shown in FIG. 4 may be a reference clock signal, and the second waveform diagram REF-TX (Case 1) is a transmission clock signal when a phase delay occurs due to a path delay. may be shown. In addition, the third waveform diagram (REF-TX (Case 2)) may show a transmission clock signal when compensation for a phase delay according to a path delay is performed in the NFC device 100 according to an embodiment of the present invention. there is. Finally, the fourth to sixth waveforms (REF1-TX1 (Case 3), REF2-TX2 (Case 3), TX2 (Case 3)) show path delay in the NFC device 100 according to an embodiment of the present invention It may be shown the transmission clock signal when the phase delay according to and compensation for the phase delay by the additional element is made.

As an example, the second waveform diagram REF-TX (Case 1) may show a reference clock signal and a transmission clock signal in the operation of the NFC device 100 shown in FIG. 6 . The third waveform diagram REF-TX (Case 2) may show a reference clock signal and a transmission clock signal in the operation of the NFC device 100 shown in FIG. 7 . The fourth to sixth waveform diagrams (REF1-TX1 (Case 3), REF2-TX2 (Case 3), and TX2 (Case 3)) are reference clock signals in the operation of the NFC device 100 shown in FIG. 8 and Transmission clock signals may be shown.

Referring to FIG. 5 , a terminal device 10 according to an embodiment of the present invention may include a terminal antenna 11, a matching network 12, and an NFC device 100. As the reader antenna 21 of the reader device 20 approaches the terminal device 10, a reference clock signal may be induced and applied to the terminal antenna 11. Referring to FIG. 4 together, as shown in the first waveform diagram REF, the phase of the derived reference clock signal may be P1.

Referring to FIG. 6 , a reference clock signal REF may be input to the NFC device 100 included in the terminal device 10 according to an embodiment of the present invention. For example, the reference clock signal REF may be input to the phase detector 110 of the NFC device 100, and the phase detector 110 may output a generated clock signal synchronized with the frequency of the reference clock signal REF. can The generated clock signal may be output from the NFC device 100 as a transmit clock signal TX through the transmit clock amplifier 140 .

In the process of outputting the reference clock signal REF as the transmission clock signal TX, a phase of the transmission clock signal TX may be delayed due to a path delay. Referring to FIG. 4 together, the transmission clock signal TX in FIG. 6 may be a signal having a phase of P2 without separate phase compensation.

Referring to FIG. 7 , a reference clock signal REF having a phase of P1 may be input to the phase detector 110 of the NFC device 100 included in the terminal device 10 according to an embodiment of the present invention. . The phase detector 110 may output a generated clock signal that is synchronized with the frequency of the reference clock signal REF and has a phase of P2.

However, unlike the operation of the NFC device 100 shown in FIG. 6, the operation of the NFC device 100 shown in FIG. 7 transmits the reference clock signal REF in the process of outputting the transmission clock signal TX. A process of compensating for a phase delay of the clock signal TX may be included. For example, the phase detector 110 may store the phase of the generated clock signal as a first digital code.

Referring to FIG. 4 together, the transmission clock generator 130 may perform a first compensation D1 for the transmission clock signal TX using a first digital code. Accordingly, the transmission clock signal TX in FIG. 7 may be a signal having a phase P3 after the first compensation D1 is performed. At this time, the phase of P3 may be the same as that of P1, which is the phase of the reference clock signal REF. However, this is merely an example and may not be limited.

Referring to FIG. 8, the operation of the NFC device 100 included in the terminal device 10 according to an embodiment of the present invention is an operation in a first interval in which transmission to the reader device 20 is not performed, It may include an operation in the second period in which signal transmission to the reader device 20 is performed.

For example, the reference clock signal input to the NFC device 100 is the first reference clock signal REF1 input to the phase detector 110 in the first period, and the phase detector 110 in the second period after the first period. ) may include a second reference clock signal REF2 input to. That is, the first reference clock signal REF1 may be a signal generated by the reader device 20 approaching, and the second reference clock signal REF2 may be a signal output based on the first reference clock signal REF1. there is.

Similarly, the transmission clock signal output from the NFC device 100 is the first transmission clock signal TX1 output from the transmission clock generator 130 in the first period, and output from the transmission clock generator 130 in the second period. A second transmission clock signal TX2 may be included. Meanwhile, the first transfer clock signal TX1 may correspond to the first transfer clock signal TX1 output based on the first reference clock signal REF1.

Accordingly, the first transmission clock signal TX1 output from the transmission clock generator 130 in the first interval is not synchronized with the reader antenna 21 of the reader device 20, and in the second interval, the transmission clock generator 130 The second transmission clock signal TX2 output from ) can be synchronized with the reader antenna 21 of the reader device 20 to implement an optimal load modulation amplitude.

For example, the first reference clock signal REF1 may be input to the phase detector 110 of the NFC device 100 in the first period. The phase detector 110 may output a first generated clock signal that is synchronized with the frequency of the first reference clock signal REF1 and has a phase P2. In the first period, the first generated clock signal may bypass the phase delay calculator 120, and similar to the operation of the NFC device 100 in FIG. 7, the transmission clock generator 130 performs the first compensation (D1) This may be performed to output the first transmission clock signal TX1 having a phase of P3.

Meanwhile, in the second interval after the first interval, the first transmission clock signal TX1 may be input again to the NFC device 100 as the second reference clock signal REF2. For example, the second reference clock signal REF2 may be a signal having a phase of P1. The phase detector 110 may output a second generated clock signal based on the second reference clock signal REF2 and store the phase of the second generated clock signal as a first digital code.

The phase delay calculator 120 may calculate a delta value by comparing the phase of the second generated clock signal with a predetermined reference phase. The calculated delta value may be stored as a second digital code. The transmission clock generator 130 performs a second compensation (D2) reflecting a delta value together with the first compensation (D1) using the first digital code and the second digital code, and then generates the second transmission clock signal (TX2). can output

In FIG. 8, the phases of the first generated clock signal and the second generated clock signal may be variously represented as P2', P2, and P2" due to additional delay factors such as coupling with the reader device 20. In the NFC device 100 according to an embodiment, when only the first compensation D1 is performed, the first transmission clock signal TX1 having a fixed phase of P3 is output without considering additional delay factors, while the first transmission clock signal TX1 having a fixed phase of P3 is output. When the second compensation D2 is performed together with the first compensation D1, the phase of the second transmission clock signal TX2 may be variously determined as P3', P3, and P3" in consideration of additional delay factors.

Accordingly, the NFC device 100 according to an embodiment of the present invention controls the phase of the transmission clock signal in consideration of all of the various delay factors, thereby providing an optimal signal for the reader device 20 regardless of phase change due to the external environment. A signal with a load modulation amplitude can be transmitted.

9 is a diagram for explaining phase compensation of a transmission clock signal in the NFC device shown in FIG. 7 . 10 is a diagram for explaining phase compensation of a transmission clock signal in an NFC device according to an embodiment of the present invention shown in FIG. 8 .

Referring to FIGS. 7 and 9 together, the reference clock signal REF input to the NFC device 100 may have a phase of P1. Referring to FIG. 9 , P1 is illustrated as having a value between 90° and 180°, but this is merely an example and may not be limited.

Meanwhile, the phases of the generated clock signals output from the phase detector 110 and returned by reflecting the path delay may be P2', P2, P2". At this time, the reference phase managed inside the NFC device 100 is P2 However, the phases of the clock signals generated by the additional delay elements may appear as P2', P2, and P2". For example, the phase of the generated clock signal may be greater than the phase of the reference clock signal. Referring to FIG. 9 , P2', P2, and P2" are illustrated as having values between 270° and 360°, but this is merely an example and may not be limited.

The transmission clock generator 130 may perform first compensation (D1', D1, D1") on the generated clock signal in which the path delay is reflected. Output by the first compensation (D1', D1, D1") The phase of the transmission clock signal TX may be fixed to P3. In this case, P3 corresponding to the phase of the transmission clock signal TX may be the same as P1 corresponding to the phase of the reference clock signal REF.

Accordingly, the degree of phase change of the transmission clock signal TX by the first compensation (D1', D1, D1") may vary according to the degree of path delay. For example, the first reference clock signal S1 is low It can be input to the transmission clock generator 130 as S1' with a path delay, and can be output as a transmission clock signal (TX) having a phase of P3 by a relatively small first compensation (D1').

Meanwhile, the second reference clock signal S2 may be input to the transmission clock generator 130 as S2' with a general path delay, and the transmission clock signal TX having a phase of P3 by the first compensation D1 can be output as The third reference clock signal S3 may be input to the transmission clock generator 130 as S3' with a high path delay, and the transmission clock signal having a phase of P3 by the relatively large first compensation D1" ( TX).

Referring to FIGS. 8 and 10 together, the first reference clock signal REF1 input to the NFC device 100 may have a phase of P1. Meanwhile, the phases of the second generated clock signals output from the phase detector 110 through the first period and the second period and returned by reflecting the path delay may be P2', P2, and P2".

The transmission clock generator 130 may perform first compensation (D1', D1, D1") and second compensation (D2', D2") with respect to the generated clock signal in which the path delay is reflected. The first compensation (D1', D1, D1") may be the same as that described in FIG. 9. Meanwhile, the second transmission clock signal (TX2) is converted to P3', P3 by the second compensation (D2', D2"). , P3" may have various non-fixed phases. Accordingly, the phase of the second transfer clock signal TX2 synchronized with the reader antenna of the reader device may be different from the phase of the first reference clock signal REF1. there is.

The magnitude of the phase compensated by the second compensation (D2', D2") may correspond to the delta value of each signal. For example, the delta value is greater than the phase of the second generated clock signal greater than a predetermined reference phase. may include a first delta value when the phase of the generated clock signal is equal to the reference phase, a second delta value when the phase of the generated clock signal is equal to the reference phase, and a third delta value when the phase of the generated clock signal is smaller than the reference phase.

When the delta value is the first delta value, a relatively large second compensation D2" may be performed on the second transmission clock signal TX2, and accordingly, the phase of the second transmission clock signal TX2 may change to the first reference value. When the delta value is the second delta value, the phase of the second transmission clock signal TX2 may be the same as the phase of the first reference clock signal REF1. When the delta value is the third delta value, a relatively small second compensation D2' may be performed on the second transmission clock signal TX2, and accordingly, the phase of the second transmission clock signal TX2 is The phase of the reference clock signal REF1 may be larger than that of the second transmission clock signal TX2 compensated in the NFC device 100 according to an embodiment of the present invention, so that the magnitude of the load modulation amplitude has a maximum value. there is.

11 and 12 are views for explaining the effect of the NFC device according to an embodiment of the present invention.

Referring to FIG. 11 , a load modulation amplitude appearing in a general NFC device may not appear in a constant direction. 11 shows the load modulation amplitude appearing in the positive direction to have a magnitude of b-a, but this is only an example and may not be limited.

Meanwhile, referring to FIG. 12 , the load modulation amplitude appearing in the NFC device 100 according to an embodiment of the present invention may appear constant to facilitate reception of the reader antenna of the reader device regardless of external conditions. For example, the higher the peak-to-peak voltage of the load modulation amplitude and the more constant the load modulation amplitude appears in the negative direction, the easier the reader antenna can receive. 12 shows the load modulation amplitude appearing in the negative direction to have a magnitude of a-c, but this is only an example and may not be limited. In this case, the size of a-c may be greater than the size of b-a.

The NFC device 100 according to an embodiment of the present invention stably adjusts the phase of the transmission clock signal so that the peak-to-peak voltage has a large and constant load modulation amplitude in the negative direction by considering the phase delay according to the path delay. You can control it.

13 is a timing diagram for explaining an operation of an NFC device according to an embodiment of the present invention.

Referring to FIG. 13, the NFC device 100 according to an embodiment of the present invention may monitor the frequency and phase of the reference clock signal in the first period (RX), and generates a clock signal synchronized with the reference clock signal. can create For example, before t1 and from t8 to t9, the phase detector 110 may monitor the frequency and phase of the reference clock signal, and may synchronize and output generated clock signals.

Meanwhile, in the second period (TX), the active load modulation operation may be controlled by an active load modulation signal (ALM) that is periodically activated and deactivated. For example, the active load modulation signal ALM may be activated from t2 to t3, t4 to t5, t6 to t7, and t10 to t11, and may be deactivated during the remaining time intervals.

The phase detector 110 included in the NFC device 100 may monitor the phase of the generated clock signal during at least part of the time that the active load modulation signal ALM is activated. For example, the generated clock signal monitored and stored during the second period TX may be the second generated clock signal.

The transmission clock generator 130 included in the NFC device 100 may track an optimal transmission clock signal based on stored phase information after the active load modulation signal (ALM) is deactivated. Accordingly, the NFC device 100 of the present invention can control the phase of the transmission clock signal in real time to have an optimal load modulation amplitude.

14 is a block diagram for explaining the detailed configuration of an NFC device according to an embodiment of the present invention.

Referring to FIG. 14, the NFC device 200 according to an embodiment of the present invention includes a phase detector 210, a phase delay calculator 220, a transmission clock generator 230, a transmission clock amplifier 240, and a phase locked loop. 250, an accumulator 260, a divider 270, and a clock extractor 280.

As the reader antenna 21 of the reader device 20 approaches the terminal antenna 11, the induced signal is impedance matched through the matching network 12 and input to the NFC device 200 along the second path L2. It can be. The clock extractor 280 may extract a reference clock signal REF from an input signal. The extracted reference clock signal REF may be input to the phase detector 210 .

Meanwhile, the phase locked loop 250 may multiply and output the reference clock signal REF. The output signal may be applied to the divider 270 . Divider 270 may be controlled by phase detector 210 .

As described above, the reference clock signal REF may be input to the NFC device 200 along the second path L2 in the first period. Meanwhile, in the second period, the accumulator 260 stops operating and the phase delay calculator 220 may operate. Accordingly, the phase delay calculator 220 may calculate a delta value using path delay information corresponding to a difference between the reference phase and the actual path delay.

On the other hand, the transmission clock generator 230 composed of a voltage controlled oscillator and a digital-time converter compensates for the phase delay of the generated clock signal output from the phase detector 210 using the delta value to generate the transmission clock signal TX. can output The output transmission clock signal (TX) may be transmitted to the terminal antenna 11 via the transmission clock amplifier 240, and the data signal transmitted to the reader antenna 21 of the reader device 20 may be transferred to the terminal antenna 11 It can be synchronized with the phase of the transmission clock signal (TX) transmitted to .

That is, the NFC device 200 compensates for the phase of the transmission clock signal TX in consideration of the phase delay in the first path L1 and the second path L2, and transmits the compensated transmission clock signal TX to the reader. It can be transmitted to the antenna (21). However, the configuration of the NFC device 200 shown in FIG. 14 may not be limited to only one embodiment. For example, the NFC device 200 may omit some components or further include other components, and may be designed to have a connection structure different from that shown.

15 is a simple block diagram for explaining an electronic system including an NFC device according to an embodiment of the present invention.

Referring to FIG. 15 , an electronic system 1000 may include an application processor (AP) 1100, an NFC device 1200, a memory device 1300, a user interface 1400, and a power supply 1500. As an example, the electronic system 1000 may be any mobile system such as a mobile phone, smart phone, personal digital assistant (PDA), portable multimedia player (PMP), digital camera, music player, portable game console, navigation system, laptop computer, etc. there is.

The application processor 1100 may control overall operations of the electronic system 1000 . The application processor 1100 may execute applications providing Internet browsers, games, and videos. The application processor 1100 may include one processor core (single core) or may include a plurality of processor cores (multi-core). Meanwhile, the application processor 1100 may include a cache memory device that temporarily stores instructions or data stored in the memory device 1300 .

The memory device 1300 may store data necessary for the operation of the electronic system 1000 . For example, the memory device 1300 may include a volatile memory device and/or a non-volatile memory device. The volatile memory device may be implemented as DRAM, SRAM, mobile DRAM, or similar memory, and the non-volatile memory device may include electrically erasable programmable read only memory (EEPROM), flash memory, phase change RAM (PRAM), and resistance RAM (RRAM). , Nano Floating Gate Memory (NFGM), Polymer RAM (PoRAM), Magnetic RAM (MRAM), Ferroelectric RAM (FRAM), or similar memory. For example, the memory device 1300 may store a boot image for booting the electronic system 1000, and may store output data to be transmitted to an external device and received input data.

The NFC device 1200 may transmit output data stored in the memory device 1300 to an external device through NFC communication, receive input data from the external device, and store the input data in the memory device 1300 . As an example, the NFC device 1200 may be the NFC devices 100 and 200 according to an embodiment of the present invention described in FIGS. 1 to 14 . That is, the NFC device 1200 may compensate for the phase of the transmission clock signal by detecting a phase delay occurring on the transmission-reception path.

The user interface 1400 may include one or more input devices, such as a keypad or touch screen, and/or one or more output devices, such as speakers or display devices. The power supply 1500 may supply an operating voltage of the electronic system 1000 . In addition, the electronic system 1000 may further include a camera image processor (CIS), a modem such as a baseband chipset, and the like. As an example, the modem may be a modem processor supporting communications such as GSM, GPRS, WCDMA, and HSxPA.

The electronic system 1000 or its components may be mounted using various types of packages. As an example, the electronic system 1000 or its components may include Package on Package (PoP), Ball Grid Arrays (BGAs), Chip Scale Packages (CSPs), Plastic Leaded Chip Carrier (PLCC), and Plastic Dual In-Line Package (PDIP). ), COB (Chip on Board), CERDIP (Ceramic Dual In-Line Package), MQFP (Plastic Metric Quad Flat Pack), TQFP (Thin Quad Flat-Pack), SOIC (Small Outline Integrated Circuit), SSOP (Shrink Small Outline) Package), TSOP (Thin Small Outline Package), TQFP (Thin Quad Flat-Pack), SIP (System In Package), MCP (Multi Chip Package), WFP (Wafer-level Fabricated Package), WSP (Wafer-Level Processed Stack) Package) may be mounted using packages such as the like.

The present invention is not limited by the above-described embodiments and accompanying drawings, but is intended to be limited by the appended claims. Therefore, various forms of substitution, modification, and change will be possible by those skilled in the art within the scope of the technical spirit of the present invention described in the claims, which also falls within the scope of the present invention. something to do.

10: terminal device 11: terminal antenna
12: matching network 20: reader device
21: reader antenna 100, 200, 1200: NFC device
110, 210: phase detector 120, 220: phase delay calculator
130, 230: transfer clock generator 140, 240: transfer clock amplifier
250 phase locked loop 260 accumulator
270 Divider 280 Clock Extractor
REF: reference clock signal TX: transmission clock signal
1000: electronic system 1100: application processor
1300: memory device 1400: user interface
1500: power supply

Claims (20)

a phase detector for receiving a reference clock signal, detecting a phase of the reference clock signal, outputting a generated clock signal synchronized in frequency with the reference clock signal, and storing phase information of the generated clock signal as a first digital code;
Calculating a delta value by comparing the phase of the generated clock signal applied from the phase detector with a reference phase during an active load modulation (ALM) operation, and storing the delta value as a second digital code phase lag calculator; and
a transmission clock generator for outputting a transmission clock signal by reflecting the phase information stored in the first digital code and the second digital code; An NFC device comprising a.
According to claim 1,
a transfer clock amplifier for amplifying and outputting the transfer clock signal applied from the transfer clock generator; NFC device further comprising a.
According to claim 1,
The transmission clock generator includes a digital-time converter for converting the first digital code and the second digital code into a time domain, and a voltage controlled oscillator for controlling an output oscillation frequency based on the input generated clock signal. NFC device.
According to claim 1,
The reference clock signal includes a first reference clock signal input to the phase detector in a first period, and a second reference clock signal input to the phase detector in a second period after the first period.
According to claim 4,
In the first interval, the first transmission clock signal based on the first reference clock signal is not transmitted to the reader device, and in the second interval, the second transmission clock signal based on the second reference clock signal is transmitted to the reader device. NFC device that does.
According to claim 4,
The first reference clock signal is a signal generated by an approach of a reader device, and the second reference clock signal corresponds to a first transmission clock signal output based on the first reference clock signal.
According to claim 4,
The transfer clock signal includes a first transfer clock signal output from the transfer clock generator in the first period and a second transfer clock signal output from the transfer clock generator in the second period, and the second reference clock The signal is an NFC device corresponding to a first transmission clock signal based on the first reference clock signal.
According to claim 7,
The first transmission clock signal is an NFC device in which phase information stored as the first digital code is reflected.
According to claim 7,
The second transmission clock signal is an NFC device in which phase information stored in the first digital code and the second digital code is reflected.
According to claim 1,
The load modulation amplitude based on the transmission clock signal appears constant in a negative direction.
According to claim 1,
The transfer clock signal is an NFC device such that the magnitude of the load modulation amplitude has a maximum value.
According to claim 1,
The delta value is determined by additional delay information, and the additional delay information includes delay information according to a matching network, impedance distribution, and coupling with a reader device.
According to claim 1,
The delta value includes a first delta value when the phase of the generated clock signal is greater than the reference phase, a second delta value when the phase of the generated clock signal is equal to the reference phase, and a phase of the generated clock signal. NFC device including a third delta value when is less than the reference phase.
According to claim 1,
The phase of the transmission clock signal synchronized with the antenna of the reader device is different from the phase of the reference clock signal NFC device.
A phase of a first reference clock signal input in a first period is detected and a first generated clock signal synchronized in frequency with the first reference clock signal is output, and the phase of the first generated clock signal and the first period a phase detector for storing a phase of a second generated clock signal output based on a second reference clock signal input in a subsequent second period as a first digital code;
a phase delay calculator calculating a delta value by comparing a phase of the second generated clock signal applied from the phase detector with a reference phase in the second period, and storing the delta value as a second digital code; and
a transmission clock generator for outputting a transmission clock signal by reflecting the phase information stored in the first digital code and the second digital code; An NFC device comprising a.
According to claim 15,
In the first interval, the first transmission clock signal output from the transmission clock generator is not synchronized with the antenna of the reader device, and is input to the phase detector as the second reference clock signal.
According to claim 15,
In the second period, an active load modulation (ALM) operation is controlled by an ALM signal that is periodically activated and deactivated.
According to claim 17,
While the ALM signal is active, the phase detector stores the phase of the second generated clock signal.
According to claim 17,
While the ALM signal is inactive, the transmission clock generator tracks an optimal transmission clock signal based on the stored phase information.
an antenna for receiving a signal from an approaching reader device;
a matching network that performs impedance matching on the signal received through the antenna and outputs a reference clock signal; and
A phase detector for receiving the reference clock signal and the feedback signal and storing path delay information of the reference clock signal and the feedback signal as a first digital code, and storing additional delay information as a second digital code based on the feedback signal A phase delay calculator, and reflecting the phase information stored as the first digital code and inputting the feedback signal to the phase detector, or reflecting the phase information stored as the first digital code and the second digital code to the reader device An NFC device including a transmission clock generator for transmitting a transmission clock signal; A terminal device including a.

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