KR20230080147A - Display apparatus - Google Patents

Abstract

A display device according to one embodiment of the present invention comprises: a substrate comprising a plurality of sub-pixels; a driving power-supply supply line (VDD) and a reference power-supply supply line (Vref) arranged in parallel and spaced apart in a first direction on the substrate; a light emitting area and driving circuit element included in each of the sub-pixel; and a plurality of connection wiring lines each connecting the driving power-supply supply line (VDD) and the reference power-supply supply line (Vref) to the sub-pixels, wherein at least one center of the connection wiring lines is positioned to overlap the light emitting area. Therefore, the present invention is capable of having an effect of increasing an area of the light emitting area.

Description

Display device {DISPLAY APPARATUS}

The present specification relates to a display device capable of improving an aperture ratio.

Display devices are applied to various electronic devices such as TVs, mobile phones, laptops, and tablets. To this end, research to develop thinning, lightening, and low power consumption of display devices is being continued.

The display device includes a liquid crystal display device (LCD), a plasma display panel device (PDP), a field emission display device (FED), and an electro-wetting display device. : EWD) and Organic Light Emitting Display Device (OLED).

Among them, the organic light emitting display device OLED includes a plurality of pixel areas arranged in a display area where images are displayed, and a plurality of organic light emitting elements corresponding to the plurality of pixel areas. Since the organic light emitting device is a self-emitting device that emits light by itself, the organic light emitting display device has advantages in that it has a fast response speed, high luminous efficiency, luminance and viewing angle, and excellent contrast ratio and color gamut compared to liquid crystal display devices.

An organic light emitting display device includes a light emitting unit and a circuit unit for driving the light emitting unit. The circuit unit includes a thin film transistor and a storage capacitor. When such an organic light emitting display device is a bottom emission method in which light generated from the light emitting layer is emitted in the opposite direction of the substrate, that is, toward the back surface of the substrate, the area where the circuit unit is disposed does not emit light to the outside. . Accordingly, there is a problem in that the aperture ratio decreases by the area where the circuit unit is disposed.

An object to be solved according to embodiments of the present specification is to provide a display device capable of improving an aperture ratio by increasing an area of an emission region in an organic light emitting display device.

Another object of the present invention is to provide a display device in which the area of the light emitting region is increased by overlapping some of the wiring electrodes with the light emitting region.

In addition, an object of the present invention is to secure a space margin and increase an additional aperture ratio by simplifying the structure of a contact hole for connecting between electrodes.

In addition, an object of the invention according to the embodiments of the present specification is to increase the lifespan of an organic light emitting device by reducing the current consumption for implementing the same luminance in individual pixels by increasing the area of the light emitting region.

Another object is to provide a display device capable of increasing the total capacitance of the storage capacitor while increasing the area of the light emitting region by reducing the area occupied by the storage capacitor.

In addition, an object of the present invention is to increase the capacitance of the storage capacitor by improving the structure of a dielectric constituting the storage capacitor.

Solving problems according to an embodiment of the present specification are not limited to the above-mentioned purposes, and other objects and advantages of the present invention not mentioned above can be understood by the following description, and can be more easily understood by the embodiments of the present specification. will be clearly understood. Further, it will be readily apparent that the objects and advantages of this specification may be realized by means of the instrumentalities and combinations indicated in the claims.

A display device according to an exemplary embodiment of the present specification includes a substrate including a plurality of sub-pixels; a driving power supply line (VDD) and a reference power supply line (Vref) arranged spaced apart in parallel in a first direction on the substrate; a light emitting region and a driving circuit element included in each of the sub-pixels; and a plurality of connection wiring lines respectively connecting the driving power supply line VDD and the reference power supply line Vref to the sub-pixels, wherein at least one of the connection wiring lines overlaps the light emitting region. It is characterized by doing.

According to the embodiments of the present specification, some of the wiring electrodes are made of a transparent material so that they overlap with the light emitting region, thereby increasing the area of the light emitting region.

In addition, by forming some of the wire electrodes with a transparent material, an area of the light emitting area is increased by extending the area of the light emitting area to the light emitting area of the adjacent sub-pixel, thereby providing an advantage of increasing the aperture ratio.

In addition, there is an effect of securing a space margin and increasing an additional aperture ratio by simplifying the structure of a contact hole for connecting between electrodes.

In addition, according to the exemplary embodiments of the present specification, an area occupied by a storage capacitor may be reduced to increase an area of a light emitting region, thereby improving an aperture ratio.

In addition, it is advantageous to increase capacitance of the storage capacitor by improving the structure of a dielectric constituting the storage capacitor while reducing the area occupied by the storage capacitor.

In addition, the reliability of the display device can be improved by increasing the lifespan of the organic light emitting device by reducing current consumption for implementing the same luminance in individual pixels by increasing the area of the light emitting region.

Effects of the present specification are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description below.

1A is a plan view of a display device according to a first embodiment of the present specification.
FIG. 1B is a cross-sectional view cut along II', II-II', III-III', IV-IV', VV', and VI-VI' directions of FIG. 1A.
2A is a plan view of a display device according to a second exemplary embodiment of the present specification.
FIG. 2B is a cross-sectional view taken along the directions II', II-II', III-III', IV-IV', VV', and VI-VI' of FIG. 1A.
3 to 12 are cross-sectional views illustrating a method of manufacturing a display device according to a second exemplary embodiment of the present specification.
13 is a plan view of a display device according to a third exemplary embodiment of the present specification.

Advantages and features of this specification, and methods of achieving them, will become clear with reference to embodiments described below in detail in conjunction with the accompanying drawings. However, this specification is not limited to the embodiments disclosed below, but will be implemented in various different forms, and only these embodiments make the disclosure of this specification complete, and common knowledge in the art to which this specification belongs. It is provided to fully inform the owner of the scope of the invention, and this specification is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of this specification are illustrative, so this specification is not limited to the matters shown. Like reference numbers designate like elements throughout the specification. In addition, in describing the present specification, if it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present specification, the detailed description will be omitted. When 'includes', 'has', 'consists of', etc. mentioned in this specification is used, other parts may be added unless 'only' is used. In the case where a component is expressed in the singular, the case including the plural is included unless otherwise explicitly stated.

In interpreting the components, even if there is no separate explicit description, it is interpreted as including the error range.

In the case of a description of a positional relationship, for example, 'on top of', 'on top of', 'at the bottom of', 'next to', etc. Or, unless 'directly' is used, one or more other parts may be located between the two parts.

In the case of a description of a temporal relationship, for example, when a temporal precedence relationship is described as 'after', 'continue to', 'after ~', 'before', etc., 'immediately' or 'directly' As long as ' is not used, non-continuous cases may also be included.

Although first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present specification.

Each feature of the various embodiments of the present specification can be partially or entirely combined or combined with each other, technically various interlocking and driving are possible, and each embodiment can be implemented independently of each other or can be implemented together in an association relationship. may be

Hereinafter, a display device according to each exemplary embodiment of the present invention will be described with reference to the accompanying drawings.

1A is a plan view of a display device according to a first embodiment of the present specification. And FIG. 1B is a cross-sectional view cut along the directions II', II-II', III-III', IV-IV', V-V', and VI-VI' of FIG. 1A.

Referring to FIGS. 1A and 1B , the display device 10 according to the first embodiment of the present specification is a bottom emission type display device that emits light in a downward direction where the substrate 100 is disposed. Such a display device 10 includes a light emitting region 194 in which an organic light emitting diode (OLED) emitting light is disposed, and a circuit portion provided with driving circuit elements for supplying driving current to the organic light emitting diode (OLED). . The light emitting area 194 and the driving circuit elements are arranged in a display area in which a plurality of sub-pixels SP1 , SP2 , and SP3 are arranged in a matrix form (M*N, where M and N are natural numbers) to display an image. Each of the sub-pixels SP1 , SP2 , and SP3 disposed in the display area includes a driving circuit element and an organic light emitting diode OLED disposed in the circuit unit.

The driving circuit element includes a thin film transistor T and a storage capacitor Cst. The driving circuit elements constituting the circuit unit are disposed in the area other than the light emitting area 194 .

The thin film transistor T includes a gate electrode 164 , a source electrode 166 , a drain electrode 168 and an active layer 125 .

The gate electrode 164 overlaps the channel region CH of the active layer 125 . A gate insulating layer 130 is disposed between the gate electrode 164 and the channel region CH of the active layer 125 . The gate electrode 164 is any one from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), or copper (Cu). It may be a single layer or multiple layers made of one or an alloy thereof. The gate electrode 164, the source electrode 166, and the drain electrode 168 may have a structure in which a first gate metal 161 and a second gate metal 163 are stacked.

The active layer 125 includes a source region SA and a drain region DA facing each other with the channel region CH interposed therebetween. The channel region CH is disposed to overlap the gate electrode 164 with the gate insulating layer 130 interposed therebetween.

The source electrode 166 is electrically connected to the source region SA of the active layer 125 , and the drain electrode 168 is electrically connected to the drain region DA of the active layer 125 . The drain electrode 168 is electrically connected to the first electrode 186 through a pixel contact hole 184 formed through the planarization layer 182 and the interlayer insulating layer 176 . In addition, the drain electrode 168 may be electrically connected to the light blocking layer 105 through the light blocking contact hole 154 penetrating the first buffer layer 120 and the second buffer layer 122 . Also, the source electrode 166 may be electrically connected to the power supply line VDD.

The source electrode 166 and the drain electrode 168 are made of the same material as the gate electrode 164 and are positioned on the same plane (layer).

The active layer 125 includes amorphous silicon, polycrystalline silicon, or an oxide semiconductor.

A light blocking layer 105 is formed between the active layer 125 and the substrate 100 . The light blocking layer 105 is formed at a position overlapping the active layer 125 . A surface of the light blocking layer 105 may be partially exposed through the light blocking contact hole 154 and electrically connected to the active layer 125 through the drain electrode 168 .

The light blocking layer 105 may be formed of the same material on the same plane as the storage lower electrode 110 and the wiring electrode 115 . Here, the wiring electrode 115 includes a driving power supply line VDD, a data line DL, and a reference power supply line Vref, and is arranged in a first direction X, for example, a horizontal line. In one example, the light blocking layer 105 may have a structure in which a first metal layer 102 and a second metal layer 104 are stacked. In addition, the light blocking layer 105 may be formed of any one selected from the group of opaque metal materials such as molybdenum (Mo), aluminum (Al), titanium (Ti), or copper (Cu), or an alloy thereof.

The first buffer layer 120 and the second buffer layer 122 are disposed on the light blocking layer 105 , the storage lower electrode 110 , and the wiring electrode 115 . The first buffer layer 120 and the second buffer layer 122 block penetration of moisture or oxygen toward the organic light emitting device and protect the thin film transistor from impurities such as hydrogen.

The storage capacitor Cst is formed by disposing the storage lower electrode 110 and the storage upper electrode 125a with the first buffer layer 120 and the second buffer layer 122 interposed therebetween. That is, a stacked structure of the first buffer layer 120 and the second buffer layer 122 is disposed as a dielectric between the storage lower electrode 110 and the storage upper electrode 125a. In this case, the storage lower electrode 110 is made of the same material as the light blocking layer 105 , and the storage upper electrode 125a is made of the same material as the active layer 125 .

The first buffer layer 120 is formed of silicon nitride (SiNx) having a first thickness (T1), and the second buffer layer 122 is formed of silicon oxide (SiOx) having a second thickness (T2) thicker than the first buffer layer 120. form with For example, the first buffer layer 120 is formed to a first thickness of 1000 Å to 1500 Å, and the second buffer layer 122 is formed to a second thickness of 2700 Å to 3300 Å. Accordingly, the buffer layers 120 and 122 positioned as a dielectric between the storage lower electrode 110 and the storage upper electrode 125a are formed to a thickness greater than at least 3700 Å.

The capacitance of the storage capacitor Cst1 is affected by the thickness of the dielectric and the area of the storage lower electrode 110 or the storage upper electrode 125a. For example, as the thickness of the dielectric increases, the capacitance decreases in inverse proportion, and as the thickness of the dielectric becomes thinner, the capacitance may increase. In addition, capacitance may increase as the area of the storage lower electrode 110 or the storage upper electrode 125a increases.

In the first embodiment of the present specification, since the dielectric constant of the first buffer layer 120 is about 6.9 and the dielectric constant of the second buffer layer 122 is about 3.9, the capacitance value of the storage capacitor Cst1 is 0.0011 * constant. has a value of In order to improve capacitance in a state where the first buffer layer 120 and the second buffer layer 122 are fixed with a dielectric material, an area occupied by the storage capacitor Cst1 needs to be increased. However, when the area of the storage capacitor Cst1 is increased, the area of the light emitting region 194 is reduced due to the area occupied by the storage capacitor Cst1, resulting in a decrease in aperture ratio.

The pad electrode 174 is disposed on the same plane as the gate electrode 164 , the source electrode 166 , and the drain electrode 168 . The pad electrode 174 is formed of the same material as the gate electrode 164, the source electrode 166, and the drain electrode 168. A pad cover electrode 188 preventing corrosion of the pad electrode 174 is disposed on the pad electrode 174 .

The pad electrode 174 is disposed on the non-display area except for the display area where an image is displayed, and the gate electrode 164, the data line DL, the driving power supply line VDD and the reference power supply line Vref, respectively. serves to supply a driving signal to In the embodiment of the present specification, a configuration in which the pad electrode 174 is connected to the driving power supply line VDD has been presented as an example, but is not limited thereto. For example, a plurality of pad electrodes 174 may be configured to be connected to each of the data line DL and the reference power supply line Vref.

The driving power supply line VDD, the data line DL, and the reference power supply line Vref are arranged on the substrate 100 in the first direction X. Here, the first direction X may be a horizontal line. A plurality of scan lines (SCAN1) in a second direction (Y), which is a direction crossing the driving power supply line (VDD), data line (DL), and reference power supply line (Vref) arranged in the first direction (X); SCAN2) and a plurality of connection wiring lines CL1 and CL2 are disposed. The second direction (Y) may be a vertical line.

The scan lines SCAN1 and SCAN2 supply scan signals for selecting each horizontal line while supplying data signals to individual sub-pixels SP1, SP2 and SP3, and each sub-pixel SCAN1 and each sub-pixel. A second scan line SCAN2 supplying a signal for selecting each horizontal line while initializing the data signal supplied to the pixels SP1, SP2, and SP3 is included.

Since the plurality of sub-pixels SP1, SP2, and SP3 are arranged in a matrix form (M * N, where M and N are natural numbers), the driving power supply line VDD or the reference power supply line Vref is connected to the sub-pixels. Separate connection wiring lines (CL1, CL2) are required to connect with each other. The driving power supply line VDD or the reference power supply line Vredf and the connection wiring lines CL1 and CL2 may be electrically connected through individual contact holes C. For reference, reference numeral 'C' in FIG. 1A refers to two elements disposed above and below each other with an insulating layer such as the gate insulating film 130 or the buffer layers 120 and 122 interposed therebetween. It means a contact hole formed on the insulating layer so that it can be connected to

The connection wiring lines CL1 and CL2 include the first connection wiring line CL1 and the reference power supply line connecting the driving power supply line VDD to the sub-pixels arranged in the second direction Y through the contact hole C. A second connection line CL2 electrically connected from the supply line Vref through the contact hole C and connected to individual sub-pixels.

In addition, in order to electrically connect the active layer 125 and the light blocking layer 105 or between the active layer 125 and the wire electrode 115, a contact electrode CT filling the contact hole C is introduced. Here, the scan lines SCAN1 and SCAN2, the connection wiring lines CL1 and CL2, and the contact electrode CT are formed of the same material through the same mask process as the gate electrode 264 and are on the same layer. Located. Accordingly, the scan lines SCAN1 and SCAN2, the connection wiring lines CL1 and CL2, and the contact electrode CT are made of an opaque metal material.

As the contact electrode CT and the scan lines SCAN1 and SCAN2 disposed between the first scan line SCAN1 and the second scan line SCAN2 are made of the same material and are positioned on the same plane, the first scan line ( A separation distance (a) should be secured between SCAN1) and the contact electrode (CT) and between the second scan line (SCAN2) and the contact electrode (CT). As such, as a space margin as much as the first width L1 including the separation distance a is required between the first scan line SCAN1 and the second scan line SCAN2, the light emitting area ( 194), there is a limit to increasing the area. Here, the first width L1 of the space margin required between the first scan line SCAN1 and the second scan line SCAN2 includes the separation distance a and the width of the contact electrode CT.

An interlayer insulating film 176 and a planarization film 182 are disposed on the substrate 100 on which the gate electrode 164 , the source electrode 166 , the drain electrode 168 , and the upper storage electrode 172 are formed. The interlayer insulating film 176 and the planarization film 182 are formed by selecting an inorganic insulating material or an organic insulating material.

A color filter 180 is disposed on the interlayer insulating layer 176 . The color filter 180 is disposed at a position overlapping the light emitting region 194 . The color filter 180 may represent a color assigned to each sub-pixel. For example, the color filter 180 may be one of red (R), green (G), and blue (B).

The planarization film 182 is formed on the substrate 100 to form a flat surface. The planarization layer 182 further includes a pixel contact hole 184 exposing a portion of the surface of the drain electrode 168 .

A first electrode 186 is disposed on the planarization layer 182 and the pixel contact hole 184 and electrically connected to the drain electrode 168 . The first electrode 186 is formed on the planarization layer 182 so as to overlap the driving circuit element including the light emitting region 194 formed by the bank hole 192 provided in the bank 190, the thin film transistor, and the storage capacitor Cst. is placed on The width EAW1 of the light emitting region 194 may be defined by the size of the bank hole 192 . The first electrode 186 includes a transparent metal oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO). The first electrode 186 may also be referred to as an anode electrode or a pixel electrode.

The organic light emitting layer 198 extends to the upper surface of the bank 190 while being connected to the first electrode 186 exposed by the bank hole 192 . The organic emission layer 198 has a stacked structure of a hole transport layer (HTL), an emission layer (EML), and an electron transport layer (ETL). The organic emission layer may further include a hole blocking layer (HBL), a hole injection layer (HIL), an electron blocking layer (EBL), and an electron injection layer (EIL). The organic emission layer 198 is made of an organic material that emits white light, and a color may be displayed by the color filter 180, but is not limited thereto.

A second electrode 199 is disposed on the organic light emitting layer 198 . Accordingly, an organic light emitting diode (OLED) composed of the first electrode 186 , the organic light emitting layer 198 and the second electrode 199 is formed. The second electrode 199 serves to apply a voltage by commonly contacting the sub-pixels SP1 , SP2 , and SP3 adjacent to each other on the display area, and may also be referred to as a common electrode or a cathode electrode.

As described above, in the first embodiment of the present specification, as the structure in which the first buffer layer 120 and the second buffer layer 122 are stacked in a double layer is introduced as the dielectric, the thickness of the dielectric is increased to improve the capacitance. There are limits. In addition, connection wiring lines CL1 and CL2 and contact electrodes CT are disposed to supply a signal for driving the driving circuit element. The connection wiring lines CL1 and CL2 and the contact electrodes As (CT) is made of an opaque metal material, there is a limit to increasing the area of the light emitting region 194 .

Accordingly, in another embodiment of the present specification, a display device structure capable of increasing the capacitance of a storage capacitor while improving an aperture ratio by increasing an area of a light emitting region within a limited space and a manufacturing method thereof will be described. It will be described with reference to the drawings below.

2A is a plan view of a display device according to a second exemplary embodiment of the present specification. And Figure 2b is a cross-sectional view cut along the II', II-II', III-III', IV-IV', V-V' and VI-VI' directions of FIG. 1a.

Referring to FIGS. 2A and 2B , the display device 20 includes a light emitting area in which an organic light emitting diode (OLED) emitting light is disposed, and driving circuit elements for supplying driving current to the organic light emitting diode (OLED). contains circuitry. The light emitting area and the driving circuit elements are disposed in a display area where the plurality of sub-pixels SP1 , SP2 , and SP3 display images. Although only some of the sub-pixels (SP1, SP2, and SP3) are shown in the embodiment of the present specification, the sub-pixels are arranged in a matrix form (M*N, where M and N are natural numbers) on the display area.

Each of the sub-pixels SP1 , SP2 , and SP3 disposed in the display area includes a driving circuit element and an organic light emitting diode OLED disposed in the circuit unit. The driving circuit element includes a thin film transistor T and a storage capacitor Cst. The driving circuit elements constituting the circuit unit are disposed in the area other than the light emitting area 292 .

The thin film transistor T includes an active layer 230 including a gate electrode 245, a source region SA in which the source electrode SE is integrated, a channel region CH, and a drain region DA.

The gate electrode 245 overlaps the channel region CH of the active layer 230 . A gate insulating layer 240 is disposed between the gate electrode 245 and the channel region CH of the active layer 230 .

The gate electrode 245 is any one from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), or copper (Cu). It may be a single layer or multiple layers made of one or an alloy thereof. In one example, the gate electrode 245 may have a structure in which a first gate metal 242 and a second gate metal 244 are stacked. For example, the first gate metal 242 may be formed of copper (Cu), and the second gate metal 244 may be formed of a titanium molybdenum alloy.

The active layer 230 includes a source area SA and a drain area DA facing each other with the channel area CH interposed therebetween. The channel region CH is disposed to overlap the gate electrode 245 with the gate insulating layer 240 interposed therebetween.

The source region SA includes a source electrode SE connected to the driving power supply line VDD and 207 while filling the source contact hole 225 formed through the buffer layers 220 and 222 . As shown in FIG. 1A , the source region SA of the active layer 230 may be arranged to extend in the direction of the driving power supply line 207 . Here, the source electrode SE extends from the lower portion of the source region SA and is integrally formed, and may be made of the same material as the source region SA. A part of the surface of the drain region DA is exposed and connected to the first electrode 283 of the organic light emitting diode OLED.

As the source region SA of the active layer 203 extends in the direction of the driving power supply line 207 and the source electrode SE is directly connected to the driving power supply line 207, the source electrode is made of an opaque metal material. In this case, a contact hole formed to connect the source electrode and the active layer may be omitted.

The active layer 230 may be a semiconductor material having a band gap greater than 3 eV and high transmittance in a visible ray region, thus having transparent characteristics. For example, the active layer 230 may include at least one of oxide semiconductor materials such as indium gallium zinc oxide (IGZO) and indium zinc oxide (IZO) materials having a band gap of 3.05 Ev. can include In addition, the active layer 230 may be formed of another oxide semiconductor material having a band gap greater than 3eV known in the art.

A light blocking layer 205 is positioned between the active layer 230 and the substrate 200 . The light blocking layer 205 is disposed at a position overlapping the active layer 230 and overlaps at least the channel region CH of the active layer 230 .

The light blocking layer 205 may be formed of the same material on the same plane as the driving power supply line (VDD, 207), the storage lower electrode 210, and the wiring electrode 215. Here, the wire electrode 215 includes a data line DL and a reference power supply line Vref, and is arranged in a first direction X, for example, a horizontal line. In one example, the light blocking layer 205 may have a structure in which a first metal layer 202 and a second metal layer 204 are stacked. In addition, the light blocking layer 205 may be formed of any one selected from the group of opaque metal materials such as molybdenum (Mo), aluminum (Al), titanium (Ti), or copper (Cu), or an alloy thereof.

Buffer layers 220 and 222 are disposed on the light blocking layer 205 , the driving power supply line 207 , the lower storage electrode 210 , and the wiring electrode 215 .

The buffer layers 220 and 222 include a first buffer layer 220 and a second buffer layer 222 . The first buffer layer 220 is formed of silicon nitride (SiNx) having a first thickness, and the second buffer layer 222 is formed of silicon oxide (SiOx) having a second thickness thicker than the first buffer layer 220 . For example, the first buffer layer 220 is formed to a first thickness of 1000 Å to 1500 Å, and the second buffer layer 222 is formed to a second thickness of 2700 Å to 3300 Å.

The storage capacitor Cst2 is formed by disposing the lower storage electrode 210 and the upper storage electrode 235 with the first buffer layer 220 therebetween. The storage upper electrode 235 fills the storage contact hole 227 penetrating the second buffer layer 222 and extends to partially cover the upper surface of the second buffer layer 222 . Accordingly, the bottom portion of the storage upper electrode 235 overlaps the storage lower electrode 210 with the first buffer layer 220 interposed therebetween, and the side portion of the storage upper electrode 235 contacts the second buffer layer 222. . In this case, the storage upper electrode 235 has a 'T' shape when viewed in cross section. The storage lower electrode 210 is made of the same material as the light blocking layer 205 , and the storage upper electrode 235a is made of the same material as the active layer 230 .

The storage capacitor Cst2 serves to maintain light emission of the organic light emitting device by charging a voltage and supplying a current to the thin film transistor. Accordingly, as the capacitance value increases, the time during which light emission of the organic light emitting diode can be maintained increases.

In the storage capacitor Cst2 according to the second exemplary embodiment of the present specification, a single layer of the first buffer layer 220 is disposed between the storage lower electrode 210 and the storage upper electrode 235a as a dielectric. The first buffer layer 220 is made of silicon nitride (SiNx) and has a first thickness of 1000 Å to 1500 Å. Since the permittivity of silicon nitride (SiNx) is about 6.9, the capacitance value of the storage capacitor Cst2 has a constant value of 0.0069*. Therefore, capacitance can be increased at least 6 times more than that of the storage capacitor Cst1 in the case where the stacked structure of the first buffer layer 120 and the second buffer layer 122 is introduced as a dielectric according to the first embodiment of FIG. 1B. there is.

As the capacitance is increased by at least 6 times by introducing the dielectric into the single layer of the first buffer layer 220, the organic light emitting device emits light more relatively than the storage capacitor Cst1 formed of the double layer of the first and second buffer layers. can be maintained for a long time. Accordingly, an area occupied by the storage capacitor Cst2 in the circuit unit may be reduced. For example, the area occupied by the storage capacitor Cst2 according to the second embodiment of the present specification may be reduced by about 84.2% compared to the area occupied by the storage capacitor Cst1 according to the first embodiment. Accordingly, the aperture ratio may be increased by increasing the light emitting area by the reduced area of the storage capacitor.

An interlayer insulating layer 255 and a planarization layer 270 are disposed on the substrate on which the gate electrode 245 , the second connection line CL2 , and the upper storage electrode 235a are formed. The interlayer insulating film 255 and the planarization film 270 are formed of a single-layer or multi-layer structure by selecting an inorganic or organic insulating material.

A color filter 260 is disposed on the interlayer insulating layer 255 at a position overlapping the emission region 260 . The color filter 260 may represent a color assigned to each sub-pixel. For example, the color filter 260 may be one of red (R), green (G), and blue (B), but is not limited thereto.

The planarization layer 270 is formed on the substrate 200 to form a flat surface, and has a pixel contact hole 280 exposing a portion of the surface of the drain region DA of the active layer 230 . The pixel contact hole 280 passes through the interlayer insulating layer 255 and the planarization layer 270 and directly contacts the drain region DA. Accordingly, as shown in FIG. 1A, the contact hole formed in the gate insulating layer 130 to connect the drain electrode DA and the drain region DA may be omitted.

A first electrode 283 electrically connected to the drain region DA whose surface is partially exposed is disposed on the planarization layer 270 and the pixel contact hole 280 . The first electrode 283 is disposed on the planarization film 270 so as to overlap the light emitting region 292 defined by the bank hole 290 provided in the bank 285 and the thin film transistor. The first electrode 283 includes a transparent metal oxide such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO). The first electrode 283 may also be referred to as an anode electrode or a pixel electrode.

The width EAW2 of the light emitting region 292 may be defined by the size of the bank hole 290 .

The organic emission layer 295 extends to the upper surface of the bank 285 while being connected to the first electrode 283 exposed by the bank hole 290 . The organic emission layer 295 has a stacked structure of a hole transport layer (HTL), an emission layer (EML), and an electron transport layer (ETL). The organic emission layer may further include a hole blocking layer (HBL), a hole injection layer (HIL), an electron blocking layer (EBL), and an electron injection layer (EIL). The organic emission layer 295 is made of an organic material that emits white light, and a color may be displayed by the color filter 260, but is not limited thereto.

A second electrode 300 is disposed on the organic emission layer 295 . Accordingly, an organic light emitting diode (OLED) composed of the first electrode 283 , the organic light emitting layer 295 and the second electrode 300 is formed. The second electrode 300 commonly contacts adjacent sub-pixels SP1 , SP2 , and SP3 on the display area to apply a voltage, and may also be referred to as a common electrode or a cathode electrode.

The pad electrode 250 is disposed on the same plane as the gate electrode 245 . The pad electrode 250 is formed of the same material as the gate electrode 245 . A pad cover electrode 284 preventing corrosion of the pad electrode 250 is disposed on the pad electrode 250 .

The pad electrode 250 is disposed on the non-display area except for the display area where an image is displayed, and the gate electrode 245, the data line DL, the driving power supply line VDD and the reference power supply line Vref, respectively. serves to supply a driving signal to In the embodiment of the present specification, a configuration in which the pad electrode 250 is connected to the driving power supply line VDD has been presented as an example, but is not limited thereto. For example, a plurality of pad electrodes 250 may be configured to be connected to each of the data line DL and the reference power supply line Vref.

The driving power supply line VDD, the data line DL, and the reference power supply line Vref are arranged on the substrate 200 in the first direction X. Here, the first direction X may be a horizontal line. A plurality of scan lines (SCAN1) in a second direction (Y), which is a direction crossing the driving power supply line (VDD), data line (DL), and reference power supply line (Vref) arranged in the first direction (X); SCAN2) and a plurality of connection wiring lines CL1 and CL2 are disposed. The second direction (Y) may be a vertical line.

The scan lines SCAN1 and SCAN2 supply scan signals for selecting each horizontal line while supplying data signals to individual sub-pixels SP1, SP2 and SP3, and each sub-pixel SCAN1 and each sub-pixel. A second scan line SCAN2 supplying a signal for selecting each horizontal line while initializing the data signal supplied to the pixels SP1, SP2, and SP3 is included.

The scan lines SCAN1 and SCAN2 are formed of the same material through the same mask process as the gate electrode 245 and are positioned on the same plane as the gate electrode 245 . Accordingly, the scan lines SCAN1 and SCAN2 are made of an opaque metal material.

A plurality of sub-pixels SP1 , SP2 , and SP3 are arranged in a matrix form (M*N, where M and N are natural numbers) in the first direction (X) and the second direction (Y). Accordingly, separate connection wiring lines CL1 and CL2 are required to connect the driving power supply line VDD or the reference power supply line Vref to each of the sub-pixels. The driving power supply line VDD or the reference power supply line Vredf and the connection wiring lines CL1 and CL2 may be electrically connected through individual contact holes C. For reference, reference numeral 'C' in FIG. 2A is to electrically connect two components disposed above and below each other with an insulating layer such as the gate insulating film 240 or the buffer layers 220 and 222 interposed therebetween. It refers to a contact hole formed through the insulating layer to be able to pass through the insulating layer.

The connecting wiring lines CL1 and CL2 connect the driving power supply line VDD and the sub-pixels arranged in the second direction Y of the substrate 200 through the contact hole C. ) and a second connection wiring line CL2 electrically connected from the reference power supply line Vref through the contact hole C and connected to individual sub-pixels.

Here, the connection wiring lines CL1 and CL2 are formed of the same material on the same plane as the active layer 230 . In one example, the connection wiring lines CL1 and CL2 are made of a transparent and conducting semiconductor material. Specifically, the connection wiring lines CL1 and CL2 may include at least one of oxide semiconductor materials such as indium gallium zinc oxide (IGZO) and indium zinc oxide (IZO).

As the connection wiring lines CL1 and CL2 are made of a transparent and conductive semiconductor material, at least one of the connection wiring lines CL1 and CL2 extends in the direction of the light emitting region 292 to form the light emitting region 292. It can be placed so that it overlaps part of the area.

For example, the second connection line CL2 of the first sub-pixel SP1 overlaps the emission area 292 of the third sub-pixel SP3 adjacent thereto, and the second sub-pixel SP2 The second connection line CL2 may overlap the emission region 292 of the first sub-pixel SP1 that is an adjacent sub-pixel. In addition, the first connection line CL1 of the first sub-pixel SP1 may overlap the emission region 292 of the first sub-pixel SP1.

As shown in FIG. 1A , when the connection wiring lines CL1 and CL2 are formed of an opaque metal material, a light emitting area is formed as space in which the connection wiring lines CL1 and CL2 are to be disposed is required. There is a limit to how much space can be increased. In addition, when the second connection line CL2 is formed of an opaque metal material, a contact hole C is required to connect the active layer 125 and the second connection line CL2.

In contrast, as the connection wiring lines CL1 and CL2 according to the second exemplary embodiment of the present specification are made of a transparent semiconductor material, they overlap the light emitting region 292 of each of the subpixels SP1, SP2, and SP3. Since the area of the light emitting region 292 can be increased, the aperture ratio can be improved. For example, the width EAW2 of the light emitting region 292 increases by the increased width ΔW as the overlapping width of the connection wiring lines CL1 and CL2 and the area of the storage capacitor Cst decrease. may have a wider width than the width EAW1 of the light emitting region 194 of the first embodiment.

As the area of the light emitting region 194 increases, current consumption for achieving the same luminance in each sub-pixel can be reduced. Accordingly, reliability of the display device may be increased by increasing the lifespan of the organic light emitting device.

The connection wiring lines CL1 and CL2 are formed to have a relatively wider width than the width of the scan lines SCAN1 and SCAN2 made of an opaque metal material to have lower resistance than when the connection wiring lines are formed of a metal material. may have the same resistance. In this case, since the connection wiring lines CL1 and CL2 are made of a transparent semiconductor material, the aperture ratio is not affected.

In addition, the light blocking layer 205 or the wiring electrode ( 214) can be linked. Accordingly, the second width L2, which is the distance between the first scan line SCAN1 and the second scan line SCAN2, is smaller than the first width L1 (see FIG. 1A) according to the first embodiment of the present specification. As the area of the light emitting region 292 can be further increased, the aperture ratio can be further increased. In addition, as the second connection line CL2 is formed of the same material as the active layer 230, when the second connection line is formed of an opaque metal material, the active layer and the second connection line CL2 are connected. The contact hole for this can be omitted.

In this way, as the connection wiring lines CL1 and CL2 are formed of a transparent semiconductor material, additionally required contact holes can be omitted when the connection wiring lines are formed of an opaque metal material, thereby increasing the light emitting area. margin can be secured.

Hereinafter, a method of manufacturing the display device of FIGS. 2A and 2B will be described with reference to drawings.

3 to 11 are cross-sectional views illustrating a method of manufacturing a display device according to a second exemplary embodiment of the present specification. Elements identical to or similar to those of FIGS. 2A and 2B will be briefly described.

Referring to FIG. 3 , a light blocking layer 205 , a driving power supply line (VDD, 207 ), a storage lower electrode 210 and a wiring electrode 215 are formed on a substrate 200 . Specifically, a first metal layer 202 and a second metal layer 204 are formed on the substrate 200 . Next, a photolithography process and an etching process using a mask are performed on the first metal layer 202 and the second metal layer 204 to form a light blocking layer 205, a driving power supply line 207, a storage lower electrode 210, and A wiring electrode 215 is formed. Here, the light blocking layer 205 is preferably formed at a position overlapping with the active layer of the thin film transistor to be formed later. The light blocking layer 205 serves to protect the thin film transistor from light incident from the outside. In one example, the wire electrode 215 may be either a data line DL or a reference power supply line Vref.

The driving power supply line 207 and the wiring electrode 215 may be arranged in the first direction of the substrate 200 . Here, the first direction may be a horizontal direction of the substrate 200 .

The substrate 200 may be made of a flat insulating material. For example, the substrate 200 may be a light-transmitting substrate. The substrate 200 may be made of a hard material such as glass or tempered glass or a flexible material such as plastic, but is not limited thereto.

The light blocking layer 205, the driving power supply line 207, the storage lower electrode 210, and the wiring electrode 215 may be formed using the same material. In one example, the first metal layer 202 and the second metal layer 204 are any one selected from the group of opaque metal materials such as molybdenum (Mo), aluminum (Al), titanium (Ti) or copper (Cu), or It may be made of a single layer or laminated structure of these alloys. For example, the first metal layer 202 may be formed of copper (Cu), and the second metal layer 205 may be formed of a titanium molybdenum alloy (MoTi).

Referring to FIG. 4 , a first buffer layer 220 and a second buffer layer 222 are formed on a substrate 200 . The first buffer layer 220 and the second buffer layer 222 are formed to cover the light blocking layer 205 , the driving power supply line 207 , the storage lower electrode 210 and the wiring electrode 215 . The first buffer layer 220 and the second buffer layer 222 block moisture or oxygen from penetrating from the substrate 200 toward the organic light emitting device to be formed thereon, and prevent impurities such as hydrogen from flowing out of the substrate 200. It serves to protect the thin film transistor formed in the subsequent process. In addition, the first and second buffer layers 220 and 222 serve to insulate the light blocking layer 205 , the driving power supply electrode 207 , the storage lower electrode 210 and the wiring electrode 215 .

The first buffer layer 220 and the second buffer layer 222 may include an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx). In one example, the first buffer layer 220 is formed of silicon nitride (SiNx) having a first thickness, and the second buffer layer 222 is formed of silicon oxide (SiOx) having a second thickness thicker than the first buffer layer 220 . can do.

Referring to FIG. 5 , a photoresist pattern 223 is formed on the second buffer layer 222 . Specifically, a photoresist film is applied on the second buffer layer 222 . Subsequently, an exposure process of selectively irradiating light onto the photoresist film through a halftone mask and a development process of removing the photoresist film modified by the exposure process are performed to form a photoresist pattern 223 . Then, the full open area 223a from which the photoresist film is completely removed to expose the surface of the second buffer layer 222 and the halftone area 223b where the photoresist film remains on the second buffer layer 222 by a predetermined thickness d1. The provided photoresist pattern 223 is formed. In one example, the portion where the halftone region 223b is disposed is a capacitor region V−V′ where the storage lower electrode 210 is formed.

Referring to FIG. 6 , a patterning process is performed using the photoresist layer pattern 223 as an etch mask to form a source contact hole 225 and a storage contact hole 227 . The patterning process may be performed by a wet etching method. The wet etching method may be performed using a buffered oxide etchant (BOE) solution in which an ammonium fluoride (NH ₄ F) solution and a hydrogen fluoride (HF) solution are mixed. In the BOE solution, silicon oxide having a higher etching selectivity than silicon nitride may be preferentially etched.

Accordingly, in the halftone region 223b where the photoresist film pattern 223 remains by a predetermined thickness d1, the photoresist film pattern 223 and the second buffer layer 222 are removed, and the first buffer layer 220 is formed. A storage contact hole 227 is formed, the surface of which is exposed. In the full open area 223a where the photoresist film is completely removed and the surface of the first buffer layer 220 is exposed, the exposed portion of the first buffer layer 220 is removed to expose a portion of the surface of the driving power supply line 207. A source contact hole 225 is formed.

During the patterning process, as the first buffer layer 220 made of silicon nitride serves as an etch stop film for the BOE solution, the full open area 223a and the halftone area 223b of the photoresist film pattern 223 are etched uniformly. can proceed In other words, since the first buffer layer 220 includes a material having a relatively slower etching rate than the second buffer layer 222 made of silicon oxide (SiOx), for example, silicon nitride (SiNx), the BOE solution is used. In the wet etching process, the storage node lower electrode 210 may be prevented from being exposed. Then, the photoresist pattern 223 is removed by a strip process.

Referring to FIG. 7 , an active layer 230, a storage upper electrode 235, and a second connection line CL2 are formed on the second buffer layer 222 in which the source contact hole 225 and the storage contact hole 227 are formed. form

The active layer 230 is formed on the surface of the second buffer layer 222 and extends to fill the source contact hole 225 . The storage upper electrode 235 may be formed to completely fill the storage contact hole 227 and extend to the surface of the second buffer layer 222 . The second connection line CL2 may be formed to extend to an area where a bank hole is to be formed. The second connection wiring line 237 may be formed in a second direction crossing the driving power supply line 207 or the wiring electrode 215 arranged in the first direction of the substrate 200 . In addition, when the second connection line CL2 is formed, the first connection line CL1 (see FIG. 2A) is also formed. Here, the second direction may be a vertical direction of the substrate 200 .

To this end, an active material layer may be formed on the second buffer layer 222 and a patterning process may be performed through a photolithography process using a photo mask and an etching process.

The active layer 230 is preferably formed of a semiconductor material having a band gap larger than 3 eV and having high transmittance in the visible ray region and thus having transparent characteristics. For example, a silicon semiconductor has a band gap of 1.1 Ev, which is similar to or equal to the energy of visible light. Accordingly, a semiconductor material having a small band gap including silicon has an opaque characteristic.

Therefore, the active layer 230 according to an embodiment of the present specification may include at least one of an oxide semiconductor material such as an indium gallium zinc oxide (IGZO)-based or an indium zinc oxide (IZO)-based having a band gap of 3.05 Ev. . In addition, the active layer 230 may be formed of another oxide semiconductor material having a band gap greater than 3 eV known in the art. Also, the storage upper electrode 235 and the second connection wire line CL2 may be formed of the same material as the active layer 230 on the same plane.

Referring to FIG. 8 , a gate electrode 245 and a pad electrode 250 are formed. To this end, a gate insulating layer 240 and gate metal layers 242 and 244 are formed on the substrate 200 on which the active layer 230, the upper storage electrode 235, and the second connection line CL2 are formed. The gate metal layers 242 and 244 may have a structure in which a first gate metal layer 242 and a second gate metal layer 244 are stacked.

In one example, the first gate metal layer 242 and the second gate metal layer 244 may be made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), It may be composed of a single layer or multiple layers made of any one from the group consisting of neodymium (Nd) or copper (Cu) or an alloy thereof, but is not limited thereto.

Next, a gate electrode 245 and a pad electrode 250 are formed by patterning the gate metal layers 242 and 244 and the gate insulating layer 240 through a photolithography process and an etching process using a photo mask. Here, the etching process may proceed in a dry etching method. As the gate electrode 245 and the pad electrode 250 are formed by patterning the same gate metal layers 242 and 244 , they may be made of the same material and formed on the same plane (layer).

Meanwhile, in the process of dry etching to form the gate electrode 245 , conductorization may be formed on the active layer 230 , the upper storage electrode 235 , and the second connection line CL2 . Specifically, in the process of forming the gate electrode 245, the gate insulating film 240 remains in the portion overlapping the gate electrode 245, while the area not covered by the gate electrode 245 is also covered with the gate insulating film 240. Together, the surfaces of the active layer 230, the upper storage electrode 235, and the second connection line CL2 are exposed.

When the active layer 230, the upper storage electrode 235, and the second connection line CL2 are formed of an oxide semiconductor, the conductivity characteristics vary according to the content of oxygen. When the dry etching process is performed, the oxygen content in the oxide semiconductor is reduced so that the oxide semiconductor can be made into a conductor while reducing its resistance. Accordingly, an etching gas applied in the dry etching may contact the exposed active layer 230 , the storage upper electrode 235 , and the second connection wiring line CL2 to be conductive, thereby forming a conductive region.

The conductive region includes a source region SA, a source electrode SE extending from a lower portion of the source region SA to fill the source contact hole 225, a drain region DA, a second connection line CL2, and a storage region. An upper electrode 235 may be included. A channel region CH may be disposed in the active layer 230 below the gate electrode 245 where no conductive region is formed. Here, the source region SA of the active layer 203 extends in the direction of the driving power supply line 207 (see FIG. 2A ) so that the source electrode SE may be directly connected to the driving power supply line 207 .

As the storage upper electrode 235 is conductive, a storage capacitor in which the storage lower electrode 210 and the upper storage electrode 235 overlap with the first buffer layer 220 interposed therebetween is formed. The bottom portion of the storage upper electrode 235 of the storage capacitor overlaps the storage lower electrode 210 with the first buffer layer 220 therebetween, and the side portion of the storage upper electrode 235 contacts the second buffer layer 222. . In this case, the storage upper electrode 235 has a 'T' shape when viewed in cross section.

As described in FIGS. 2A and 2B , the storage capacitor is formed of a double layer of a first buffer layer and a second buffer layer as capacitance increases by at least 6 times by introducing a dielectric into a single layer of the first buffer layer 220 . Light emission of the organic light emitting diode can be maintained relatively longer than that of the storage capacitor. Accordingly, an area occupied by the storage capacitor in the circuit unit may be reduced. Accordingly, the aperture ratio may be increased by increasing the light emitting area by the reduced area of the storage capacitor.

Referring to FIG. 9 , an interlayer insulating layer 255 is formed on the substrate 200 on which the gate electrode 245 and the pad electrode 250 are formed. The interlayer insulating layer 255 is formed to a thickness sufficient to cover all surfaces of the gate electrode 245, the upper storage electrode 235, and the second connection line CL2. Here, the interlayer insulating layer 255 may not be formed in the pad region II′ where the pad electrode 250 is formed. The interlayer insulating layer 255 may be formed of an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx).

Next, a color filter 260 is formed on the interlayer insulating film 255 . To this end, red (R), green (G), and blue (B) pigments are applied on the interlayer insulating film 255, and a mask process is performed to form a color filter 260 corresponding to the light emitting area. When the color filter 260 is made of red (R), green (G), and blue (B), the mask process may require three mask processes.

Referring to FIG. 10 , a planarization layer 270 is formed on the interlayer insulating layer 255 on which the color filter 260 is disposed.

The planarization layer 270 may be formed to have a sufficient thickness to planarize the surface of the substrate 200 while serving to protect underlying devices. The planarization layer 270 may be formed by coating an organic insulating material such as acrylic resin. Subsequently, the planarization layer 270 and the interlayer insulating layer 255 are patterned to form a pixel contact hole 280 exposing a portion of the surface of the drain region DA.

Referring to FIG. 11 , a first electrode 283 is formed on the planarization layer 270 and a bank 285 having a bank hole 290 exposing a portion of the surface of the first electrode 283 is formed.

The first electrode 283 may be electrically connected to the gate electrode 245 through the drain region DA exposed by the pixel contact hole 280 . The first electrode 283 may be formed of a transparent metal oxide such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO). The first electrode 283 may also be referred to as an anode electrode or a pixel electrode. The first electrode 283 may be formed as a pad cover electrode 284 to prevent corrosion of the pad electrode 250 by covering the exposed surface of the pad electrode 250 disposed on the pad region II'. .

A bank 285 having a bank hole 290 is disposed on the planarization layer 280 on which the first electrode 283 is formed. The bank 285 is a boundary region defining the light emitting region 292 of the region where pixels are to be formed, and serves to divide each sub-pixel. In addition, the bank 285 serves as a barrier to prevent light of different colors from adjacent pixels from being mixed and output. The bank 285 may be formed using an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx) or an organic insulating material such as polyimide.

Meanwhile, as the second connection line CL2 is formed of a transparent and conductive semiconductor material, the second connection line CL2 overlaps the light emitting region 292 defined by the bank hole 290. do. Also, as shown in FIG. 2A , the first connection line CL1 may also overlap the light emitting region 292 .

As described above, since the first connection line CL1 or the second connection line CL2 may overlap the light emitting region 292, the area occupied by the light emitting region 292 may be increased, thereby improving the aperture ratio. . For example, the width of the light emitting region 292 may increase by an increased area due to a decrease in the overlapping width of the connection line lines CL1 and CL2 and a decrease in the area of the storage capacitor.

The bank 285 may be formed in an area other than the pad area II′ so as not to cover the pad electrode 250 covered with the pad cover electrode 284 .

Referring to FIG. 12 , the organic light emitting layer 295 and the second electrode 300 are formed on the light emitting region 292 defined by the bank 285 . Accordingly, an organic light emitting diode (OLED) including the first electrode 283 , the organic light emitting layer 295 and the second electrode 300 may be configured. The organic light emitting layer 295 and the second electrode 300 may be formed in the remaining area except for the pad area I-I'.

The organic emission layer 295 is directly connected to the first electrode 283 exposed through the bank hole 290 . In one example, the organic emission layer 295 may be formed to extend to the top surface of the bank 285 along the exposed surface of the first electrode 283 . In one example, the organic light emitting layer 295 is made of an organic material that emits white light, and can display colors by the color filter 260 .

Although not shown in the figure, the organic emission layer 295 may include a stacked structure of a hole transport layer (HTL), an emission layer (EML), and an electron transport layer (ETL). The organic light emitting layer includes a hole transport layer (HTL), a light emitting layer (EML) and an electron transport layer (ETL) together with a hole blocking layer (HBL), a hole injection layer (HIL), an electron blocking layer (EBL) and an electron injection layer (EIL). It may be configured to include more.

The second electrode 300 may be formed to cover the entire exposed surface of the organic light emitting layer 295 . The second electrode 300 may be formed as a common electrode that commonly contacts adjacent pixels on the display area and applies a voltage thereto. The second electrode 300 may also be referred to as a cathode electrode.

In one example, the second electrode 300 may be formed of a transparent metal oxide such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO). Alternatively, the second electrode 300 may be formed of a translucent metal material composed of molybdenum (Mo), tungsten (W), silver (Ag) or aluminum (Al) and an alloy containing at least one of them.

13 is a plan view of a display device according to a third exemplary embodiment of the present specification. As the display device 30 of FIG. 13 has the same configuration as the display device 20 according to the second exemplary embodiment of FIG. 2A except for the shape of the first connection line CL1, the description of the same configuration will be to omit

The first connection wiring line CL1 of the display device 30 according to the third exemplary embodiment of the present specification connects the driving power supply line VDD through the contact hole C to the sub-pixels arranged in the second direction Y. connect with the The first connection line CL1 is formed of the same material as the active layer 230 and is disposed on the same plane as the active layer 230 . For example, the first connection wiring line CL1 may include a semiconductor material having a band gap greater than 3 eV and high transmittance in the visible light region, thus having transparent characteristics.

The first connection wiring line CL1 overlaps the driving power supply line VDD and the buffer layers 220 and 222 in between, and has a width at least equal to or wider than that of the driving power supply line VDD. . Driving is performed by forming the first connection wiring line CL1 to have at least the same width as the driving power supply line VDD while the first connection wiring line CL1 and the driving power supply line VDD overlap each other at the top and bottom. Resistance of the power supply line VDD may be reduced.

The first connection wire CL1 includes a first portion overlapping the driving power supply line VDD disposed in the first direction X of the substrate 200 and a second direction crossing the first direction X. (Y) and a second part disposed. Accordingly, the first connection wire CL1 may have an 'L' shape.

As described above, in the display device according to the exemplary embodiments of the present specification, some of the wiring electrodes may be formed of a transparent material that transmits light in the visible ray region, and the light emitting region and the wiring electrodes may be overlapped.

Accordingly, there is an effect of increasing an aperture ratio by increasing the area of the light emitting region by reducing the area occupied by the circuit part in each sub-pixel.

100, 200: substrate 164, gate electrode
125, 230: active layer SA: source region
DA: drain region 110, 210: storage lower electrode
115, 215: wiring electrode 120, 220: first buffer layer
122, 222: second buffer layer 125a, 235a: storage upper electrode
SP1, SP2, SP3: sub pixels SCAN1, SCAN2: scan line
CL1, CL2: Connection wiring line

Claims (13)

a substrate including a plurality of sub-pixels;
a driving power supply line (VDD) and a reference power supply line (Vref) arranged spaced apart in parallel in a first direction on the substrate;
a light emitting region and a driving circuit element included in each of the sub-pixels; and
A plurality of connection wiring lines respectively connecting the driving power supply line (VDD) and the reference power supply line (Vref) to the sub-pixel,
At least one of the connection wiring lines is positioned to overlap the light emitting region. According to claim 1,
The substrate further includes a scan line arranged in a second direction crossing the first direction in which the driving power supply line (VDD) and the reference power supply line (Vref) are arranged, and dividing the sub-pixels adjacent to each other. display device. According to claim 1,
At least one of the connection wiring lines is positioned to extend into a light emitting region of an adjacent sub-pixel. According to claim 1,
The display device of claim 1 , wherein the connection wiring line is made of a conductive semiconductor material that is transparent by transmitting a light source in a visible ray region while having a band gap greater than 3 eV. According to claim 1,
The display device may further include connecting each of the connection wiring lines to the driving power supply line (VDD) or the reference power supply line (Vref) through a contact hole. According to claim 1,
The connection wiring line has a wider width than the scan line including an opaque metal material. According to claim 1,
The connection wiring line is arranged in a first direction from the second direction of the substrate and has an 'L' shape such that at least a portion overlaps with the driving power supply line (VDD). According to claim 1,
The driving circuit element,
Including a thin film transistor connected to the organic light emitting element,
The thin film transistor may include the power supply line positioned on the substrate;
a buffer layer positioned on the light blocking layer and the power supply line;
an active layer including a channel region positioned on the buffer layer, a drain region, a source region, and a source electrode connected to the power supply line through the buffer layer from below the source region while sandwiching the channel region; and
A display device including a gate electrode positioned on the active layer. According to claim 8,
The substrate further includes a light blocking layer, and the light blocking layer is made of the same material on the same plane as the power supply line and the reference power supply line. According to claim 8,
The active layer is formed of the same material on the same plane as the connection wiring line. According to claim 1,
The driving circuit element,
a storage capacitor connected to the thin film transistor;
The storage capacitor may include a storage lower electrode positioned on the same plane as the light blocking layer;
a first buffer layer on the storage lower electrode;
a second buffer layer disposed on the storage lower electrode and having a storage contact hole exposing a portion of a surface of the first buffer layer; and
A display device including a storage upper electrode filling the storage contact hole. According to claim 11,
A bottom portion of the storage upper electrode overlaps the storage lower electrode with the first buffer layer interposed therebetween, and a side portion of the storage upper electrode contacts the second buffer layer. According to claim 8 or 11,
The storage upper electrode is made of the same material as the active layer, the first buffer layer is made of a material having a first permittivity of a first thickness, and the second buffer layer has a second thickness thicker than that of the first buffer layer. A display device having a second permittivity lower than the first permittivity.

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