KR20230078674A - Optimized contact structure - Google Patents

Abstract

An optimized contact structure and manufacturing technology thereof are disclosed. At least one aspect includes a semiconductor die. A semiconductor die includes a substrate and contacts disposed within the substrate. The contact includes a first portion having a first vertical cross-section with a first cross-sectional area. The first vertical section has a first width and a first height. The contact also includes a second portion having a second vertical cross-section having a second cross-sectional area smaller than the first cross-sectional area. The second vertical section has a lower portion having the first width and a second height less than the first height, and a third portion disposed over the lower portion and having a second width less than the first width and a third height less than the first height. It includes an upper part having a height.

Description

Optimized contact structure

CROSS REFERENCES TO RELATED APPLICATIONS

This patent application claims the benefit of US Non-Application Serial No. 17/061,709, entitled "OPTIMIZED CONTACT STRUCTURE", filed on October 2, 2020, assigned to the assignee of the present application and incorporated herein by reference in its entirety. integrated into the

field of initiation

This disclosure relates generally to wafer fabrication methods, and more specifically, and non-exclusively, to optimized contact structures and fabrication techniques thereof.

background

1A illustrates part of a conventional complementary metal oxide semiconductor (CMOS) structure with contacts and a gate, such as, for example, a simple inverter with n-type (NMOS) and p-type (PMOS) transistors. In the structure shown in FIG. 1A, the contacts and gates are vertical plate structures of electrically conductive material that are parallel and proximate to each other. This creates parasitic capacitance between each contact and the gate. Parasitic capacitance is proportional to the areas of the contact and gate parallel to each other and inversely proportional to the distance between the surfaces of the contact and gate facing each other, labeled in FIG. 1A as D1. Since the operation speed of a CMOS device is inversely proportional to this parasitic capacitance, it is desirable to reduce the parasitic capacitance between a contact and a gate (hereinafter referred to as "contact-gate capacitance"). Reducing this capacitance will increase the operating speed of the CMOS device, and thus the performance of the CMOS device.

FIG. 1B illustrates one conventional approach taken to reduce contact-gate capacitance in a CMOS device; in the CMOS structure illustrated in FIG. 1B, a portion of the contact is removed to reduce the area of the contact parallel to the gate structure. , which reduces contact-gate parasitic capacitance. The height of the remaining contact structure is indicated by H in FIG. 1B. However, this approach has drawbacks: removing part of the contact structure increases the internal resistance of the contact because the cross-sectional area is much smaller, which reduces performance, and removing too much of the contact structure makes it electrically open. conditions may arise. In order to avoid electrical open potential and to maintain an acceptably low internal resistance, the height H is set to a conservative value. On the other hand, if the contact structure is not sufficiently removed, for example if the height H is too conservative, the reduction in parasitic capacitance will be negligible.

Accordingly, what is needed are systems, apparatus and methods that overcome the deficiencies of prior approaches to reducing contact-gate capacitance, including the methods, system and apparatus provided herein.

outline

The following presents a brief overview of one or more aspects and/or examples in connection with the apparatus and methods disclosed herein. Accordingly, the following summary is not to be considered an extensive overview of all contemplated aspects and/or examples, nor does the following summary identify key or critical elements with respect to all contemplated aspects and/or examples, or It should not be construed as outlining the scope of any particular aspect and/or example. Accordingly, the following summary is presented for the sole purpose of presenting specific concepts relating to one or more aspects and/or examples of the apparatus and methods disclosed herein in a simplified form in order to precede the more detailed description presented below. have

According to various aspects disclosed herein, at least one aspect includes a semiconductor die. A semiconductor die includes a substrate and contacts disposed within the substrate. The contact includes a first portion having a first vertical cross-section with a first cross-sectional area. The first vertical section has a first width and a first height. The contact also includes a second portion having a second vertical cross-section having a second cross-sectional area smaller than the first cross-sectional area. The second vertical section has a lower portion having the first width and a second height smaller than the first height, and a second width disposed over the lower portion and having a second width smaller than the first width and a second height smaller than the first height. and an upper portion having a small third height.

According to various aspects disclosed herein, at least one aspect includes a method for manufacturing a semiconductor die. The method includes providing a substrate and creating contacts at least partially embedded in the substrate. The contact includes a first portion having a first vertical cross-section with a first cross-sectional area. The first vertical section has a first width and a first height. The contact also includes a second portion having a second vertical cross-section having a second cross-sectional area smaller than the first cross-sectional area. The second vertical section has a lower portion having the first width and a second height less than the first height, and a second width disposed over the lower portion and having a second width less than the first width and a third height less than the first height. It includes an upper part having

According to various aspects disclosed herein, at least one aspect includes a method for manufacturing a contact. The method includes creating a contact hole in a substrate having a first width, a first length, and a first depth. The method includes depositing an electrically conductive material forming a first portion of the contact into at least a portion of the contact. The method includes etching a first portion of electrically conductive material to create a recess having a first width, a second length less than the first length, and a second depth less than the first depth. The method includes depositing a conformal spacing material having a thickness T in the recess. The method includes anisotropically etching the conformal spacing material to depth = T to expose the electrically conductive material at the bottom of the recess. The method includes selectively depositing additional electrically conductive material over the exposed electrically conductive material to a third depth less than the second depth, a second portion of the contact having a second width and a third length less than the second length. forming a lower portion of the second portion of the contact having an upper portion, a first width, and a first height. The method includes removing conformal spacing material to create a gap between outer surfaces of the second portion of the contact and inner surfaces of the recess.

Other features and advantages associated with the apparatus and methods disclosed herein will be apparent to those skilled in the art based on the accompanying drawings and detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS
A more complete understanding of aspects of the present disclosure and many of its attendant advantages, as may be better understood by reference to the following detailed description when considered in conjunction with the accompanying drawings, which are presented for purposes of illustration only and not limitation of the present disclosure. will be easily obtained. The drawings are not to scale.
1A shows a portion of a conventional complementary metal oxide semiconductor (CMOS) structure.
Figure 1b shows a conventional approach for reducing contact-gate parasitic capacitance.
2A-2C show views of portions of an optimized contact in accordance with some aspects.
3A-3C show views of portions of an optimized contact in accordance with some aspects.
4-6 show portions of example processes for fabricating an optimized contact in accordance with some aspects.
7 and 8 illustrate methods for fabricating an optimized contact according to some aspects.
9 illustrates an example mobile device in accordance with one or more aspects of the present disclosure.
10 illustrates various electronic devices that may be integrated with any of the aforementioned integrated devices or semiconductor dies in accordance with one or more aspects of the present disclosure.
In accordance with general practice, features illustrated by the drawings may not be drawn to scale. Accordingly, the dimensions of features shown may be arbitrarily expanded or reduced for clarity. In accordance with common practice, some of the drawings are simplified for clarity. Accordingly, the drawings may not depict all components of a particular apparatus or method. Additionally, like reference numbers designate like features throughout the specification and drawings.

details

Aspects of the present disclosure are illustrated in the following description and related drawings directed to specific embodiments. Alternative aspects or embodiments may be devised without departing from the scope of the teachings herein. Additionally, well-known elements of the example embodiments herein may not be described in detail or may be omitted so as not to obscure the relevant details of the teachings of this disclosure.

In certain described example implementations, examples are identified in which some of the various component structures and operations are taken from known prior art and then arranged in accordance with one or more example embodiments. In such instances, some internal details of known conventional component structures and/or operations may be omitted to help avoid potential obfuscation of concepts illustrated in example embodiments disclosed herein.

The terminology used herein is only used to describe specific embodiments and is not intended to limit the present invention. As used herein, the singular forms "a," "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. “Comprising,” “comprises,” and/or “comprising,” when used herein, specifies the presence of described features, integers, steps, operations, elements, and/or components. However, it will be further understood that this does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

To fully illustrate aspects of the design of this disclosure, fabrication methods are presented. Other fabrication methods are possible, and the fabrication methods discussed are presented only to aid in the understanding of the concepts disclosed herein.

2A shows a perspective view of a portion of a semiconductor die 200 having optimized contacts in accordance with some aspects. In FIG. 2A , semiconductor die 200 includes a substrate 202 partially embedded with contacts 204A, contacts 204B, and contacts 204C, which may be collectively referred to as contacts 204. there is. Contact 204 may be made of tungsten, cobalt, or other electrically conductive material. In addition, a gate 206 is partially buried in the substrate 202 . Contact 204 and gate 206 are separated by some distance, where the minimum distance between contact 204 and gate 206 is distance S1. Each contact 204 includes a first portion having a first vertical cross-section with a first area and a second portion having a second vertical cross-section with a second area. The first part has a height of H1 and a width of W1. A second portion having a second vertical section has a height of H2 and a width of W1 and a lower portion at a distance S1 from the gate 206, and a height of H3 and a width of W2, where W2 is less than W1, and a gate ( 206) at a distance S2, where S2 is greater than S1. Electrical contact 208 connects contact 204A to a higher level conductor, and an insulating layer 210 is present between contact 204A and substrate 202 . In some aspects, H1 is approximately 50 nm, H2 is approximately 10 nm, and H3 may range from 10 nm to 30 nm.

2B shows a top view (i) and three cross-sectional views (ii), (iii) and (iv) of an optimized contact 204A in accordance with some aspects. In FIG. 2B , contact 204A has a first cross-section AA having a first cross-sectional area and a second cross-section BB having a second cross-sectional area. In cross sections (ii)-(iv), contacts 204A are flanked on each side by spacer material 212.

In section AA(ii), the total cross-sectional area of contact 204A has width W1 and extends to electrical contact 208 to the surface of substrate 202 . In FIG. 2B, contact 204A has a second cross section BB having a second cross sectional area.

In section BB(iii), the lower portion has a width W1 and a height H2, and the upper portion has a width W2 and a height H3 above the top of the lower portion, where W2 is less than W1. Since W2 is smaller than W1, the upper portion of cross-section BB is a greater distance S3 from gate 206 than a conventional contact. For convenience only, and without imposing any limitation on the claimed subject matter, the upper portion may be referred to herein as a vertical fin. In some aspects, such as those shown in FIGS. 2A , 2B and 2C , the vertical fin has a substantially rectangular cross-sectional shape.

Sections CC and DD(iv) look similar to each other. As described in more detail below, these cross sections do not have an upper portion with width W2 and height H3 due to an artifact of the wafer process that creates cross section BB.

Since capacitance is inversely proportional to the distance between the conductive plates, the parasitic capacitance between contact 204A and gate 206 is reduced compared to the conventional structures of FIGS. It has a cross-sectional area large enough to minimize the increase in internal resistance.

2C shows a top view (i) and three cross-sectional views (ii), (iii) and (iv) of an optimized contact 204A in accordance with some aspects. The contact 204A of FIG. 2C differs from the contact 204A of FIG. 2B in that in FIG. 2B the upper portion of the contact (ie, the vertical pin) is surrounded by and in contact with SiO ₂ or another insulating material; In FIG. 2C, the vertical fin is surrounded by air gap 214, which has a higher dielectric coefficient than SiO ₂ and thus reduces the parasitic contact-gate capacitance even more compared to contact 204A in FIG. 2B.

3A shows a perspective view of a portion of a semiconductor die 300 having optimized contacts in accordance with some aspects. In FIG. 3A , semiconductor die 300 includes a substrate 302 partially embedded with contacts 304A, contacts 304B, and contacts 304C, which may be collectively referred to as contacts 304. there is. In addition, a gate 306 is partially buried in the substrate 302 . Each contact 304 includes a first portion having a first vertical cross-section with a first area and a second portion having a second vertical cross-section with a second area. The minimum distance between contact 304 and gate 306 is distance S1. Each contact 304 includes a first portion having a first vertical cross-section with a first area and a second portion having a second vertical cross-section with a second area. A second portion having a second vertical cross-section has a lower portion having a height of H2 and a width of W1 and being a distance S1 from gate 206, and a gate having a height of H3 and a maximum width of W2, where W2 is less than W1. 206, the average distance S2, where S2 is greater than S1. Electrical contact 308 connects contact 304A to higher level conductors, and an insulating layer 310 is present between contact 304A and substrate 302 . In some aspects as shown in FIGS. 3A , 3B and 3C , the upper portion of the second portion of the contact has a substantially triangular cross-sectional shape.

3B shows a top view (i) and three cross-sectional views AA (ii), BB (iii) and CC,DD (iv) of a contact 304A in accordance with some aspects. In FIG. 3B , contact 304A has a first cross section AA having a first cross sectional area. In cross-sections (ii)-(iv), contacts 304A are flanked on each side by spacer material 312.

In section AA(ii), the total cross-sectional area of contact 302A has width W1 and extends to electrical contact 308 to the surface of substrate 302. In FIG. 3B , contact 304A has a second cross section BB having a second cross sectional area.

In section BB(iii), the lower portion has a width W1 and a height H2, and the upper portion has a substantially triangular cross-sectional shape, the triangle having a base of width W2 and a height above the top of the lower portion. (H3), where W2 is less than W1. Because W2 is smaller than W1, and because the upper portion is substantially triangular in cross section, the upper portion of cross-section BB has a greater average distance S4 from gate 306 than a conventional contact.

Sections CC and DD(iv) look similar to each other. As described in more detail below, these cross sections do not have an upper portion with width W2 and height H3 due to an artifact of the wafer process that creates cross section BB.

Because capacitance is inversely proportional to the distance between the conductive plates, the parasitic capacitance between contact 304A and gate 306 is reduced compared to the conventional structures of FIGS. 1A and 1B, and for the same W1 and H2 values, the contact It is reduced compared to (202A). However, since the cross-sectional area of cross-section BB for contact 304A is smaller than the cross-sectional area of cross-section BB for contact 204A, the internal resistance of contact 304A is less than that of contact 204A for the same value of W1 and H2. ) may be slightly higher than the internal resistance of

3C shows a top view (i) and three cross-sectional views AA (ii), BB (iii) and CC,DD (iv) of a contact 304A in accordance with some aspects. Contact 304A of FIG. 3C differs from contact 304A of FIG. 3B in that the upper portion of the contact in FIG. 3B is surrounded by and in contact with SiO ₂ or another insulating material, but the upper portion of the contact in FIG. 3C The portion is surrounded by air gap 314, which has a higher dielectric constant than SiO ₂ and thus reduces the parasitic contact-gate capacitance even more compared to contact 302A of FIG. 3B.

4 shows portions of an exemplary process for fabricating an optimized contact in accordance with some aspects. FIG. 4 shows what would be the equivalent of a cross section BB of an optimized contact, such as any of contacts 204 of FIG. 2 or any of contacts 304 of FIG. 3 . In FIG. 4 , (i) is a contact hole made of tungsten (elemental abbreviation “W”) via, for example, chemical vapor deposition (CVD) followed by chemical mechanical planarization (CMP), surrounded by an insulating layer 404 . A substrate comprising a buried contact 402 that is filled and has a width W1, a depth D1 (which may also be referred to as a height H1), and a length L1 (not visible in this cross-sectional view). 400 shows the process after steps to create. In FIG. 4, (ii) shows the results of an etching step that protects a first portion of the tungsten from etching but includes vertically etching a second portion of the tungsten, which removes a portion of the tungsten and forms a recess of depth D2. Leaving a portion, the remaining tungsten has a width W1 and a height H2. In FIG. 4 , (iii) shows the results of the deposition of the conformal material to create the sacrificial spacer 406 having a thickness T. In Fig. 4, (iv) shows the results of the anisotropic etching of the sacrificial spacer 406, where the contact 402 is exposed at the bottom portion of the concave portion. In FIG. 4, (v) shows the results of an optional tungsten deposition step that at least partially fills the recess created in (ii) and creates an upper portion of contact 402 having a second width W2 less than W1. In FIG. 4 , (vi) shows the results of selective etching to remove the sacrificial spacer 406 . The gap thus created in FIG. 4 has a width of S3. The width of the lower portion of contact 402 will have a width of W1 and a height of H2, and the upper portion of contact 402 will have a width of W2 and a height of H3. Since the second width W2 is a function of the first width W1 and the thickness of the sacrificial layer T, W2 = W1 - 2*T. Although not shown in the cross-sectional view of FIG. 4, the upper portion of contact 402 will also have a length L2 = L1 - 2*T. The result displayed in FIG. 4(vi) may be further processed as shown in FIG. 5 or FIG. 6 .

5 shows portions of an exemplary process for fabricating an optimized contact in accordance with some aspects. The results shown in FIG. 5(i), FIG. 4(vi) are conformal filler material 500 such as SiO ₂ that fills the remainder of the recess and completely surrounds the upper portion of contact 402 . (eg reflow) deposition follows. Alternatively, in FIG. 5(ii), the results shown in FIG. 4(vi) are non-conformal (eg, CVD) filler material 502, which again may be SiO ₂ ) deposition follows, which does not completely fill the concavity above the contact 402 but instead leaves at least some of the concavity unfilled, which is, for example, air surrounding the upper portion of the contact 402. Leave a gap 504.

6 shows portions of an exemplary process for fabricating an optimized contact in accordance with some aspects. In FIG. 6 (i), the results shown in FIG. 4 (vi) were subjected to an argon sputtering step. Argon ions tend to trim the sharpest edges fastest, resulting in a substantially rectangular cross-section of the upper portion of contact 402 being etched into a substantially triangular cross-section, as shown in FIG. 6(i). In FIG. 6(ii), the result shown in FIG. 6(i) is followed by a conformal deposition of filler material 500 that fills the remainder of the recess and completely surrounds the upper portion of the contact 402. . Alternatively, in FIG. 6(iii), the result shown in FIG. 6(i) is followed by a non-conformal deposition of filler material 502, which completely fills the recess over the contact 402. instead, leaving at least a portion of the recess unfilled, leaving, for example, an air gap 504 . This filler material 502 may be a non-conformal insulating material such as SiO ₂ .

The optimized contact thus created may be a portion of a semiconductor die that also includes a gate structure disposed within the substrate, at least a portion of the gate structure being substantially planar, substantially parallel to the contact, and having a bottom portion of a second vertical section of the contact. and separated from the upper portion of the second vertical section of the contact by a second distance greater than the first distance.

7 is a flow diagram illustrating a partial method 700 for manufacturing a semiconductor die, in accordance with some examples of the present disclosure. As shown in FIG. 7 , the partial method 700 may begin at block 702 with providing a substrate. The partial method 700 may continue at block 704 with creating a contact at least partially buried in the substrate. The contact includes a first portion having a first vertical cross-section with a first cross-sectional area. The contact also includes a second portion having a second vertical cross-section having a second cross-sectional area smaller than the first cross-sectional area. The first vertical section has a first width W1 and a first height H1. The second vertical section includes a first portion having a width W1 and a second height H2, and also having a second width W2 and a third height H3 disposed above the first portion and smaller than W1. Including the second part.

In some aspects, the upper portion of the second vertical cross section is substantially rectangular. In some aspects, an upper portion of the second vertical section is at least partially surrounded by an insulating material. In some aspects, the insulating material includes SiO ₂ . In some aspects, the insulating material includes air.

In some aspects, the upper portion of the second vertical cross section is substantially triangular. In some aspects, an upper portion of the second vertical section is at least partially surrounded by an insulating material. In some aspects, the insulating material includes SiO ₂ . In some aspects, the insulating material includes air.

In some aspects, the electrically conductive material includes tungsten. In some aspects, the electrically conductive material includes cobalt.

In some aspects, the method further comprises creating a gate structure disposed within the substrate, at least a portion of the gate structure being substantially planar, substantially parallel to the contact, and extending from a lower portion of the second vertical section of the contact. separated by a first distance and separated from the upper portion of the second vertical section of the contact by a second distance greater than the first distance.

The optimized contacts described herein have a number of technical advantages over the prior art. For example, because the upper portion of the second portion of the contact is narrower than the lower portion of the second portion of the contact, the upper portion has less parasitic contact-to-gate parasitic capacitance than conventional contacts. Also, the presence of the upper part allows for a reduction in the height of the lower part, since the combined cross-sectional area of the two parts is sufficient to avoid an increase in the internal resistance of the contact. Thus, while for conventional contact designs a decrease in parasitic capacitance results in an increase in internal resistance and vice versa (i.e., these are mutually exclusive performance benefits), the optimized contacts described herein A reduced parasitic capacitance without an increase can be achieved. That is, unlike conventional contacts, the optimized contacts disclosed herein exhibit improved alternating current (AC) performance without degradation of direct current (DC) performance.

8 is a flow diagram illustrating a partial method 800 for fabricating a contact in a semiconductor die, in accordance with some examples of the present disclosure. As shown in FIG. 8 , partial method 800 may begin at block 802 by creating a contact hole in a substrate having a first width, a first length, and a first depth. In some aspects, the contact hole may be created by an isotropic or anisotropic etch process. Partial method 800 may continue at block 804 with depositing an electrically conductive material within the contact hole to form a contact having a first width and a first length. In some aspects, the electrically conductive material may include a metal. Examples of electrically conductive materials include, but are not limited to, tungsten and cobalt. In some aspects, a conformal insulating material may be deposited in the contact hole prior to depositing the electrically conductive material.

Partial method 800 may continue at block 806 with protecting the first portion of the contact from etching. In some aspects, the first portion of the contact is protected from etching by a resist layer or an insulating layer. The partial method 800 includes creating a recess having a first width, a second length less than the first length, and a second depth less than the first depth such that the second portion of the contact has a first width and a first height. Block 808 may continue to vertically etch a second portion of the contact for the purpose. In some aspects, the vertical etch process is an anisotropic etch process.

Partial method 800 may continue at block 810 by depositing a conformal spacing material having a thickness T in the recess. The partial method 812 may continue at block 804 with anisotropically etching the conformal spacing material to a depth = T to expose at least a portion of the second portion of the contact. The partial method 800 continues at block 814 by selectively depositing additional electrically conductive material on the second portion of the contact to a third depth less than the second depth, such that an upper portion of the second portion of the contact is formed. It has a second width and a third length smaller than the second length, and a lower portion of the second portion of the contact has a first width and a first height. The partial method 800 may continue at block 816 with removing the conformal spacing material to create a gap between the outer surfaces of the upper portion of the second portion of the contact and the inner surfaces of the recess.

In some aspects, the resulting gap will have a width of approximately T. In some aspects, the second width = first width - 2*T and the third length = second length - 2*T. In some aspects, the upper portion of the second portion of the contact has a substantially rectangular cross-sectional shape.

In some aspects, partial method 800 includes depositing an insulating material into the recess to at least partially fill a gap between the outer surfaces of the upper portion of the second portion of the contact and the inner surfaces of the recess. contains more In some aspects, the insulating material is a conformal material that completely fills the gap between the outer surfaces of the upper portion of the second portion of the contact and the inner surfaces of the recess. In some aspects, the insulating material is a non-conformal insulating material that fills an upper portion of the recess but leaves at least a portion of the gap between the outer surfaces of the upper portion of the second portion of the contact and the inner surfaces of the recess unfilled. It is a non-conformal insulating material.

In some aspects, the partial method 800 further includes creating a gate structure at least partially buried in the substrate, at least a portion of the gate structure being substantially parallel to the contact, and a lower portion of the second portion of the contact. and from the upper portion of the second portion of the contact by a second distance greater than the first distance.

In some aspects, partial method 800 further includes etching an upper portion of the second portion of the contact to reduce a cross-sectional area of the contact. In some aspects, the upper portion of the second portion of the contact has a substantially triangular cross-sectional shape.

In some aspects, partial method 800 includes depositing an insulating material into the recess to at least partially fill a gap between the outer surfaces of the upper portion of the second portion of the contact and the inner surfaces of the recess. contains more In some aspects, the insulating material is a conformal material that completely fills the gap between the outer surfaces of the upper portion of the second portion of the contact and the inner surfaces of the recess. In some aspects, the insulating material is a non-conformal insulating material that fills an upper portion of the recess but leaves at least a portion of the gap between the outer surfaces of the upper portion of the second portion of the contact and the inner surfaces of the recess unfilled. It is a material.

In some aspects, the partial method 800 further includes creating a gate structure at least partially buried in the substrate, at least a portion of the gate structure being substantially parallel to the contact, and a lower portion of the second portion of the contact. and from the upper portion of the second portion of the contact by a second distance greater than the first distance.

9 illustrates an exemplary mobile device in accordance with some embodiments of the present disclosure. Referring now to FIG. 9 , a block diagram of a mobile device constructed in accordance with example aspects is shown and generally designated mobile device 900 . According to some aspects, mobile device 900 may be configured as a wireless communication device. As shown, mobile device 900 includes a processor 902 . Processor 902 includes instruction pipeline 904, buffer processing unit (BPU) 906, branch instruction queue (BIQ) 908, and throttler 910, as is well known in the art. is shown to Other well-known details of these blocks (eg, counters, entries, confidence fields, weighted sum, comparator, etc.) have been omitted from this view of processor 902 for clarity. Processor 902 may be communicatively coupled to memory 912 over a link, which may be a die-to-die or chip-to-chip link. The mobile device 900 also includes a display 914 and a display controller 916 , the display controller 916 being coupled to the processor 902 and the display 914 .

In some aspects, FIG. 9 shows a coder/decoder (CODEC) 918 (eg, an audio and/or voice CODEC) coupled to the processor 902; speaker 920 and microphone 922 coupled to CODEC 918; and radio controller circuits 924 coupled to a radio antenna 926 and processor 902 (modem, radio frequency (RF), which may be implemented using one or more flip-chip devices, as disclosed herein) may include circuitry, filters, etc.).

In certain aspects, when one or more of the blocks noted above are present, processor 902, display controller 916, memory 912, CODEC 918, and radio controller circuits 924 may It can be included in a system-in-package or system-on-chip device, including but not limited to semiconductor die 200 or semiconductor die 300, which may be implemented in whole or in part using the disclosed techniques. Input device 928 (eg, physical or virtual keyboard), power supply 930 (eg, battery), display 914, input device 928, speaker 920, microphone 922, wireless antenna 926 ), and power supply 930 may be external to the system-on-chip device, or may be coupled to a component of the system-on-chip device, such as an interface or controller.

9 illustrates a mobile device, processor 902 and memory 912 can also be used in a set top box, music player, video player, entertainment unit, navigation device, personal digital assistant (PDA), fixed location data unit. , it may be incorporated into a computer, laptop, tablet, communication device, mobile phone, or other similar devices.

10 illustrates various electronic devices that may be integrated with any of the aforementioned integrated device or semiconductor device 1000, which may be semiconductor die 200 or semiconductor die 300, according to various examples of the present disclosure. For example, mobile phone device 1002, laptop computer device 1004, and fixed location terminal device 1006 may each be generally considered user equipment (UE), e.g., as described herein. Similarly, the semiconductor die 200 or the semiconductor die 300 may be included. Semiconductor die 200 or semiconductor die 300 may include, for example, the integrated circuits, dies, integrated devices, integrated device packages, integrated circuit devices, device packages, integrated circuit (IC) described herein. ) packages, package-on-package devices. The mobile phone device 1002, laptop computer device 1004, and fixed position terminal device 1006 shown in FIG. 10 are exemplary only. Other electronic devices also include mobile devices, handheld personal communication systems (PCS) units, portable data units such as personal digital assistants, global positioning system (GPS) enabled devices, navigation devices, set top Boxes, music players, video players, entertainment units, fixed position data units, e.g. metrology reading equipment, communication devices, smartphones, tablet computers, computers, wearable devices, servers, routers devices, including electronic devices implemented in automotive vehicles (eg, autonomous vehicles), an Internet of Things (IoT) device or any other device that stores or retrieves data or computer instructions, or any combination thereof. may feature a device including, but not limited to, a group of (eg, electronic devices).

The disclosed packages, devices and functions described above may be designed and configured as computer files (eg, Raster Transfer Language (RTL), Graphics Database System Information Interchange (GDSII), Gerber, etc.) stored on a computer readable medium. there is. Some or all such files may be provided to manufacturing handlers that manufacture devices based on such files. The resulting products may include semiconductor wafers that are then cut into semiconductor dies and packaged into flip-chips or other packages. Packages may then be used with the devices described herein.

It will be appreciated that the various aspects disclosed herein may be described as functional equivalents to structures, materials and/or devices described and/or recognized by those skilled in the art. For example, in one aspect, an apparatus may include means for performing the various functions discussed above. It will be appreciated that the foregoing aspects are provided as examples only, and that the various claimed aspects are not limited to the specific references and/or examples cited as examples.

One or more of the components, processes, features and/or functions illustrated in FIGS. 2A-10 may be rearranged and/or combined into a single component, process, feature or function, or several components, processes. , or may be incorporated into functions. Additional elements, components, processes, and/or functions may also be added without departing from the present disclosure. Also, it should be noted that FIGS. 2A-10 and corresponding description in this disclosure are not limited to dies and/or ICs. In some implementations, FIGS. 2A-10 and their corresponding descriptions may be used to manufacture, create, provide, and/or produce integrated devices. In some implementations, a device may include a die, integrated device, die package, integrated circuit (IC), device package, integrated circuit (IC) package, wafer, semiconductor device, package on package (PoP) device, and/or interposer. may also include

As used herein, the terms "user equipment" (or "UE"), "user device", "user terminal", "client device", "communication device", "wireless device", "wireless communication device" ", "handheld device", "mobile device", "mobile terminal", "mobile station", "handset", "access terminal", "subscriber device", "subscriber terminal", "subscriber station", "terminal" , and variations thereof may interchangeably refer to any suitable mobile or stationary device capable of receiving wireless communication and/or navigation signals. These terms include music players, video players, entertainment units, navigation devices, communication devices, smartphones, personal digital assistants, fixed location terminals, tablet computers, computers, wearable devices, laptop computers, servers, automotive devices in automobile vehicles, and and/or other types of portable electronic devices that are typically carried by a person and/or have communication capabilities (eg, wireless, cellular, infrared, short range wireless, etc.). These terms also refer to radio, e.g., by short-range radio, infrared, wired connection, or other connection, regardless of whether satellite signal reception, assistance data reception, and/or position-related processing occurs on that device or on another device. It is intended to include devices in communication with other devices capable of receiving communication and/or navigation signals. Additionally, these terms refer to a radio and wireless network that can communicate with a core network through a radio access network (RAN) and through which UEs can communicate with external networks such as the Internet and with other UEs. It is intended to include all devices, including wired communication devices. Of course, other mechanisms for accessing the core network and/or the Internet may also be eg, wired access networks, wireless local area networks (WLANs) (eg, based on Institute of Electrical and Electronic Engineers (IEEE) standard 802.11, etc.), etc. It is possible for UEs through UEs include, but are not limited to, printed circuit (PC) cards, compact flash devices, external or internal modems, wireless or landline phones, smartphones, tablets, tracking devices, asset tags, etc. It can be implemented by any of a number of device types. The communication link through which UEs can send signals to the RAN is called an uplink channel (eg, reverse traffic channel, reverse control channel, access channel, etc.). The communication link over which the RAN can send signals to UEs is called a downlink or forward link channel (eg, paging channel, control channel, broadcast channel, forward traffic channel, etc.). As used herein, the term traffic channel (TCH) can refer to either an uplink/reverse or downlink/forward traffic channel.

Wireless communication between electronic devices includes code division multiple access (CDMA), wide-band CDMA (W-CDMA), time division multiple access (TDMA), frequency division multiple access (FDMA), and orthogonal frequency division multiplexing (OFDM). , GSM (global system for mobile communications), 3GPP (3rd generation partnership project) LTE (long term evolution), 5th generation (5G) NR (new radio), Bluetooth (BT), BLE (Bluetooth low energy), IEEE 802.11 ( WiFi), and IEEE 802.15.4 (Zigbee/Thread) or other protocols that may be used in wireless communication networks or data communication networks. Bluetooth Low Energy (also known as Bluetooth LE, BLE, and Bluetooth Smart) is a wireless personal area network technology designed and marketed by the Bluetooth Special Interest Group that is intended to provide significantly reduced power consumption and cost while maintaining similar communication ranges. am. BLE was merged into the main Bluetooth standard in 2010 with the adoption of the Bluetooth Core Specification version 4.0, updated to Bluetooth 5.

The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any details described herein as "exemplary" should not be construed as advantageous over other examples. Likewise, the term "examples" does not mean that all examples include the discussed feature, advantage, or mode of operation. Moreover, certain features and/or structures may be combined with one or more other features and/or structures. Additionally, at least a portion of an apparatus described herein may be configured to perform at least a portion of a method described herein.

The terms “connected,” “coupled,” or any variation thereof, means any direct or indirect connection or coupling between elements, unless the connection is explicitly disclosed as being directly connected together through intermediate elements. It should be noted that “connected” or “coupled” can encompass the presence of an intermediate element between two elements.

Any reference herein to elements using designations such as "first", "second", etc., does not limit the amount and/or order of those elements. Instead, these designations are used as a convenient way to distinguish between two or more elements and/or instances of an element. Also, unless stated otherwise, a set of elements may include one or more elements.

Those of skill in the art will appreciate that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

Described or exemplified in this application may be any component, action, feature, benefit, advantage, or equivalent, regardless of whether or not the component, action, feature, benefit, advantage, or equivalent is recited in the claims. It is not intended to divert equivalents to the public.

Those of skill will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithmic acts described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and acts have been described above generally in terms of their functionality. Whether such functionality is implemented in hardware or software depends on the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

Although some aspects have been described in relation to a device, it will be understood that these aspects also constitute a description of a corresponding method, and thus a block or component of a device should also be understood as a corresponding method action or feature of a method action. Similarly, aspects described in connection with or as method actions also constitute a description of a corresponding block or a detail or characteristic of a corresponding device. Some or all of the method actions may be performed by (or using a hardware device) a hardware device, such as, for example, a microprocessor, programmable computer, or electronic circuitry. In some examples, some or a plurality of method actions may be performed by such an apparatus.

In the detailed description above it can be seen that different features have been grouped together in the examples. This method of disclosure is not to be construed as an intention that the claimed examples have more features than are expressly recited in an individual claim. Rather, the disclosure may include less than all features of an individual disclosed example. Accordingly, the following claims are to be regarded as being incorporated into the description, wherein each claim may stand on its own as a separate example. Each claim may stand out on its own as a separate example, but even if a dependent claim may refer in the claims to a particular combination with one or more claims, other examples may also differ from the subject matter of any other dependent claim. It should be noted that may encompass or include combinations of the above dependent claims or any combination of features with other dependent and independent claims. Unless expressly stated that a particular combination is not intended, such combinations are suggested herein. Moreover, it is also intended that features of a claim may be included in any other independent claim, even if the claim is not directly dependent thereon.

Moreover, it should be noted that the methods, systems, and apparatus disclosed in this description or claims may be implemented by a device that includes means for performing respective actions and/or functions of the disclosed methods.

Moreover, in some examples, an individual action may be subdivided into or include a plurality of sub-actions. Such sub-actions may be included in the initiation of an individual action, and may be part of the initiation of an individual action.

While the foregoing disclosure represents illustrative examples of this disclosure, it should be noted that various changes and modifications may be made without departing from the scope of the disclosure as defined by the appended claims. The functions and/or actions of the method claims in accordance with examples of the present disclosure described herein need not be performed in any particular order. Additionally, well-known elements may not be described in detail or omitted so as not to obscure the relevant details of the aspects and examples disclosed herein. Moreover, although elements of this disclosure may be described or claimed in the singular, the plural is contemplated unless limitations to the singular are expressly recited.

Claims (39)

As a semiconductor die,
Board; and
a contact disposed within the substrate;
The contact is:
a first portion having a first vertical cross-section with a first cross-sectional area, the first vertical cross-section having a first width and a first height; and
a second portion having a second vertical cross-section having a second cross-sectional area smaller than the first cross-sectional area;
including,
The second vertical section is:
a lower portion having the first width and a second height smaller than the first height; and
an upper portion disposed over the lower portion, having a second width less than the first width, and having a third height less than the first height;
Including, a semiconductor die. According to claim 1,
wherein the upper portion of the second vertical cross section is substantially rectangular. According to claim 2,
wherein the upper portion of the second vertical section is at least partially surrounded by an insulating material. According to claim 3,
wherein the insulating material comprises SiO ₂ . According to claim 3,
wherein the insulating material comprises air. According to claim 1,
wherein the upper portion of the second vertical cross-section is substantially triangular. According to claim 6,
wherein the upper portion of the second vertical section is at least partially surrounded by an insulating material. According to claim 7,
wherein the insulating material comprises SiO ₂ . According to claim 7,
wherein the insulating material comprises air. According to claim 1,
wherein the contact comprises an electrically conductive material. According to claim 10,
wherein the electrically conductive material comprises tungsten. According to claim 10,
wherein the electrically conductive material comprises cobalt. According to claim 1,
and a gate structure disposed within the substrate, wherein at least a portion of the gate structure is substantially planar, substantially parallel to the contact, and separated from the lower portion of the second vertical section of the contact by a first distance. and separated from the upper portion of the second vertical cross-section of the contact by a second distance greater than the first distance. A method of manufacturing a semiconductor die, comprising:
providing a substrate; and
creating a contact at least partially embedded in the substrate;
The contact is:
a first portion having a first vertical cross-section with a first cross-sectional area, the first vertical cross-section having a first width and a first height; and
a second portion having a second vertical cross-section having a second cross-sectional area smaller than the first cross-sectional area;
including,
The second vertical section is:
a lower portion having the first width and a second height smaller than the first height; and
an upper portion disposed over the lower portion, having a second width less than the first width, and having a third height less than the first height;
A method of manufacturing a semiconductor die comprising: 15. The method of claim 14,
wherein the upper portion of the second vertical cross section is substantially rectangular. According to claim 15,
wherein the upper portion of the second vertical section is at least partially surrounded by an insulating material. 17. The method of claim 16,
The method of claim 1 , wherein the insulating material comprises SiO ₂ . 17. The method of claim 16,
The method of claim 1 , wherein the insulating material comprises air. 15. The method of claim 14,
wherein the upper portion of the second vertical cross section is substantially triangular. According to claim 19,
wherein the upper portion of the second vertical section is at least partially surrounded by an insulating material. 21. The method of claim 20,
The method of claim 1 , wherein the insulating material comprises SiO ₂ . 21. The method of claim 20,
The method of claim 1 , wherein the insulating material comprises air. 15. The method of claim 14,
The method of claim 1 , wherein the contact comprises an electrically conductive material. 24. The method of claim 23,
The method of claim 1 , wherein the electrically conductive material comprises tungsten. 24. The method of claim 23,
The method of claim 1 , wherein the electrically conductive material comprises cobalt. 15. The method of claim 14,
further comprising creating a gate structure disposed within the substrate, wherein at least a portion of the gate structure is substantially planar, substantially parallel to the contact, and third from the lower portion of the second vertical cross-section of the contact. separated by one distance and separated from the upper portion of the second vertical cross-section of the contact by a second distance greater than the first distance. A method of fabricating a contact in a semiconductor die comprising:
creating a contact hole in the substrate having a first width, a first length, and a first depth;
depositing an electrically conductive material into the contact hole to form the contact having the first width and the first length;
protecting the first portion of the contact from etching;
to create a recess having the first width, a second length less than the first length, and a second depth less than the first depth such that the second portion of the contact has the first width and the first height. vertically etching the second portion of the contact;
depositing a conformal spacing material having a thickness T in the concave portion;
anisotropically etching the conformal spacing material to a depth = T to expose at least a portion of the second portion of the contact;
selectively depositing additional electrically conductive material on the second portion of the contact to a third depth less than the second depth, thereby forming the first portion of the contact having a second width and a third length less than the second length. forming a lower portion of the second portion of the contact having an upper portion of two portions, the first width and the first height;
removing the conformal spacing material to create a gap between outer surfaces of the upper portion of the second portion of the contact and inner surfaces of the recess. . 28. The method of claim 27,
wherein the second width = the first width - 2*T, and wherein the third length = the second length - 2*T. 28. The method of claim 27,
wherein the upper portion of the second portion of the contact has a substantially rectangular cross-sectional shape. 28. The method of claim 27,
depositing an insulating material into the recess to at least partially fill the gap between the outer surfaces of the upper portion of the second portion of the contact and the inner surfaces of the recess. , A method of fabricating a contact in a semiconductor die. 31. The method of claim 30,
wherein the insulating material is a conformal material that completely fills the gap between the outer surfaces of the upper portion of the second portion of the contact and the inner surfaces of the recess. 31. The method of claim 30,
wherein the insulating material fills an upper portion of the recess but leaves at least a portion of the gap between the outer surfaces of the upper portion of the second portion of the contact and the inner surfaces of the recess portion unfilled. - A method of manufacturing a contact in a semiconductor die, which is a conformal insulating material. 31. The method of claim 30,
further comprising creating a gate structure at least partially buried within the substrate;
At least a portion of the gate structure is substantially parallel to the contact, separated from the lower portion of the second portion of the contact by a first distance and greater than the first distance from the upper portion of the second portion of the contact. A method of fabricating contacts in a semiconductor die that are separated by a large second distance. 28. The method of claim 27,
etching the upper portion of the second portion of the contact to reduce the cross-sectional area of the contact. 35. The method of claim 34,
wherein the upper portion of the second portion of the contact has a substantially triangular cross-sectional shape. 35. The method of claim 34,
depositing an insulating material into the recess to at least partially fill the gap between the outer surfaces of the upper portion of the second portion of the contact and the inner surfaces of the recess. , A method of fabricating a contact in a semiconductor die. 37. The method of claim 36,
wherein the insulating material is a conformal material that completely fills the gap between the outer surfaces of the upper portion of the second portion of the contact and the inner surfaces of the recess. 37. The method of claim 36,
wherein the insulating material fills an upper portion of the recess but leaves at least a portion of the gap between the outer surfaces of the upper portion of the second portion of the contact and the inner surfaces of the recess portion unfilled. - A method of manufacturing a contact in a semiconductor die, which is a conformal insulating material. 37. The method of claim 36,
further comprising creating a gate structure at least partially buried within the substrate;
At least a portion of the gate structure is substantially parallel to the contact, separated from the lower portion of the second portion of the contact by a first distance and greater than the first distance from the upper portion of the second portion of the contact. A method of fabricating contacts in a semiconductor die that are separated by a large second distance.

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