KR20230078448A - Memory device - Google Patents

Abstract

According to an embodiment of the present invention, a semiconductor device comprises: a memory cell area which includes a plurality of memory cells arranged on a first semiconductor substrate, gate electrodes that are stacked on the first semiconductor substrate and spaced apart from each other, and channel structures that pass through the gate electrodes and are connected to the first semiconductor substrate; and a peripheral circuit area including peripheral circuits which are arranged on a second semiconductor substrate that includes first conductivity-type impurities and has an upper surface facing an upper surface of the first semiconductor substrate in a first direction perpendicular to the upper surface of the first semiconductor substrate, and control the plurality of memory cells. The peripheral circuits include a plurality of well areas formed on the second semiconductor substrate, an ion implantation area arranged between the plurality of well areas and including the first conductivity-type impurities, and a plurality of antenna diodes, wherein at least one of the plurality of antenna diodes may overlap the ion implantation area in the first direction. Accordingly, in the semiconductor device according to an embodiment of the present invention, the antenna diodes can be inserted while minimizing an increase in intervals between the plurality of well areas, and furthermore, the peripheral circuits can be integrated and wiring complexity can be reduced.

Description

Semiconductor device {MEMORY DEVICE}

The present invention relates to semiconductor devices.

A manufacturing process of a semiconductor device includes a plurality of unit processes, and various methods have been proposed to protect already formed semiconductor devices while the plurality of unit processes are in progress. For the purpose of minimizing damage to semiconductor devices already formed by unit processes, various protection devices may be additionally formed on the semiconductor substrate. For example, a semiconductor device is manufactured to include a transistor and an antenna diode in a predetermined region of a semiconductor substrate. The antenna diode protects the transistor from plasma damage by naturally emitting plasma ions into the semiconductor substrate during the manufacturing process of the semiconductor device. However, when considering the fact that as many semiconductor devices as possible must be placed in a limited area, problems such as a decrease in the degree of integration of the semiconductor device due to the arrangement of protection devices or a decrease in freedom of design due to an increase in the complexity of metal wiring may occur. can

One of the problems to be achieved by the technical idea of the present invention is an integrated semiconductor device capable of minimizing an increase in spacing between a plurality of well regions and reducing the complexity of metal wiring by forming an antenna diode on top of an ion implantation region. It is intended to provide

A semiconductor device according to an embodiment of the present invention includes a plurality of memory cells disposed on a first semiconductor substrate, gate electrodes stacked spaced apart from each other on the first semiconductor substrate, and passing through the gate electrodes. A memory cell region including channel structures connected to the first semiconductor substrate, a second semiconductor substrate including first conductivity type impurities and having upper surfaces facing each other in a first direction perpendicular to the upper surface of the first semiconductor substrate and a peripheral circuit area disposed on the second semiconductor substrate and including peripheral circuits for controlling the plurality of memory cells, wherein the peripheral circuits are interposed between a plurality of well areas formed on the second semiconductor substrate and the plurality of well areas. and an ion implantation region including impurities of the first conductivity type, and a plurality of antenna diodes, wherein at least one of the plurality of antenna diodes overlaps the ion implantation region in the first direction.

A semiconductor device according to an exemplary embodiment of the present invention includes a first well region formed on a semiconductor substrate including impurities of a first conductivity type and containing impurities of the first conductivity type, and a first well region containing impurities of the first conductivity type and a second conductivity type different from the first conductivity type. A plurality of well regions including a second well region containing impurities of two conductivity types, an ion implantation region disposed between the plurality of well regions and including impurities of the first conductivity type, the first well region A plurality of antenna diodes including a first antenna diode formed on the ion implantation region and a second antenna diode disposed over the ion implantation region, and an active region included in the plurality of well regions and a gate formed thereon. It includes a plurality of transistors defined by the structure.

A semiconductor device according to an exemplary embodiment of the present invention includes a plurality of well regions formed on a semiconductor substrate including impurities of a first conductivity type, and disposed between the plurality of well regions to remove impurities of the first conductivity type. defined by an ion implantation region including an ion implantation region, a plurality of antenna diodes, at least one of which is disposed above the ion implantation region, and an active region included in the plurality of well regions and a gate structure formed thereon; The gate structure includes a plurality of transistors electrically connected to a most adjacent antenna diode among the plurality of antenna diodes through a metal wire.

In a semiconductor device according to an embodiment of the present invention, an antenna diode for protecting a gate oxide layer of a low voltage transistor may be inserted while minimizing an increase in a gap between well regions by forming an antenna diode on an ion implantation region. can

In a semiconductor device according to an embodiment of the present invention, an antenna diode may be inserted while minimizing an increase in the area of a well region of a peripheral circuit in a memory semiconductor device having a COP (Cell On Peri) structure in which a large amount of plasma is generated during a manufacturing process. .

In the semiconductor device according to an embodiment of the present invention, the complexity of metal wiring connected to the antenna diode can be reduced by forming the antenna diode above the ion implantation region.

Various advantageous advantages and effects of the present invention are not limited to the above description, and will be more easily understood in the process of describing specific embodiments of the present invention.

1 is a top view of a semiconductor device in which an antenna diode is disposed.
2 is a diagram for explaining a method for arranging an antenna diode in a semiconductor device.
FIG. 3 is a simplified cross-sectional view of a semiconductor device in which an antenna diode is disposed according to the method shown in FIG. 2 .
4 is a diagram for explaining problems that may occur in a semiconductor device according to an exemplary embodiment of the present invention.
5 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the present invention.
6 is a top view of a semiconductor device according to an exemplary embodiment in which an antenna diode is disposed.
7 is a diagram for explaining a method for arranging an antenna diode in a semiconductor device according to an embodiment of the present invention.
FIG. 8 is a simplified cross-sectional view of a semiconductor device in which an antenna diode is disposed according to the method shown in FIG. 7 .
9 is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment of the present invention.
10 is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment of the present invention.
11 is a top view illustrating an application example of a semiconductor device according to an exemplary embodiment.
12 to 14 are diagrams for explaining characteristics of an antenna diode included in a semiconductor device according to an embodiment of the present invention.
15 is a block diagram illustrating an electronic device including a semiconductor device according to an exemplary embodiment.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a top view of a semiconductor device in which an antenna diode is disposed.

Referring to FIG. 1 , a semiconductor device 1 may include a plurality of regions 10 , 20 , 30 , and 40 . Among the plurality of regions 10, 20, 30, and 40, adjacent regions 10, 20, 30, and 40 include well regions 12, 22, 32, and 42 doped with impurities of different conductivity types. can do. For example, the first region 10 and the fourth region 40 may include P-well regions in which NMOS transistors are formed, and the second region 20 and the third region 30 are formed with PMOS transistors. It may include an N-well region. However, this is merely an example and may not be limited.

The plurality of regions 10, 20, 30, and 40 are ion implanted regions 11, 21, and 21 for preventing breakdown voltage from being generated due to interference between the plurality of well regions 12, 22, 32, and 42. 31, 41) may be included. The ion implantation regions 11 , 21 , 31 , and 41 may be formed to surround the plurality of well regions 12 , 22 , 32 , and 42 .

The ion implantation regions 11 , 21 , 31 , and 41 of the semiconductor device may be formed by intensively doping a semiconductor substrate doped with first conductivity type impurities. In this case, the doping concentration of the ion implantation regions 11, 21, 31, and 41 may be higher than that of the semiconductor substrate. For example, the impurity of the first conductivity type may be a P-type dopant, and when the semiconductor substrate is P-doped, the ion implantation regions 11, 21, 31, and 41 may be P+-doped. However, this is merely an example and may not be limited.

The plurality of well regions 12, 22, 32, and 42 may include device regions 13, 23, 33, and 43 in which a plurality of semiconductor devices may be formed. The types of the plurality of semiconductor devices formed in the device regions 13, 23, 33, and 43 include well regions 12, 22, 32, and 42 formed in the plurality of regions 10, 20, 30, and 40, respectively. ) can be determined by the conductivity type.

The plurality of semiconductor devices may include transistors having a gate structure and an active region. The gate structure may be erected in a first direction (eg, a Z direction) perpendicular to an upper surface of a semiconductor substrate on which the semiconductor device 1 is formed. In order to prevent the gate structure from collapsing in subsequent processes after forming the active region and the gate structure, the gate structure may need to be disposed at predetermined reference intervals. In addition, in order to prevent damage to the gate structure that may occur during an etching process using plasma, an antenna diode connected to the gate structure may be disposed in the semiconductor device 1 .

The antenna diode can protect semiconductor elements such as transistors from plasma damage by naturally emitting plasma ions accumulated to form various patterns during a semiconductor manufacturing process into the semiconductor substrate.

2 is a diagram for explaining a method for arranging an antenna diode in a semiconductor device.

Referring to FIG. 2 , region A including well regions W1 and W2 adjacent to each other may correspond to region A shown in FIG. 1 . In other words, the well regions W1 and W2 adjacent to each other may be separated from each other by the ion implantation region IIP. However, the well regions W1 and W2 adjacent to each other may be N-well regions.

In this case, the thickness of the ion implantation region IIP separating the adjacent well regions W1 and W2 may be a. For example, a may have a value between about 4.6 um and about 5.0 um. However, this is merely an example and may not be limited. As an example, a in region A of FIG. 2 represents the thickness of the ion implantation region IIP, but a may also be a distance between adjacent well regions W1 and W2.

In general, separate diode active regions S1 and S2 separated from a plurality of semiconductor devices may be formed in a semiconductor device, and an antenna diode D may be formed in the diode active regions S1 and S2. At this time, the diode active regions S1 and S2 may be formed in an area where the ion implantation region IIP is not present, and the gate structure constituting the plurality of semiconductor devices is an antenna diode formed in the diode active regions S1 and S2 ( D) can be connected to

Meanwhile, as the diode active regions S1 and S2 are formed, intervals between gate structures included in the plurality of semiconductor devices may be increased. Intervals between the plurality of semiconductor elements included in the semiconductor device may directly affect the performance of the semiconductor device, and thus there may be limitations in reducing the size of the semiconductor device. Accordingly, a problem in that the degree of integration of the semiconductor device may be lowered due to the diode active regions S1 and S2 for disposing the antenna diode D may occur.

For example, in the area A1 including the well areas W1 and W2 adjacent to each other, the diode active area S1 in which the antenna diode D is formed includes impurities of a different conductivity type from those of the adjacent well areas W1 and W2, For example, it may be a P-well region doped with a P-type dopant. In region A1 , the diode active region S1 may be formed between the ion implantation regions IIP.

In this case, the thickness of each of the ion implantation regions IIP disposed on both sides of the diode active region S1 may be b. For example, b may have a value between about 4.4 μm and about 4.8 μm. However, this is merely an example and may not be limited. As an example, b shown in area A1 of FIG. 2 represents the thickness of the ion implantation region IIP, but b may be a distance between each of the well regions W1 and W2 and the diode active region S1. may be

Meanwhile, the thickness of the diode active region S1 in which the antenna diode D is formed may be c. As an example, c may have a value between about 2.8 um and 3.2 um. However, this is merely an example and may not be limited. For example, the thickness c of the diode active region S1 may be smaller than 2.8 μm for integration of the semiconductor device and larger than 3.2 μm for stable operation of the semiconductor device.

Accordingly, the distance between the well regions W1 and W2 adjacent to each other in region A1 may correspond to the sum of twice b and c. The distance between the well regions W1 and W2 adjacent to each other may be between about 11.6 um and 12.8 um, for example, about 12.2 um. Accordingly, the distance between the adjacent well regions W1 and W2 may be increased by about 2.4 times or more compared to a case in which the antenna diode D is not additionally disposed.

Meanwhile, in area A2 including well areas W1 and W2 adjacent to each other, the diode active area S2 where the antenna diode D is formed may be a region in which a portion of the ion implantation area IIP is removed.

In this case, the thickness of each of the ion implantation regions IIP disposed on both sides of the diode active region S2 may be d. As an example, d may have a value between about 4.0 um and 4.4 um. However, this is merely an example and may not be limited. As an example, d shown in area A2 of FIG. 2 represents the thickness of the ion implantation area IIP, but d is a distance between each of the well areas W1 and W2 and the diode active area S2. may be

Meanwhile, the thickness of the diode active region S2 where the antenna diode D is formed may be e. For example, the thickness of the diode active region S2 may be the thickness of the antenna diode D in the second direction (eg, Y direction), and e may have a value between about 0.2 um and 0.5 um. However, this is merely an example and may not be limited. For example, the thickness e of the diode active region S2 may be smaller than 0.2 μm for integration of the semiconductor device and larger than 0.5 μm for stable operation of the semiconductor device.

Accordingly, the distance between the well regions W1 and W2 adjacent to each other in region A2 may correspond to the sum of twice d and e. The distance between the adjacent well regions W1 and W2 may be between about 8.2 μm and about 9.3 μm, for example, about 8.6 μm. Accordingly, the distance between the adjacent well regions W1 and W2 may be increased by about 1.7 times or more compared to a case in which the antenna diode D is not additionally disposed.

FIG. 3 is a simplified cross-sectional view of a semiconductor device in which an antenna diode is disposed according to the method shown in FIG. 2 .

Referring to FIG. 3 , the semiconductor device in which the antenna diode Db is disposed by applying the diode active region S2 of the area A2 shown in FIG. 2 has a plurality of well regions PWELL formed on the semiconductor substrate PSUB. , NWELL), an ion implantation region (IIP), a plurality of antenna diodes (Da1, Da2, Db), and a plurality of transistors.

The semiconductor substrate PSUB may include impurities of a first conductivity type, for example, a P-type dopant, and the ion implantation region IIP is disposed between the plurality of well regions PWELL and NWELL and contains impurities of the first conductivity type. can include A plurality of transistors defined by active regions included in the plurality of well regions PWELL and NWELL and gate structures GSn and GSp formed thereon may be formed on the semiconductor substrate PSUB.

Meanwhile, the antenna diodes Da1, Da2, and Db for protecting the plurality of transistors are formed in the first well region PWELL including impurities of the first conductivity type among the plurality of well regions PWELL and NWELL. A second antenna diode Db formed in a diode active region between the first antenna diodes Da1 and Da2 and the plurality of well regions PWELL and NWELL may be included.

In this case, the diode active region may not overlap the ion implantation region IIP in the first direction (eg, Z direction). Accordingly, the ion implantation regions IIP may be discontinuously disposed between the plurality of well regions PWELL and NWELL.

The antenna diodes Da1, Da2, and Db may be connected to the upper metal wire ML through a plurality of contacts. The metal wiring ML may extend to upper portions of the gate structures GSn and GSp of the transistors along the second direction (eg, the Y direction). The gate structures GSn and GSp of the transistor may be connected to the antenna diodes Da1 , Da2 , and Db through contacts and metal lines ML.

Therefore, when charges or currents are generated due to discharge in a subsequent process of a semiconductor device using plasma or the like, the charges or currents generated by the antenna diodes Da1, Da2, and Db flow and are applied to the gate structures GSn and GSp. Losing damage can be minimized.

4 is a diagram for explaining problems that may occur in a semiconductor device according to an exemplary embodiment of the present invention.

The metal wires and gate structure GS shown in FIG. 4 may be components included in a memory device, for example, a memory device including NAND flash memory cells. In a conventional memory semiconductor device, the gate structure GS may be electrically connected to the metal wires L0, M0, M1, and M2 disposed thereon. In this case, the gate structure GS and the metal lines L0 , M0 , M1 , and M2 may be connected through vias VIA, contacts MC1 and MC2 , and studs STUD.

Meanwhile, a semiconductor device according to an embodiment of the present invention may be a memory semiconductor device having a COP (Cell On Peri) structure. A memory semiconductor device having a COP structure may be manufactured so that a memory cell region and a peripheral circuit region have a stacked structure.

For example, the upper metal wires M1 , M2 , and M3 included in the memory cell area may be connected to each other by upper vias VIA1 and VIA2 , an upper contact MC2 , and a stud STUD, and the peripheral circuit area The lower metal wires LM0 , LM1 , and LM2 included in may be electrically connected to the gate structure GS by lower vias LVIA and lower contacts LMC1 and LMC2 . Meanwhile, the memory cell area and the peripheral circuit area may be connected to each other through the connection part THV.

As such, the memory semiconductor device having the COP structure uses a lot of metal wiring compared to the conventional structure, so that an amount of plasma accumulated in semiconductor devices may increase when a process such as an etching process is performed. Accordingly, the need for the aforementioned antenna diode D may increase in order to protect semiconductor elements, particularly the gate oxide layer of the low voltage transistor, from plasma damage.

5 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the present invention.

Referring to FIG. 5 , a semiconductor device according to an exemplary embodiment of the present invention may be a memory semiconductor device 100 . The memory semiconductor device 100 includes a memory cell area CELL in which data is stored and a memory cell area CELL ) may include a peripheral circuit area PERI disposed below.

In the memory semiconductor device 100 according to an exemplary embodiment shown in FIG. 5 , the memory cell region CELL includes a first semiconductor substrate 101 , a plurality of insulating layers 120 , and a plurality of gate electrodes. 130 , a first conductive layer 104 , a second conductive layer 105 , channel structures CH, and an isolation region SR.

In the memory semiconductor device 100 according to an exemplary embodiment, a direction perpendicular to the upper surface of the first semiconductor substrate 101 (eg, a Z direction) may be defined as a first direction. In this case, the first semiconductor substrate 101 may have a top surface extending in the second direction (eg, the Y direction) and the third direction (eg, the X direction).

The first semiconductor substrate 101 may include a semiconductor material, for example, a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI oxide semiconductor. For example, the group IV semiconductor may include silicon, germanium, or silicon-germanium. However, the configuration of the first semiconductor substrate 101 is not limited thereto, and the first semiconductor substrate 101 may be provided as an epitaxial layer, a silicon on insulator (SOI) layer, or a semiconductor on insulator (SeOI) layer. there is.

The memory semiconductor device 100 according to an embodiment is alternately stacked on a first semiconductor substrate 101 spaced apart in a first direction (eg, z direction) perpendicular to the top surface of the first semiconductor substrate 101 . It may include insulating layers 120 and gate electrodes 130 . The insulating layers 120 may include an insulating material such as silicon oxide or silicon nitride.

Each of the gate electrodes 130 may include a first gate layer 130a and a second gate layer 130b. For example, the first gate layer 130a may include tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof. Also, the second gate layer 130b may include a metal material, such as tungsten (W). However, the structure of the gate electrodes 130 is not limited thereto, and the gate electrodes 130 may include a plurality of layers of three or more, and may include polycrystalline silicon or a metal silicide material.

Meanwhile, the first conductive layer 104 and the second conductive layer 105 may be sequentially stacked on the upper surface of the first semiconductor substrate 101 . At least a portion of the first semiconductor substrate 101, the first conductive layer 104, and the second conductive layer 105 may function as a common source line in the memory semiconductor device 100 according to an embodiment of the present invention. there is. The first conductive layer 104 and the second conductive layer 105 may include a semiconductor material, for example polycrystalline silicon. For example, at least the first conductive layer 104 may be doped with impurities, and the second conductive layer 105 may be doped with impurities or may include impurities diffused from the first conductive layer 104 .

In the memory semiconductor device 100 according to an exemplary embodiment, each of the channel structures CH may extend in the first direction and pass through the gate electrodes 130 and the insulating layers 120 . However, this is only an example and is not limited to that shown in FIG. 3 , and the channel structures CH may be disposed to pass through at least a portion of the first semiconductor substrate 101 . Meanwhile, the channel structures CH may be spaced apart from each other in a horizontal direction on the upper surface of the first semiconductor substrate 101 while forming rows and columns on the first semiconductor substrate 101 . Meanwhile, each of the channel structures CH has a columnar shape having a side surface perpendicular to the upper surface of the first semiconductor substrate 101 or an inclined side surface that becomes narrower as it approaches the first semiconductor substrate 101 according to an aspect ratio. can be

In the memory semiconductor device 100 according to an exemplary embodiment, each of the channel structures CH may include a channel layer 145 , a channel insulating layer 150 , and a pad layer 155 . For example, each of the channel structures CH may further include a gate dielectric layer 140 disposed between the channel layer 145 and the gate electrodes 130 and including a plurality of layers for trapping charges. Meanwhile, a portion of the gate dielectric layer 140 may be removed from the bottom of each of the channel structures CH, and the channel layer 145 may be electrically connected to the first conductive layer 104 in the removed region.

In the memory semiconductor device 100 according to an exemplary embodiment, the channel layer 145 may include a semiconductor material such as polycrystalline silicon or single crystal silicon. The channel layer 145 may implement memory cell strings including a plurality of memory cells.

In the memory semiconductor device 100 according to an exemplary embodiment, the isolation region SR may extend in the first direction and the second direction, and may include gate electrodes 130 and insulating layers 120 that are alternately stacked. can penetrate The isolation region SR may include an insulating material, such as silicon oxide. For example, the gate electrodes 130 may be disposed to be separated from each other in the third direction by the separation region SR.

In addition, the memory cell region CELL of the memory semiconductor device 100 includes a contact plug 170 electrically connected to the first interlayer insulating layer 160 , the second interlayer insulating layer 165 , and the channel structures CH. , and a bit line 180 electrically connected to the contact plug 170 may be further included. For example, the first interlayer insulating layer 160 and the second interlayer insulating layer 165 cover the insulating layers 120 and the gate electrodes 130 and may include an insulating material such as silicon oxide. The contact plug 170 penetrates the first interlayer insulating layer 160 and the second interlayer insulating layer 165 to form the bit line 180 and the channel structures CH disposed on the second interlayer insulating layer 165 . ) can be electrically connected.

In the memory semiconductor device 100 according to an exemplary embodiment, the peripheral circuit area PERI is first fabricated, and then the first semiconductor substrate 101 of the memory cell area CELL is fabricated on the peripheral circuit area PERI. can be formed by The first semiconductor substrate 101 may have the same size as the second semiconductor substrate 102 of the peripheral circuit region PERI or may be smaller than the second semiconductor substrate 102 .

The peripheral circuit region PERI includes a second semiconductor substrate 102, circuit elements disposed on the second semiconductor substrate 102 and driving and controlling a plurality of memory cells, circuit contact plugs, and a plurality of metal wires ( LM0, LM1) may be included. For example, circuit elements included in the peripheral circuit area PERI may include planar transistors. Meanwhile, each of the circuit elements may include a circuit gate dielectric layer, a spacer layer, and a circuit gate electrode, and active regions may be disposed in the second semiconductor substrate 102 on both sides of the circuit gate electrode. Active regions can function as source/drain regions.

In the memory semiconductor device 100 of the present invention, the plurality of metal wires LM0 and LM1 are metal wires disposed below the memory cells, and may be distinguished from metal wires disposed above the memory cells. However, this is only one embodiment, and the arrangement and shape of the plurality of metal wires LM0 and LM1 are not limited to those shown in FIG. 5, and the number and location of the plurality of metal wires LM0 and LM1 according to the embodiment , and structure may vary.

The memory cell area CELL and the peripheral circuit area PERI may be connected to each other in an area not shown. For example, in the memory semiconductor device 100 according to an exemplary embodiment, the peripheral circuit region PERI may be electrically connected to the memory cell region CELL through a connection portion. For example, the connection unit may be a through hole via (THV).

According to an embodiment of the present invention, the peripheral circuit region PERI may include circuit elements and an antenna diode D formed on the second semiconductor substrate 102 including impurities of the first conductivity type. . The antenna diode may be electrically connected to a circuit element, for example, a gate structure of a transistor. However, the structure of the memory semiconductor device 100 illustrated in FIG. 5 is only an example and may not be limited to the illustrated one.

6 is a top view of a semiconductor device according to an exemplary embodiment in which an antenna diode is disposed.

FIG. 6 may correspond to a top view of the semiconductor device shown in FIG. 1 . Meanwhile, FIG. 6 may illustrate an area corresponding to a part of a peripheral circuit area of the memory semiconductor device.

Referring to FIG. 6 , a semiconductor device 1 according to an exemplary embodiment may include a plurality of regions 10 , 20 , 30 , and 40 . The plurality of regions 10, 20, 30, 40 yield due to interference between the plurality of well regions 12, 22, 32, 42 and the plurality of well regions 12, 22, 32, 42. It may include ion implantation regions 11, 21, 31, and 41 for preventing voltage from being generated. The ion implantation regions 11 , 21 , 31 , and 41 may be formed to surround the plurality of well regions 12 , 22 , 32 , and 42 .

In the semiconductor device according to an embodiment of the present invention, the ion implantation regions 11, 21, 31, and 41 are formed in a method of intensively doping a semiconductor substrate doped with impurities of the first conductivity type with impurities of the first conductivity type. can be formed by In this case, the doping concentration of the ion implantation regions 11, 21, 31, and 41 may be higher than that of the semiconductor substrate. For example, the impurity of the first conductivity type may be a P-type dopant, and when the semiconductor substrate is P-doped, the ion implantation regions 11, 21, 31, and 41 may be P+-doped. However, this is merely an example and may not be limited.

The plurality of well regions 12, 22, 32, and 42 may include device regions 13, 23, 33, and 43 in which a plurality of semiconductor devices may be formed. The types of the plurality of semiconductor devices formed in the device regions 13, 23, 33, and 43 include well regions 12, 22, 32, and 42 formed in the plurality of regions 10, 20, 30, and 40, respectively. ) can be determined by the conductivity type.

The plurality of semiconductor devices may include transistors having a gate structure and an active region. The gate structure may be erected in a first direction (eg, a Z direction) perpendicular to an upper surface of a semiconductor substrate on which the semiconductor device 1 is formed. The semiconductor device 1 according to an embodiment of the present invention may include an antenna diode connected to the gate structure to prevent damage to the gate structure that may occur during an etching process using plasma.

However, unlike the semiconductor device shown in FIG. 1 , the semiconductor device 1 according to an embodiment of the present invention includes an antenna diode on top of the ion implantation regions 11, 21, 31, and 41 without a separate diode active region. can be placed Accordingly, the semiconductor device 1 according to an exemplary embodiment of the present invention may minimize an increase in the distance between the well regions 12 , 22 , 32 , and 42 as the antenna diode is disposed.

7 is a diagram for explaining a method for arranging an antenna diode in a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 7 , region B including well regions W1 and W2 adjacent to each other may correspond to region B shown in FIG. 6 . In other words, the well regions W1 and W2 adjacent to each other may be separated from each other by the ion implantation region IIP. For example, the well regions W1 and W2 adjacent to each other may be N-well regions.

In this case, the thickness of the ion implantation region IIP where the antenna diode D is disposed may be e. However, this is only an example and may not be limited, and e may be defined as a thickness of the antenna diode D in the second direction (eg, Y direction). For example, e may be the same as the thickness e of the diode active region S2 shown in FIG. 2 or the thickness e of the antenna diode D. For example, e may have a value between about 0.2 um and 0.5 um. However, the thickness of the antenna diode D may be formed differently as needed.

Meanwhile, a distance between each of the adjacent well regions W1 and W2 and the ion implantation region IIP where the antenna diode D is disposed may be f. However, this is only an example and may not be limited, and f may be defined as a distance between each of the adjacent well regions W1 and W2 and the antenna diode D. For example, f may have a value between about 3.0 μm and about 3.4 μm.

Accordingly, the distance between the well regions W1 and W2 adjacent to each other in region B may correspond to the sum of twice f and e. The distance between the adjacent well regions W1 and W2 may be between about 6.2 μm and about 7.3 μm, for example, about 6.6 μm. Accordingly, the distance between the adjacent well regions W1 and W2 may be increased by about 1.5 times or less compared to a case where the antenna diode D is not additionally disposed.

Also, in the semiconductor device according to an exemplary embodiment of the present invention, the distance between the well regions W1 and W2 adjacent to each other may be reduced by about 20% to 30% compared to a case in which a diode active region is used. Accordingly, in the semiconductor device according to an exemplary embodiment of the present invention, the antenna diode D for protecting the gate oxide layer of the transistor may be inserted while minimizing an increase in the distance between the adjacent well regions W1 and W2 .

FIG. 8 is a simplified cross-sectional view of a semiconductor device in which an antenna diode is disposed according to the method shown in FIG. 7 .

Referring to FIG. 8 , a semiconductor device according to an exemplary embodiment of the present invention includes a plurality of well regions PWELL and NWELL formed on a semiconductor substrate PSUB, an ion implantation region IIP, and a plurality of antenna diodes Da. , Db1, Db2), and a plurality of transistors. FIG. 8 may illustrate only major components of a semiconductor device for convenience of description. Accordingly, the illustrated main components and the arrangement of the metal wires ML are merely examples and may not be limited.

The semiconductor substrate PSUB may include impurities of a first conductivity type, for example, a P-type dopant, and the ion implantation region IIP is disposed between the plurality of well regions PWELL and NWELL and contains impurities of the first conductivity type. can include The plurality of well regions PWELL and NWELL include a first well region PWELL including impurities of a first conductivity type and a second well region NWELL including impurities of a second conductivity type different from the first conductivity type. ) may be included. For example, the impurity of the first conductivity type may be a P-type dopant, and the impurity of the second conductivity type may be an N-type dopant.

Concentrations of the first conductivity type impurities included in the ion implantation region IIP may vary depending on positions. Meanwhile, the doping concentration of the ion implantation region IIP may be higher than that of the plurality of well regions PWELL and NWELL, particularly the first well region PWELL.

A plurality of transistors defined by active regions included in the plurality of well regions PWELL and NWELL and gate structures GSn and GSp formed thereon may be formed on the semiconductor substrate PSUB. In the semiconductor device according to an exemplary embodiment, the antenna diodes Da, Db1, and Db2 may be configured to protect a gate oxide layer included in a low voltage transistor. However, this is only one embodiment and is not limited, and the antenna diodes Da, Db1, and Db2 may be used as a configuration for protecting other semiconductor elements other than the low voltage transistor.

Meanwhile, the antenna diodes Da, Db1, and Db2 for protecting the plurality of transistors are formed in the first well region PWELL including impurities of the first conductivity type among the plurality of well regions PWELL and NWELL. It may include second antenna diodes Db1 and Db2 formed between the first antenna diode Da and the ion implantation region IIP.

The plurality of antenna diodes Da, Db1, and Db2 may include impurities of the second conductivity type. Specifically, the plurality of antenna diodes Da, Db1, and Db2 may be formed in an active region including impurities of the second conductivity type. The plurality of antenna diodes Da, Db1, and Db2 may form a PN junction adjacent to a structure including impurities of the first conductivity type.

At least one of the plurality of antenna diodes Da, Db1, and Db2 may overlap the ion implantation region IIP in the first direction (eg, Z direction). For example, the second antenna diodes Db1 and Db2 may overlap the ion implantation region IIP in the first direction. Accordingly, in the second direction (eg, the Y direction), the ion implantation regions IIP between the plurality of well regions PWELL and NWELL may be continuously disposed.

The antenna diodes Da, Db1, and Db2 may be connected to the upper metal wire ML through a plurality of contacts. The metal wiring ML may extend to upper portions of the gate structures GSn and GSp of the transistors along the second direction. The gate structures GSn and GSp of the transistor may be connected to the antenna diodes Da, Db1 and Db2 through contacts and metal lines ML. For example, the metal wire ML may include at least one conductive material selected from among aluminum (Al), copper (Cu), and tungsten (W).

In the semiconductor device according to an embodiment of the present invention, since the antenna diodes Da, Db1, and Db2 are inserted while minimizing an increase in the distance between the adjacent well regions PWELL and NWELL, they are adjacent to the gate structures GSn and GSp. Since antenna diodes Da, Db1 and Db2 can be formed, diode efficiency can be increased.

In addition, the gate structures GSn and GSp of the transistors included in the semiconductor device may be electrically connected to the nearest antenna diode among the plurality of antenna diodes Da, Db1 and Db2 through the metal line ML. Accordingly, in the semiconductor device, routing complexity of the metal line ML may be reduced.

A semiconductor device according to an embodiment of the present invention uses the antenna diodes Da, Db1, and Db2 disposed above the ion implantation region IIP to charge or discharge according to discharge in a subsequent process of the semiconductor device using plasma or the like. When current is generated, damage applied to the gate structures GSn and GSp may be minimized by discharging the electric charge or current generated by the antenna diodes Da, Db1, and Db2.

9 is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment of the present invention. 10 is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment of the present invention.

Referring to FIG. 9 , a semiconductor device according to an exemplary embodiment may include various types of transistors LV, MV, and HV formed on a semiconductor substrate PSUB. The antenna diode D included in the semiconductor device may be used for the purpose of protecting the gate oxide layer Gox1 of the low voltage transistor LV. However, this is merely an example and may not be limited. For example, the antenna diode D may be used for the purpose of protecting the gate oxide layers Gox2 and Gox3 of the transistors MV and HV other than the low voltage transistor LV.

The transistors LV, MV, and HV may be separated from each other by a device isolation region TRN formed by a shallow trench isolation (STI) process or a deep trench isolation (DTI) process.

The device isolation region TRN may define active regions ACT in the semiconductor substrate PSUB. The device isolation region TRN may include a region extending deeper into the lower portion of the semiconductor substrate PSUB between adjacent active regions ACT, but is not limited thereto. The device isolation region TRN may be made of an insulating material, and may include, for example, oxide, nitride, or a combination thereof.

The active regions ACT are defined by the device isolation region TRN in the semiconductor substrate PSUB and may be disposed to extend in a third direction (eg, X direction). The active regions ACT disposed on both sides of the gate structures GS1 , GS2 , and GS3 may function as source/drain regions.

Meanwhile, in the semiconductor device according to an exemplary embodiment, the active regions ACT other than the active regions ACT disposed on both sides of the gate structures GS1, GS2, and GS3 function as regions for forming antenna diodes. can do.

According to example embodiments, the active regions ACT may have doped regions including impurities. However, the shape of the active region ACT may not be limited to a structure having a flat top surface as shown.

The active region ACT may be formed of an epitaxial layer and may include, for example, silicon (Si), silicon germanium (SiGe), or silicon carbide (SiC). In addition, the active region ACT may further include impurities such as arsenic (As) and/or phosphorus (P). In example embodiments, the active region ACT may include a plurality of regions including different concentrations of elements and/or doping elements.

Gate Structure The gate structures GS1 , GS2 , and GS3 may be disposed above the active regions ACT to overlap the active regions ACT and extend in the third direction. Gate Structure Channel regions of transistors may be formed in the active regions ACT overlapping the gate structures GS1 , GS2 , and GS3 . Gate Structure The gate structures GS1 , GS2 , and GS3 may include a gate insulating layer, a gate electrode layer, gate spacer layers, and a gate capping layer. However, the shape and configuration of the gate structure GS included in each transistor may not be limited to those illustrated.

Gate oxide layers Gox1 , Gox2 , and Gox3 may be disposed on the semiconductor substrate PSUB on which the transistors are formed. Meanwhile, thicknesses of the gate oxide layers Gox1 , Gox2 , and Gox3 may vary depending on the type of transistor. In the semiconductor device according to an embodiment of the present invention, the plurality of antenna diodes D may be applied to various types of transistors.

Therefore, the thickness of the gate oxide layers Gox1, Gox2, and Gox3 disposed on one of the plurality of antenna diodes D is the same as the gate oxide layer disposed on the other one of the plurality of antenna diodes D. It may be different from the thickness of the layers Gox1, Gox2 and Gox3. For example, the thickness of the gate oxide layer Gox1 corresponding to the low voltage transistor LV using the antenna diode D is the gate oxide layer corresponding to the other transistors MV and HV using the other antenna diode D. It may be thinner than the thickness of (Gox2, Gox3).

Although not shown in FIG. 9 , the plurality of antenna diodes D may be connected to contacts penetrating the gate oxide layers Gox1 , Gox2 , and Gox3 . The contact may be electrically connected to the gate structures GS1 , GS2 , and GS3 of transistors adjacent to the contact through a metal wire.

Referring to FIG. 10 , in another semiconductor device according to an embodiment of the present invention, at least one of the plurality of antenna diodes D may be formed to partially overlap the ion implantation region IIP.

For example, a first gate oxide layer Gox1 corresponding to the first gate structure GS1 , a second gate oxide layer Gox2 corresponding to the second gate structure GS2 , and a gate oxide layer Goxm therebetween ) may have different thicknesses. Any one antenna diode D may be formed over gate oxide layers Goxm and Gox2 having different thicknesses. In this case, the ion implantation region IIP may partially overlap the corresponding antenna diode D.

However, the structure and form of the semiconductor device shown in FIGS. 9 and 10 are merely examples and may not be limited. For example, the semiconductor device may further include additional components, some components may be omitted, or the shapes of some components may be changed.

11 is a top view illustrating an application example of a semiconductor device according to an exemplary embodiment.

Referring to FIG. 11 , a semiconductor device according to an exemplary embodiment includes a pad area PAD, an ion implantation area IIP, a plurality of well areas WELL, and a plurality of antenna diodes D. can do. The pad area PAD may be an area where a plurality of pads for inputting/outputting control signals and data are formed. The characteristics of the semiconductor device described above with reference to FIGS. 5 to 10 may be applied to the ion implantation region IIP, the plurality of well regions WELL, and the plurality of antenna diodes D.

Meanwhile, although it may be modified and applied according to embodiments, the ion implantation region (IIP), the plurality of well regions (WELL), and the plurality of antenna diodes (D) may implement various semiconductor devices formed in the circuit region. there is. That is, the plurality of antenna diodes D may prevent damage to a semiconductor element, for example, a transistor formed in the plurality of well regions WELL.

12 to 14 are diagrams for explaining characteristics of an antenna diode included in a semiconductor device according to an embodiment of the present invention.

Referring to FIGS. 12 to 14 , an antenna diode D included in a semiconductor device according to an exemplary embodiment may be formed by bonding a P+ doped region and an N+ doped region. The antenna diode D may include impurities of the second conductivity type, for example, N+ dopants.

Referring to FIG. 8 together, the first antenna diode Da formed in the first well region PWELL may form a Zener diode based on a PN junction with the first well region PWELL. Meanwhile, the second antenna diodes Db1 and Db2 formed over the ion implantation region IIP may form Zener diodes based on a PN junction with the ion implantation region IIP.

12, which shows the modeling of the PN junction diode, shows a P+ doped region and an N+ doped region to which the diode voltage Vd is applied, and a depletion region therebetween. The diode voltage Vd may correspond to a potential difference between a P+ doped region and an N+ doped region formed by charges, eg, positive charges, accumulated on the gate electrode.

When positive charges are accumulated on the gate electrode, it can be modeled as providing a positive voltage as the diode voltage Vd by the N+ doped region composed of conductors and the metal line ML. Accordingly, as the number of positive charges accumulated in the gate electrode increases, the diode voltage Vd applied in the reverse direction may also increase.

13 may be an energy band diagram of a PN junction diode in a state where the diode voltage (Vd) is 0V. When the bias voltage is not applied in the high concentration PN junction diode, the conduction band energy level (Ec), the valence band energy level (Ev), and the Fermi level (Ef) may be as shown in FIG. 13 . In this case, in the state in which the bias is removed, both sides of the Fermi level (Ef) may have the same value as shown in FIG. 13 .

14 may be an energy band diagram when the diode voltage (Vd) is lower than the breakdown voltage (VB). In other words, the energy level shown in FIG. 14 may be an energy level in a situation where the absolute value of the reversely applied diode voltage Vd is greater than the breakdown voltage VB. In this case, the Fermi level (Ef) in the P+ doped region and the Fermi level (Ef) in the N+ doped region may be different.

When the reverse voltage is greater than the breakdown voltage (VB), the reverse bias voltage increases and a very high electric field can be formed in the depletion region. A degree of bending of an energy band in a depletion region may be increased by a large electric field. In this case, an energy band in the depletion region may be thinned, and band-to-band tunneling of charges may easily occur. Therefore, when the reverse voltage is greater than the breakdown voltage (VB), a large current may flow.

In the semiconductor device according to an embodiment of the present invention, a Zener diode having a relatively low breakdown voltage may be formed by bonding an N+ doped region to an upper portion of a P+ doped region of the antenna diode. On the other hand, by implanting ions at a high concentration into the doped region, the carrier concentration at the time of breakdown may be increased. Therefore, even if the amount of charge accumulated in the antenna diode is large, the upper limit of the current that can be bypassed is high, so that the accumulated charge can be quickly removed.

15 is a block diagram illustrating an electronic device including a semiconductor device according to an exemplary embodiment.

An electronic device 1000 according to the embodiment shown in FIG. 15 may include a display 1010, an image sensor 1020, a memory 1030, a port 1040, and a processor 1050. In addition, the electronic device 1000 may further include a wired/wireless communication device, a power supply, and the like. Among the components shown in FIG. 15 , the port 1040 may be a device provided for the electronic device 1000 to communicate with a video card, sound card, memory card, or USB device. The electronic device 1000 may be a concept encompassing not only a general desktop computer or laptop computer, but also a smart phone, a tablet PC, and a smart wearable device.

The processor 1050 may perform specific operations, instructions, and tasks. The processor 1050 may be a central processing unit (CPU) or a microprocessor unit (MCU), and may include a display 1010, an image sensor 1020, a semiconductor device 1030, as well as a port 1040 via a bus 1060. ) can communicate with other devices connected to it.

The memory 1030 may be a storage medium that stores data necessary for the operation of the electronic device 1000 or multimedia data. As described above with reference to FIG. 5 , the memory 1030 may be a NAND flash memory having a COP structure. However, this is merely an example and may not be limited, and the memory 1030 may be a non-volatile memory having a different structure and configuration, or a concept including a volatile memory such as random access memory (RAM). Also, the memory 1030 may include at least one of a solid state drive (SSD), a hard disk drive (HDD), and an optical drive (ODD) as a storage device.

The semiconductor device according to an embodiment of the present invention may be applied to components including transistors formed through a semiconductor process, such as the display 1010, the image sensor 1020, the memory 1030, and the processor 1050. there is. That is, in order to provide an antenna diode electrically connected to gate structures of transistors while minimizing an increase in the distance between the well regions, the antenna diode may be disposed above the ion implantation region formed between the well regions. can In addition, the gate structures of the transistors are connected to the nearest antenna diode to reduce the complexity of metal wiring.

The present invention is not limited by the above-described embodiments and accompanying drawings, but is intended to be limited by the appended claims. Therefore, various forms of substitution, modification, and change will be possible by those skilled in the art within the scope of the technical spirit of the present invention described in the claims, which also falls within the scope of the present invention. something to do.

1, 100: semiconductor device
10, 20, 30, 40: multiple areas
11, 21, 31, 41, IIP: ion implantation area
12, 22, 32, 42, Wl, W2, PWELL, NWELL, WELL: plurality of well regions
13, 23, 33, 43: element regions
D: antenna diode
Da, Da1, Da2: first antenna diode
Db, Db1, Db2: second antenna diode
S1, S2: diode active area
PSUB: semiconductor substrate
GSn, GSp, GS1, GS2, GS3: gate structure
Gox1, Gox2, Gox3, Goxm: gate oxide layer
ACT: active area
ML: metal wiring
CELL: memory cell area
PERI: Peripheral circuit area

Claims (10)

It includes a plurality of memory cells disposed on a first semiconductor substrate, gate electrodes spaced apart from each other and stacked on the first semiconductor substrate, and channel structures passing through the gate electrodes and connected to the first semiconductor substrate. a memory cell area to;
peripheral circuits disposed on a second semiconductor substrate including impurities of a first conductivity type and having top surfaces facing each other in a first direction perpendicular to the top surface of the first semiconductor substrate and controlling the plurality of memory cells; peripheral circuit area; including,
The peripheral circuits include a plurality of well regions formed on the second semiconductor substrate, an ion implantation region disposed between the plurality of well regions and including impurities of the first conductivity type, and a plurality of antenna diodes; ,
At least one of the plurality of antenna diodes overlaps the ion implantation region in the first direction.
According to claim 1,
The plurality of well regions include a first well region containing impurities of the first conductivity type and a second well region including impurities of a second conductivity type different from the first conductivity type;
The plurality of antenna diodes include a first antenna diode formed in the first well region and a second antenna diode disposed between the plurality of well regions.
According to claim 1,
The plurality of antenna diodes include impurities of a second conductivity type different from the first conductivity type.
According to claim 1,
A doping concentration of the ion implantation region is higher than a doping concentration of the plurality of well regions.
According to claim 1,
The semiconductor device of claim 1 , wherein the ion implantation regions are continuously disposed between the plurality of well regions in a second direction perpendicular to the first direction.
According to claim 1,
A gate oxide layer is disposed on the second semiconductor substrate, and the thickness of the gate oxide layer disposed on one of the plurality of antenna diodes is the same as the gate disposed on the other one of the plurality of antenna diodes. A semiconductor device different from the thickness of the oxide layer.
According to claim 1,
At least one of the plurality of antenna diodes partially overlaps the ion implantation region.
According to claim 1,
Each of the plurality of well regions includes an active region including impurities of a conductivity type different from that of the impurities included in each of the plurality of well regions, and the active region and a gate structure formed thereon are Defining transistors included in the peripheral circuits,
Among the plurality of antenna diodes, a transistor adjacent to an antenna diode disposed between the plurality of well regions is a low voltage transistor.
A first well region formed on a semiconductor substrate including impurities of a first conductivity type, including impurities of the first conductivity type, and a second well region including impurities of a second conductivity type different from the first conductivity type. A plurality of well regions including;
an ion implantation region disposed between the plurality of well regions and including impurities of the first conductivity type;
a plurality of antenna diodes including a first antenna diode formed in the first well region and a second antenna diode disposed above the ion implantation region; and
a plurality of transistors defined by an active region included in the plurality of well regions and a gate structure formed thereon; A semiconductor device comprising a.
a plurality of well regions formed in the semiconductor substrate including impurities of a first conductivity type;
an ion implantation region disposed between the plurality of well regions and including impurities of the first conductivity type;
a plurality of antenna diodes, at least one of which is disposed above the ion implantation region; and
A plurality of antenna diodes defined by an active region included in the plurality of well regions and a gate structure formed thereon, wherein the gate structure is electrically connected to a most adjacent antenna diode among the plurality of antenna diodes through a metal wire. transistors; A semiconductor device comprising a.

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