KR20230076493A - Display Device Including Transition Transistor And Method Of Driving The Same - Google Patents

Abstract

The present invention provides a display device including a transition transistor, capable of operating at a high speed and reducing a ripple of a data voltage. The display device includes: a timing control unit generating image data, a data control signal, and a gate control signal; first and second data operating units individually generating first and second data voltages by using the image data and the data control signal; a first gate operating unit generating a gate voltage by using the gate control signal; a display panel including multiple subpixels, a gate wire transmitting the gate voltage to the multiple subpixels, a first data wire arranged on a first side of each subpixel, and a second data wire arranged on a second side of each subpixel; a first transition unit connected to a first end of the first gate operating unit, a first end of the first data wire, and a first end of the second data wire and including a first transition transistor and a second transition transistor; and a second transition unit connected to a second end of the first gate operating unit, a second end of the first data wire, and a second end of the second data wire and including the first transition transistor and the second transition transistor.

Description

Display device including transition transistor and method of driving the same {Display Device Including Transition Transistor And Method Of Driving The Same}

The present invention relates to a display device, and more particularly, to a display device including a transition transistor for supplying a data voltage from both ends of a data line to a sub-pixel during one frame using the transition transistor, and a driving method thereof.

In line with the information age, the display field has also developed rapidly, and in response to this, a liquid crystal display device (LCD) as a flat panel display device (FPD) has advantages of thinning, lightening, and low power consumption. ), plasma display panel device (PDP), organic light emitting diode display device (OLED), field emission display device (FED), etc. It is rapidly replacing the cathode ray tube (CRT).

In such a display device, an image is displayed by supplying a data voltage output from a data driver to pixels of a display panel. As the resolution increases, the number of pixels increases, and accordingly, the application time of the data voltage for each pixel decreases. There is a problem in that the charging time for the data wiring is reduced.

In particular, in order to solve this problem in a large, high-resolution portrait mode, a display device supplying a data voltage to one vertical pixel column using two mux transistors and two data lines has been proposed.

In such a display device, the size (width) of the mux transistor must be increased in order to improve the speed of the mux transistor, but in a high-resolution display device, delay increases due to an increase in load due to an increase in the size of the mux transistor, and as a result, data There is a problem that the charging time of the voltage is less than one horizontal time (1H).

In addition, a data floating section occurs during 1 horizontal time, resulting in a sampling difference for each pixel, and luminance deviation due to DC and AC data voltage variations (ripple) due to kickback when the mux transistor is turned on and off. There is a problem that occurs.

The present invention has been proposed to solve this problem, and arranges transition transistors at both ends of data wires of a display panel, and switches the transition transistors in frame units to generate top data voltages and bottom data voltages from both ends of the data wires in odd-numbered rows. and a transition transistor capable of high-speed driving by securing sufficient charging time and sampling time by supplying to sub-pixels in even-numbered rows and reducing data voltage ripple, and a driving method thereof.

Further, in the present invention, the data voltage deviation and the luminance deviation due to the difference in maximum delay point are offset by supplying the top data voltage and the bottom data voltage from both ends of the data line to sub-pixels in odd rows and even rows through a transition transistor. Another object is to provide a display device including a transition transistor and a driving method thereof.

In order to solve the above problems, the present invention includes a timing controller for generating image data, a data control signal, and a gate control signal; first and second data drivers which respectively generate first and second data voltages using the image data and the data control signal; a first gate driver generating a gate voltage using the gate control signal; A plurality of sub-pixels, a gate line for transmitting the gate voltage to the plurality of sub-pixels, a first data line arranged on a first side of each of the plurality of sub-pixels, and a second line of each of the plurality of sub-pixels. a display panel including a second data line disposed on a side thereof; a first transition unit connected to the first end of the first gate driver, the first end of the first data line, and the first end of the second data line, and including first and second transition transistors; A second transition part connected to the second end of the first gate driver, the second end of the first data line, and the second end of the second data line, and including the first and second transition transistors. display device is provided.

And, the first and second transition transistors are switched according to the first and second transition signals, respectively, and the first and second transition signals have values opposite to each other among a low level and a high level, respectively, 1 frame The low level and the high level may be alternately provided with a period of .

The first gate driver includes a plurality of stages, and the first transition transistor of the first transition unit and the second transition transistor of the second transition unit are connected to odd-numbered stages among the plurality of stages. The second transition transistor of the first transition unit and the first transition transistor of the second transition unit may be connected to even-numbered stages among the plurality of stages.

The first transition transistor of the first transition part and the second transition transistor of the second transition part are connected to odd-numbered sub-pixels among the plurality of sub-pixels, and the second transition transistor of the first transition part and the second transition transistor of the first transition part are connected. The first transition transistor of the second transition unit may be connected to even-numbered sub-pixels among the plurality of sub-pixels.

In addition, the first transition transistor of the first transition unit and the second transition transistor of the second transition unit are connected to the first data line, and the second transition transistor of the first transition unit and the second transition transistor of the second transition unit are connected to each other. A first transition transistor may be connected to the second data line.

The first data line may be connected to odd-numbered sub-pixels among the plurality of sub-pixels, and the second data line may be connected to even-numbered sub-pixels among the plurality of sub-pixels.

The display device may further include a second gate driver that generates the gate voltage using the gate control signal and is disposed opposite to the first gate driver.

The first and second data drivers may be disposed on two short sides of the display panel, respectively.

Also, the display panel may be folded based on a folding axis parallel to a short side of the display panel.

Meanwhile, the present invention includes first and second data drivers for generating first and second data voltages, respectively; first and second gate drivers generating gate voltages; a display panel including a plurality of sub-pixels, a gate line, a first data line connected to an odd-numbered sub-pixel among the plurality of sub-pixels, and a second data line connected to an even-numbered sub-pixel among the plurality of sub-pixels; A first transition unit connected to first ends of the first and second gate drivers, a first end of the first data line, and a first end of the second data line, and including first and second transition transistors. and; The second transition is connected to the second terminal of the first and second gate drivers, the second terminal of the first data line, and the second terminal of the second data line, and includes the first and second transition transistors. A display device including a portion is provided.

On the other hand, the present invention comprises the steps of generating image data, a data control signal and a gate control signal; generating first and second data voltages using the image data and the data control signal; generating a gate voltage using the gate control signal; During the p-th frame, the first data voltage is transferred to the first data line through the first transition transistor of the first transition unit, and the second data voltage is transferred to the second data line through the second transition transistor of the second transition unit. delivering; During the (p+1)th frame, the first data voltage is transmitted to the second data line through the second transition transistor of the first transition unit, and the first data voltage is transferred to the second data line through the first transition transistor of the second transition unit. transferring 2 data voltages to the first data line; A method of driving a display device including displaying an image using the first and second data voltages and the gate voltage is provided.

And, the first and second transition transistors are switched according to the first and second transition signals, respectively, and the first and second transition signals have values opposite to each other among a low level and a high level, respectively, 1 frame The low level and the high level may be alternately provided with a period of .

The present invention arranges transition transistors at both ends of data lines of a display panel, switches the transition transistors in frame units, and supplies top data voltages and bottom data voltages from both ends of the data lines to sub-pixels in odd and even rows. , sufficient charging time and sampling time are secured, enabling high-speed driving and reducing the ripple of the data voltage.

Further, in the present invention, the data voltage deviation and the luminance deviation due to the difference in maximum delay point are offset by supplying the top data voltage and the bottom data voltage from both ends of the data line to sub-pixels in odd rows and even rows through a transition transistor. has the effect of

In addition, according to the present invention, by arranging the data driver on the short side of the display panel and omitting the driver on the long side of the display panel, multi-curves are possible and folding reliability is improved.

1 is a diagram showing a display device according to a first embodiment of the present invention;
2A and 2B are diagrams illustrating operations of the p-th and (p+1)-th frames of the display device according to the first embodiment of the present invention, respectively.
3 is a diagram illustrating sub-pixels of a display device according to a first embodiment of the present invention;
4 is a timing diagram illustrating a plurality of signals of a display device according to a first embodiment of the present invention.
5 is a diagram showing a display device according to a second embodiment of the present invention;

Hereinafter, a display device and a driving method thereof according to the present invention will be described with reference to the accompanying drawings.

1 is a view showing a display device according to a first embodiment of the present invention. The display device according to the first embodiment may be an organic light emitting diode display device (OLED display device), The long side of the display panel may be used in a portrait mode in which the long side is disposed along the vertical direction.

As shown in FIG. 1, the display device 110 according to the first embodiment of the present invention includes a timing controller 120, first and second data driver units 130 and 132, and first and second gate driver units. 140 and 142 , first and second transition units 150 and 152 , and a display panel 160 .

The timing controller 120 uses a video signal transmitted from an external system (not shown) such as a graphic card or a TV system, a data enable signal, a horizontal sync signal, a vertical sync signal, and a plurality of timing signals such as a clock to display an image. Data, data control signals and gate control signals can be generated. Then, the generated image data and data control signals are transferred to the first and second data drivers 130 and 132, and the generated gate control signals are transferred to the first and second gate drivers 140 and 142.

The first and second data drivers 130 and 132 respectively generate a top data voltage (top data signal) and a bottom data voltage (bottom data signal) using the data control signal and image data transmitted from the timing controller 120. generated, and the generated top data voltage and bottom data voltage are applied to the left and right data lines DLL and DLR of the display panel 160 .

The first and second gate drivers 140 and 142 generate a gate voltage (gate signal) using the gate control signal transmitted from the timing controller 120, and use the generated gate voltage to the gate of the display panel 160. When applied to the wiring GL, the first and second gate drivers 140 and 142 may output the same gate voltage at the same timing.

Here, the first and second gate drivers 140 and 142 are together with the substrate of the display panel 160 on which the gate lines GL, left and right data lines DLL and DLR, and sub-pixels SP are formed. The formed gate-in-panel (GIP) type may be formed.

In the first embodiment, the first and second gate driving units 140 and 142 are arranged corresponding to the two long sides of the display panel 160 as an example, but in other embodiments, the first and second gate driving units 140 , 142) may be disposed corresponding to one of the two long sides of the display panel 160, and the other may be omitted.

The first and second transition units 150 and 152 transfer the gate control signal including the clock received from the timing control unit 120 to the first and second gate driving units 140 and 142, respectively, and The top data voltage and the bottom data voltage received from the second data drivers 130 and 132 are selectively transferred to one of the left and right data lines DLL and DLR.

Here, the first and second transition units 150 and 152 are disposed to correspond to two short sides of the display panel 160, respectively, and the first and second gate drivers 140 and 142, left and right data It is connected to both ends of the wiring (DLL, DLR). Each of the first and second transition units 150 and 152 includes a plurality of transition transistors, the specific configuration of which will be described in detail later.

The display panel 160 displays an image using a gate voltage, a top data voltage, and a bottom data voltage. The display panel 160 includes a plurality of sub-pixels (SP), a plurality of gate lines (GL), a plurality of left data lines (DLL), and a plurality of right data lines (DLR) arranged in a display area to display an image. include

The display panel 160 has a rectangular shape, and two short sides and two long sides of the display panel 160 are disposed along the X axis and the Y axis, respectively.

Each of the plurality of sub-pixels SP may be one of red, green, and blue sub-pixels, and the red, green, and blue sub-pixels may constitute one pixel. The gate line GL may cross the left data line DLL and the right data line DLR to define the sub-pixel SP.

Here, the left and right data lines DLL and DLR are disposed on the left and right sides of the sub-pixel SP, respectively, and each sub-pixel SP is connected to one of the left and right data lines DLL and DLR. Specifically, the q subpixel SP(q) (q is an odd number) of the odd-numbered horizontal pixel column is connected to the gate line GL and the left data line DLL, and the even-numbered horizontal pixel column (q+1) ) The sub-pixel SP(q+1) may be connected to the gate line GL and the right data line DLR.

When the display device 110 is an organic light emitting diode display, each of the plurality of subpixels SP may include a plurality of transistors such as a switching transistor, a driving transistor, and a sensing transistor, a storage capacitor, and a light emitting diode.

When the display device 110 is a liquid crystal display device, each of the plurality of subpixels SP may include a transistor, a storage capacitor, and a liquid crystal capacitor.

The configuration and driving method of the display panel 160 will be described with reference to the drawings.

2A and 2B are diagrams illustrating operations of the p-th and (p+1)-th frames of the display device according to the first embodiment of the present invention, respectively, and will be described with reference to FIG. 1 together.

As shown in FIGS. 2A and 2B , in the display device 110 according to the first embodiment of the present invention, the first gate driver 140 includes the first to rth stages STG1 to STGr (r is an even number). ), and the first transition unit 150 includes a plurality of first transition transistors Tt1 and a plurality of second transition transistors Tt2, and the second transition unit 152 ) includes a plurality of first transition transistors Tt1 and a plurality of second transition transistors Tt2.

The first to rth stages STG1 to STG(r) generate gate voltages using the clock CLK and outputs (gate voltages) of previous or subsequent stages, respectively, and control the generated gate voltages. 1 to rth gate wirings GL1 to GL(r).

For example, the first to rth stages STG1 to STG(r) may be connected in a cascade manner.

The first and second transition transistors Tt1 and Tt2 of the first and second transition units 150 and 152 are switched according to the first and second transition signals TS1 and TS2, respectively, and generate clock signals (CLK) of the gate control signal. ) is transferred to the first to rth stages STG1 to STG(r).

For example, the first and second transition transistors Tt1 and Tt2 of the first transition unit 150 are disposed on top of the first to rth stages STG1 to STG(r), and the second The first and second transition transistors Tt1 and Tt2 of the transition unit 152 are disposed at the bottom of the first to rth stages STG1 to STG(r), and the first and second transition transistors ( Tt1 and Tt2) may be P-type.

The first transition transistor Tt1 of the first transition unit 150 and the second transition transistor Tt2 of the second transition unit 152 are odd-numbered stages, i.e., first, third, ..., (r-) 3), it is connected to the (r-1)th stage (STG1, STG3, ..., STG(r-3), STG(r-1)) to transfer the clock CLK, and the first transition unit 150 The second transition transistor Tt2 of ) and the first transition transistor Tt1 of the second transition unit 152 are even-numbered stages of the second, fourth, (r-2)th, and rth stages STG2 and STG4. , STG(r-2), STG(r)) to transmit the clock (CLK).

The display panel 160 includes first to rth gate wires GL1 to GL(r), first to fourth left data wires DLL1 to DLL4, and first to fourth right data wires DLR1 to DLR4. , contains a plurality of sub-pixels.

The first to rth gate wires GL1 to GL(r) may be connected to output terminals of the first to rth stages STG1 to STG(r), respectively.

Sub-pixels of odd-numbered horizontal pixel columns are connected to the left data line, and sub-pixels of even-numbered horizontal pixel columns are connected to the right data line.

For example, the first to rth sub-pixels SP1 to SP(r) of the first vertical pixel column are connected to the first to rth gate lines GL1 to GL(r), respectively, and the odd-numbered horizontal pixel columns The first, third, ..., (r-3), (r-1)th sub-pixels SP1, SP3, ..., SP(r-3), SP(r-1) are It is connected to the 1st-left data wire (DLL1) and is connected to the 2nd, 4th, ..., (r-2)th (r-2)th, and rth sub-pixels (SP2, SP4, ..., SP(r- 2), SP(r)) may be connected to the first right data line DLR1.

The first and second transition transistors Tt1 and Tt2 of the first and second transition units 150 and 152 are switched according to the first and second transition signals TS1 and TS2, respectively, to generate a top data voltage and a bottom data voltage. is transferred to the first to fourth left data wires DLL1 to DLL4 and the first to fourth right data wires DLR1 to DLR4.

For example, the first and second transition transistors Tt1 and Tt2 of the first transition unit 150 are disposed on top of the plurality of sub-pixels, and the first and second transition transistors Tt1 and Tt2 of the second transition unit 152 are arranged. The two transition transistors Tt1 and Tt2 may be disposed at the bottom of the plurality of sub-pixels.

The first transition transistor Tt1 of the first transition unit 150 and the second transition transistor Tt2 of the second transition unit 152 are connected to the left data line, so that the sub-pixels of the odd-numbered horizontal pixel column have top data voltages, respectively. (DT) and the bottom data voltage (DB), and the second transition transistor Tt2 of the first transition unit 150 and the first transition transistor Tt1 of the second transition unit 152 are connected to the right data line. connected to transfer the top data voltage (DT) and the bottom data voltage (DB) to sub-pixels of even-numbered horizontal pixel columns, respectively.

For example, the first transition transistor Tt1 of the first transition unit 150 and the second transition transistor Tt2 of the second transition unit 152 are connected to the first left data line DLL1 so that the odd-numbered horizontal 1st, 3rd, ..., (r-3)th, (r-1)th sub-pixels (SP1, SP3, ..., SP(r-3), SP(r-1)) of the pixel column The first top data voltage DT1 and the first bottom data voltage DB1 are respectively transferred to the second transition transistor Tt2 of the first transition unit 150 and the first transition transistor Tt2 of the second transition unit 152. The transistor Tt1 is connected to the first right data line DLR1 and is connected to the second, fourth, ..., (r-2)th, rth sub-pixels SP2, SP4, ... of the even-numbered horizontal pixel column. , SP(r-2), and SP(r), respectively, the first top data voltage DT1 and the first bottom data voltage DB1 may be delivered.

As shown in FIG. 2A, the first transition transistor Tt1 of the first and second transition units 150 and 152 according to the low-level first transition signal TS1 during the p-th frame (Fp in FIG. 3) is turned on, and according to the high level second transition signal TS2, the second transition transistors Tt2 of the first and second transition units 150 and 152 are turned off. off).

Accordingly, the first, third, ..., (r-3), (r-1)th stages (STG1, STG3, ..., STG( r-3) and STG(r-1)), the clock CLK is transferred, and the first, third, ..., (r-3), (r-1)th stages STG1, STG3, ..., STG(r-3), STG(r-1)) are the first, third, ..., (r-3)th (r-3)th, (r- 1) Delivered to the gate wires (GL1, GL3, ..., GL(r-3), GL(r-1)).

In addition, the even-numbered stages from the bottom of the display panel 160, r, th (r-2), ..., 4th, and 2nd stages (STG(r), STG(r-2), ... , STG4, STG2), the clock CLK is transmitted to the rth, stg (r-2), ..., fourth, and second stages (STG(r), STG(r-2), .. ., STG4, STG2) sequentially generate low-level pulses of gate voltages r, th (r-2), ..., 4th, and 2nd gate wires (GL(r), GL(r-2) , ..., GL4, GL2).

Therefore, the first tower data voltage DT1 from the top of the display panel 160 passes through the first left data line DLL1 to the first, third, ..., (r-3)th (r-3) odd-numbered horizontal pixel columns. , is sequentially transferred to the (r−1)th subpixels SP1, SP3, ..., SP(r−3), and SP(r−1), and the first bottom data from the bottom of the display panel 160 The voltage DB1 is applied to the rth, (r-2), ..., fourth, and second subpixels SP(r) and SP(r) of the even-numbered horizontal pixel column through the first right data line DLR1. -2), ..., SP4, SP2) are sequentially delivered.

As shown in FIG. 2B, the first and second transition units 150 and 152 according to the high level first transition signal TS1 during the (p+1)th frame (F(p+1) in FIG. 3) The first transition transistor Tt1 of ) is turned off, and the second transition transistors Tt2 of the first and second transition parts 150 and 152 are turned off according to the low level second transition signal TS2. come on

Accordingly, the second, fourth, ..., (r-2)th, and rth stages (STG2, STG4, ..., STG(r-2)), which are even-numbered stages from the top of the display panel 160 , STG (r)), the clock (CLK) is transferred, and the second, fourth, ..., (r-2), rth stages (STG2, STG4, ..., STG (r-2)) , STG(r)) sequentially transmits low-level pulses of the gate voltage to the second, fourth, ..., (r-2)th, and rth gate wirings GL2, GL4, ..., GL(r -2), forwarded to GL(r)).

Further, odd-numbered stages from the bottom of the display panel 160 (r-1), (r-3), ..., third, and first stages (STG(r-1), STG(r-1) 3), ..., STG3, STG1)), the clock CLK is transmitted, and the (r-1)th (r-3), ..., third, first stages (STG(r- 1), STG(r-3), ..., STG3, STG1) sequentially transmit low-level pulses of the gate voltage to the (r-1), (r-3), ..., 3rd, It is transmitted to the first gate wires GL(r-1), GL(r-3), ..., GL3, GL1.

Therefore, the first tower data voltage DT1 from the top of the display panel 160 passes through the first right data line DLR1 to the second, fourth, ..., (r-2)th (r-2) even-numbered horizontal pixel columns. , is sequentially transmitted to the r-th sub-pixels SP2, SP4, ..., SP(r-2), SP(r), and the first bottom data voltage DB1 from the bottom of the display panel 160 is The (r-1), (r-3), ..., 3rd, and 1st sub-pixels (SP(r-1), SP(r) of the odd-numbered horizontal pixel column through the 1st-left data wire (DLL1) -3), ..., SP3, SP1) are sequentially delivered.

Here, since the top and bottom data voltages DT and DB are applied from the top and bottom of the display panel 160, the vertical resolution is reduced by half, so that it can be applied to a high-resolution portrait mode and high-speed driving of 120 Hz or more is possible.

The configuration and driving timing of each sub-pixel SP of the display panel 160 will be described with reference to the drawings.

3 is a diagram showing sub-pixels of a display device according to the first embodiment of the present invention, and FIG. 4 is a timing diagram showing a plurality of signals of the display device according to the first embodiment of the present invention. , will be described with reference to FIGS. 2A and 2B together.

As shown in FIG. 3 , the n-th sub-pixel SP(n) (n is one of 1 to r) of the display panel 160 of the display device 110 according to the first embodiment of the present invention It includes first to tenth transistors T1 to T10, a storage capacitor Cst, and a light emitting diode Del.

For example, the first to tenth transistors T1 to T10 may be P-type.

The first transistor (T1), which is a switching transistor, is switched according to the nth gate voltage (S(n)) and receives the top data voltage (DT) or the bottom data voltage (DB) through the left or right data lines (DLL, DLR). ) is transmitted as the data voltage (Vdata). The gate electrode of the first transistor (T1) receives the n-th gate voltage (S(n)) of the n-th gate line, and the source electrode of the first transistor (T1) is connected to the left or right data lines (DLL, DLR). and the drain electrode of the first transistor T1 is connected to the source electrodes of the second and fourth transistors T2 and T4.

The driving transistor, the second transistor T2, is switched according to the voltage of the first electrode of the storage capacitor Cst. The gate electrode of the second transistor T2 is connected to the first electrode of the storage capacitor Cst, the drain electrode of the fifth transistor T5 and the source electrode of the eighth transistor T8, and The source electrode is connected to the drain electrode of the first transistor T1 and the source electrode of the fourth transistor T4, and the drain electrode of the second transistor T2 is connected to the source electrodes of the third and fifth transistors T3 and T5. connected to

The third transistor T3 is switched according to the nth emission voltage Em(n). The gate electrode of the third transistor T3 receives the n-th emission voltage Em(n), and the source electrode of the third transistor T3 is connected to the drain electrode of the second transistor T2 and the fifth transistor T5. is connected to the source electrode of the third transistor T3, and the drain electrode of the third transistor T3 is connected to the source electrode of the sixth transistor T6 and the anode of the light emitting diode Del.

The fourth transistor T4 is switched according to the nth emission voltage Em(n). The gate electrode of the fourth transistor T4 receives the n-th emission voltage Em(n), and the source electrode of the fourth transistor T4 is connected to the drain electrode of the first transistor T1 and the second transistor T2. The drain electrode of the fourth transistor T4 receives the high potential voltage VDD and is connected to the source electrode of the seventh transistor T7.

The fifth transistor T5 is switched according to the nth gate voltage S(n). The gate electrode of the fifth transistor T5 receives the n-th gate voltage S(n), and the source electrode of the fifth transistor T5 connects to the drain electrode of the second transistor T2 and the third transistor T3. can be connected to the source electrode of Also, the drain electrode of the fifth transistor T5 is connected to the gate electrode of the second transistor T2, the first electrode of the storage capacitor Cst, and the source electrode of the eighth transistor T8.

The sixth transistor T6 may be switched according to the nth gate voltage Scan(n). The gate electrode of the sixth transistor T6 receives the nth gate voltage Scan(n), and the source electrode of the sixth transistor T6 is connected to the drain electrode of the third transistor T3 and the light emitting diode Del. connected to the anode, and the drain electrode of the sixth transistor T6 receives the initial voltage Vini and is connected to the drain electrode of the eighth transistor T8.

The seventh transistor T7 is switched according to the nth emission voltage Em(n). The gate electrode of the seventh transistor T7 receives the n-th emission voltage Em(n), the source electrode of the seventh transistor T7 receives the high potential voltage VDD, and the seventh transistor T7 The drain electrode of is connected to the second electrode of the storage capacitor Cst and the source electrodes of the ninth and tenth transistors T9 and T10.

The eighth transistor T8 is switched according to the (n−1)th gate voltage S(n−1). The gate electrode of the eighth transistor T8 receives the (n-1)th gate voltage S(n-1), the source electrode of the eighth transistor T8 is the first electrode of the storage capacitor Cst, It is connected to the gate electrode of the second transistor T2 and the drain electrode of the fifth transistor T5, and the drain electrode of the eighth transistor T8 receives the initial voltage Vini and is connected to the drain electrode of the sixth transistor T6. connected to

The ninth transistor T9 is switched according to the nth gate voltage S(n). The gate electrode of the ninth transistor T9 receives the n-th gate voltage S(n), and the source electrode of the ninth transistor T9 connects the second electrode of the storage capacitor Cst and the seventh transistor T7. is connected to the drain electrode of the ninth transistor T9, and the drain electrode of the ninth transistor T9 receives the reference voltage Vref.

The tenth transistor T10 is switched according to the (n−1)th gate voltage S(n−1). The gate electrode of the tenth transistor T10 receives the (n−1)th gate voltage S(n−1), and the source electrode of the tenth transistor T10 receives the second electrode and the second electrode of the storage capacitor Cst. It is connected to the drain electrode of the seventh transistor T7, and the drain electrode of the tenth transistor T10 receives the reference voltage Vref.

The light emitting diode Del is connected between the third transistor T3 and the low potential voltage VSS, and emits light with luminance proportional to the current of the second transistor T2.

Here, the source electrode of the second transistor T2 constitutes the first node N1, the gate electrode of the second transistor and the first electrode of the storage capacitor Cst constitute the second node N2, and The second electrode of the capacitor Cst constitutes a third node N3.

According to the operation of the first to tenth transistors T1 to T10 and the storage capacitor Cst, the light emitting diode Del emits light to display an image. The display device 110 may compensate for threshold voltage fluctuations or deterioration of light emitting diodes according to use time by using sub-pixels, and drive light emitting diodes Del according to a duty ratio corresponding to light emission time. You can adjust the luminance.

As shown in FIG. 4, during the pth and (p+1)th frames Fp and F(p+1), the first and second data drivers 130 and 132 respectively generate the top data voltage DT and a bottom data voltage (DB).

During the pth frame Fp, the first and second transition signals TS1 and TS2 have a low level and a high level, respectively, and during the (p+1)th frame F(p+1), the first and second transition signals TS1 and TS2 have a low level and a high level. The transition signals TS1 and TS2 have a high level and a low level, respectively.

That is, the first and second transition signals TS1 and TS2 have values opposite to each other among a low level and a high level, and each has a low level and a high level alternately in a cycle of one frame.

Accordingly, during the p-th frame Fp, the first transition transistors Tt1 of the first and second transition parts 150 and 152 are turned on and the second transition transistors Tt2 are turned off, and the second ( During the p+1 frame (F(p+1)), the first transition transistors Tt1 of the first and second transition parts 150 and 152 are turned off and the second transition transistors Tt2 are turned on. do.

Here, since the first and second transition transistors Tt1 and Tt2 maintain on and off states for one frame, the charging time of the data voltage can be secured at least 2 horizontal cycles (2H), and DC due to kickback And it is possible to prevent the luminance deviation caused by the variation (ripple) of the AC data voltage.

The pth and (p+1)th frames Fp and F(p+1) include the first, second, and third time intervals TP1, TP2, and TP3, respectively.

During the first time period TP1, which is the initialization period of the pth and (p+1)th frames (Fp, F(p+1)) corresponding to the second horizontal period (2H), the (n−1)th gate voltage (S(n−1)) has a low level, and the nth gate voltage S(n) and the nth emission voltage Em(n) each have a high level.

Accordingly, during the first time period TP1, the eighth and tenth transistors T8 and T10 are turned on, and the first, third, fourth, fifth, sixth, seventh, and ninth transistors are turned on. (T1, T3, T4, T5, T6, T7, T9) are turned off, the second node (N2) is charged with the initial voltage (Vini) and the third node (N3) is charged with the reference voltage (Vref) do.

During the second time period TP2, which is the sampling period of the pth and (p+1)th frames (Fp, F(p+1)) corresponding to the second horizontal period (2H), the (n−1)th gate voltage (S(n−1)) and the nth light emitting voltage Em(n) each have a high level, and the nth gate voltage S(n) has a low level.

Accordingly, during the second time period TP2, the first, fifth, sixth, and ninth transistors T1, T5, T6, and T9 are turned on, and the third, fourth, seventh, and eighth transistors are turned on. , the tenth transistors T3, T4, T7, T8, and T10 are turned off so that the first node N1 is charged with the data voltage Vdata and the second node N2 is charged with the data voltage Vdata and the threshold It is charged with the sum (Vdata+Vth) of the voltage Vth, and the third node N3 is maintained at the reference voltage Vref.

Here, the first and second gate driving units 140 and 142 apply a gate voltage from both ends of the gate line GL, and an RC load connected to the first and second gate driving units 140 and 142, respectively, is Since it is reduced by half, it is possible to improve the output of the first and second gate drivers 140 and 142 and secure a sampling period of 2 horizontal hours or more.

During the third time period TP3, which is the holding period of the p and (p+1)th frames (Fp, F(p+1)), the (n-1)th gate voltage (S(n-1)), The nth gate voltage S(n) and the nth emission voltage Em(n) each have a high level.

Accordingly, during the third time period TP3, the first, third, fourth, fifth, sixth, seventh, eighth, ninth, and tenth transistors T1, T3, T4, T5, T6, T7, T8, T9, and T10 are turned off, and the second node N2 is maintained at the sum (Vdata+Vth) of the data voltage Vdata and the threshold voltage Vth.

During the fourth time period TP4, which is the emission period of the p and (p+1)th frames (Fp, F(p+1)), the (n−1)th gate voltage (S(n−1)) and Each of the nth gate voltages S(n) has a high level, and the nth light emitting voltage Em(n) has a low level.

Accordingly, during the fourth time period TP4, the third, fourth, and seventh transistors T3, T4, and T7 are turned on, and the first, fifth, sixth, eighth, ninth, and ninth transistors are turned on. 10 The transistors T1, T5, T6, T8, T9, and T10 are turned off, the first node N2 is charged with the high potential voltage VDD, and the second node N2 has the data voltage Vdata. and the sum (Vdata+Vth) of the threshold voltage (Vth) plus the difference (VDD-Vref) between the high potential voltage (VDD) and the reference voltage (Vref) (VDD-Vref+Vdata+Vth).

Here, since a current proportional to the square of the value (-Vref + Vdata) obtained by subtracting the threshold voltage (Vth) from the gate-source voltage (Vgs) flows through the second transistor (T2), the high potential voltage (VDD) and the threshold voltage Variations in (Vth) are compensated for.

As described above, in the display device 110 according to the first embodiment of the present invention, since the first and second transition transistors Tt1 and Tt2 maintain on and off states for one frame, the charging time of the data voltage is reduced. It can be secured at least 2 horizontal cycles (2H), and it is possible to prevent the occurrence of luminance deviation due to the variation (ripple) of DC and AC data voltages caused by kickback.

Further, the first and second gate driving units 140 and 142 apply a gate voltage from both ends of the gate line GL, and an RC load connected to the first and second gate driving units 140 and 142, respectively, Since it is reduced by half, it is possible to improve the output of the first and second gate drivers 140 and 142 and secure a sampling period of 2 horizontal hours or more.

In addition, since the first and second data drivers 130 and 132 apply the data voltage from both ends of the data lines DLL and DLR, the vertical resolution is reduced by half, so that it can be applied to a high-resolution portrait mode and is driven at a speed of 120Hz or higher. this becomes possible

In addition, by forming the first and second gate drivers 140 and 142 of the GIP type instead of the integrated circuit (IC) on the long side of the display panel 160, the degree of freedom in design, such as curvature restriction, is improved and the cross-section of the flexible display device is improved. A multi-curve display device that is curved in an S-shape may be implemented.

In addition, by forming the gate line GL made of relatively low ductility molybdenum (Mo) parallel to the short side of the display panel 160, the gate line GL is parallel to the short side of the display panel 160 and is parallel to the long side of the display panel 160. When the display panel 160 is folded based on a folding axis passing through the central portion, the relatively high rigidity of the gate lines GL is disposed parallel to the folding axis, thereby improving folding reliability.

In addition, since the first and second data drivers 130 and 132 are connected to the short side of the display panel 160, an increase in circuit components (COF, etc.) due to an increase in resolution is prevented, thereby preventing an increase in manufacturing cost.

In another embodiment, a display device may have a landscape mode, which will be described with reference to the drawings.

5 is a view showing a display device according to a second embodiment of the present invention. The display device according to the second embodiment may be an organic light emitting diode display device (OLED display device), The long side of the display panel may be used in a landscape mode in which the long side is disposed along the horizontal direction, and descriptions of the same parts as those of the first embodiment are omitted.

As shown in FIG. 5, the display device 210 according to the second embodiment of the present invention includes a timing controller 220, first and second data driver units 230 and 232, and first and second gate driver units. 240 and 242 , first and second transition units 250 and 252 , and a display panel 260 .

The timing controller 220 uses a video signal transmitted from an external system (not shown) such as a graphic card or a TV system, a data enable signal, a horizontal sync signal, a vertical sync signal, and a plurality of timing signals such as a clock to display an image. Data, data control signals and gate control signals can be generated. Then, the generated image data and data control signals are transferred to the first and second data drivers 230 and 232 , and the generated gate control signals are transferred to the first and second gate drivers 240 and 242 .

The first and second data drivers 230 and 232 respectively generate a left data voltage (left data signal) and a right data voltage (right data signal) using the data control signal and image data transmitted from the timing controller 220. generated, and the generated left data voltage and right data voltage are applied to the top and bottom data lines DLT and DLB of the display panel 260 .

The first and second gate drivers 240 and 242 generate a gate voltage (gate signal) using the gate control signal transmitted from the timing controller 220, and use the generated gate voltage to the gate of the display panel 160. When applied to the wiring GL, the first and second gate drivers 240 and 242 may output the same gate voltage at the same timing.

Here, the first and second gate drivers 240 and 242 are together with the substrate of the display panel 260 on which the gate lines GL, top and bottom data lines DLT and DLB, and sub-pixels SP are formed. The formed gate-in-panel (GIP) type may be formed.

The first and second transition units 250 and 252 transfer the gate control signal including the clock received from the timing control unit 220 to the first and second gate driving units 240 and 242, respectively, and The left and right data voltages received from the second data drivers 230 and 232 are selectively transmitted to one of the top and bottom data lines DLT and DLB.

Here, the first and second transition units 250 and 252 are disposed corresponding to the two short sides of the display panel 260, respectively, and the first and second gate driving units 240 and 242, top and bottom data, respectively. It is connected to both ends of the wires DLT and DLB. The first and second transition units 250 and 252 each include a plurality of transition transistors.

The display panel 260 displays an image using a gate voltage, a left data voltage, and a right data voltage. The display panel 260 includes a plurality of sub-pixels (SP), a plurality of gate lines (GL), a plurality of top data lines (DLT), and a plurality of bottom data lines (DLB) arranged in a display area to display an image. include

The display panel 260 has a rectangular shape, and an example in which two long sides and two short sides of the display panel 260 are disposed along the X axis and the Y axis will be described as an example.

Each of the plurality of sub-pixels SP may be one of red, green, and blue sub-pixels, and the red, green, and blue sub-pixels may constitute one pixel. Also, the gate line GL may cross the top data line DLT and the bottom data line DLB to define the sub-pixel SP.

Here, the top and bottom data lines DLT and DLB are disposed above and below the sub-pixel SP, respectively, and each sub-pixel SP is connected to one of the top and bottom data lines DLT and DLB. Specifically, the qth sub-pixel SP(q) (q is an odd number) of the odd-numbered vertical pixel column is connected to the gate line GL and the top data line DLT, and the even-numbered vertical pixel column (q+1 ) The sub-pixel SP(q+1) may be connected to the gate line GL and the bottom data line DLB.

When the display device 210 is an organic light emitting diode display, each of the plurality of subpixels SP may include a plurality of transistors such as a switching transistor, a driving transistor, and a sensing transistor, a storage capacitor, and a light emitting diode.

When the display device 210 is a liquid crystal display device, each of the plurality of subpixels SP may include a transistor, a storage capacitor, and a liquid crystal capacitor.

As described above, in the display device 210 according to the second embodiment of the present invention, since the first and second transition transistors maintain on and off states for one frame, the charging time of the data voltage is set to two horizontal cycles (2H). ) or more, and it is possible to prevent the occurrence of luminance deviation due to the variation (ripple) of DC and AC data voltages caused by kickback.

In addition, the first and second gate driving units 240 and 242 apply a gate voltage from both ends of the gate line GL, and an RC load connected to the first and second gate driving units 240 and 242, respectively, Since it is reduced by half, it is possible to improve the output of the first and second gate drivers 240 and 242 and secure a sampling period of 2 horizontal hours or more.

In addition, by forming the first and second gate drivers 240 and 242 of the GIP type instead of the integrated circuit (IC) on the long side of the display panel 260, the degree of freedom in design such as curvature restriction is improved, so that the cross section of the flexible display device is improved. A multi-curve display device that is curved in an S-shape may be implemented.

In addition, by forming the gate line GL made of relatively low ductility molybdenum (Mo) parallel to the short side of the display panel 160, it is parallel to the short side of the display panel 160 and the long side of the display panel 160. When the display panel 160 is folded based on a folding axis passing through the central portion, the relatively high rigidity of the gate lines GL is disposed parallel to the folding axis, thereby improving folding reliability.

In addition, since the first and second data drivers 230 and 232 are connected to the short side of the display panel 260, an increase in circuit components (COF, etc.) due to an increase in resolution is prevented, thereby preventing an increase in manufacturing cost.

Although the above has been described with reference to preferred embodiments of the present invention, those skilled in the art will variously modify and change the present invention within the scope not departing from the technical spirit and scope of the present invention described in the claims below. You will understand that it can be done.

110: display device 120: timing control unit
130, 132: first and second data driver 140, 142: first and second gate driver
150, 152: first and second transition units 160: display panel

Claims (12)

a timing controller for generating image data, a data control signal, and a gate control signal;
first and second data drivers which respectively generate first and second data voltages using the image data and the data control signal;
a first gate driver generating a gate voltage using the gate control signal;
A plurality of sub-pixels, a gate line for transmitting the gate voltage to the plurality of sub-pixels, a first data line arranged on a first side of each of the plurality of sub-pixels, and a second line of each of the plurality of sub-pixels. a display panel including a second data line disposed on a side thereof;
a first transition unit connected to the first end of the first gate driver, the first end of the first data line, and the first end of the second data line, and including first and second transition transistors;
A second transition part connected to a second end of the first gate driver, a second end of the first data line, and a second end of the second data line, and including the first and second transition transistors.
A display device including a.
According to claim 1,
The first and second transition transistors are switched according to the first and second transition signals, respectively;
The first and second transition signals have values opposite to each other among a low level and a high level, and alternately have the low level and the high level in a cycle of one frame.
According to claim 1,
The first gate driver includes a plurality of stages,
The first transition transistor of the first transition part and the second transition transistor of the second transition part are connected to odd-numbered stages among the plurality of stages;
The second transition transistor of the first transition part and the first transition transistor of the second transition part are connected to even-numbered stages among the plurality of stages.
According to claim 1,
The first transition transistor of the first transition part and the second transition transistor of the second transition part are connected to odd-numbered sub-pixels among the plurality of sub-pixels;
The second transition transistor of the first transition part and the first transition transistor of the second transition part are connected to even-numbered sub-pixels among the plurality of sub-pixels.
According to claim 1,
The first transition transistor of the first transition unit and the second transition transistor of the second transition unit are connected to the first data wire,
The second transition transistor of the first transition part and the first transition transistor of the second transition part are connected to the second data line.
According to claim 5,
The first data line is connected to odd-numbered sub-pixels among the plurality of sub-pixels, and the second data line is connected to even-numbered sub-pixels among the plurality of sub-pixels.
According to claim 1,
The display device further comprises a second gate driver that generates the gate voltage using the gate control signal and is disposed opposite to the first gate driver.
According to claim 1,
The first and second data drivers are respectively disposed on two short sides of the display panel.
According to claim 1,
The display device of claim 1 , wherein the display panel is folded based on a folding axis parallel to a short side of the display panel.
first and second data drivers for generating first and second data voltages, respectively;
first and second gate drivers generating gate voltages;
a display panel including a plurality of sub-pixels, a gate line, a first data line connected to an odd-numbered sub-pixel among the plurality of sub-pixels, and a second data line connected to an even-numbered sub-pixel among the plurality of sub-pixels;
A first transition unit connected to first ends of the first and second gate drivers, a first end of the first data line, and a first end of the second data line, and including first and second transition transistors. and;
The second transition is connected to the second terminal of the first and second gate drivers, the second terminal of the first data line, and the second terminal of the second data line, and includes the first and second transition transistors. wealth
A display device including a.
generating image data, data control signals and gate control signals;
generating first and second data voltages using the image data and the data control signal;
generating a gate voltage using the gate control signal;
During the p-th frame, the first data voltage is transferred to the first data line through the first transition transistor of the first transition unit, and the second data voltage is transferred to the second data line through the second transition transistor of the second transition unit. delivering;
During the (p+1)th frame, the first data voltage is transmitted to the second data line through the second transition transistor of the first transition unit, and the first data voltage is transferred to the second data line through the first transition transistor of the second transition unit. transferring 2 data voltages to the first data line;
Displaying an image using the first and second data voltages and the gate voltage
A method of driving a display device comprising a.
According to claim 11,
The first and second transition transistors are switched according to the first and second transition signals, respectively;
The first and second transition signals have values opposite to each other among a low level and a high level, and alternately have the low level and the high level at a period of one frame, respectively.

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