KR20230072363A - Storage device and mehtod of operating storage device - Google Patents

Abstract

According to the present invention, a storage device comprises a non-volatile memory device and a storage controller. The non-volatile memory device includes a first memory area having a first writing speed and a second memory area having a second writing speed slower than the first writing speed. In addition, the storage controller reads a first unit of second data pre-stored in the first memory area and performs a read-transfer operation of providing the read first unit of data to a data input and output circuit of the non-volatile memory device a plurality of times, and controls a data migration operation so that the second data provided to the data input and output circuit is stored in the second memory area. Accordingly, a size of the storage controller can be reduced by reducing a size of an internal buffer.

Description

Storage device and method of operating the storage device {STORAGE DEVICE AND MEHTOD OF OPERATING STORAGE DEVICE}

The present invention relates to a semiconductor integrated circuit, and more particularly, to a storage device and a method of operating the storage device.

Semiconductor memory devices are largely classified into volatile memory devices and nonvolatile memory devices.

A volatile memory device is a memory device in which stored data is lost when power supply is cut off. On the other hand, non-volatile memory devices retain their contents even when power supply is interrupted. Therefore, non-volatile memory devices are used to store contents to be preserved regardless of whether power is supplied or not. A flash memory device, which is one of nonvolatile memory devices, has advantages such as low noise, low power consumption, and high operating speed, and thus is used in various fields. For example, mobile systems such as smart phones and tablet PCs use large-capacity flash memory devices as storage media.

When a storage device including a non-volatile memory device and a storage controller is used in a mobile device, techniques for reducing the size of the storage controller are being developed.

One object of the present invention is to provide a storage device capable of reducing the size of a storage controller.

One object of the present invention is to provide a method of operating a storage device capable of reducing the size of a storage controller.

A storage device according to embodiments of the present invention for achieving the above object includes a non-volatile memory device and a storage controller. The nonvolatile memory device includes a first memory area having a first write speed and a second memory area having a second write speed lower than the first write speed. The storage controller performs a plurality of read-and-transfer operations of reading second data pre-stored in the first memory area by a first unit and providing the read first unit of data to a data input/output circuit of the nonvolatile memory device. and controls a data migration operation so that the second data provided to the data input/output circuit is stored in the second memory area.

A non-volatile memory device having a first memory area having a first write speed and a second memory area having a second write speed slower than the first write speed according to embodiments of the present invention for achieving the above object; and In the operating method of a storage device including a storage controller controlling the non-volatile memory device, the storage controller receives first data from an external host, and the storage controller receives second data pre-stored in the first memory area. by a first unit, and performing a read-and-transfer operation of providing the read first unit of data to a data input/output circuit of the nonvolatile memory device a plurality of times, and the nonvolatile memory device performs the data input/output circuit. The second data provided to the circuit is programmed into the second memory area.

A storage device according to embodiments of the present invention for achieving the above object includes a non-volatile memory device and a storage controller. The nonvolatile memory device includes a first memory area having a first write speed and a second memory area having a second write speed lower than the first write speed. The storage controller preferentially stores first data provided from the outside in the first memory area in a first mode and includes an internal buffer. The storage controller performs a plurality of read-and-transfer operations of reading second data pre-stored in the first memory area by a first unit and providing the read first unit of data to a data input/output circuit of the nonvolatile memory device. and controls a data migration operation so that the second data provided to the data input/output circuit is stored in the second memory area. The storage controller includes a processor, a program/migration manager and an error correction code (ECC) engine. The processor determines a write mode related to the first data as one of the first mode and a second mode for storing the first data in the second memory area based on a write request related to the first data. The program/migration manager controls the program operation and the data migration operation based on the control of the processor. The ECC engine corrects errors in the read first unit data by performing ECC decoding on the read first unit data.

In the storage device and method of operating the storage device according to embodiments of the present invention, when first data is to be programmed in a first memory area having a high write speed, second data pre-stored in the first memory area is stored inside the storage controller. After sequentially moving the data to the buffer, a data migration operation may be performed in which the second data is programmed into a second memory area having a second write speed slower than the first write speed. Since the data storage capacity of the internal buffer may be smaller than the data storage capacity of the first memory area, the size of the storage controller may be reduced by reducing the size of the internal buffer.

1 is a block diagram illustrating a storage system according to example embodiments.
2 is a block diagram illustrating the host of FIG. 1 according to embodiments of the present invention.
FIG. 3 is a block diagram illustrating a configuration of a storage controller in the storage device of FIG. 1 according to example embodiments.
FIG. 4A is a block diagram illustrating a connection between a storage controller and one nonvolatile memory device in the storage device of FIG. 1 .
Figure 4b shows the processor and program/migration manager in Figure 4a.
4C is a timing diagram for explaining an operation of the storage device of FIG. 4A.
5 is a block diagram illustrating the non-volatile memory device of FIG. 4A according to example embodiments.
FIG. 6 is a block diagram illustrating a memory cell array in the nonvolatile memory device of FIG. 5 .
FIG. 7A is a circuit diagram illustrating one memory block among the memory blocks of FIG. 6 .
FIG. 7B is a perspective view illustrating one memory block among the memory blocks of FIG. 6 .
7C is a plan view illustrating one memory block among the memory blocks of FIG. 6 .
8 shows an example of a structure of one NAND string of the memory block of FIG. 7A.
9 illustrates threshold voltage distributions of memory cells in a first memory area and threshold voltage distributions of second memory cells in a second memory area.
10 and 11 are block diagrams each illustrating an example of the memory cell array of FIG. 5 according to example embodiments.
12 and 13 show that the storage device of FIG. 4 performs a write operation in a first mode and a second mode, respectively.
14 illustrates that the storage device of FIG. 4 performs a data migration operation in a first mode.
15A illustrates an operation sequence of the storage device of FIG. 14 according to embodiments of the present invention.
15B shows another example of an operation sequence in the first mode of the storage device of FIG. 14 according to embodiments of the present invention.
16 illustratively illustrates the memory cell array of FIG. 5 according to embodiments of the present invention.
17 and 18 are diagrams for explaining the turbo write buffer type of FIG. 16 .
19 is a flowchart illustrating an operation of the storage system of FIG. 1 as an example.
FIG. 20 is a block diagram showing a physical storage space of the storage device of FIG. 1 as an example.
21 is a flowchart illustrating a method of operating a storage device according to example embodiments.
22 is a cross-sectional view illustrating a nonvolatile memory device according to example embodiments.
23 is a block diagram illustrating an electronic system including a semiconductor device according to example embodiments.
24 is a block diagram illustrating a storage system according to example embodiments.
25 shows a conceptual diagram to which an embodiment of the present invention is applied to a storage system.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in more detail. The same reference numerals are used for the same components in the drawings, and redundant descriptions of the same components are omitted.

1 is a block diagram illustrating a storage system according to example embodiments.

Referring to FIG. 1 , a storage system 50 may include a host 100 and a storage device 200 . The host 100 includes a storage interface 140 .

The storage device 200 of FIG. 1 may be any type of storage device capable of storing data.

The storage device 200 includes a storage controller 300, a plurality of nonvolatile memory devices (400a to 400k, where k is a natural number greater than or equal to 2), a power management integrated circuit (hereinafter 'PMIC', 600), and a host interface 240. can include The host interface 240 may include a signal connector 241 and a power connector 243 . The storage device 200 may further include a buffer memory (BM) 250 .

The plurality of nonvolatile memory devices 400a to 400k are used as storage media of the storage device 200 . Each of the nonvolatile memory devices 400a to 400k may be implemented as a flash memory or a vertical NAND memory device. The storage controller 300 is connected to each of the non-volatile memory devices 400a to 400k through a plurality of channels CHK1 to CHk.

The storage controller 300 receives a request REQ from the host 100 through the signal connector 241 and transmits and receives data DTA with the host 100 . The storage controller 300 writes data DTA into the nonvolatile memory devices 400a to 400k based on the request REQ received from the host 100 or data from the nonvolatile memory devices 400a to 400k. (DTA) is read.

In this case, the storage controller 300 may transmit and receive data DTA with the host 100 by using the buffer memory 250 as an input/output buffer. In one embodiment, the buffer memory 250 may include Dynamic Random Access Memory (DRAM).

The PMIC 600 may receive a plurality of power supply voltages (or external power supply voltages, VES1 to VESt) from the host 100 through the power connector 243 . For example, the power connector 243 includes a plurality of power lines P1 to Pt, and the PMIC 600 receives power voltages VES1 to Pt from the host 100 through the power lines P1 to Pt. VESt) can be received respectively. Here, t represents a positive integer of 2 or more.

The PMIC 600 provides at least one first operating voltage VOP1 necessary for the operation of the storage controller 300 and necessary for the operation of the nonvolatile memory devices 400a to 400k based on the power supply voltages VES1 to VESt. At least one second operating voltage VOP2 and at least one third operating voltage VOP3 necessary for the operation of the buffer memory 250 may be generated.

For example, when the PMIC 600 receives all of the power supply voltages VES1 to VESt from the host 100, it generates at least one first operating voltage VOP1 by using all of the power supply voltages VES1 to VESt. , at least one second operating voltage VOP2 , and at least one third operating voltage VOP3 may be generated. On the other hand, when the PMIC 500 receives only some of the power supply voltages VES1 to VESt from the host 100, it uses all of the received power supply voltages to generate at least one first operating voltage VOP1, At least one second operating voltage VOP2 and at least one third operating voltage VOP3 may be generated.

2 is a block diagram illustrating the host of FIG. 1 according to embodiments of the present invention.

Referring to FIG. 2 , the host 100 includes a central processing unit (CPU) 110, a ROM 120, a main memory 130, a storage interface 140, a user interface 150, and a bus ( 160) may be included.

The bus 160 means a transmission path for transferring data between the CPU 110, the ROM 120, the main memory 130, the storage interface 140, and the user interface 150 of the host 100. Various application programs are stored in the ROM 120 . In the embodiment, application programs supporting storage protocols such as ATA (Advanced Technology Attachment), SCSI (Small Computer System Interface), eMMC (embedded Multi Media Card), UFS (Unix File System), etc. are stored in the ROM 120 It can be.

Data or programs may be temporarily stored in the main memory 130 . The user interface 150 includes physical hardware and logical software as a physical or virtual medium capable of exchanging information between a user, a host device, and a computer program. That is, the user interface 150 may include an input device through which a user can manipulate the host 100 and an output device displaying a result of processing a user input.

The CPU 110 controls overall operations of the host 100 . The CPU 110 requests (or commands) to store data in the storage device 200 or reads data from the storage device 200 using an application or tool stored in the ROM 120. Commands and power supply voltages VES1 to VESt may be generated and transmitted to the storage device 200 through the storage interface 140 .

FIG. 3 is a block diagram illustrating a configuration of a storage controller in the storage device of FIG. 1 according to example embodiments.

Referring to FIG. 3 , the storage controller 300 includes a processor 310, an error correction code (ECC) engine 320, and an on-chip memory 330 connected to each other through a bus 305. ), a randomizer 340, a host interface 350, a ROM 360, an internal buffer 380, and a memory interface 370.

The processor 310 controls overall operations of the storage controller 300 . The processor 310 may control the on-chip memory 330 , the ECC engine 320 , the randomizer 340 , the internal buffer 380 and the memory interface 370 .

Processor 310 may include one or more cores (eg, homogeneous multi-core or heterogeneous multi-core). For example, the processor 310 may include a central processing unit (CPU), an image signal processing unit (ISP), a digital signal processing unit (DSP), a graphics processing unit (GPU), a vision processing unit (VPU), and a neural processing unit (NPU). Processing Unit) may include at least one. The processor 310 may execute various application programs (eg, a Flash Translation layer (FTL), hereinafter referred to as 'FTL'), firmware, etc.) loaded in the on-chip memory 330 .

The on-chip memory 330 may store various application programs executed by the processor 310 . The on-chip memory 330 may operate as cache memory adjacent to the processor 310 . The on-chip memory 330 may store commands, addresses, data, etc. to be processed by the processor 310 or may store processing results of the processor 310 . For example, the on-chip memory 330 includes a latch, a register, a static random access memory (SRAM), a dynamic random access memory (DRAM), a thyristor random access memory (TRAM), and a tightly coupled TCM (tightly coupled memory). Memory) or the like, or a working memory.

The processor 310 may execute the FTL 335 loaded into the on-chip memory 330 .

The FTL 335 may be loaded into the on-chip memory 330 as firmware or a program stored in one of the non-volatile memory devices 400a to 400k. The FTL 335 may include an address mapping table manager that manages and updates mapping between logical addresses and physical addresses of the nonvolatile memory devices 400a to 400k. In addition to the aforementioned address mapping, the FTL 335 may further perform garbage collection, wear leveling, and the like. The FTL 335 has limitations of the non-volatile memory devices 400a to 400k (eg, overwrite or in-place write not possible, lifespan of a memory cell, limited P/E (Program-Erase) cycle, erase speed is slower than write speed, etc.).

In particular, the FTL 335 stores program/erase cycle information of the first memory area and the second memory area of each of the nonvolatile memory devices 400a to 400k, the number of free blocks in the first memory area and the second memory area. and at least one of data retention time information of the first memory area and the second memory area may be stored and the stored information may be provided to the processor 310 as status information sinf.

The processor 310 may execute the program/migration manager 331 loaded in the on-chip memory 330 .

The program/migration manager 331 is a valid area capable of storing data of the first memory area of the target nonvolatile memory device among the nonvolatile memory devices 400a to 400k in the first mode under the control of the processor 310 . When the size of is smaller than the size of the first data to be programmed, the second data pre-stored in the first memory area is read by a first unit corresponding to the data storage capacity of the internal buffer 380, and the read first A read-correction-transfer operation of correcting errors in unit data and providing error-corrected first unit data to the data input/output circuit of the nonvolatile memory device is performed a plurality of times, and the data input/output circuit A program operation and a data migration operation may be controlled so that the provided second data is stored in the second memory area.

Memory cells included in the non-volatile memory devices 400a to 400k have physical characteristics in which a threshold voltage distribution changes due to factors such as elapsed program time, temperature, program disturbance, and read disturbance. That is, errors may occur in data stored in the non-volatile memory devices 400a to 400k due to the above factors.

The storage controller 300 may use various error correction techniques to correct these errors. For example, the storage controller 300 may include the ECC engine 320 . The ECC engine 320 corrects errors generated in data stored in the nonvolatile memory devices 400a to 400k. The ECC engine 320 may include an ECC encoder 321 and an ECC decoder 323. The ECC encoder 321 performs ECC encoding on data to be stored in the nonvolatile memory devices 400a to 400k, and the ECC decoder 323 performs ECC encoding on data read from the nonvolatile memory devices 400a to 400k. Errors in the read data may be corrected by performing ECC decoding.

The ROM 360 may store various information required for the operation of the storage controller 300 in the form of firmware.

The randomizer 340 may randomize data to be stored in one of the nonvolatile memory devices 400a to 400k. For example, the randomizer 340 may randomize data to be stored in one of the nonvolatile memory devices 400a to 400k in units of word lines.

For example, the randomizer 340 may randomize page data. By way of example, the configuration of an ideal randomizer 340 has been described for concise description. However, the technical idea of the present invention is not limited thereto, and the randomizer 340 actually determines the number of memory cells having an erase state and each of the first to seventh program states among memory cells connected to one word line. You can randomize the data so that they are close to the same value. That is, memory cells storing randomized data may have substantially similar numbers of program states.

The internal buffer 380 may have a data storage capacity capable of storing the first unit of data. The data of the first unit may correspond to a page unit of the first memory area and the second memory area of each of the nonvolatile memory devices 400a to 400k. Since the internal buffer 380 has a data storage capacity capable of storing data in units of pages, the area occupied by the storage controller 300 may be reduced by reducing the size of the internal buffer 380 .

The storage controller 300 may communicate with the host 100 through the host interface 350 . For example, the host interface 350 may include universal serial bus (USB), multimedia card (MMC), peripheral component interconnection (PCI), PCI-express (PCI-E), advanced technology attachment (ATA), serial-ATA, Parallel-ATA, SCSI (small computer small interface), ESDI (enhanced small disk interface), IDE (Integrated Drive Electronics), MIPI (Mobile Industry Processor Interface), NVMe (Nonvolatile Memory-express), UFS (Universal Flash Storage), etc. At least one of the same various interfaces may be provided.

The storage controller 300 may communicate with the non-volatile memory devices 400a to 400k through the memory interface 370 .

FIG. 4A is a block diagram illustrating a connection between a storage controller and one nonvolatile memory device in the storage device of FIG. 1 . Figure 4b shows the processor and program/migration manager in Figure 4a.

In FIG. 4A , for convenience of description, it is assumed that the storage system 200a includes the storage controller 300 and the nonvolatile memory device 400a.

Referring to FIG. 4A , the storage controller 300 operates based on the first operating voltage VOP1.

The nonvolatile memory device 400a may perform erase, write, and read operations under the control of the storage controller 300 . To this end, the nonvolatile memory device 400a receives a command CMD and an address ADDR through an input/output line and receives data DTA through a buffer memory 250 . In addition, the nonvolatile memory device 400a may receive a control signal CTRL through a control line and may receive power PWR1 through a power line. In addition, the nonvolatile memory device 400a may provide a status signal RnB to the storage controller 300 through a control line. Also, the nonvolatile memory device 400a may provide data DTA to the storage controller 300 using the buffer memory 250 .

The nonvolatile memory device 400a may include a first memory area MRG1 and 421 and a second memory area MRG2 and 423 .

The first memory area 421 may have a first write speed, and the second memory area 423 may have a second write speed different from the first write speed and faster than the first write speed. N-bit data (N is a natural number) is stored in each of the first memory cells of the first memory area 421, and M-bit data (M is less than N) is stored in each of the second memory cells of the second memory area 423. large natural numbers) can be stored.

In an embodiment, the first memory area 421 may be a single level cell (SLC) area, and the second memory area 423 may be a triple level cell (TLC) area.

The storage controller 300 may include a processor 310 , an ECC engine 320 , a program/migration manager 331 and an internal buffer 380 .

The ECC engine 320 performs ECC encoding on data to be programmed into one of the first memory area 421 and the second memory area 423, and performs ECC encoding on the first memory area 421 and the second memory area 423. ECC decoding may be performed on data read from one of the

The program/migration manager 331, under the control of the processor 310, when the size of an effective area in which data of the first memory area 421 can be stored is smaller than the size of the first data, the program/migration manager 331 stores the data in the first memory area 421 as a base. The stored second data is read as much as the first unit corresponding to the data storage capacity of the internal buffer 380, the error of the read first unit data is corrected, and the error-corrected first unit data is read at the ratio. Program to perform a read-correction-transfer operation provided to the data input/output circuit of the volatile memory device 400a a plurality of times, and store the second data provided to the data input/output circuit in the second memory area 423 You can control the operation and data migration behavior.

If the first memory area 421 is a single level cell (SLC) area and the second memory area 423 is a triple level cell (TLC) area, the read-correction-transfer operation may be performed three times.

When the processor 310 programs the first data into the non-volatile memory device 400a, the first mode for preferentially storing the first data in the first memory area 421 and the first mode related to the first data are stored in the first memory area 421. One of the second modes for storing 1 data in the second memory area 423 may be determined.

Referring to FIG. 4B , the processor 310 may determine the write mode as one of a first mode and a second mode based on a write request related to first data. The processor 310 may determine continuity of the write request REQ from the host 100 based on the idle time, and determine the write mode as one of the first mode and the second mode according to the determination result. The idle time may indicate an idle time between write requests received before the write request. Exemplarily, the idle time indicates the duration of the idle state of the storage device 200a, and the idle state indicates a state in which the storage device 200a is not operating or there is no request from the host 100. That is, the aforementioned idle time between the first write request and the second write request may refer to a time from when the operation for the first write request is completed to when the second write request is received.

The processor 310 compares the idle time and a reference time (RT), determines that the write command is continuous when the idle time is less than the reference time, and determines that the write command is continuous when the idle time is greater than or equal to the reference time. It may be determined that is discontinuous, and a mode signal MS indicating the first mode and the second mode may be provided to the program/migration manager 331 .

When it is determined that the write request is continuous, the processor 310 performs a write operation for the write request based on the first mode, and when it is determined that the write request is discontinuous, the processor 310 executes the second mode. A write operation for the write command may be performed based on the second mode of performing the write operation for the write request based on

In an embodiment, the processor 310 may determine the write mode as one of the first mode and the second mode based on the size of the first data DTA. The processor 310 stores the first data in the first memory area 421 in response to the size of the first data DTA being greater than or equal to the reference size RSZ, and the size of the first data DTA is equal to or greater than the reference size RSZ. In response to being less than (RSZ), the first data may be stored in the second memory area 423 . The processor 310 compares the first data DTA and the reference size RSZ, and transmits a mode signal MS designating one of the first mode and the second mode to the program/migration manager 331 according to the result of the comparison. can be provided to

In an embodiment, the processor 310 selects the write mode based on state information SINF of the first memory area 421 and the second memory area 423 provided from the program/migration manager 331. One of the first mode and the second mode may be determined. The state information includes program/erase cycle information of the first memory area 421 and the second memory area 423, the number and number of free blocks in the first memory area 421 and the second memory area 423, and It may include at least one of data retention time information of the first memory area 421 and the second memory area 423 . The processor 310 may provide a mode signal MS designating one of the first mode and the second mode to the program/migration manager 331 based on the state information SINF.

4C is a timing diagram for explaining an operation of the storage device of FIG. 4A.

4A to 4C , the nonvolatile memory device 400a may perform first to third write operations WR1 , WR2 , and WR3 under the control of the storage controller 300 . The first to third write operations WR1 , WR2 , and WR3 may correspond to each of the write requests REQ1 , REQ2 , and REQ3 from the host 100 .

The nonvolatile memory device 400a may perform a first write operation WR1 under the control of the storage controller 300 . The first write operation WR1 may be performed in the second mode. The nonvolatile memory device 400a may program data into the second memory area 423 under the control of the storage controller 300 .

After the first idle time t1 has elapsed from the completion of the first write operation WR1 , the nonvolatile memory device 400a may perform the second write operation WR2 under the control of the storage controller 300 . can The processor 310 sets the first idle time t1 from the time when the first write operation WR1 is completed to the time when the write request REQ2 is received (or the time when the second write operation starts) as the reference time (RT). ) can be compared with Since the first idle time t1 is greater than the reference time RT, the processor 310 determines that the write request REQ2 is discontinuous with the write request REQ1. Accordingly, the nonvolatile memory device 400a may perform the second write operation WR2 in the second mode under the control of the storage controller 300 .

After the second idle time t2 has elapsed from the completion of the second write operation WR2 , the nonvolatile memory device 400a performs the third write operation WR3 under the control of the storage controller 300 . can The processor 310 sets the third idle time t3 from the time when the third write operation WR3 is completed to the time when the write request REQ3 is received (or the time when the third write operation starts) as the reference time (RT). ) can be compared with Since the second idle time t2 is shorter than the reference time RT, the processor 310 determines that the write request REQ3 and the write request REQ2 are discontinuous. Accordingly, the nonvolatile memory device 400a may perform the third write operation WR3 in the first mode under the control of the storage controller 300 .

5 is a block diagram illustrating the non-volatile memory device of FIG. 4A according to example embodiments.

Referring to FIG. 5 , a nonvolatile memory device 400a includes a memory cell array 420, an address decoder 450, a page buffer circuit 430, a data input/output circuit 440, a control circuit 460, and a voltage generator ( 470) may be included.

The memory cell array 420 may be connected to the address decoder 450 through a string select line SSL, a plurality of word lines WLs, and a ground select line GSL. Also, the memory cell array 420 may be connected to the page buffer circuit 430 through a plurality of bit lines BLs. The memory cell array 420 may include a plurality of memory cells connected to a plurality of word lines WLs and a plurality of bit lines BLs. The memory cell array 420 may include a first memory area 421 and a second memory area 423 .

In one embodiment, the memory cell array 420 may be a three-dimensional memory cell array formed in a three-dimensional structure (or vertical structure) on a substrate. In this case, the memory cell array 420 may include a plurality of NAND strings including a plurality of memory cells formed by being stacked on each other.

FIG. 6 is a block diagram illustrating a memory cell array in the nonvolatile memory device of FIG. 5 .

Referring to FIG. 6 , the memory cell array 420 includes a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz extend along the first horizontal direction HD1 , the second horizontal direction HD2 , and the vertical direction VD. In an embodiment, the memory blocks BLK1 to BLKz are selected by the address decoder 450 shown in FIG. 5 . For example, the address decoder 450 may select a memory block BLK corresponding to a block address from among the memory blocks BLK1 to BLKz.

FIG. 7A is a circuit diagram illustrating one memory block among the memory blocks of FIG. 6 .

The memory block BLKia shown in FIG. 7A represents a three-dimensional memory block formed on the substrate SUB in a three-dimensional structure. For example, a plurality of memory NAND strings included in the memory block BLKi may be stacked in a direction VD perpendicular to the substrate SUB.

Referring to FIG. 7A , the memory block BLKia may include a plurality of memory NAND strings NS11 to NS33 connected between the bit lines BL1 , BL2 , and BL3 and the common source line CSL. Each of the plurality of memory NAND strings NS11 to NS33 may include a string select transistor SST, a plurality of memory cells MC1, MC2, ..., MC8, and a ground select transistor GST.

The string select transistor SST may be connected to corresponding string select lines SSL1 , SSL2 , and SSL3 . The plurality of memory cells MC1 , MC2 , ..., MC8 may be connected to corresponding word lines WL1 , WL2 , ..., WL8 , respectively. The ground select transistor GST may be connected to corresponding ground select lines GSL1 , GSL2 , and GSL3 . The string select transistor SST may be connected to corresponding bit lines BL1 , BL2 , and BL3 , and the ground select transistor GST may be connected to the common source line CSL.

Word lines (eg, WL1) having the same height may be commonly connected, and ground select lines GSL1, GSL2, and GSL3 and string select lines SSL1, SSL2, and SSL3 may be separated from each other.

FIG. 7B is a perspective view illustrating one memory block among the memory blocks of FIG. 6 .

Referring to FIG. 7B , at least one ground string line GSL, a plurality of word lines WLs, and at least one string select line SSL are provided between the word line cut regions WLC of the memory block BLKi. It may be implemented in a form of being stacked on the substrate SUB in the vertical direction VD. Doped regions DOP may be formed on the substrate SUB of the word line cut regions WLC, and the doped regions DOP are formed by a common source line (CSL) to which a common source voltage is supplied. Alternatively, it may be used as a common source node (CSN). At least one string selection line SSL may be divided by a string selection line cut area SSLC extending in the first horizontal direction HD1.

A plurality of vertical channels or channel holes pass through at least one ground string line substrate (GSL), a plurality of word lines (WLs), and at least one string select line (SSL). Here, at least one ground string line (GSL), a plurality of word lines (WLs), and at least one string select line (SSL) may be implemented in the form of a substrate. Bit lines BL extending in the second horizontal direction HD2 are connected to upper surfaces of the plurality of vertical channels.

7C is a plan view illustrating one memory block among the memory blocks of FIG. 6 .

In FIG. 7C, a white circle represents an inner cell or inner channel hole, and a dotted circle represents an outer cell or outer channel hole. Common source lines corresponding to the doped regions DOP shown in FIG. 7B are arranged in the word line cut region WLC.

Referring to FIG. 7C , channel holes may be arranged in a zig-zag structure in the memory block BLKi. This zig-zag structure has an effect of reducing the area of the memory cell array including the memory block BLKi. In the memory block BLKi, outer channel holes and inner channel holes may be disposed in the second horizontal direction HD2 between two adjacent word line cut regions WLC. As such, one of the outer channel holes and inner channel holes arranged in the second horizontal direction HD2 may be connected to an even-numbered bit line and the other may be connected to an odd-numbered bit line. In FIG. 7C, for convenience, one bit line pair (BLin, BLot) is shown, and other bit lines are omitted.

8 shows an example of a structure of one NAND string of the memory block of FIG. 7A.

Referring to FIGS. 7A and 8 , the NAND string NS11 may be provided with a pillar PL extending in a direction perpendicular to the substrate SUB and contacting the substrate SUB. The ground select line GSL1, the word lines WL1 to WL8, and the string select line SSL1 shown in FIG. 7A may be formed of conductive materials parallel to the substrate SUB, for example, metal materials. can The pillar PL may contact the substrate SUB by passing through conductive materials forming the ground select line GSL1 , the word lines WL1 to WL8 , and the string select line SSL1 .

In Fig. 8, a cross-sectional view along the cutting line V-V' is also shown. Exemplarily, a cross-sectional view of the first memory cell MC1 corresponding to the first word line WL1 is shown. The pillar PL may include a cylindrical body BD. An air gap AG may be provided inside the body BD.

The body BD may include P-type silicon and may be a region in which a channel is formed. The pillar PL may further include a cylindrical tunnel insulating layer TI surrounding the body BD and a cylindrical charge trapping layer CT surrounding the tunnel insulating layer TI.

A blocking insulating layer BI may be provided between the first word line WL1 and the pillar PL. The body BD, the tunnel insulating layer TI, the charge trapping layer CT, the blocking insulating layer BI, and the first word line WL1 are formed in a direction perpendicular to the substrate SUB or an upper surface of the substrate SUB. It may be a formed charge trapping transistor. The string select transistor SST, the ground select transistor GST, and other memory cells may have the same structure as the first memory cell MC1.

9 illustrates threshold voltage distributions of memory cells in a first memory area and threshold voltage distributions of second memory cells in a second memory area.

In FIG. 9 , reference numeral 511 denotes a distribution of threshold voltages of first memory cells of the first memory area 421 including an erase state (E) and a first program state (P11), and reference numeral 513 is The threshold voltage distribution of the first memory cells of the second memory area 423 including the erase state E and the first to seventh program states P1 to P7 is shown.

Referring to FIG. 9, the erase state E and the first program state P11 are distinguished using the read voltage Vr, and the read voltages Vr1, Vr2, Vr3, Vr4, Vr5, Vr6, and Vr7 are respectively An erased state E and two adjacent states among the first to seventh program states P1 to P7 may be distinguished by using .

10 and 11 are block diagrams each illustrating an example of the memory cell array of FIG. 5 according to example embodiments.

Referring to FIG. 10 , a memory cell array 420a may include a first memory area 421a and a second memory area 423a. The first memory area 421a may include a plurality of SLC blocks (SLC_BLK1 to TLC_BLKj, where j is a natural number greater than or equal to 2), and the second memory area 423a may include a plurality of TLC blocks (TLC_BLK1 to TLC_BLKj). there is.

Referring to FIG. 11 , the memory cell array 420a may include a plurality of blocks 425, and each block may be used as an SLC block or a TLC block as needed.

12 and 13 show that the storage device of FIG. 4 performs a write operation in a first mode and a second mode, respectively.

Referring to FIG. 12 , when the storage device 200a performs a write operation in the first mode, the storage controller 300 designates the write mode as the first mode in response to the request REQ, and the ECC engine 320 ) performs ECC encoding on the write data DTA to generate parity data PRT, and the program/migration manager 331 converts the write data DTA and the parity data PRT as indicated by reference numeral 521. is stored in the first memory area 421 of the non-volatile memory device 400a.

Referring to FIG. 13 , when the storage device 200a performs a write operation in the second mode, the storage controller 300 designates the write mode as the second mode in response to the request REQ, and the ECC engine 320 ) performs ECC encoding on the write data DTA to generate parity data PRT, and the program/migration manager 331 converts the write data DTA and the parity data PRT as indicated by reference numeral 521. is stored in the second memory area 423 of the non-volatile memory device 400a.

14 illustrates that the storage device of FIG. 4 performs a data migration operation in a first mode.

Referring to FIG. 14 , the storage controller 300 designates the write mode as the first mode in response to the request REQ and stores the first data DTA1 in the first memory area 421 in the first mode. When attempting to perform a write operation, when the size of an effective area capable of storing data in the first memory area 421 is smaller than the size of the first data DTA, a write operation is performed under the control of the program/migration manager 331. The volatile memory device 400a reads the second data DTA2 previously stored in the first memory area 421 by the first unit corresponding to the data storage capacity of the internal buffer 380 and provides the read data to the internal buffer 380. (531). Here, the data of the first unit may include partial user data and partial parity data corresponding to portions of the second data DTA2.

The internal buffer 380 provides data of the first unit to the ECC engine 320, and the ECC engine 320 performs ECC decoding on the data of the first unit to correct errors in the data of the first unit, and The corrected data of the first unit may be provided to the internal buffer 380 (533).

The internal buffer 380 provides the error-corrected data of the first unit to the data input/output circuit 440 of the non-volatile memory device 400a (535), and the first unit read from the first memory area 421 Data of is received from the non-volatile memory device 400a (541).

The internal buffer 380 provides data of the first unit to the ECC engine 320, and the ECC engine 320 performs ECC decoding on the data of the first unit to correct errors in the data of the first unit, and The corrected data of the first unit may be provided to the internal buffer 380 (543).

The internal buffer 380 provides the error-corrected data of the first unit to the data input/output circuit 440 of the non-volatile memory device 400a (545), and the first unit read from the first memory area 421 Data of is received from the non-volatile memory device 400a (551).

The internal buffer 380 provides data of the first unit to the ECC engine 320, and the ECC engine 320 performs ECC decoding on the data of the first unit to correct errors in the data of the first unit, and The corrected data of the first unit may be provided to the internal buffer 380 (553).

The internal buffer 380 provides the error-corrected data of the first unit to the data input/output circuit 440 of the non-volatile memory device 400a (555), and the page buffer circuit 420 provides the second data DTA2 may be stored in the second memory area 423 (560) to complete the data migration operation.

15A illustrates an operation sequence of the storage device of FIG. 14 according to embodiments of the present invention.

14 and 15A, the second data DTA2 pre-stored in the first memory area 421 is read as much as the first unit (SLC read, 531) in the first period INT11, and the internal buffer 380 , the ECC engine 320 performs ECC decoding on the data of the first unit (533), the internal buffer 380 inputs the error-corrected data of the first unit to the data input/output circuit 440, (535), in the second interval (INT12), the second data (DTA2) pre-stored in the first memory area 421 is read as much as the first unit (541) and provided to the internal buffer 380, and the ECC engine 320 ) performs ECC decoding on the data of the first unit (543), the internal buffer 380 inputs the error-corrected data of the first unit to the data input/output circuit 440 (545), and the third section ( INT13), the second data DTA2 pre-stored in the first memory area 421 is read as much as the first unit (551) and provided to the internal buffer 380, and the ECC engine 320 reads the data of the first unit ECC decoding is performed on (553), the internal buffer 380 inputs the data of the first error-corrected unit to the data input/output circuit 440 (555), and the page buffer circuit 420 in the fourth interval (INT14) ) may store the second data DTA2 in the second memory area 423 (TLC PGM, 560) to complete the data migration operation.

In FIG. 15A, the state signal RnB corresponds to sections 531, 541, and 551 in which a read operation is performed in the first to third sections INT1, INT2, and INT3, and sections in which a program in the fourth section INT4 is performed. Indicates a busy state as a low level in .

15B shows another example of an operation sequence in the first mode of the storage device of FIG. 14 according to embodiments of the present invention.

In FIG. 15B , the second area 423 of FIG. 14 is a quadruple level cell (QLC) area, and the size of an effective area capable of storing data in the first memory area 421 is the size of the first data DTA. Assume a smaller case.

Referring to FIG. 15B, in each of the first to fourth sections INT21, INT22, INT23, and INT24, the second data DTA2 previously stored in the first memory area 421 is read as much as the first unit (SLC read) The data is provided to the internal buffer 380, the ECC engine 320 performs ECC decoding on the data of the first unit, and the internal buffer 380 transmits the error-corrected data of the first unit to the data input/output circuit 440. input, and in the fifth period INT25, the page buffer circuit 420 may store the second data DTA2 in the second memory area 423 (QLC PGM) to complete the data migration operation.

That is, the embodiment of the present invention may be applied even when the memory cells of the second region 423 are QLC or store data bits rather than QLC.

16 illustratively illustrates the memory cell array of FIG. 5 according to embodiments of the present invention.

The memory cell array 420c may be referred to as a physical storage space of the nonvolatile memory device 400a. The physical storage space may indicate a physical area in which actual user data is stored in the non-volatile memory device 400a. That is, the physical storage space may be a space that can be identified by the host 100 as the capacity of the storage device 200a.

Referring to FIG. 16 , the memory cell array 420c includes a turbo write buffer area (TWB) (hereinafter referred to as a “turbo write buffer” for convenience of explanation) and a user storage area ( UST) (User Storage area) (hereinafter, for convenience of description, referred to as “User Storage”).

The turbo live buffer TWB may correspond to part (a) of the physical storage space of the non-volatile memory device 400a of the storage device 200 . The user storage UST corresponds to the remaining part (b) of the physical storage space of the non-volatile memory device 400a of the storage device 200 or all (a) of the physical storage space PS of the non-volatile memory device 400a. +b) can be matched.

In an exemplary embodiment, each of the memory cells corresponding to the turbo write buffer (TWB) may be used as a single level cell (SLC), and each of the memory cells corresponding to the user storage (UST) may be a triple level cell ( TLC; can be used as a triple level cell). Alternatively, each of the memory cells corresponding to the turbo write buffer TWB may be configured to store n-bit (n is a positive integer) data, and each of the memory cells corresponding to the user storage UST may store m-bit data. It may be configured to store data (where m is a positive integer greater than n). That is, the turbo write buffer (TWB) may indicate an area that supports high-speed writing faster than the user storage (UST).

In an embodiment, symbols “a” and “b” may mean the number of memory blocks corresponding to each storage space. Depending on the size of the Turbo Light Buffer (TWB) and User Storage (UST) and how the Turbo Light Buffer (TWB) and User Storage (UST) are implemented (e.g. SLC, MLC, TLC, QLC, etc.), "a" And the value of "b" can be varied in various ways.

The storage device 200a may support normal write and turbo write functions. When the turbo write function is activated by the host 100, the storage device 1200 may perform a turbo write operation. When the turbo write function is disabled by the host 100, the storage device 200a may perform a normal write operation.

For example, when the turbo write function is activated, the storage device 200a may first write write data received from the host 100 into the turbo write buffer TWB. In this case, since the write data received from the host 100 is written (eg, SLC program) to the turbo write buffer (TWB), a normal write operation (eg, TLC program) for the user storage (UST) is performed. A higher operating speed than when this is performed can be guaranteed. When the turbo write function is deactivated, the storage device 200 may not first write write data into the turbo write buffer TWB. The storage device 1200 may directly write write data into the user storage UST or into the turbo write buffer TWB according to an internally determined policy (eg, normal write policy). How to write write data may be determined by reflecting various factors such as data occupancy of the turbo write buffer (TWB) and state of the physical storage space (PS) according to the normal light policy.

In an exemplary embodiment, data written in the turbo write buffer (TWB) may be flushed or migrated to the user space (UST) according to an explicit command from the host 1100 or an internally determined policy. there is.

17 and 18 are diagrams for explaining the turbo write buffer type of FIG. 16 .

Referring to FIGS. 4, 16, 17, and 18 , the storage device 200a may include first to fourth logical units LU1 to LU4. Each of the first to fourth logical units LU1 to LU4 may indicate an externally manageable and independent processing object that processes a command from the host 100 . The host 100 may manage the storage space of the storage device 200a through the first to fourth logical units LU1 to LU4. Each of the first to fourth logical units LU1 to LU4 may be used to store user data in the storage device 200 .

Each of the first to fourth logic units LU1 to LU4 may be associated with at least one memory block of the nonvolatile memory device 400a. Although there are various types of logical units used for various purposes, it is assumed here that the first to fourth logical units LU1 to LU4 correspond to physical storage spaces and are used to store data of the host 100. do.

Although the first to fourth logic units LU1 to LU4 are shown in FIGS. 17 and 18 , the scope of the present invention is not limited thereto. For example, the storage device 200a may further include other logical units for storing and managing user data in addition to the first to fourth logical units LU1 to LU4. Alternatively, the storage device 200 may further include other logical units for supporting various functions in addition to the first to fourth logical units LU1 to LU4 .

The turbo write buffer TWB of the storage device 200a according to an embodiment of the present invention may be composed of various types. The turbo write buffer (TWB) may be configured in any one of a LU dedicated buffer type and a shared buffer type.

In the case of a logical unit dedicated buffer type (LU dedicated buffer type), the turbo write buffer (TWB) may be independently or individually configured for each logical unit (LU). For example, as shown in FIG. 17A , in a logic unit-only buffer type, a first turbo write buffer TWB1 is provided for a first logical unit LU1 among first to fourth logical units LU1 to LU4. may be configured, and a third turbo write buffer (TWB) may be configured for the third logic unit (LU3).

In this logical unit-only buffer type, when a write command for the first logical unit LU1 is received after the turbo write is activated, the first turbo write buffer TWB1 corresponding to the first logical unit LU1 is written. Data may be written first. When write data for the third logic unit LU3 is received after the turbo write is activated, the write data may be first written in the third turbo write buffer TWB3 corresponding to the third logic unit LU3.

User storage corresponding to the second and fourth logical units LU2 and LU4 when a write command for the second and fourth logical units LU2 and LU4 in which the turbo write buffer TWB is not configured is received Write data may be written in (UST).

Also, when a write command for the first logical unit LU1 or the third logical unit LU3 is received after the turbo light is deactivated, the write data is sent to the user of the first logical unit LU1 according to the normal light policy. The storage UST1 or the first turbo write buffer TWB1 may be written, or the user storage UST or the third turbo write buffer TWB3 of the third logic unit LU3 may be written.

In an exemplary embodiment, the capacity of each of the first and third turbo write buffers TWB1 and TWB3 may be set independently of each other. However, the scope of the present invention is not limited thereto, and the number of logic units to which the turbo write buffer is allocated, the capacity of each turbo write buffer, and the like may be modified in various ways.

In an exemplary embodiment, the size of the turbo write buffer (TWB) for each logical unit may be set in a turbo write buffer size field per unit (eg, “dLUNumTurboWriteBufferAllocUnits”) of the Unit Descriptor. In an exemplary embodiment, the turbo write buffer size per unit field (eg, “dLUNumTurboWriteBufferAllocUnits”) may be a configurable parameter.

In the case of a shared buffer type, one turbo write buffer may be configured for all of a plurality of logic units. For example, as shown in FIG. 17B , in the shared buffer type, one shared turbo write buffer TWB0 may be configured for all of the first to fourth logical units LU1 to LU4.

In this case, when a write command for each of the first to fourth logical units LU1 to LU4 is received after turbo light is activated, write data may be first written into the shared turbo write buffer TWB0. When a write command for each of the first to fourth logical units LU1 to LU4 is received after the turbo light is deactivated, write data is sent to the first to fourth logical units LU1 to LU4 according to the normal light policy. ) or to the shared turbo write buffer TWB0.

As described above, the storage device 200a according to an embodiment of the present invention may include a turbo write buffer (TWB) for supporting a turbo write function. The turbo write buffer (TWB) may be independently configured for each of a plurality of logical units, or all of the plurality of logical units, depending on the buffer type (eg, a buffer type dedicated to a logical unit or a shared buffer type). It can be configured as one for .

19 is a flowchart illustrating an operation of the storage system of FIG. 1 as an example. A write operation of the storage system 50 is described with reference to FIGS. 1 and 19 .

In step S21 , the host 100 may transmit a universal flash storage protocol information unit (UPIU) command including the command WR CMD to the storage device 200a.

In step S22, the host 100 and the storage device 200 may perform a data transaction. For example, the storage device 200 may transmit an RTT UPIU (Ready to Transfer UPIU) to the host 100 . The RTT UPIU may include information about a range of data that the storage device 200 can receive. The host 100 may transmit a DATA OUT UPIU including write data to the storage device 200 in response to the RTT UPIU. By repeatedly performing the above-described operation, write data may be transmitted from the host 100 to the storage device 200 .

After all write data is completely received, the storage device 200 may transmit a RESPONSE UPIU to the host 100 in step S13 . The RESPONSE UPIU may include information indicating that the operation for the write command received in step S21 has been completed.

In an embodiment, the storage device 200 may perform a normal write operation on the write data received during step S22. For example, in step S21 , the storage device 200 may determine whether the turbo light function is activated. As a more detailed example, the storage device 200 may determine whether the turbo write function is activated by checking the value of the turbo light enable field (eg, “fTurboWriteEn”) of the flag. If the value of the turbo light activation field (eg, "fTurboWriteEn") of the flag is "0b", the turbo light function may not be activated, and if the value is "1b", the turbo light function is activated. may be in a state In an embodiment, the value of the turbo light activation field (eg, “fTurboWriteEn”) of the flag may be set by the host 1100 requesting a query for the set flag.

The value of the turbo light activation field (eg, “fTurboWriteEn”) [0102] from the host 100 may not be set. In this case, the write data received in step S22 may be written (ie, normal write) to the user storage UST.

In step S30, the host 100 may set the value of the turbo light activation field (eg, “fTurboWriteEn”) to a specific value (eg, “1b”). For example, the host 1100 transmits a query request for setting the value of a turbo light activation field (eg, “fTurboWriteEn”) to a specific value (eg, “1b”) to the storage device 200 . can In response to a query request from the host 100, the value of the turbo light activation field (eg, “fTurboWriteEn”) is set to a specific value (eg, “1b”), and the storage device 200 responds to the query. may be transmitted to the host 100.

Thereafter, in step S31, the host 100 may perform operations of steps S31 to S33. Since the operations of steps S31 to S33 are similar to those of steps S21 to S23, a detailed description thereof will be omitted.

In an embodiment, the write data received in step S32 may be written into the turbo write buffer (TWB). For example, in step S30 , the turbo light function may be activated as the value of the turbo light activation field (eg, “fTurboWriteEn”) is set to a specific value (eg, “1b”). In this case, write data received from the host 100 may be first written into the turbo write buffer TWB. For example, in step S31, data received from the host 100 is stored in a fixed turbo light buffer (TWB-p) or a non-fixed turbo light buffer (TWB-np) according to a specific factor value of the command UPIU. It can be. A specific configuration of the turbo light buffer, which is divided into a fixed turbo light buffer (TWB-p) and a non-fixed turbo light buffer (TWB-np), will be described in detail with reference to FIG. 20 .

In an embodiment, even when the turbo write function is activated, if the space of the turbo write buffer TWB is insufficient, the storage device 200 may write the received write data into the user storage UST. In an embodiment, when the space of the turbo write buffer (TWB) is insufficient even when the turbo write function is activated, the storage device 200 performs a data migration operation using the internal buffer 380 of the storage controller. Write data received later may be written into the turbo write buffer TWB.

FIG. 20 is a block diagram showing a physical storage space of the storage device 200 of FIG. 1 as an example.

Referring to FIGS. 1 and 20 , a memory cell array 420d that is a physical storage space of the storage device 200 may include a turbo write buffer TWB and a user storage UST. Since the physical storage space PS, the turbo write buffer TWB, and the user storage UST of the storage device 200 have been described above, a detailed description thereof will be omitted.

The turbo write buffer (TWB) may be divided into a pinned turbo write buffer (TWB-p) and a non-pinned turbo write buffer (TWB-np). Similarly as described above, when the turbo write function of the storage device 200 is activated, write data is stored in either a fixed turbo write buffer TWB-p or a non-fixed turbo write buffer TWB-np. can be stored

Among the fixed turbo light buffer (TWB-p) and the non-fixed turbo light buffer (TWB-np), the buffer in which write data is stored can be stored in various ways (e.g., internal policy, change of internal policy according to the request of the host). , host's explicit request, etc.).

In an exemplary embodiment, as described above, the size of the turbo write buffer (TWB) may be determined by a control of the host 100 or an internal policy of the storage device 200 . At this time, the ratio of the fixed turbo light buffer (TWB-p) and the non-fixed turbo light buffer (TWB-np) included in the turbo light buffer (TWB) can be determined in various ways (eg, internal policy, host It can be determined or changed by a change in internal policy according to a request, an explicit request from the host, etc.).

In an exemplary embodiment, user data is flushed, migrated ( migrate), or may be moved. For example, the fixed turbo write buffer (TWB-p) and the non-fixed turbo according to an explicit request of the host 100, an internal policy of the storage device 200, or a change of internal policy according to a request of the host. User data may be moved between the write buffers TWB-np.

Alternatively, between the non-fixed turbo write buffer (TWB-np) and the user storage (UST) according to an explicit request of the host 100, an internal policy of the storage device 200, or a change in internal policy according to a request of the host. User data can be moved in Alternatively, between the fixed turbo light buffer (TWB-p) and the user storage (UST) according to an explicit request of the host 100, an internal policy of the storage device 200, or a change of internal policy according to a request of the host. User data may move.

In an example embodiment, the storage device 200 may perform a flush operation during an idle state or a hibernation state. At this time, the storage device 200 may perform a flush operation on the non-fixed turbo write buffer TWB-np among the turbo write buffers TWB. That is, the storage device 200 may flush user data stored in the non-fixed turbo write buffer TWB-np of the turbo write buffer TWB to the user storage UST.

In an exemplary embodiment, the storage device 200 may perform a write operation when the size of an effective area capable of storing data of the non-fixed turbo write buffer TWB-np is smaller than the size of data to be written. Data pre-stored in the turbo write buffer TWB-np may be migrated to the user storage UST by performing the above-described read-correction-transfer operation a plurality of times using the buffer 480 .

At this time, the user data written in the fixed turbo write buffer TWB-p will not be flushed to the user storage UST. That is, even if the storage device 200 performs a flush operation, the user data written in the fixed turbo write buffer TWB-p will be maintained.

As another example, data to be stored in the non-fixed turbo write buffer TWB-np may be stored in the fixed turbo write buffer TWB-p according to an internal policy of the storage device 200 . These exceptional data can be flushed from the fixed turbo write buffer (TWB-p) to the user storage (UTS). Accordingly, when the host 100 issues a read command for the first user data written in the fixed turbo write buffer TWB-p, the first user data is read from the fixed turbo write buffer TWB-p. It will be. In this case, high-speed reading of the first user data may be possible.

For example, as described above, the fixed turbo light buffer TWB-p may store user data based on the SLC method, and the user storage UST may store user data based on the TLC method. . The time to read the user data stored based on the SLC method will be faster than the time to read the user data stored based on the TLC method.

That is, by maintaining the specific user data in the fixed turbo write buffer TWB-p, the speed of a subsequent read operation for the specific user data can be improved. This function of the storage device 1200 may be called “Turbo Read”.

In FIGS. 16 to 20 , it is assumed that the storage device 200 of FIG. 1 or the storage device 400a of FIG. 4 is a UFS device.

21 is a flowchart illustrating a method of operating a storage device according to example embodiments.

3 to 15 and 21, a first memory area 421 having a first write speed and a second memory area 423 having a second write speed different from the second write speed. A method of operating a storage device 200a including a nonvolatile memory device 400a and a storage controller 300 controlling the nonvolatile memory device 400a is provided.

According to the above method, the storage controller 200 receives first data from the external host 100 (S110). The storage controller 200 programs the first data into the first memory area 421 in the first mode (S120). The storage controller 200 determines whether the first memory area 421 is full (S130). That is, the storage controller 200 determines whether the size of an effective area for storing data in the first memory area 421 is smaller than the size of the first data.

If the first memory area 421 is not full (NO in S130), the storage controller 200 programs the first data into the first memory area 421 (S120).

When the first memory area 421 is full (YES in S130 ), the storage controller 200 converts the second data pre-stored in the first memory area (by a first unit corresponding to the data storage capacity of the internal buffer 380). ECC decoding is sequentially read to correct the error (S140), and the error-corrected data is provided to the data input/output circuit 440 of the non-volatile memory device 400a.

The non-volatile memory device 400a programs error-corrected second data into the second memory area 423 (S150). The storage controller 100 receives third data from the host 100 (S160). The storage controller 100 programs third data into the first memory area 421 in the first mode (S170).

Accordingly, in the storage device and method of operating the storage device according to embodiments of the present invention, when first data is programmed in a first memory area having a high writing speed, second data pre-stored in the first memory area is stored in the storage controller. After sequentially moving the data into the internal buffer, a data migration operation of programming the second data into the second memory area may be performed. Since the data storage capacity of the internal buffer may be smaller than the data storage capacity of the first memory area, the size of the storage controller may be reduced by reducing the size of the internal buffer.

22 is a cross-sectional view illustrating a nonvolatile memory device according to example embodiments.

Referring to FIG. 22 , the nonvolatile memory device 2000 may have a chip to chip (C2C) structure. The C2C structure fabricates an upper chip (first chip) including a cell region (CELL) on a first wafer, and a lower chip (first chip) including a peripheral circuit region (PERI) on a second wafer different from the first wafer. 2), and then connecting the upper chip and the lower chip by a bonding method. For example, the bonding method may refer to a method of electrically connecting the bonding metal formed on the uppermost metal layer of the upper chip and the bonding metal formed on the uppermost metal layer of the lower chip to each other. For example, when the bonding metal is formed of copper (Cu), the bonding method may be a Cu-to-Cu bonding method, and the bonding metal may also be formed of aluminum (Al) or tungsten (W).

Each of the peripheral circuit area PERI and the cell area CELL of the nonvolatile memory device 2000 may include an external pad bonding area PA, a word line bonding area WLBA, and a bit line bonding area BLBA. there is.

The peripheral circuit region PERI includes a first substrate 2210, an interlayer insulating layer 2215, a plurality of circuit elements 2220a, 2220b, and 2220c formed on the first substrate 2210, and a plurality of circuit elements 2220a. , 2220b, 2220c) to include first metal layers 2230a, 2230b, and 2230c connected to each other, and second metal layers 2240a, 2240b, and 2240c formed on the first metal layers 2230a, 2230b, and 2230c. can In an embodiment, the first metal layers 2230a, 2230b, and 2230c may be formed of tungsten having a relatively high electrical resistivity, and the second metal layers 2240a, 2240b, and 2240c may be made of copper having a relatively low electrical resistivity. can be formed

In this specification, only the first metal layers 2230a, 2230b, and 2230c and the second metal layers 2240a, 2240b, and 2240c are shown and described, but are not limited thereto, and the second metal layers 2240a, 2240b, and 2240c At least one or more metal layers may be further formed. At least some of the one or more metal layers formed on the second metal layers 2240a, 2240b, and 2240c are made of aluminum having a lower electrical resistivity than copper forming the second metal layers 2240a, 2240b, and 2240c. can be formed

The interlayer insulating layer 2215 covers the plurality of circuit elements 2220a, 2220b, and 2220c, the first metal layers 2230a, 2230b, and 2230c, and the second metal layers 2240a, 2240b, and 2240c on the first substrate. 2210, and may include an insulating material such as silicon oxide, silicon nitride, or the like.

Lower bonding metals 2271b and 2272b may be formed on the second metal layer 2240b of the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 2271b and 2272b of the peripheral circuit area PERI may be electrically connected to the upper bonding metals 2371b and 2372b of the cell area CELL by a bonding method. , The lower bonding metals 2271b and 2272b and the upper bonding metals 2371b and 2372b may be formed of aluminum, copper, or tungsten.

The cell area CELL may provide at least one memory block. The at least one memory block may include a first area and a second area, and the first area may store the above-described compensation data set and may be an SLC block. The cell region CELL may include a second substrate 2310 and a common source line 2320 . On the second substrate 2310, a plurality of word lines 2331, 2332, 2333, 2334, 2335, 2336, 2337, 2338, and 2330 are provided along the third direction VD perpendicular to the upper surface of the second substrate 2310. ) can be stacked. String select lines and a ground select line may be disposed on upper and lower portions of the word lines 2330 , and a plurality of word lines 2330 may be disposed between the string select lines and the ground select line.

In the bit line bonding area BLBA, the channel structure CH extends in a direction VD perpendicular to the upper surface of the second substrate 2310 to form word lines 2330, string select lines, and ground select lines. can penetrate The channel structure CH may include a data storage layer, a channel layer, and a buried insulating layer, and the channel layer may be electrically connected to the first metal layer 2350c and the second metal layer 2360c. For example, the first metal layer 2350c may be a bit line contact, and the second metal layer 2360c may be a bit line. In one embodiment, the bit line 2360c may extend along the second horizontal direction HD2 parallel to the upper surface of the second substrate 2310 .

In the example of FIG. 22 , a region where the channel structure CH and the bit line 2360c are disposed may be defined as a bit line bonding region BLBA. The bit line 2360c may be electrically connected to the circuit elements 2220c providing the page buffer 2393 in the peripheral circuit area PERI in the bit line bonding area BLBA. For example, the bit line 2360c is connected to upper bonding metals 2371c and 2372c in the peripheral circuit area PERI, and the upper bonding metals 2371c and 2372c are connected to circuit elements 2220c of the page buffer 2393. It may be connected to the connected lower bonding metals 2271c and 2272c.

In the word line bonding area WLBA, the word lines 2330 may extend along a second horizontal direction HD2 perpendicular to the first horizontal direction HD1 and parallel to the upper surface of the second substrate 310. , may be connected to a plurality of cell contact plugs 2341, 2342, 2343, 2344, 2345, 2346, 3347; 3340. The word lines 2330 and the cell contact plugs 2340 may be connected to each other at pads provided by extending different lengths from at least some of the word lines 2330 along the first horizontal direction HD1. . A first metal layer 2350b and a second metal layer 2360b may be sequentially connected to upper portions of the cell contact plugs 2340 connected to the word lines 2330 . The cell contact plugs 2340 are connected to peripheral circuits in the word line bonding area WLBA through the upper bonding metals 2371b and 2372b of the cell area CELL and the lower bonding metals 2271b and 2272b of the peripheral circuit area PERI. It may be connected to the area PERI.

The cell contact plugs 2340 may be electrically connected to circuit elements 2220b forming the address decoder or row decoder 2394 in the peripheral circuit area PERI. In one embodiment, the operating voltage of the circuit elements 2220b forming the row decoder 2394 may be different from the operating voltage of the circuit elements 2220c forming the page buffer 2393. For example, the operating voltage of the circuit elements 2220c forming the page buffer 2393 may be higher than the operating voltage of the circuit elements 2220b forming the row decoder 2394 .

A common source line contact plug 2380 may be disposed in the external pad bonding area PA. The common source line contact plug 2380 is formed of a conductive material such as metal, metal compound, or polysilicon, and may be electrically connected to the common source line 2320 . A first metal layer 2350a and a second metal layer 2360a may be sequentially stacked on the common source line contact plug 2380 . For example, an area where the common source line contact plug 2380, the first metal layer 2350a, and the second metal layer 2360a are disposed may be defined as an external pad bonding area PA.

Meanwhile, input/output pads 2205 and 2305 may be disposed in the external pad bonding area PA. A lower insulating film 2201 covering a lower surface of the first substrate 2210 may be formed under the first substrate 2210, and a first input/output pad 2205 may be formed on the lower insulating film 2201. The first input/output pad 2205 is connected to at least one of the plurality of circuit elements 2220a, 2220b, and 2220c arranged in the peripheral circuit area PERI through the first input/output contact plug 2203, and the lower insulating layer 2201 ) may be separated from the first substrate 2210. In addition, a side insulating layer may be disposed between the first input/output contact plug 2203 and the first substrate 2210 to electrically separate the first input/output contact plug 2203 from the first substrate 2210 .

An upper insulating layer 2301 covering the upper surface of the second substrate 2310 may be formed on the second substrate 2310, and second input/output pads 2305 may be disposed on the upper insulating layer 2301. The second input/output pad 2305 may be connected to at least one of the plurality of circuit elements 2220a, 2220b, and 2220c disposed in the peripheral circuit area PERI through the second input/output contact plug 2303. In one embodiment, the second input/output pad 2305 may be electrically connected to the circuit element 2220a.

Depending on the embodiment, the second substrate 2310 and the common source line 2320 may not be disposed in the region where the second input/output contact plug 2303 is disposed. Also, the second input/output pad 2305 may not overlap the word lines 2380 in the third direction D3. The second input/output contact plug 2303 is separated from the second substrate 2310 in a direction parallel to the top surface of the second substrate 2310, and penetrates the interlayer insulating layer 2315 of the cell region CELL to form the second input/output contact plug. It can be connected to pad 2305.

According to embodiments, the first input/output pad 2205 and the second input/output pad 2305 may be selectively formed. For example, the non-volatile memory device 2000 includes only the first input/output pad 2205 disposed on the first substrate 2201, or the second input/output pad 2205 disposed on the second substrate 2301 ( 2305) may be included. Alternatively, the memory device 2000 may include both the first input/output pad 2205 and the second input/output pad 2305 .

In each of the external pad bonding area PA and the bit line bonding area BLBA included in the cell area CELL and the peripheral circuit area PERI, the metal pattern of the uppermost metal layer exists in a dummy pattern, or The top metal layer may be empty.

In the nonvolatile memory device 2000, in the external pad bonding area PA, the cell area is formed on the uppermost metal layer of the peripheral circuit area PERI corresponding to the upper metal pattern 2372a formed on the uppermost metal layer of the cell area CELL. A lower metal pattern 2273a having the same shape as the upper metal pattern 2372a of the cell may be formed. The lower metal pattern 2273a formed on the uppermost metal layer of the peripheral circuit area PERI may not be connected to a separate contact in the peripheral circuit area PERI. Similarly, in the external pad bonding area PA, the upper metal layer of the cell area CELL corresponds to the lower metal pattern 2273a formed on the uppermost metal layer of the peripheral circuit area PERI. An upper metal pattern 2372a having the same shape as the lower metal pattern 2273a may be formed.

Lower bonding metals 2271b and 2272b may be formed on the second metal layer 2240b of the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 2271b and 2272b of the peripheral circuit area PERI may be electrically connected to the upper bonding metals 2371b and 2372b of the cell area CELL by a bonding method. .

In addition, in the bit line bonding area BLBA, the uppermost metal layer of the cell area CELL corresponds to the lower metal pattern 2252 formed on the uppermost metal layer of the peripheral circuit area PERI. An upper metal pattern 2392 having the same shape as the metal pattern 2252 may be formed. A contact may not be formed on the upper metal pattern 2392 formed on the uppermost metal layer of the cell region CELL.

The aforementioned word line voltages are applied to at least one memory block of the cell area CELL through the lower bonding metals 2271b and 2272b of the peripheral circuit area PERI and the upper bonding metals 2371b and 2372b of the cell area CELL. can be provided.

23 is a block diagram illustrating an electronic system including a semiconductor device according to example embodiments.

Referring to FIG. 23 , the electronic system 3000 may include a semiconductor device 3100 and a controller 3200 electrically connected to the semiconductor device 3100 . The electronic system 3000 may be a storage device including one or a plurality of semiconductor devices 3100 or an electronic device including the storage device. For example, the electronic system 3000 may be a solid state drive (SSD) device including one or a plurality of semiconductor devices 3100, a universal serial bus (USB), a computing system, a medical device, or a communication device. may be a device.

The semiconductor device 3100 may be a non-volatile memory device, for example, the non-volatile memory device described above with reference to FIGS. 5 to 11 . The semiconductor device 3100 may include a first structure 3100F and a second structure 3100S on the first structure 3100F. The first structure 3100F may be a peripheral circuit structure including a decoder circuit 3110 , a page buffer circuit 3120 , and a logic circuit 3130 . The second structure 3100S includes a bit line BL, a common source line CSL, word lines WL, first and second gate upper lines UL1 and UL2, and first and second gate lower lines. LL1 and LL2, and memory NAND strings CSTR between the bit line BL and the common source line CSL.

In the second structure 3100S, each of the memory NAND strings CSTR includes lower transistors LT1 and LT2 adjacent to the common source line CSL and upper transistors UT1 adjacent to the bit line BL. UT2), and a plurality of memory cell transistors MCT disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of lower transistors LT1 and LT2 and the number of upper transistors UT1 and UT2 may be variously modified according to embodiments.

In example embodiments, the upper transistors UT1 and UT2 may include string select transistors, and the lower transistors LT1 and LT2 may include ground select transistors. The lower gate lines LL1 and LL2 may be gate electrodes of the lower transistors LT1 and LT2, respectively. The word lines WL may be gate electrodes of the memory cell transistors MCT, and the upper gate lines UL1 and UL2 may be gate electrodes of the upper transistors UT1 and UT2, respectively.

In example embodiments, the lower transistors LT1 and LT2 may include a lower erase control transistor LT1 and a ground select transistor LT2 connected in series. The upper transistors UT1 and UT2 may include a string select transistor UT1 and an upper erase control transistor UT2 connected in series. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT1 performs an erase operation of erasing data stored in the memory cell transistors MCT using a gate induce drain leakage (GIDL) phenomenon. can be used for

The common source line CSL, the first and second lower gate lines LL1 and LL2, the word lines WL, and the first and second upper gate lines UL1 and UL2 have a first structure ( 3100F) may be electrically connected to the decoder circuit 3110 through first connection wires 3115 extending to the second structure 1100S. The bit lines BL may be electrically connected to the page buffer circuit 3120 through second connection lines 3125 extending from the first structure 3100F to the second structure 3100S.

In the first structure 3100F, the decoder circuit 1110 and the page buffer circuit 3120 may execute a control operation on at least one selected memory cell transistor among the plurality of memory cell transistors MCT. The decoder circuit 3110 and the page buffer circuit 3120 may be controlled by the logic circuit 3130 . The semiconductor device 3000 may communicate with the controller 3200 through the input/output pad 3101 electrically connected to the logic circuit 3130 . The input/output pad 3101 may be electrically connected to the logic circuit 3130 through an input/output connection wire 3135 extending from the first structure 3100F to the second structure 3100S.

The controller 3200 may include a processor 3210 , a NAND controller 3220 , and a host interface 1230 . According to example embodiments, the electronic system 3000 may include a plurality of semiconductor devices 3100 , and in this case, the controller 3200 may control the plurality of semiconductor devices 3000 .

The processor 3210 may control the overall operation of the electronic system 3000 including the controller 3200 . The processor 3210 may operate according to predetermined firmware and access the semiconductor device 3100 by controlling the NAND controller 3220 . The NAND controller 3220 may include a NAND interface 3221 that processes communication with the semiconductor device 3100 . Through the NAND interface 3221, a command for controlling the semiconductor device 3100, data to be written to the memory cell transistors MCT of the semiconductor device 3100, and memory cell transistors MCT of the semiconductor device 3100 ), data to be read from can be transmitted. The host interface 3230 may provide a communication function between the electronic system 3000 and an external host. When a control command is received from an external host through the host interface 3230, the processor 3210 may control the semiconductor device 3100 in response to the control command.

24 is a block diagram illustrating a storage system according to example embodiments.

Referring to FIG. 24 , a storage system 4000 includes a host 4100 and a storage device 4200 . The host 4100 and the storage device 4200 may operate as described with reference to FIGS. 1 to 20 .

The storage device 4200 may include a program/migration manager 4210 .

The host 4100 includes an application processor 4110, a random access memory 4120 (RAM), a modem 4130, a device driver 4140, a speaker 4150, a display 4160, a touch panel 4170, a microphone ( 4180), and image sensors 4190.

The application processor 4110 may execute an application (AP-h) and a file system (FS-h). The application processor 4110 may use the RAM 4120 as system memory. The application processor 4110 may communicate with an external device through wired or wireless communication through the modem 4130 . For example, the modem 4130 may be built into the application processor 4110.

The application processor 4110 may communicate with peripheral devices through the device driver 4140 . For example, the application processor 4110, through the device driver 4140, controls the speaker 4150, the display 4160, the touch panel 4170, the microphone 4180, the image sensors 4190, and the storage device 4200. ) can communicate with.

Speaker 4150 and display 4160 can be user output interfaces that convey information to the user. The touch panel 4170, the microphone 4180, and the image sensors 4190 may be user input interfaces that receive information from a user.

25 shows a conceptual diagram to which an embodiment of the present invention is applied to a storage system.

Referring to FIGS. 24 and 25 , the storage system 4000 may provide setting screens through the display 4160 . One of the setting screens may provide information on the acceleration mode to the user.

The storage system 4000 may display, through the display 4160 , a list of first to u-th applications APP1 to APPu to which the acceleration mode may be applied. Also, the storage system may display, through the display 1160 , switches capable of adjusting the acceleration modes of the first to u-th applications APP1 to APPu.

In step S210, the user may touch the activation position of the acceleration mode of the third application APP3. The storage system 4000 may detect a user's touch, that is, an instruction to activate the third application APP3 through the touch panel 4170 . In step S220 , information on the third application APP3 or processes of the third application APP3 may be transferred to the program/migration manager 4210 .

As information on the third application APP3 or processes of the third application APP3 is received, in step S230, the program/migration manager 4210 performs a migration operation on the subsequent write operation of the selected third application APP3 or processes. can be reserved. The program/migration manager 4210 may write data related to the subsequent write operation into the first memory area by performing the above-described migration operation on the subsequent write operation of the selected third application APP3 or processes.

The present invention can be usefully used in any electronic device having a storage device. For example, the present invention relates to a mobile phone having a storage device, a smart phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera ( Digital Camera), music player, portable game console, navigation system, etc.

As described above, although it has been described with reference to the preferred embodiments of the present invention, those skilled in the art can make the present invention various without departing from the spirit and scope of the present invention described in the claims below. It will be understood that it can be modified and changed accordingly.

Claims (9)

a nonvolatile memory device including a first memory area having a first write speed and a second memory area having a second write speed slower than the second write speed; and
In a first mode, a storage controller preferentially stores first data provided from the outside in the first memory area and includes an internal buffer;
The storage controller
A read-and-transfer operation of reading the second data previously stored in the first memory area by a first unit and providing the read data of the first unit to a data input/output circuit of the nonvolatile memory device is performed a plurality of times. and controlling a data migration operation so that the second data provided to the data input/output circuit is stored in the second memory area. According to claim 1,
The first unit corresponds to the data storage capacity of the internal buffer,
The storage controller performs a correction operation of correcting an error of the read first unit data when the size of an effective area capable of storing data of the first memory area is smaller than the size of the first data in the first mode. the plurality of times, and the read operation and the transmission operation are performed in parallel. According to claim 1,
The first memory area is a single level cell (SLC) area, the second memory area is a triple level cell (TLC) area,
The storage controller performs the read-transfer operation on the second data three times;
The storage device of claim 1 , wherein the first unit corresponds to a page unit of the first memory area and the second memory area. The method of claim 1 , wherein the storage controller
a processor that determines a write mode related to the first data as one of the first mode and a second mode for storing the first data in the second memory area, based on a write request related to the first data;
a program/migration manager controlling a program operation and the data migration operation based on the control of the processor; and
Further comprising an ECC engine correcting an error of the read first unit data by performing error correction code (ECC) decoding on the read first unit data;
The read first unit of data includes a user data portion and a parity data portion;
Wherein the ECC engine corrects the error based on the parity data portion. The method of claim 4 , wherein the storage controller
Further comprising an on-chip memory into which the program/migration manager is loaded;
The storage device according to claim 1 , wherein the processor executes the program/migration manager loaded into the on-chip memory. According to claim 4,
The processor determines continuity of a write request from the outside based on an idle time, and determines the write mode as one of the first mode and the second mode according to the determination result;
the idle time indicates an idle time between write requests received prior to the write request;
The processor
Compare the idle time and the reference time,
When the idle time is less than the reference time, it is determined that the write command is continuous;
When the idle time is greater than or equal to the reference time, it is determined that the write command is discontinuous;
The processor
When it is determined that the write request is continuous, a write operation for the write request is performed based on the first mode;
and performing a write operation on the write request based on the second mode when it is determined that the write request is discontinuous. 5. The method of claim 4, wherein the processor
determining the writing mode as one of the first mode and the second mode based on the size of the first data;
Storing the first data in the first memory area in response to a size of the first data being greater than or equal to a reference size;
and storing the first data in the second memory area in response to a size of the first data being smaller than the reference size. According to claim 4,
The processor determines the write mode as one of the first mode and the second mode based on state information of the first memory area and the second memory area;
The state information includes program/erase cycle information of the first memory area and the second memory area, the number of free blocks in the first memory area and the second memory area, and the first memory area and the second memory area. A storage device comprising at least one of data retention time information of A storage comprising a nonvolatile memory device including a first memory area having a first write speed and a second memory area having a second write speed slower than the first write speed, and a storage controller controlling the nonvolatile memory device As a method of operating the device,
receiving, by the storage controller, first data from an external host;
programming the first data into the first memory area in a first mode by the storage controller; and
The storage controller may perform a read-and-transfer operation of reading second data previously stored in the first memory area by a first unit and providing the read first unit of data to a data input/output circuit of the nonvolatile memory device. performing as many times as; and
and programming, by the non-volatile memory device, the second data provided to the data input/output circuit into the second memory area.

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