KR20230050197A - Storage device and method of operating storage device - Google Patents

Abstract

The present invention provides a storage device capable of improving error correction capacity. The storage device includes a non-volatile memory device and a storage controller. The non-volatile memory device includes a memory cell array including: multiple word lines laminated on the upper surface of a substrate; multiple memory cells formed in channel holes extended in a vertical direction from the substrate; and word line cut areas dividing the word lines into multiple memory blocks and extended in a first horizontal direction. The storage controller includes an error correction code (ECC) engine and a memory interface. The ECC engine forms multiple ECC sectors by generating parity bits about each of sub-data units by executing first ECC encoding about each of the multiple sub-data units included in user data in a writing motion about the memory cells of a target page connected to a target word line among the multiple word lines. The ECC engine also selects outer cell bits to be stored in the outer cells and forms an outer ECC sector including the outer cell bits. Moreover, the ECC engine includes an ECC encoder generating outer parity bits by performing second ECC encoding about the outer ECC sector. The memory interface transmits a code word set including the ECC sectors and the outer parity bits to the non-volatile memory device.

Description

Storage device and method of operating the storage device {STORAGE DEVICE AND METHOD OF OPERATING STORAGE DEVICE}

The present invention relates to a semiconductor integrated circuit, and more particularly, to a storage device and a method of operating the storage device including the same.

Semiconductor memory devices are largely classified into volatile memory devices and nonvolatile memory devices.

A volatile memory device is a memory device in which stored data is lost when power supply is cut off. On the other hand, non-volatile memory devices retain their contents even when power supply is interrupted. Therefore, non-volatile memory devices are used to store contents to be preserved regardless of whether power is supplied or not. A flash memory device, which is one of nonvolatile memory devices, has advantages such as low noise, low power consumption, and high operating speed, and thus is used in various fields. For example, mobile systems such as smart phones and tablet PCs use large-capacity flash memory devices as storage media.

As memory cells of a flash memory device are gradually miniaturized and stacked, memory cells are deteriorated and data retention characteristics of the memory cells are degraded.

One object of the present invention is to provide a storage device capable of improving error correction capability.

One object of the present invention is to provide a method of operating a storage device capable of improving error correction capability.

A storage device according to embodiments of the present invention for achieving the above object includes a non-volatile memory device and a storage controller. The non-volatile memory device includes a plurality of word lines stacked on a top surface of a substrate, a plurality of memory cells formed in channel holes extending in a direction perpendicular to the substrate, and a plurality of memory cells extending in a first horizontal direction and connecting the word lines to a plurality of memories. and a memory cell array including word line cut regions divided into blocks. The storage controller includes an error correction code (ECC) engine and a memory interface. The ECC engine performs first ECC encoding on each of a plurality of sub data units included in user data in a write operation on memory cells of a target page connected to a target word line among the plurality of word lines, and the sub data units are encoded. Configuring a plurality of ECC sectors by generating parity bits for each of the data units, selecting outer cell bits to be stored in the outer cells in the ECC sectors based on an error correction mode signal, and including the outer cell bits An ECC encoder configured to configure an outer ECC sector and perform second ECC encoding on the outer ECC sector to generate outer parity bits. The memory interface transmits a codeword set including the ECC sectors and the outer parity bits to the nonvolatile memory device.

A storage device according to embodiments of the present invention for achieving the above object includes a non-volatile memory device and a storage controller. The non-volatile memory device includes a plurality of word lines stacked on a top surface of a substrate, a plurality of memory cells formed in channel holes extending in a direction perpendicular to the substrate, and a plurality of memory cells extending in a first horizontal direction and connecting the word lines to a plurality of memories. and a memory cell array including word line cut regions divided into blocks. The storage controller includes an error correction code (ECC) engine and a memory interface. In a write operation on memory cells of a target page connected to a target word line among the plurality of word lines, the ECC engine divides the memory cells into outer cells and inner cells based on a relative distance from the word line cut region. Selecting outer cell bits to be stored in the outer cells from a plurality of sub data units included in user data based on a location index and an error correction mode signal to configure an outer ECC sector including the outer cell bits, First error correction code (ECC) encoding is performed on the outer ECC sector to generate outer parity bits, and second ECC encoding is performed on each of the sub data units to generate the outer parity bits. and an ECC encoder constituting a plurality of ECC sectors by generating parity bits in each of the ECC sectors. The memory interface transmits a codeword set including the ECC sectors and the outer parity bits to the nonvolatile memory device.

According to embodiments of the present invention for achieving the above object, a plurality of word lines stacked on a top surface of a substrate, a plurality of memory cells formed in channel holes extending in a vertical direction from the substrate, and extending in a first horizontal direction. and a memory cell array including word line cut regions dividing the word lines into a plurality of memory blocks, and a method of operating the storage device controlling the non-volatile memory device, the storage controller includes A plurality of sub-data units included in user data in a write operation for memory cells of a target page connected to a target word line among the plurality of word lines by an error correction code (ECC) encoder that is A plurality of ECC sectors are configured by generating parity bits for each of the sub data units by performing first ECC encoding on each of the sub data units, and dividing the memory cells into outer cells and An outer ECC sector including the outer cell bits is configured by selecting outer cell bits to be stored in the outer cells from the ECC sectors based on a location index for classifying the inner cells, and the ECC encoder determines the outer ECC sector A second ECC encoding is performed on the ECC to generate outer parity bits, and a codeword set including the ECC sectors and the outer parity bits is transmitted to the nonvolatile memory device.

A storage device according to embodiments of the present invention for achieving the above object includes a non-volatile memory device and a storage controller. The non-volatile memory device includes a plurality of word lines stacked on a top surface of a substrate, a plurality of memory cells formed in channel holes extending in a direction perpendicular to the substrate, and a plurality of memory cells extending in a first horizontal direction and connecting the word lines to a plurality of memories. and a memory cell array including word line cut regions divided into blocks. The storage controller controls an operation of the non-volatile memory device. The storage controller includes an ECC engine and a memory interface. The ECC engine generates a first error correction code for each of a plurality of sub data units included in user data in a write operation on memory cells of a target page connected to a target word line among the plurality of word lines. , Hereinafter, 'ECC') encoding is performed to generate parity bits for each of the sub data units to configure a plurality of ECC sectors, and the ECC sectors are assigned to inner cells among the memory cells based on an error correction mode signal. An ECC encoder that selects some of the inner cell bits to be stored, configures an inner ECC sector including the selected inner cell bits, and performs second ECC encoding on the inner ECC sector to generate inner parity bits provide The memory interface transmits a codeword set including the ECC sectors and the inner parity bits to the nonvolatile memory device.

A plurality of word lines stacked on an upper surface of a substrate to achieve the above object, a plurality of memory cells formed in channel holes extending in a vertical direction from the substrate, and a plurality of memory cells extending in a first horizontal direction and connecting the word lines to a plurality of memory cells. In a method of operating a nonvolatile memory device including a memory cell array having word line cut regions divided into blocks and a storage device controlling the nonvolatile memory device, an error correction code included in the storage controller , hereinafter referred to as 'ECC'), an encoder performs first ECC encoding on each of a plurality of sub data units included in user data in a write operation on memory cells of a target page connected to a target word line among the plurality of word lines. to form a plurality of ECC sectors by generating parity bits for each of the sub data units, select inner cell bits to be stored in inner cells among the memory cells from the ECC sectors, and select some of the inner cell bits configures an inner ECC sector that includes the inner ECC sector, the ECC encoder performs second ECC encoding on the inner ECC sector to generate inner parity bits, and a codeword set including the ECC sectors and the inner parity bits is Transfer to a non-volatile memory device.

In the storage device and method of operating the storage device according to embodiments of the present invention, memory cells of a target page are divided into outer cells and inner cells based on a relative distance from a word line cut region based on a location index, and first In the error correction mode, first ECC encoding and first ECC decoding are performed on each of a plurality of sub data units included in user data, and outer cell bits to be stored (read) in outer cells having a high error occurrence probability are included. An outer ECC sector that cannot be corrected by the first ECC decoding may be corrected by the second ECC decoding by configuring the outer ECC sector and performing second ECC encoding and second ECC decoding on the outer ECC sector. In addition, in the second error correction mode, an inner ECC sector including inner cell bits to be stored in inner cells with a low error occurrence probability is configured, second ECC encoding is performed on the inner ECC sector, and in a read operation, the inner ECC sector First ECC decoding may be performed on , and errors of the sub data units may be corrected by performing second ECC decoding on each of the sub data units with reference to a result of the first ECC decoding.

1 is a block diagram illustrating a storage system according to example embodiments.
2 is a block diagram illustrating the host of FIG. 1 according to embodiments of the present invention.
FIG. 3 is a block diagram illustrating a configuration of a storage controller in the storage device of FIG. 1 according to example embodiments.
FIG. 4 is a block diagram illustrating a connection between a storage controller and one nonvolatile memory device in the storage device of FIG. 1 .
5 is a block diagram illustrating the configuration of an ECC engine in the storage controller of FIG. 4 according to embodiments of the present invention.
6 shows the operation of an ECC encoder in the ECC engine of FIG. 5 according to embodiments of the present invention.
FIG. 7 shows that the ECC encoder of FIG. 5 sequentially performs first ECC encoding on a plurality of sub data units.
8A and 8B show that the ECC encoder of FIG. 5 performs first ECC encoding on a plurality of sub data units in parallel.
9 illustrates an operation of the ECC decoder of FIG. 5 according to embodiments of the present invention.
10 is a block diagram illustrating the configuration of an ECC engine in the storage controller of FIG. 4 according to embodiments of the present invention.
11 is a block diagram illustrating a nonvolatile memory device in FIG. 4 according to example embodiments.
FIG. 12 is a block diagram illustrating a memory cell array in the nonvolatile memory device of FIG. 11 .
FIG. 13 is a circuit diagram illustrating one memory block among the memory blocks of FIG. 12 .
FIG. 14 shows an example of the structure of one NAND string of the memory block of FIG. 13 .
15 is a block diagram illustrating an example of a configuration of a memory cell array in the nonvolatile memory device of FIG. 11 according to example embodiments.
FIG. 16 is a perspective view illustrating one memory block among the memory blocks of FIG. 12 .
FIG. 17 is a plan view illustrating one memory block among the memory blocks of FIG. 12 .
FIG. 18 is a circuit diagram illustrating connections of NAND strings included in the memory block of FIG. 17 .
FIG. 19A is a graph showing a distribution of threshold voltages of memory cells when the memory cells included in the memory cell array of FIG. 11 are 4-bit quadruple level cells.
19B and 19C are graphs illustrating cases in which the threshold voltage of a memory cell in the graph of FIG. 19A is changed.
19D is a diagram for explaining bit mapping for programming memory cells according to example embodiments.
FIG. 20 is an enlarged graph of the first program state P1 and the second program state P2 of FIG. 19A.
21 illustrates a cell region in which the memory cell array of FIG. 12 according to example embodiments is formed.
22A and 22B illustratively show cross-sections of NAND strings respectively included in the memory blocks of FIG. 21 .
FIG. 23 shows a vertical structure of one channel hole of FIG. 21 .
24 illustrates a write operation of the storage device of FIG. 4 according to example embodiments.
25 illustrates a read operation of the storage device of FIG. 4 according to example embodiments.
26 is a flowchart illustrating a method of operating a storage device according to example embodiments.
27 is a block diagram illustrating another example of the configuration of an ECC engine in the storage controller of FIG. 4 according to embodiments of the present invention.
28 illustrates the operation of an ECC encoder in the ECC engine of FIG. 27 according to embodiments of the present invention.
29 illustrates the operation of an ECC encoder in the ECC engine of FIG. 27 according to embodiments of the present invention.
30 illustrates the operation of an ECC encoder in the ECC engine of FIG. 27 according to embodiments of the present invention.
31 illustrates that the ECC encoder of FIG. 27 sequentially performs first ECC encoding on a plurality of sub data units.
32 illustrates that the ECC encoder of FIG. 27 performs first ECC encoding on a plurality of sub data units and second ECC encoding on an inner ECC sector in parallel.
33 illustrates that the ECC encoder of FIG. 27 sequentially performs first ECC encoding on a plurality of sub data units.
34 illustrates that the ECC encoder of FIG. 27 performs first ECC encoding on a plurality of sub data units and second ECC encoding on inner ECC sectors in parallel.
35 illustrates an operation of the ECC decoder of FIG. 27 according to embodiments of the present invention.
36 shows that the ECC decoder of FIG. 27 performs third ECC decoding.
37 is a flowchart illustrating a method of operating a storage device according to example embodiments.
38 is a cross-sectional view illustrating a nonvolatile memory device according to example embodiments.
39 is a block diagram illustrating an electronic system including a semiconductor device according to example embodiments.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in more detail. The same reference numerals are used for the same components in the drawings, and redundant descriptions of the same components are omitted.

1 is a block diagram illustrating a storage system according to example embodiments.

Referring to FIG. 1 , a storage system 50 may include a host 100 and a storage device 200 . The host 100 includes a storage interface 140 .

The storage device 200 of FIG. 1 may be any type of storage device capable of storing data.

The storage device 200 may include a storage controller 300 , a plurality of nonvolatile memory devices 400a to 400k , a power management integrated circuit (PMIC) 600 , and a host interface 240 . The host interface 240 may include a signal connector 241 and a power connector 243 . The storage device 200 may further include a volatile memory device 250 .

The plurality of nonvolatile memory devices 400a to 400k are used as storage media of the storage device 200 . Each of the nonvolatile memory devices 400a to 400k may be implemented as a flash memory or a vertical NAND memory device. The storage controller 300 is connected to each of the non-volatile memory devices 400a to 400k through a plurality of channels CHK1 to CHk.

The storage controller 300 receives a request REQ from the host 100 through the signal connector 241 and transmits and receives data DTA with the host 100 . The storage controller 300 writes data DTA into the nonvolatile memory devices 400a to 400k based on the request REQ received from the host 100 or data from the nonvolatile memory devices 400a to 400k. (DTA) is read.

In this case, the storage controller 300 may transmit and receive data DTA with the host 100 by using the volatile memory device 250 as an input/output buffer. In one embodiment, the volatile memory device 250 may include Dynamic Random Access Memory (DRAM).

The PMIC 600 may receive a plurality of power supply voltages (or external power supply voltages, VES1 to VESt) from the host 100 through the power connector 243 . For example, the power connector 243 includes a plurality of power lines P1 to Pt, and the PMIC 600 receives power voltages VES1 to Pt from the host 100 through the power lines P1 to Pt. VESt) can be received respectively. Here, t represents a positive integer of 2 or more.

The PMIC 600 provides at least one first operating voltage VOP1 necessary for the operation of the storage controller 300 and necessary for the operation of the nonvolatile memory devices 400a to 400k based on the power supply voltages VES1 to VESt. At least one second operating voltage VOP2 and at least one third operating voltage VOP3 necessary for the operation of the volatile memory device 250 may be generated.

For example, when the PMIC 600 receives all of the power supply voltages VES1 to VESt from the host 100, it generates at least one first operating voltage VOP1 by using all of the power supply voltages VES1 to VESt. , at least one second operating voltage VOP2 , and at least one third operating voltage VOP3 may be generated. On the other hand, when the PMIC 500 receives only some of the power supply voltages VES1 to VESt from the host 100, it uses all of the received power supply voltages to generate at least one first operating voltage VOP1, At least one second operating voltage VOP2 and at least one third operating voltage VOP3 may be generated.

2 is a block diagram illustrating the host of FIG. 1 according to embodiments of the present invention.

Referring to FIG. 2 , the host 100 includes a central processing unit (CPU) 110, a ROM 120, a main memory 130, a storage interface 140, a user interface 150, and a bus ( 160) may be included.

The bus 160 means a transmission path for transferring data between the CPU 110, the ROM 120, the main memory 130, the storage interface 140, and the user interface 150 of the host 100. Various application programs are stored in the ROM 120 . In the embodiment, application programs supporting storage protocols such as ATA (Advanced Technology Attachment), SCSI (Small Computer System Interface), eMMC (embedded Multi Media Card), UFS (Unix File System), etc. are stored in the ROM 120 It can be.

Data or programs may be temporarily stored in the main memory 130 . The user interface 150 includes physical hardware and logical software as a physical or virtual medium capable of exchanging information between a user, a host device, and a computer program. That is, the user interface 150 may include an input device through which a user can manipulate the host 100 and an output device displaying a result of processing a user input.

The CPU 110 controls overall operations of the host 100 . The CPU 110 requests (or commands) to store data in the storage device 200 or reads data from the storage device 200 using an application or tool stored in the ROM 120. Commands and power supply voltages VES1 to VESt may be generated and transmitted to the storage device 200 through the storage interface 140 .

FIG. 3 is a block diagram illustrating a configuration of a storage controller in the storage device of FIG. 1 according to example embodiments.

Referring to FIG. 3 , the storage controller 300 includes a processor 310, an ECC engine 500, an on-chip memory 330, a randomizer 340, and a host interface 350 connected to each other through a bus 305. ), a ROM 360 and a memory interface 370.

The processor 310 controls overall operations of the storage controller 300 . The processor 310 may control the on-chip memory 330 , the ECC engine 500 , the randomizer 540 and the memory interface 370 . Processor 310 may include one or more cores (eg, homogeneous multi-core or heterogeneous multi-core). For example, the processor 310 may include a central processing unit (CPU), an image signal processing unit (ISP), a digital signal processing unit (DSP), a graphics processing unit (GPU), a vision processing unit (VPU), and a neural processing unit (NPU). Processing Unit) may include at least one. The processor 310 may execute various application programs (eg, a Flash Translation layer (FTL)), firmware, etc. loaded in the on-chip memory 130 .

The on-chip memory 330 may store various application programs executed by the processor 310 . The on-chip memory 330 may operate as cache memory adjacent to the processor 310 . The on-chip memory 330 may store commands, addresses, data, etc. to be processed by the processor 110 or may store processing results of the processor 310 . For example, the on-chip memory 330 includes a latch, a register, a static random access memory (SRAM), a dynamic random access memory (DRAM), a thyristor random access memory (TRAM), and a tightly coupled TCM (tightly coupled memory). Memory) or the like, or a working memory.

The processor 310 may execute the FTL 335 loaded into the on-chip memory 330 . The FTL 335 may be loaded into the on-chip memory 330 as firmware or a program stored in one of the non-volatile memory devices 400a to 400k. The FTL 335 may include an address mapping table manager that manages and updates mapping between logical addresses and physical addresses of the nonvolatile memory devices 400a to 400k. In addition to the aforementioned address mapping, the FTL 335 may further perform garbage collection, wear leveling, and the like. The FTL 335 has limitations of the non-volatile memory devices 400a to 400k (eg, overwrite or in-place write not possible, lifespan of a memory cell, limited P/E (Program-Erase) cycle, erase speed is slower than write speed, etc.).

In particular, the FTL 335 ECC a location index (LIDX) for classifying memory cells included in each page of the nonvolatile memory devices 400a to 400k into outer cells and inner cells according to a distance from the word line cut region. It can be provided to the engine 500. The location index LIDX may divide the memory cells included in each page into outer cells relatively close in distance from the word line cut area and inner cells relatively far from the word line cut area.

The ECC engine 500 may include an ECC encoder 520 and an ECC decoder 550.

In a write operation of writing the user data DTA to a target page connected to a target word line among a plurality of word lines in the first error correction mode, the ECC encoder 520 uses a first one of data bits of the user data DTA. A plurality of ECC sectors are formed by performing first ECC encoding on the data bits of the unit a plurality of times to generate parity bits for each of the first units, memory cells based on a location index (IDX) or known in advance An outer ECC sector including the outer data bits is configured by selecting outer data bits to be stored in the outer cells from the ECC sectors based on location information for , and second ECC encoding is performed on the outer ECC sector. Thus, outer parity bits may be generated. The ECC encoder 520 may transmit a codeword set including ECC sectors, parity bits, and outer parity bits to the nonvolatile memory devices 400a to 400k through the memory interface 370 .

In a read operation for a target page, the ECC decoder 550 receives a codeword set from one of the non-volatile memory devices 400a to 400k in a first error correction mode, and reads the ECC sectors based on the location index. configures the outer ECC sector, performs first ECC decoding on each of the ECC sectors, and when an uncorrectable error is detected in at least one of the ECC sectors as a result of the first ECC decoding, the outer parity Second ECC decoding may be performed on the outer ECC sector based on the bits.

In a write operation of writing the user data DTA to a target page connected to a target word line among a plurality of word lines in the second error correction mode, the ECC encoder 520 uses first data bits of the user data DTA. A plurality of ECC sectors are formed by performing first ECC encoding on the data bits of the unit a plurality of times to generate parity bits for each of the first units, memory cells based on a location index (IDX) or known in advance An inner ECC sector including at least some of the inner data bits is configured by selecting inner data bits to be stored in the inner cells from the ECC sectors based on location information for the second ECC sector for the inner ECC sector. Encoding may be performed to generate inner parity bits. The ECC encoder 520 may transmit a codeword set including ECC sectors, parity bits, and inter parity bits to the nonvolatile memory devices 400a to 400k through the memory interface 370 .

The ECC decoder 550 receives a codeword set from one of the nonvolatile memory devices 400a to 400k in the second error correction mode of a read operation for a target page, and in the ECC sectors based on the location index configuring the inner ECC sector, performing first ECC decoding on the inner ECC sector based on the inter parity bits to correct at least one error bit of the inner ECC sector, and at least some of the ECC sectors At least one error bit of each of the ECC sectors may be corrected by performing second ECC decoding on .

In an embodiment, when at least some of the ECC sectors include uncorrectable errors, the ECC decoder 550 may perform third ECC decoding on all of the ECC sectors.

To control the operation of the ECC engine 500, the processor 310 may provide an error correction mode signal EMS to the ECC engine 500. The error correction mode signal EMS may be related to selection of outer cell bits and inner cell bits, and when the error correction mode signal EMS has a first logic level, the ECC engine 500 operates in the first error correction mode. operates in , selects outer cell bits to form an outer ECC sector, and when the error correction mode signal EMS is at the second logic level, the ECC engine 500 operates in the second error correction mode and selects inner cell bits. In this way, the inner ECC sector can be configured.

The randomizer 340 may randomize data to be stored in one of the nonvolatile memory devices 400a to 400k. For example, the randomizer 340 may randomize data to be stored in one of the nonvolatile memory devices 400a to 400k in units of word lines.

For example, the randomizer 340 may randomize page data. By way of example, the configuration of an ideal randomizer 340 has been described for concise description. However, the technical idea of the present invention is not limited thereto, and the actual randomizer 340 determines the number of memory cells having an erase state and each of the first to fifteenth program states among memory cells connected to one word line. You can randomize the data so that they are close to the same value. That is, memory cells storing randomized data may have substantially similar numbers of program states.

The storage controller 300 may communicate with the host 100 through the host interface 350 . For example, the host interface 350 may include universal serial bus (USB), multimedia card (MMC), peripheral component interconnection (PCI), PCI-express (PCI-E), advanced technology attachment (ATA), serial-ATA, Parallel-ATA, SCSI (small computer small interface), ESDI (enhanced small disk interface), IDE (Integrated Drive Electronics), MIPI (Mobile Industry Processor Interface), NVMe (Nonvolatile Memory-express), UFS (Universal Flash Storage Interface) It may be provided with at least one of various interfaces such as The storage controller 300 may communicate with the non-volatile memory devices 400a to 400k through the memory interface 370 .

FIG. 4 is a block diagram illustrating a connection between a storage controller and one nonvolatile memory device in the storage device of FIG. 1 .

Referring to FIG. 4 , the storage controller 300 may operate based on the first operating voltage VOP1. The nonvolatile memory device 400a may perform erase, write, and read operations under the control of the storage controller 300 . To this end, the nonvolatile memory device 400a receives a command (CMD), an address (ADDR), and data (DTA or write data (WD)) through input/output lines. In addition, the nonvolatile memory device 400a may receive a control signal CTRL through a control line and may receive power PWR1 through a power line. In addition, the nonvolatile memory device 400a may provide a status signal RnB to the storage controller 300 through a control line. Also, the nonvolatile memory device 400a may provide data DTA or read data RD to the storage controller 300 .

The storage controller 300 may include an ECC engine 500, and the ECC engine 500 may include an ECC encoder 520 and an ECC decoder 550. The ECC encoder 510 may perform ECC encoding on data to be stored in the nonvolatile memory device 400a, and the ECC decoder 550 may perform ECC decoding on data read from the nonvolatile memory device 400a. there is.

5 is a block diagram illustrating an example of a configuration of an ECC engine in the storage controller of FIG. 4 according to embodiments of the present invention.

Referring to FIG. 5, the ECC engine 500a may include an ECC memory 510 storing ECC 515, an ECC encoder 520a, an ECC decoder 550a, a data selector 580a, and a buffer 590a. can

The ECC encoder 520a is connected to the ECC memory 510 and performs first ECC encoding on data bits of user data for each sub data unit (SDUI) in a write operation for a target page using the ECC 515 to generate the corresponding parity bits PRTi, and provide the ECC sector ECCSi including the sub data unit SDUI and the corresponding parity bits PRTi to the data selector 580a and the buffer 590a. can

The data selector 580a selects outer cell bits in each of the sub data units SDUI in the first error correction mode based on the error correction mode signal EMS and the location index LIDX to form the outer ECC sector OECCS. and provide the outer ECC sector (OECCS) to the ECC encoder 520a.

The ECC encoder 520a performs second ECC encoding on the outer ECC sector OECCS using the ECC 515 to generate outer parity bits OPRT, and stores the outer parity bits OPRT in a buffer ( 590a).

The buffer 590a transmits ECC sectors ECCSi including parity bits PRTi corresponding to the sub data unit SDUI and a codeword set SCW including outer parity bits OPRT to a memory interface ( It can be provided to the non-volatile memory device 400a through 370).

In a read operation on the target page, the buffer 590a includes ECC sectors ECCSi including the parity bits PRTi corresponding to the sub data unit SDUI and a codeword including the outer parity bits OPRT. The set (SCW) is received from the non-volatile memory device 400a through the memory interface 370, the ECC sectors (ECCSi) are provided to the ECC decoder 550a, and the ECC sectors (ECCSi) and outer parity bits ( OPRT) to data selector 580a. .

The ECC decoder 550a is connected to the ECC memory 510 and performs first ECC decoding on each of the ECC sectors (ECCSi) using the ECC 515 to obtain correctable information included in each of the ECC sectors (ECCSi). Errors can be corrected. When an uncorrectable error is detected in at least one of the ECC sectors (ECCSi) as a result of performing the first ECC encoding, the ECC decoder 550a indicates that an uncorrectable error is detected in at least one of the ECC sectors (ECCSi). An error flag (ERR) may be provided to the data selector 580a.

The data selector 580a configures the outer ECC sector OECCS by selectively selecting outer cell bits from each of the ECC sectors ECCSi based on the location index LIDX in response to the error flag ERR, and constructs the outer ECC sector OECCS. The sector OECCS and the outer parity bits OPRT may be provided to the ECC decoder 550a.

The ECC decoder 550a may correct an uncorrectable error of the outer ECC sector OECCS by performing second ECC decoding on the outer ECC sector OECCS based on the outer parity bits OPRT.

6 shows the operation of an ECC encoder in the ECC engine of FIG. 5 according to embodiments of the present invention.

In FIG. 6 , it is assumed that the user data DTA of FIG. 5 includes first to fourth sub data units SDU1 , SDU2 , SDU3 , and SDU4 . Also, each of the first to fourth sub data units SDU1 , SDU2 , SDU3 , and SDU4 may include outer cell bits OCB and inner cell bits ICB.

5 and 6, the ECC encoder 520a performs first ECC encoding on the first sub data unit SDU1 using the ECC 515 to generate first parity bits PRT1, A first ECC sector ECCS1 including the first sub data unit SDU1 and the first parity bits PRT1 is formed.

The ECC encoder 520a performs first ECC encoding on the second sub data unit SDU2 using the ECC 515 to generate second parity bits PRT2, and generates second parity bits PRT2 and the second sub data unit SDU2. A second ECC sector ECCS2 including the second parity bits PRT2 is configured.

The ECC encoder 520a performs first ECC encoding on the third sub data unit SDU3 using the ECC 515 to generate third parity bits PRT3, and generates third sub data unit SDU3 and A third ECC sector ECCS3 including the third parity bits PRT3 is configured.

The ECC encoder 520a performs first ECC encoding on the fourth sub data unit SDU4 using the ECC 515 to generate fourth parity bits PRT4, and generates fourth sub data unit SDU4 and A fourth ECC sector ECCS4 including the fourth parity bits PRT4 is configured.

The ECC encoder 520a may sequentially or in parallel perform first ECC encoding on the first to fourth sub data units SDU1 , SDU2 , SDU3 , and SDU4 .

The ECC encoder 520a configures the outer ECC sector OECCS with the outer cell bits OCB of each of the first to fourth sub data units SDU1 , SDU2 , SDU3 , and SDU4 , and constructs the outer ECC sector OECCS The outer cell parity bits (OPRT) may be generated by performing second ECC encoding on .

FIG. 7 shows that the ECC encoder of FIG. 5 sequentially performs first ECC encoding on a plurality of sub data units.

Referring to FIG. 7 , the ECC encoder 520a performs first ECC encoding on each of the first to fourth sub data units SDU1 , SDU2 , SDU3 , and SDU4 including outer cell bits OCB, respectively. Thus, the first parity bits PRT1 , the second parity bits PRT2 , the third parity bits PRT3 , and the fourth parity bits PRT4 may be sequentially generated. In addition, the ECC encoder 520a configures the outer ECC sector OECCS with the outer cell bits OCB of each of the first to fourth sub data units SDU1, SDU2, SDU3, and SDU4, and configures the outer ECC sector OECCS. ) may be subjected to second ECC encoding to generate outer cell parity bits (OPRT).

8A and 8B respectively show that the ECC encoder of FIG. 5 performs first ECC encoding on a plurality of sub data units in parallel.

Referring to FIG. 8A , an ECC encoder 520aa may include first to fifth sub ECC encoders 521 , 523 , 525 , 527 , and 529 .

The first to fifth sub-ECC encoders 521, 523, 525, 527, and 529 are connected to the ECC 515 of FIG. 5, respectively, and the first to fourth sub-ECC encoders 521, 523, 525, and 527 ) Parallelly performs first ECC encoding on each of the first to fourth sub data units SDU1 , SDU2 , SDU3 , and SDU4 each including the outer cell bits OCB to obtain first parity bits. PRT1 , second parity bits PRT2 , third parity bits PRT3 , and fourth parity bits PRT4 may be generated in parallel. In addition, the fifth sub-ECC encoder 529 outputs the outer ECC sector OECCS composed of the outer cell bits OCB of the first to fourth sub data units SDU1, SDU2, SDU3, and SDU4 in the second ECC encoding may be performed in parallel with the first ECC encoding to generate outer cell parity bits (OPRT).

Referring to FIG. 8B , an ECC encoder 520ab may include first to fourth sub-ECC encoders 521, 523, 525, and 527.

The first to fourth sub-ECC encoders 521, 523, 525, and 527 are respectively connected to the ECC 515 of FIG. 5, and the first to fourth sub-data units each include outer cell bits (OCB). (SDU1, SDU2, SDU3, SDU4), the first ECC encoding is performed in parallel to obtain first parity bits PRT1, second parity bits PRT2, third parity bits PRT3 and Fourth parity bits PRT4 may be generated in parallel. In addition, the first sub-ECC encoder 521 generates a second sub-ECCS for the outer ECC sector OECCS composed of the outer cell bits OCB of the first to fourth sub-data units SDU1, SDU2, SDU3, and SDU4. ECC encoding may be performed to generate outer cell parity bits (OPRT).

9 illustrates an operation of the ECC decoder of FIG. 5 according to embodiments of the present invention.

5 and 9 , the ECC decoder 550a includes a first sub data unit SDU1′ including first outer cell bits OCB1′ read from a target page of the nonvolatile memory device 400a. ) and the first parity bits PRT1, the second sub data unit SDU2' including the second outer cell bits OCB2', and the second parity bits PRT2. a second ECC sector including third outer cell bits OCB3', a third sub data unit SDU3' including third parity bits PRT3, a third ECC sector including third outer cell bits, and a fourth outer cell First ECC decoding is performed on each of the fourth sub data unit SDU4′ including the bits OCB4′ and the fourth ECC sector including the fourth parity bits PRT4, and (SDU1'), the second sub data unit (SDU2'), the third sub data unit (SDU3'), and the fourth sub data unit (SDU4') are each corrected to form a first sub data unit (SDU1). , the second sub data unit SDU2 , the third sub data unit SDU3 , and the fourth sub data unit SDU4 ″ can be output.

Each of the first parity bits PRT1 , the second parity bits PRT2 , the third parity bits PRT3 , and the fourth parity bits PRT4 may also include outer parity bits read from outer cells. .

As a result of performing the first ECC decoding, errors in the outer cell bits OCB1 , OCB2 , and OCB3 of the first sub data unit SDU1 , the second sub data unit SDU2 , and the third sub data unit SDU3 respectively is corrected, and an uncorrectable error is detected in the outer cell bits OCB4″ of the fourth sub data unit SDU4″. The ECC decoder 550 performs second ECC decoding on an outer ECC sector composed of outer cell bits OCB1 , OCB2 , and OCB3 and outer cell bits OCB4 ″ using the outer cell parity bits OPRT. The outer cell bits OCB4 may be output by correcting errors of the outer cell bits OCB4 ″ by performing .

10 is a block diagram illustrating the configuration of an ECC engine in the storage controller of FIG. 4 according to embodiments of the present invention.

Referring to FIG. 10, the ECC engine 500b may include an ECC memory 510 storing ECC 515, an ECC encoder 520b, an ECC decoder 550b, a data selector 580b, and a buffer 590b. can

The data selector 580b configures the outer ECC sector OECCS by selecting outer cell bits from each of the sub data units SDUI based on the error correction mode signal EMS and the location index LIDX, and (OECCS) may be provided to the ECC encoder 520b.

The ECC encoder 520b is connected to the ECC memory 510 and performs first ECC encoding on the outer ECC sector OECCS in a write operation for a target page using the ECC 515 to obtain outer parity bits OPRT ) is generated, outer cell parity bits (OPRT) are provided to the buffer 590b, and second ECC encoding is performed on each of the sub data units (SDUI) included in the user data to obtain corresponding parity bits ( PRTi) may be generated, and the ECC sector ECCSi including the sub data unit SDUI and the corresponding parity bits PRTi may be provided to the buffer 590b.

The buffer 590b transmits ECC sectors ECCSi including parity bits PRTi corresponding to the sub data unit SDUI and a codeword set SCW including outer parity bits OPRT to a memory interface ( It can be provided to the non-volatile memory device 400a through 370).

In a read operation on the target page, the buffer 590b includes ECC sectors ECCSi including a plurality of sub data units SDUI and corresponding parity bits PRTi and outer parity bits OPRT. receives a codeword set (SCW) from the non-volatile memory device 400a through the memory interface 370, provides ECC sectors (ECCSi) to the ECC decoder 550b, and transmits ECC sectors (ECCSi) and outer parity The bits OPRT may be provided to the data selector 580b.

The ECC decoder 550b is connected to the ECC memory 510 and performs first ECC decoding on each of the ECC sectors (ECCSi) using the ECC 515 to obtain correctable information included in each of the ECC sectors (ECCSi). Errors can be corrected.

The data selector 580b configures the outer ECC sector OECCS by selecting outer cell bits from each of the ECC sectors ECCSi based on the error correction mode signal EMS and the location index LIDX, and configures the outer ECC sector ( OECCS) and outer parity bits (OPRT) may be provided to the ECC decoder 550b.

The ECC decoder 550b may correct an uncorrectable error of the outer ECC sector OECCS by performing second ECC decoding on the outer ECC sector OECCS based on the outer parity bits OPRT.

11 is a block diagram illustrating a nonvolatile memory device in FIG. 4 according to example embodiments.

Referring to FIG. 11 , a nonvolatile memory device 400a includes a memory cell array 420, an address decoder 450, a page buffer circuit 430, a data input/output circuit 440, a control circuit 460, and a voltage generator ( 470) may be included.

The memory cell array 420 may be connected to the address decoder 450 through a string select line SSL, a plurality of word lines WLs, and a ground select line GSL. Also, the memory cell array 420 may be connected to the page buffer circuit 430 through a plurality of bit lines BLs. The memory cell array 420 may include a plurality of memory cells connected to a plurality of word lines WLs and a plurality of bit lines BLs.

In one embodiment, the memory cell array 420 may be a three-dimensional memory cell array formed in a three-dimensional structure (or vertical structure) on a substrate. In this case, the memory cell array 420 may include a plurality of NAND strings including a plurality of memory cells formed by being stacked on each other.

FIG. 12 is a block diagram illustrating a memory cell array in the nonvolatile memory device of FIG. 11 .

Referring to FIG. 12 , the memory cell array 420 includes a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz extend along the first horizontal direction HD1 , the second horizontal direction HD2 , and the vertical direction VD. In an embodiment, the memory blocks BLK1 to BLKz are selected by the address decoder 450 shown in FIG. 5 . For example, the address decoder 450 may select a memory block BLK corresponding to a block address from among the memory blocks BLK1 to BLKz.

FIG. 13 is a circuit diagram illustrating one memory block among the memory blocks of FIG. 12 .

The memory block BLKi shown in FIG. 13 represents a three-dimensional memory block formed on the substrate SUB in a three-dimensional structure. For example, a plurality of memory NAND strings included in the memory block BLKi may be stacked in a direction VD perpendicular to the substrate SUB.

Referring to FIG. 13 , the memory block BLKi may include a plurality of NAND strings NS11 to NS33 connected between the bit lines BL1 , BL2 , and BL3 and the common source line CSL. Each of the plurality of NAND strings NS11 to NS33 may include a string select transistor SST, a plurality of memory cells MC1, MC2, ..., MC8, and a ground select transistor GST.

The string select transistor SST may be connected to corresponding string select lines SSL1 , SSL2 , and SSL3 . The plurality of memory cells MC1 , MC2 , ..., MC8 may be connected to corresponding word lines WL1 , WL2 , ..., WL8 , respectively. The ground select transistor GST may be connected to corresponding ground select lines GSL1 , GSL2 , and GSL3 . The string select transistor SST may be connected to corresponding bit lines BL1 , BL2 , and BL3 , and the ground select transistor GST may be connected to the common source line CSL.

Word lines (eg, WL1) having the same height may be commonly connected, and ground select lines GSL1, GSL2, and GSL3 and string select lines SSL1, SSL2, and SSL3 may be separated from each other.

FIG. 14 shows an example of the structure of one NAND string of the memory block of FIG. 13 .

Referring to FIGS. 13 and 14 , the NAND string NS11 may be provided with a pillar PL extending in a direction VD perpendicular to the substrate SUB and contacting the substrate SUB. The ground select line GSL1, the word lines WL1 to WL8, and the string select line SSL1 shown in FIG. 13 may be formed of conductive materials parallel to the substrate SUB, for example, metal materials. can The pillar PL may contact the substrate SUB by passing through conductive materials forming the ground select line GSL1 , the word lines WL1 to WL8 , and the string select line SSL1 .

In Fig. 14, a cross-sectional view along the cutting line V-V' is also shown. Exemplarily, a cross-sectional view of the first memory cell MC1 corresponding to the first word line WL1 is shown. The pillar PL may include a cylindrical body BD. An air gap AG may be provided inside the body BD.

The body BD may include P-type silicon and may be a region in which a channel is formed. The pillar PL may further include a cylindrical tunnel insulating layer TI surrounding the body BD and a cylindrical charge trapping layer CT surrounding the tunnel insulating layer TI.

A blocking insulating layer BI may be provided between the first word line WL1 and the pillar PL. The body BD, the tunnel insulating layer TI, the charge trapping layer CT, the blocking insulating layer BI, and the first word line WL1 are formed in a direction perpendicular to the substrate SUB or an upper surface of the substrate SUB. It may be a formed charge trapping transistor. The string select transistor SST, the ground select transistor GST, and other memory cells may have the same structure as the first memory cell MC1.

Referring back to FIG. 11 , the control circuit 460 receives the command CMD and the address signal ADDR from the storage controller 300, and the nonvolatile memory device based on the command CMD and the address signal ADDR. The erase loop, program loop and read operation of 400a can be controlled. Here, the program loop may include a program operation and a program verify operation, and the erase loop may include an erase operation and an erase verify operation.

For example, the control circuit 460 generates control signals CTLs for controlling the voltage generator 470 based on the command signal CMD, and generates the row address R_ADDR based on the address signal ADDR. And a column address (C_ADDR) can be generated. The control circuit 460 may provide the row address R_ADDR to the address decoder 450 and the column address C_ADDR to the data input/output circuit 440 .

The address decoder 450 may be connected to the memory cell array 420 through a string select line SSL, a plurality of word lines WLs, and a ground select line GSL. During a program operation or a read operation, the address decoder 450 determines one of a plurality of word lines WLs as a first word line, which is a selected word line, based on the row address R_ADDR provided from the control circuit 460 And, among the plurality of word lines WLs, word lines other than the first word line may be determined as unselected word lines.

The voltage generator 470 generates word line voltages VWLs necessary for the operation of the nonvolatile memory device 400a using the power PWR1 based on the control signals CTLs provided from the control circuit 460. can do. The word line voltages VWLs generated by the voltage generator 470 may be applied to the plurality of word lines WLs through the address decoder 450 .

For example, during an erase operation, the voltage generator 470 may apply an erase voltage to a well of a memory block and a ground voltage to all word lines of the memory block. During the erase verify operation, the voltage generator 470 may apply the erase verify voltage to all word lines of one memory block or may apply the erase verify voltage in units of word lines.

For example, during a program operation, the voltage generator 470 may apply a program voltage to a first word line and a program pass voltage to unselected word lines. Also, during the program verify operation, the voltage generator 470 may apply a program verify voltage to the first word line and apply a verify pass voltage to unselected word lines.

Also, during a read operation, the voltage generator 470 may apply a read voltage to the first word line and apply a read pass voltage to unselected word lines.

The page buffer circuit 430 may be connected to the memory cell array 420 through a plurality of bit lines BLs. The page buffer circuit 430 may include a plurality of page buffers. In one embodiment, one bit line may be connected to one page buffer. In another embodiment, two or more bit lines may be connected to one page buffer.

The page buffer circuit 430 may temporarily store data to be programmed in a selected page during a program operation, and may temporarily store data read from the selected page during a read operation.

The data input/output circuit 440 may be connected to the page buffer circuit 430 through data lines DLs. During a program operation, the data input/output circuit 440 receives ECC sectors (ECCSi) and outer parity bits (OPRT) or ECC sectors (ECCSi) and inner parity bits (IPRT) from the storage controller 300, Based on the column address C_ADDR provided from the control circuit 460, the ECC sectors ECCSi and the outer parity bits OPRT or the ECC sectors ECCSi and the inner parity bits IPRT are stored in the page buffer circuit ( 430) can be provided.

During a read operation, the data input/output circuit 440 outputs ECC sectors ECCSi and outer parity bits OPRT stored in the page buffer circuit 430 based on the column address C_ADDR provided from the control circuit 500 or ECC sectors (ECCSi) and inner parity bits (IPRT) may be provided to the storage controller 300 .

The page buffer circuit 430 and the data input/output circuit 440 may be controlled by the control circuit 460 .

The control circuit 460 may include a state signal generator 465 that generates a state signal RnB indicating whether the program, erase, and read operations of the memory cell array 420 are completed and/or progressed. .

The storage controller 300 may determine an idle state and a busy state of each of the nonvolatile memory devices 400a to 400k based on the state signal RnB.

15 is a block diagram illustrating an example of a configuration of a memory cell array in the nonvolatile memory device of FIG. 11 according to example embodiments.

Referring to FIG. 15 , the memory cell array 420 may include a plurality of blocks BLK1 to BLKz. Each of the plurality of blocks BLK1 to BLKz may include a plurality of pages PAG1 to PAGq, where q is a natural number greater than or equal to 2.

In addition, the memory cell array 420 may include a normal cell area NCA in which user data DTA is stored and a parity cell area PCA in which parity bits PRTi and outer parity bits OPRT are stored. can

Memory cells of the normal cell area NCA and the parity cell area PCA may be connected to bit lines BL1 to BLn, where n is a natural number equal to or greater than 4. Each of the pages of the normal cell area NCA and the parity cell area PCA may include a plurality of sectors SEC1 to SECk, where k is a natural number greater than or equal to 3.

FIG. 16 is a perspective view illustrating one of the memory blocks of FIG. 12 , and FIG. 17 is a plan view of the memory block of FIG. 16 .

Referring to FIG. 16 , at least one ground string line GSL, a plurality of word lines WLs, and at least one string select line SSL are provided between the word line cut regions WLC of the memory block BLKi. It may be implemented in a form of being stacked on the substrate SUB in the vertical direction VD. Doped regions DOP may be formed on the substrate SUB of the word line cut regions WLC, and the doped regions DOP are formed by a common source line (CSL) to which a common source voltage is supplied. Alternatively, it may be used as a common source node (CSN). At least one string selection line SSL may be divided by a string selection line cut area SSLC extending in the first horizontal direction HD1.

A plurality of vertical channel holes or channel holes pass through at least one ground string line substrate (GSL), a plurality of word lines (WLs), and at least one string select line (SSL). Here, at least one ground string line (GSL), a plurality of word lines (WLs), and at least one string select line (SSL) may be implemented in the form of a substrate. Bit lines BL extending in the second horizontal direction HD2 are connected to upper surfaces of the plurality of vertical channels.

FIG. 17 is a plan view illustrating one of the memory blocks of FIG. 12 , and FIG. 18 is a circuit diagram illustrating connections of NAND strings included in the memory block of FIG. 17 .

In FIG. 17, a white circle indicates an inner cell or inner channel hole, and a dotted circle indicates an outer cell or outer channel hole. Common source lines corresponding to the doped regions DOP shown in FIG. 16 are arranged in the word line cut region WLC.

Referring to FIG. 17 , channel holes may be arranged in a zig-zag structure in the memory block BLKi. This zig-zag structure has an effect of reducing the area of the memory cell array including the memory block BLKi. One external channel hole and one internal channel hole may be disposed in the second horizontal direction HD2 between two adjacent word line cut regions WLC in the memory block BLKi. As such, one of the external channel hole and the ss channel hole disposed in the second horizontal direction HD2 may be connected to an even-numbered bit line and the other may be connected to an odd-numbered bit line. 17 shows one pair of bit lines BLi and BLo for convenience, and other bit lines are omitted.

17, the outer memory cells are formed in outer channel holes having a relatively close distance Do from the word line cut area WLC, and the inter memory cells have a distance (Do) from the word line cut area WLC. Di) is formed in relatively far inner channel holes.

Referring to FIG. 18 , an inner NAND string NSi is formed in an inner channel hole and an outer NAND string is formed in an outer channel hole. One end of the outer NAND string NSi is connected to the inner bit line BLi and the other end is connected to the common source line CSL through the inner resistor Ri. One end of the outer NAND string NSo is connected to the outer bit line BLo and the other end is connected to the common source line CSL through the outer resistor Ro.

As described above with reference to FIG. 17, the distance Di between the inner NAND string NSi (ie inner channel hole) and the common source line (ie word line cut area) is the outer NAND string NSo (ie outer channel hole) ) and the common source line, the inter resistance Ri has a greater value than the outer resistance Ro.

As such, it can be seen that the internal NAND string NSi and the outer NAND string NSo are connected to the common source line CSL through resistors Ri and Ro having different values. That is, since the inner NAND string (NSi) and the outer NAND string (NSo) have an asymmetric connection structure, the inner cells of the inner NAND string (NSi) and the outer cells of the outer NAND string (NSo) have different electrical characteristics in operation. may occur. This characteristic difference may appear as a difference in error bit level. That is, an error occurrence probability may be higher in external cells of the outer NAND string NSo closer to the word line cut region.

FIG. 19A is a graph illustrating a distribution according to threshold voltages of memory cells when the memory cells included in the memory cell array of FIG. 11 are 4-bit quadruple level cells (QLCs).

When the memory cell is a 4-bit multi-level cell programmed with 4 bits, the memory cell may have an erase state (E) or one of first to fifteenth program states (P1 to P15). In the case of a multi-level cell, compared to a single-level cell, since the interval between distributions of the threshold voltage (Vth) is narrow, a small change in the threshold voltage (Vth) may cause a serious problem in the multi-level cell.

The first read voltage Vr1 has a voltage level between the distribution of memory cells having an erase state E and the distribution of memory cells having a first program state P1. The second to fifteenth read voltages Vr2 to Vr15 have voltage levels between adjacent memory cells having a distribution of corresponding program states P1 to P15.

In one embodiment, it can be distinguished that data '1' is stored when the memory cell is turned on by applying the first read voltage Vr1, and data '0' is stored when the memory cell is turned off. However, the present invention is not limited thereto, and in another embodiment, data '0' is stored when the memory cell is turned on by applying the first read voltage Vr1, and data '1' is stored when the memory cell is turned off. It can also be identified as stored. In this way, the allocation of logical levels of data may be changed according to embodiments.

19B and 19C are graphs illustrating cases in which the threshold voltage of a memory cell in the graph of FIG. 19A is changed.

19B shows that the threshold voltages of inner cells are changed, and FIG. 19C shows that the threshold voltages of outer cells are changed.

Referring to FIGS. 19B and 19C , memory cells programmed to the erase state E and the first to fifteenth program states P1 to P15, respectively, are changed as shown in FIGS. 19B and 19C according to the read environment. may have a distribution. In FIGS. 19B and 19C , a read error may occur in memory cells belonging to hatched portions, and thus reliability of the memory device may deteriorate. More read errors may occur in the case of FIG. 19C than in the case of FIG. 19B.

For example, when a read operation is performed on the memory device using the first read voltage Vr1, even though the memory cells belonging to the shaded area are programmed to the first program state P1, the threshold voltage Vth ) can be determined as the erased state (E). Accordingly, an error may occur in a read operation, and reliability of the memory device may deteriorate.

When data is read from the non-volatile memory device 400a, a raw bit error rate (RBER) varies depending on the voltage level of the read voltage, and the optimum voltage level of the read voltage may be determined according to the distribution shape of memory cells. Accordingly, as the distribution of memory cells changes, the optimum voltage level of the read voltage required to read data from the memory device may also change.

19D is a diagram for explaining bit mapping for programming memory cells according to example embodiments.

In FIG. 19D, it is assumed that the memory cells are QLC, but this is for convenience of description and is not limited thereto.

Referring to FIG. 19D , when the memory cells are QLC, the memory cells may store LSB, ESB, USB, and MSB, respectively. Referring further to FIG. 14 , the LSB stored in the memory cells of the first row among the memory cells connected to the word line WL1 may form a least significant bit page, and the MSB may form a most significant bit page. In addition, USB may form a next-order bit page, and ESB may form a bit page between USB and LSB.

FIG. 20 is an enlarged graph of the first program state P1 and the second program state P2 of FIG. 19A.

Referring to FIG. 20 , a “Read Window (RDW)” between the first program state P1 and the second program state P2 is a fall voltage (for the first program state P1) VF) and the rise voltage VR for the second program state P2.

Here, the falling voltage VF represents a threshold voltage in which the number of off cells corresponds to the reference number REF, as a result of off-cell counting of memory cells programmed to the first program state P1. The rising voltage VR represents a threshold voltage in which the number of on-cells corresponds to the reference number REF as a result of on-cell counting of memory cells programmed to the second program state P2 . The read voltage Vr2 for determining the second program state P2 must have a voltage level between the read windows RDW, and the read window RDW must be sufficiently wide to reduce read errors. Read windows of outer cells relatively close from the word line cut region may be smaller than read windows of inner cells relatively close from the word line cut region.

21 illustrates a cell region in which the memory cell array of FIG. 12 according to example embodiments is formed.

Referring to FIG. 21 , the cell region CR includes a plurality of channel holes CH.

A channel hole size, eg, a channel hole diameter, may vary according to a location within the cell region CR. Specifically, since the peripheral density of the channel holes CHa adjacent to the first and second edges EDG1 and EDG2 is low, the diameter may be different from that of the other channel holes CHb for process reasons. The diameters of the channel holes CHb located in the central region of the cell region CR may be greater than the diameters of the channel holes CHa adjacent to the first and second edges EDG1 and EDG2 . The memory block BLKa may be adjacent to the second edge EDG2 and spaced apart from the second edge EDG2 by a first distance d1. The memory block BLKb is not adjacent to the first and second edges EDG1 and EDG2, is located in the center of the cell region CR, and is spaced apart from the second edge EDG2 by a second distance d2. can The first diameter D1 of the first channel hole CHa included in the memory block BLKa may be smaller than the second diameter D2 of the second channel hole CHb included in the memory block BLKb. .

22A and 22B illustratively show cross-sections of NAND strings respectively included in the memory blocks of FIG. 21 .

Referring to FIG. 22A , a pillar including a surface layer 314 and an inner layer 315 may be formed in the first channel hole CHa included in the memory block BLKa, and A charge storage layer CS may be formed around it, and the charge storage layer CS may have an ONO structure.

Referring to FIG. 22B , a pillar including a surface layer 314 and an inner layer 315 may be formed in the second channel hole CHb included in the memory block BLKb. A charge storage layer CS may be formed around it, and the charge storage layer CS may have an ONO structure.

In an embodiment, the thickness of the charge storage layer CS included in the memory block BLKb may be different from the thickness of the charge storage layer CS included in the memory block BLKa. Due to the difference in the channel hole diameter, a difference in characteristics of the memory cell may occur. Specifically, in the case of a gate all-around type vertical memory device in which a gate electrode is positioned around a channel hole, the concentration of an electric field formed from the gate electrode to the channel region 314 decreases as the channel hole diameter decreases. will rise Accordingly, a memory cell having a small channel hole diameter D1, such as the first channel hole CHa, has higher program and erase operations than a memory cell having a large channel hole diameter D2, such as the second channel hole CHb. speed will increase

Referring back to FIG. 21 , one memory block in the cell region CR includes all memory cells corresponding to one page in the first horizontal direction VD1 , that is, in the word line direction, and includes all memory cells corresponding to one page in the second horizontal direction VD1 . (VD2), that is, in the bit line direction, it is configured to include several strings. Accordingly, since each memory block is configured to be long in the first horizontal direction, a difference in channel hole size, that is, a diameter may appear in units of memory blocks. Accordingly, the program speed and erase speed of memory cells included in the memory block BLKa may be higher than the program speed and erase speed of memory cells included in the memory block BLKb.

FIG. 23 shows a vertical structure of one channel hole of FIG. 21 .

Referring to FIG. 23 , a channel hole CH1 corresponding to one NAND string included in a NAND flash memory device is illustrated. Since the channel hole CH1 is formed by etching some regions of the gate electrodes and insulating films stacked on the substrate, etching may not be performed well as the depth from the surface increases. Accordingly, the diameter of the channel hole CH1 may decrease toward the substrate.

In one embodiment, the channel hole CH1 may be divided into three zones according to the channel hole diameter. For example, a region having a channel hole diameter smaller than the first value is determined as the first region Z1, and a region having a channel hole diameter greater than or equal to the first value and smaller than the second value is determined as the second region Z2. and a region having a channel hole diameter greater than or equal to the second value and smaller than the third value may be determined as the third region Z3. Therefore, even in one NAND string, a difference in characteristics of a memory cell may occur due to a difference in channel hole diameter according to a position of a word line in a vertical direction (VD).

In addition, the word line WLb is disposed in the first zone Z1 , the word line WLa is disposed in the second zone Z2 , and the word line WLc is disposed in the third zone Z3 . Since the word line WLb is adjacent to the lower edge of the channel hole CH1, the word line WLb is placed adjacent to the ground selection line or the substrate, so that the probability of a bridge occurring between the word line WLb and the channel increases. , If a bridge occurs between the word line WLb and the channel, leakage current is generated through the bridge, and defects in program/read operations and erase operations may occur according to the leakage current. In addition, since the word line WLc is adjacent to the upper edge of the channel hole CH1, the word line WLc is disposed adjacent to the string selection line, so that a bridge is more likely to occur in the word line WLc.

Therefore, the error of pages connected to the word line WLc disposed adjacent to the upper edge of the channel hole CH1 and connected to the word line WLb disposed adjacent to the lower edge of the channel hole CH1 The occurrence probability may be higher than the error occurrence probability of pages connected to the word line WLa disposed in the center of the channel hole CH1.

20 to 23 are diagrams for explaining that an error attribute of a target page varies according to a location of a target word line and an error occurrence probability of a target page varies based on the error attribute according to embodiments of the present invention.

The processor 310 of the storage controller 300 according to example embodiments may apply an individual location index to each of the NAND strings. In another embodiment, the processor 310 may apply the same location index to at least two NAND strings sharing the same channel hole among the NAND strings. In another embodiment, the processor 310 may apply an individual location index to each of a plurality of memory blocks. In an embodiment, the processor 310 may apply the location index to at least one word line having a large difference in error occurrence probability between inner cells and outer cells among a plurality of word lines.

24 illustrates a write operation of the storage device of FIG. 4 according to example embodiments.

Referring to FIG. 24 , in a write operation to the target page PAG_T of the nonvolatile memory device 400a, the ECC encoder 520 of the storage controller 300 uses the user data DTA including the outer cell bits OCB. ) to generate parity bits (PRT), and perform second ECC encoding on the outer ECC sector including the outer cell bits (OCB) to generate the outer parity bits (OPRT). generate The storage device 300 transmits user data DTA, parity bits PRT, and outer parity bits OPRT to the nonvolatile memory device 400a through the memory interface 370, and the nonvolatile memory device ( 400a) writes the user data DTA, the parity bits PRT, and the outer parity bits OPRT to the target page PAG_T.

25 illustrates a read operation of the storage device of FIG. 4 according to example embodiments.

Referring to FIG. 25 , in a read operation of the target page PAG_T of the nonvolatile memory device 400a, the storage controller 300 retrieves the user data DTA read from the target page PAG_T through the memory interface 370. , parity bits (PRT) and outer parity bits (OPRT) are provided to the ECC decoder 550. The ECC decoder 550 performs first ECC decoding on the user data DTA including the outer cell bits OCB to generate parity bits PRT. If an uncorrectable error is included in the user data DTA as a result of the first ECC decoding, the ECC decoder 550 generates an outer ECC sector including the outer cell bits OCB based on the outer parity bits OPRT. An error that cannot be corrected in the first ECC decoding may be corrected by performing second ECC decoding on the first ECC decoding.

26 is a flowchart illustrating a method of operating a storage device according to example embodiments.

3 to 26, a plurality of word lines stacked on a top surface of a substrate, a plurality of memory cells formed in channel holes extending in a direction perpendicular to the substrate, and a plurality of memory cells extending in a first horizontal direction and extending the word lines A non-volatile memory device (400a) including a memory cell array having word line cut regions divided into a plurality of memory blocks and a method of operating the storage device (300) for controlling the non-volatile memory device (400a) are provided. do.

According to the above method, the ECC encoder 520 included in the storage controller 300 performs a write operation on memory cells of a target page connected to a target word line among the plurality of word lines, and the plurality of user data DTA are included. A plurality of ECC sectors are formed by performing first ECC encoding on each of the sub data units of , generating parity bits for each of the sub data units (S110).

Selecting outer cell bits to be stored in the outer cells in the ECC sectors based on a location index (LIDX) for classifying the memory cells into outer cells and inner cells based on a relative distance from the word line cut region, An outer ECC sector including outer cell bits is configured (S120). That is, the ECC encoder 520 constructs an outer ECC sector based on the outer cell bits.

The ECC encoder 520 generates outer parity bits (OPRT) by performing second ECC encoding on the outer ECC sector (S130).

The memory interface 370 transmits a codeword set (SCW) including the ECC sectors and the outer parity bits to the nonvolatile memory device 400a (S140).

The storage controller 300 receives a codeword set (SCW) including the ECC sectors and the outer parity bits from the nonvolatile memory device 400a in a read operation on the nonvolatile memory device 400a (S150). .

The data selector 580 configures the outer ECC sector from the ECC sectors based on the location index (LIDX) (S160).

The ECC decoder 550 performs first ECC decoding on each of the ECC sectors (S170).

The ECC decoder 550 selectively performs second ECC decoding on the outer ECC sector based on the outer parity bits based on the result of the first ECC decoding (S180), and in at least one of the ECC sectors When an uncorrectable error is detected, the uncorrectable error may be corrected by the first ECC decoding.

27 is a block diagram illustrating another example of the configuration of an ECC engine in the storage controller of FIG. 4 according to embodiments of the present invention.

Referring to FIG. 27, the ECC engine 500c may include an ECC memory 510 storing ECC 515, an ECC encoder 520c, an ECC decoder 550c, a data selector 580c, and a buffer 590c. can

The ECC encoder 520c is connected to the ECC memory 510 and performs first ECC encoding on data bits of user data for each sub data unit (SDUI) in a write operation on a target page using the ECC 515 to generate the corresponding parity bits PRTi, and provide the ECC sector ECCSi including the sub data unit SDUI and the corresponding parity bits PRTi to the data selector 580c and the buffer 590c. can In addition, the ECC encoder 520c may perform ECC encoding on all of the sub data units SDUI to generate corresponding parity bits PRT_t and provide the parity bits PRT_t to the buffer 590c. there is.

The data selector 580c selects at least some of the inner cell bits in each of the sub data units SDUI in the second error correction mode based on the error correction mode signal EMS and the location index LIDX, and selects at least some of the selected inner cell bits. An inner ECC sector (IECCS) may be configured with cell bits of , and the inner ECC sector (IECCS) may be provided to the ECC encoder 520c.

The ECC encoder 520c generates inner parity bits (IPRT) by performing second ECC encoding on the inner ECC sector (IECCS) using the ECC 515, and stores the inner parity bits (IPRT) in a buffer ( 590c).

The buffer 590c transmits a codeword set (SCW) including ECC sectors (ECCSi) including parity bits (PRTi) corresponding to the sub data unit (SDUI) and inter parity bits (IPRT) to the memory interface ( It can be provided to the non-volatile memory device 400a through 370).

In a read operation of the target page, the buffer 590c includes ECC sectors ECCSi including the sub data unit SDUI and corresponding parity bits PRTi and a codeword including inter parity bits IPRT. The set (SCW) is received from the non-volatile memory device 400a through the memory interface 370, the ECC sectors (ECCSi) and inner parity bits (IPRT) are provided to the ECC decoder 550c, and the ECC sector ( ECCSi) to the data selector 580c.

The data selector 580c selects inner cell bits from each of the sub data units SDUI in the second error correction mode based on the error correction mode signal EMS and the location index LIDX to form the inner ECC sector IECCS. and provide the inner ECC sector (IECCS) to the ECC encoder 520a.

The ECC decoder 550c is connected to the ECC memory 510, receives the inner ECC sector (IECCS) from the data selector 580c, uses the ECC 515 and inner parity bits (IPRT) based on the inner ECC. First ECC decoding is performed on the sector IECCS, correctable errors of the inner ECC sector IECCS are corrected, and each of the ECC sectors ECCSi is corrected based on the inner ECC sector IECCS in which the error is loaded. A second ECC decoding may be performed to correct correctable errors included in each of the ECC sectors (ECCSi). The first ECC decoding is first performed on the inner ECC sector (IECCS) having a relatively low error occurrence probability to correct correctable errors, and the second ECC is applied to each of the ECC sectors (ECCSi) to which the result of the first ECC decoding is reflected. By performing decoding, error correction capability can be improved.

As a result of performing the second ECC encoding, when an uncorrectable error is detected in at least one of the ECC sectors (ECCSi), the ECC decoder 550c indicates that an uncorrectable error is detected in at least one of the ECC sectors (ECCSi). An error flag (ERR1) may be provided to the buffer 590a.

The buffer 590a may provide parity bits PRT_t related to all of the sub data units SDUI to the ECC decoder 550c in response to the error flag ERR1.

The ECC decoder 550c may correct uncorrectable errors in some of the sub-data units (SDUI) by performing third ECC decoding on all of the sub-data units (SDUI) based on the parity bits (PRT_t). .

28 illustrates the operation of an ECC encoder in the ECC engine of FIG. 27 according to embodiments of the present invention.

In FIG. 28, it is assumed that the user data DTA of FIG. 27 includes first to fourth sub data units SDU1, SDU2, SDU3, and SDU4. Also, each of the first to fourth sub data units SDU1 , SDU2 , SDU3 , and SDU4 may include outer cell bits OCB and inner cell bits ICB.

27 and 28, the ECC encoder 520c performs first ECC encoding on the first sub data unit SDU1 using the ECC 515 to generate first parity bits PRT1, A first ECC sector ECCS1 including the first sub data unit SDU1 and the first parity bits PRT1 is formed.

The ECC encoder 520c performs first ECC encoding on the second sub data unit SDU2 using the ECC 515 to generate second parity bits PRT2, and generates second parity bits PRT2 and A second ECC sector ECCS2 including the second parity bits PRT2 is configured.

The ECC encoder 520c performs first ECC encoding on the third sub data unit SDU3 using the ECC 515 to generate third parity bits PRT3, and generates third sub data unit SDU3 and A third ECC sector ECCS3 including the third parity bits PRT3 is configured.

The ECC encoder 520c performs first ECC encoding on the fourth sub data unit SDU4 using the ECC 515 to generate fourth parity bits PRT4, and the fourth sub data unit SDU4 and A fourth ECC sector ECCS4 including the fourth parity bits PRT4 is configured.

The ECC encoder 52ca may sequentially or in parallel perform first ECC encoding on the first to fourth sub data units SDU1 , SDU2 , SDU3 , and SDU4 .

The ECC encoder 520c configures an inter-cell ECC sector (IECCS) with the inner cell bits (ICB) of each of the first to fourth sub-data units (SDU1, SDU2, SDU3, and SDU4), and constructs an inter-cell ECC sector ( IECCS) may be subjected to second ECC encoding to generate inner cell parity bits (IPRT).

The first to th parity bits PRT1 , PRT2 , PRT3 , and PRT4 may include inner cell bits and outer cell bits, respectively.

29 illustrates the operation of an ECC encoder in the ECC engine of FIG. 27 according to embodiments of the present invention.

In FIG. 29, a description overlapping with that of FIG. 28 is omitted.

Referring to FIGS. 27 and 29 , the ECC encoder 520c generates inner cell bits ICB related to the first location index LIUDX1 of each of the first to fourth sub data units SDU1, SDU2, SDU3, and SDU4. ) to form the first inner ECC sector IECCS1, and second ECC encoding is performed on the first inner ECC sector IECCS1 to generate first inner cell parity bits IPRT1.

The ECC encoder 520c converts the second inner ECC sector IECCS2 into inner cell bits ICB related to the second location index LIUDX2 of each of the first to fourth sub data units SDU1, SDU2, SDU3, and SDU4. ), and second inner cell parity bits IPRT2 may be generated by performing second ECC encoding on the second inner ECC sector IECCS2.

30 illustrates the operation of an ECC encoder in the ECC engine of FIG. 27 according to embodiments of the present invention.

In FIG. 30, a description overlapping with that of FIG. 28 is omitted.

27 and 30, the ECC encoder 520c converts all inner cell bits ICB of the first to fourth sub data units SDU1, SDU2, SDU3, and SDU4. An inner ECC sector (IECCS_t) is formed, and ECC encoding is performed on all inner ECC sectors (IECCS_t) to generate all inner cell parity bits (IPRT_t).

31 illustrates that the ECC encoder of FIG. 27 sequentially performs first ECC encoding on a plurality of sub data units.

Referring to FIG. 31, the ECC encoder 520c performs first ECC encoding on each of the first to fourth sub data units SDU1, SDU2, SDU3, and SDU4 including inner cell bits ICB. Thus, the first parity bits PRT1 , the second parity bits PRT2 , the third parity bits PRT3 , and the fourth parity bits PRT4 may be sequentially generated. In addition, the ECC encoder 520c configures an inner ECC sector OECCS with the inner cell bits ICB of each of the first to fourth sub data units SDU1, SDU2, SDU3, and SDU4, and constructs an inner ECC sector OECCS. ), inner cell parity bits (IPRT) may be generated by performing second ECC encoding.

32 illustrates that the ECC encoder of FIG. 27 performs first ECC encoding on a plurality of sub data units and second ECC encoding on an inner ECC sector in parallel.

Referring to FIG. 32 , an ECC encoder 520ca may include first to fifth sub ECC encoders 521 , 523 , 525 , 527 , and 529 .

The first to fifth sub ECC encoders 521, 523, 525, 527, and 529 are connected to the ECC 515 of FIG. 27, respectively, and the first to fourth sub ECC encoders 521, 523, 525, and 527 ) Parallelly performs first ECC encoding on each of the first to fourth sub data units SDU1, SDU2, SDU3, and SDU4 each including inner cell bits ICB to obtain first parity bits. PRT1 , second parity bits PRT2 , third parity bits PRT3 , and fourth parity bits PRT4 may be generated in parallel. In addition, the fifth sub-ECC encoder 529 generates the second to fourth sub-data units SDU1, SDU2, SDU3, and SDU4 for the inner ECC sector IECCS composed of the inner cell bits ICB. ECC encoding may be performed in parallel with the first ECC encoding to generate inner cell parity bits (IPRT).

33 illustrates that the ECC encoder of FIG. 27 sequentially performs first ECC encoding on a plurality of sub data units.

Referring to FIG. 33, the ECC encoder 520c performs first ECC encoding on each of the first to fourth sub data units SDU1, SDU2, SDU3, and SDU4 to obtain first parity bits PRT1, 2 parity bits PRT2 , third parity bits PRT3 , and fourth parity bits PRT4 may be sequentially generated. The first sub data unit SDU1 may include at least inner cell bits ICB11 and ICB12, and the second sub data unit SDU2 may include at least inner cell bits ICB21 and ICB22. The third sub data unit SDU3 may include at least inner cell bits ICB31 and ICB32, and the fourth sub data unit SDU4 may include at least inner cell bits ICB21 and ICB22.

In addition, the ECC encoder 520c configures the first inner ECC sector IECCS1 with the inner cell bits ICB11, ICB21, ICB31, and ICB41 of the first to fourth sub data units SDU1, SDU2, SDU3, and SDU4. And, second ECC encoding may be performed on the first inner ECC sector IECCS1 to generate first inner cell parity bits IPRT1. Also, the ECC encoder 520c configures the second inner ECC sector IECCS2 with the inner cell bits ICB12, ICB22, ICB32, and ICB42 of the first to fourth sub data units SDU1, SDU2, SDU3, and SDU4. and second inner cell parity bits IPRT2 may be generated by performing second ECC encoding on the second inner ECC sector IECCS2.

The ECC encoder 520c may perform the second ECC encoding at least twice.

34 illustrates that the ECC encoder of FIG. 27 performs first ECC encoding on a plurality of sub data units and second ECC encoding on inner ECC sectors in parallel.

Referring to FIG. 34 , an ECC encoder 520cb may include first to sixth sub ECC encoders 521 , 523 , 525 , 527 , 529 , and 529a.

The first to sixth sub ECC encoders 521, 523, 525, 527, 529, and 529a are respectively connected to the ECC 515 of FIG. 27, and the first to fourth sub ECC encoders 521, 523, 525, 527) First ECC encoding is performed in parallel on each of the first to fourth sub data units (SDU1, SDU2, SDU3, and SDU4), each of which includes inner cell bits (ICB), to obtain a first parity bit PRT1 , second parity bits PRT2 , third parity bits PRT3 , and fourth parity bits PRT4 may be generated in parallel.

In addition, the fifth sub-ECC encoder 529 generates the first inner ECC sector IECCS1 composed of the first inner cell bits of the first to fourth sub data units SDU1, SDU2, SDU3, and SDU4. The first inner cell parity bits IPRT1 may be generated by performing 2 ECC encoding in parallel with the first ECC encoding. In addition, the sixth sub ECC encoder 529a transmits the second inner ECC sector IECCS2 composed of the second inner cell bits of the first to fourth sub data units SDU1, SDU2, SDU3, and SDU4. Second inner cell parity bits IPRT2 may be generated by performing 2 ECC encoding in parallel with the first ECC encoding.

35 illustrates an operation of the ECC decoder of FIG. 27 according to embodiments of the present invention.

27 and 35 , the ECC decoder 550c uses the first to fourth sub data units (read from the target page of the nonvolatile memory device 400a) based on the inner cell parity bits (IPRT). First ECC decoding is performed on the inner ECC sectors of SDU1', SDU2', SDU3', and SDU4', so that each inner ECC sector of the first to fourth sub-data units SDU1', SDU2', SDU3', and SDU4' Correctable errors of cell data bits may be corrected and the first to fourth sub data units SDU1'', SDU2'', SDU3'', and SDU4'' may be output.

The first sub data unit SDU1' may include inner cell bits ICB11' and ICB12' corresponding to errors, and the second sub data unit SDU2' may include inner cell bits corresponding to errors ( ICB21' and ICB22', the third sub data unit SDU3' may include inner cell bits corresponding to errors ICB31' and ICB32', and the fourth sub data unit SDU4 ') may include inner cell bits ICB41' and ICB42' corresponding to errors.

As a result of the first ECC decoding, the first sub data unit SDU1″ includes the corrected inner cell bit ICB11 and the uncorrected inner cell bit ICB12′, and the second sub data unit SDU2′ ') includes the corrected inner cell bit ICB21 and the uncorrected inner cell bit ICB22', and the third sub data unit SDU3'' includes the corrected inner cell bit ICB31 and the uncorrected inner cell bit. The cell bit ICB32' may be included, and the fourth sub data unit SDU4'' may include a corrected inner cell bit ICB41 and an uncorrected inner cell bit ICB42'.

The ECC decoder 550c uses the first to fourth parity bits PRT1 , PRT2 , PRT3 , and PRT3 for each of the first to fourth sub data units SDU1 ″, SDU2 ″, SDU3 ″, and SDU4 ″. PRT4), correctable errors of each of the first to fourth sub data units SDU1'', SDU2'', SDU3'', and SDU4'' are corrected by performing second ECC decoding based on each of the first to fourth sub-data units. The fourth sub data units SDU1 , SDU2 , SDU3 , and SDU4 may be output.

36 shows that the ECC decoder of FIG. 27 performs a third ECC decoding.

Referring to FIGS. 27 and 36, as a result of performing the second ECC decoding, when the third sub data unit SDU3''' includes an uncorrectable error ICB31'', the ECC decoder 550c buffers the buffer. An error flag (ERR1) indicating that an uncorrectable error (ICB31″) has occurred is applied to 590c, and the buffer 590c applies all of the first to fourth sub data units SDU1, SDU2, SDU3, and SDU4. All parity bits (PRT_t) obtained by performing ECC encoding on may be provided to the ECC decoder 550c.

The ECC decoder 550c performs third ECC decoding on all of the first to fourth sub data units SDU1, SDU2, SDU3''', and SDU4 based on all parity bits PRT_t, resulting in an uncorrectable error. (ICB31″) may be corrected, and the first to fourth sub data units SDU1, SDU2, SDU3, and SDU4 may be output.

37 is a flowchart illustrating a method of operating a storage device according to example embodiments.

Referring to FIGS. 3 and 27 to 36 , a plurality of word lines stacked on an upper surface of a substrate, a plurality of memory cells formed in channel holes extending in a direction perpendicular to the substrate, and a plurality of memory cells extending in a first horizontal direction, Operation of a non-volatile memory device 400a including a memory cell array having word line cut regions dividing word lines into a plurality of memory blocks and a storage device 300 controlling the non-volatile memory device 400 a A method is provided.

According to the method, the ECC encoder 520c included in the storage controller 300 performs a write operation on memory cells of a target page connected to a target word line among the plurality of word lines, and includes a plurality of data included in the user data DTA. A plurality of ECC sectors are configured by performing first ECC encoding on each of the sub data units of , generating parity bits for each of the sub data units (S210).

Inner cell bits to be stored in the inner cells are selected from the ECC sectors based on a location index (LIDX) for classifying the memory cells into outer cells and inner cells based on a relative distance from the word line cut region, An inner ECC sector including some of the inner cell bits is configured (S220).

The ECC encoder 520c generates inner parity bits (OPRT) by performing second ECC encoding on the inner ECC sector (S230).

The memory interface 370 transmits a codeword set (SCW) including the ECC sectors and the inner parity bits to the nonvolatile memory device 400a (S440).

The storage controller 300 receives a codeword set (SCW) including the ECC sectors and the inner parity bits from the nonvolatile memory device 400a in a read operation on the nonvolatile memory device 400a (S250). .

The data selector 580c constructs the inner ECC sector from the ECC sectors based on the location index (LIDX) (S260).

The ECC decoder 550c performs a first ECC decoding on the inner ECC sector based on the inner parity bits (S270) to correct correctable errors of the inner ECC sector.

The ECC decoder 550c performs second ECC decoding on each of the ECC sectors to which the result of the first encoding is reflected (S280), and corrects each correctable error in the ECC sectors.

Accordingly, in the storage device and method of operating the storage device according to embodiments of the present invention, memory cells of a target page are divided into outer cells and inner cells based on a relative distance from a word line cut region based on a location index, and In 1 error correction mode, first ECC encoding and first ECC decoding are performed on each of a plurality of sub data units included in user data, and outer cell bits to be stored (read) in outer cells having a high error occurrence probability An outer ECC sector including an outer ECC sector is configured, and second ECC encoding and second ECC decoding are performed on the outer ECC sector to correct an error that cannot be corrected by the first ECC decoding by the second ECC decoding.

In addition, in the second error correction mode, an inner ECC sector including inner cell bits to be stored in inner cells with a low error occurrence probability is configured, second ECC encoding is performed on the inner ECC sector, and in a read operation, the inner ECC sector First ECC decoding may be performed on , and errors of the sub data units may be corrected by performing second ECC decoding on each of the sub data units with reference to a result of the first ECC decoding. Accordingly, the error correction capability of the ECC engine can be improved. In addition, since the same ECC is used for the first ECC encoding and the second ECC encoding, and the same ECC is used for the first ECC decoding and the second ECC decoding, an area occupied by the ECC engine may not increase.

38 is a cross-sectional view illustrating a nonvolatile memory device according to example embodiments.

Referring to FIG. 38 , the nonvolatile memory device 2000 may have a chip to chip (C2C) structure. The C2C structure fabricates an upper chip (first chip) including a cell region (CELL) on a first wafer, and a lower chip (first chip) including a peripheral circuit region (PERI) on a second wafer different from the first wafer. 2), and then connecting the upper chip and the lower chip by a bonding method. For example, the bonding method may refer to a method of electrically connecting the bonding metal formed on the uppermost metal layer of the upper chip and the bonding metal formed on the uppermost metal layer of the lower chip to each other. For example, when the bonding metal is formed of copper (Cu), the bonding method may be a Cu-to-Cu bonding method, and the bonding metal may also be formed of aluminum (Al) or tungsten (W).

Each of the peripheral circuit area PERI and the cell area CELL of the nonvolatile memory device 2000 may include an external pad bonding area PA, a word line bonding area WLBA, and a bit line bonding area BLBA. there is.

The peripheral circuit region PERI includes a first substrate 2210, an interlayer insulating layer 2215, a plurality of circuit elements 2220a, 2220b, and 2220c formed on the first substrate 2210, and a plurality of circuit elements 2220a. , 2220b, 2220c) to include first metal layers 2230a, 2230b, and 2230c connected to each other, and second metal layers 2240a, 2240b, and 2240c formed on the first metal layers 2230a, 2230b, and 2230c. can In an embodiment, the first metal layers 2230a, 2230b, and 2230c may be formed of tungsten having a relatively high electrical resistivity, and the second metal layers 2240a, 2240b, and 2240c may be made of copper having a relatively low electrical resistivity. can be formed

In this specification, only the first metal layers 2230a, 2230b, and 2230c and the second metal layers 2240a, 2240b, and 2240c are shown and described, but are not limited thereto, and the second metal layers 2240a, 2240b, and 2240c At least one or more metal layers may be further formed. At least some of the one or more metal layers formed on the second metal layers 2240a, 2240b, and 2240c are made of aluminum having a lower electrical resistivity than copper forming the second metal layers 2240a, 2240b, and 2240c. can be formed

The interlayer insulating layer 2215 covers the plurality of circuit elements 2220a, 2220b, and 2220c, the first metal layers 2230a, 2230b, and 2230c, and the second metal layers 2240a, 2240b, and 2240c on the first substrate. 2210, and may include an insulating material such as silicon oxide, silicon nitride, or the like.

Lower bonding metals 2271b and 2272b may be formed on the second metal layer 2240b of the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 2271b and 2272b of the peripheral circuit area PERI may be electrically connected to the upper bonding metals 2371b and 2372b of the cell area CELL by a bonding method. , The lower bonding metals 2271b and 2272b and the upper bonding metals 2371b and 2372b may be formed of aluminum, copper, or tungsten.

The cell area CELL may provide at least one memory block. The at least one memory block may include a first area and a second area, and the first area may store the above-described compensation data set and may be an SLC block. The cell region CELL may include a second substrate 2310 and a common source line 2320 . On the second substrate 2310, a plurality of word lines 2331, 2332, 2333, 2334, 2335, 2336, 2337, 2338, and 2330 are provided along the third direction VD perpendicular to the upper surface of the second substrate 2310. ) can be stacked. String select lines and a ground select line may be disposed on upper and lower portions of the word lines 2330 , and a plurality of word lines 2330 may be disposed between the string select lines and the ground select line.

In the bit line bonding area BLBA, the channel structure CH extends in a direction VD perpendicular to the upper surface of the second substrate 2310 to form word lines 2330, string select lines, and ground select lines. can penetrate The channel structure CH may include a data storage layer, a channel layer, and a buried insulating layer, and the channel layer may be electrically connected to the first metal layer 2350c and the second metal layer 2360c. For example, the first metal layer 2350c may be a bit line contact, and the second metal layer 2360c may be a bit line. In one embodiment, the bit line 2360c may extend along the second horizontal direction HD2 parallel to the upper surface of the second substrate 2310 .

In the example of FIG. 38 , an area where the channel structure CH and the bit line 2360c are disposed may be defined as a bit line bonding area BLBA. The bit line 2360c may be electrically connected to the circuit elements 2220c providing the page buffer 2393 in the peripheral circuit area PERI in the bit line bonding area BLBA. For example, the bit line 2360c is connected to upper bonding metals 2371c and 2372c in the peripheral circuit area PERI, and the upper bonding metals 2371c and 2372c are connected to circuit elements 2220c of the page buffer 2393. It may be connected to the connected lower bonding metals 2271c and 2272c.

In the word line bonding area WLBA, the word lines 2330 may extend along a second horizontal direction HD2 perpendicular to the first horizontal direction HD1 and parallel to the upper surface of the second substrate 310. , may be connected to a plurality of cell contact plugs 2341, 2342, 2343, 2344, 2345, 2346, 3347; 3340. The word lines 2330 and the cell contact plugs 2340 may be connected to each other at pads provided by extending different lengths from at least some of the word lines 2330 along the first horizontal direction HD1. . A first metal layer 2350b and a second metal layer 2360b may be sequentially connected to upper portions of the cell contact plugs 2340 connected to the word lines 2330 . The cell contact plugs 2340 are connected to peripheral circuits in the word line bonding area WLBA through the upper bonding metals 2371b and 2372b of the cell area CELL and the lower bonding metals 2271b and 2272b of the peripheral circuit area PERI. It may be connected to the area PERI.

The cell contact plugs 2340 may be electrically connected to circuit elements 2220b forming the address decoder or row decoder 2394 in the peripheral circuit area PERI. In one embodiment, the operating voltage of the circuit elements 2220b forming the row decoder 2394 may be different from the operating voltage of the circuit elements 2220c forming the page buffer 2393. For example, the operating voltage of the circuit elements 2220c forming the page buffer 2393 may be higher than the operating voltage of the circuit elements 2220b forming the row decoder 2394 .

A common source line contact plug 2380 may be disposed in the external pad bonding area PA. The common source line contact plug 2380 is formed of a conductive material such as metal, metal compound, or polysilicon, and may be electrically connected to the common source line 2320 . A first metal layer 2350a and a second metal layer 2360a may be sequentially stacked on the common source line contact plug 2380 . For example, an area where the common source line contact plug 2380, the first metal layer 2350a, and the second metal layer 2360a are disposed may be defined as an external pad bonding area PA.

Meanwhile, input/output pads 2205 and 2305 may be disposed in the external pad bonding area PA. A lower insulating film 2201 covering a lower surface of the first substrate 2210 may be formed under the first substrate 2210, and a first input/output pad 2205 may be formed on the lower insulating film 2201. The first input/output pad 2205 is connected to at least one of the plurality of circuit elements 2220a, 2220b, and 2220c arranged in the peripheral circuit area PERI through the first input/output contact plug 2203, and the lower insulating layer 2201 ) may be separated from the first substrate 2210. In addition, a side insulating layer may be disposed between the first input/output contact plug 2203 and the first substrate 2210 to electrically separate the first input/output contact plug 2203 from the first substrate 2210 .

An upper insulating layer 2301 covering the upper surface of the second substrate 2310 may be formed on the second substrate 2310, and second input/output pads 2305 may be disposed on the upper insulating layer 2301. The second input/output pad 2305 may be connected to at least one of the plurality of circuit elements 2220a, 2220b, and 2220c disposed in the peripheral circuit area PERI through the second input/output contact plug 2303. In one embodiment, the second input/output pad 2305 may be electrically connected to the circuit element 2220a.

Depending on the embodiment, the second substrate 2310 and the common source line 2320 may not be disposed in the region where the second input/output contact plug 2303 is disposed. Also, the second input/output pad 2305 may not overlap the word lines 2380 in the third direction D3. The second input/output contact plug 2303 is separated from the second substrate 2310 in a direction parallel to the top surface of the second substrate 2310, and penetrates the interlayer insulating layer 2315 of the cell region CELL to form the second input/output contact plug. It can be connected to pad 2305.

According to embodiments, the first input/output pad 2205 and the second input/output pad 2305 may be selectively formed. For example, the non-volatile memory device 2000 includes only the first input/output pad 2205 disposed on the first substrate 2201, or the second input/output pad 2205 disposed on the second substrate 2301 ( 2305) may be included. Alternatively, the memory device 2000 may include both the first input/output pad 2205 and the second input/output pad 2305 .

In each of the external pad bonding area PA and the bit line bonding area BLBA included in the cell area CELL and the peripheral circuit area PERI, the metal pattern of the uppermost metal layer exists in a dummy pattern, or The top metal layer may be empty.

In the nonvolatile memory device 2000, in the external pad bonding area PA, the cell area is formed on the uppermost metal layer of the peripheral circuit area PERI corresponding to the upper metal pattern 2372a formed on the uppermost metal layer of the cell area CELL. A lower metal pattern 2273a having the same shape as the upper metal pattern 2372a of the cell may be formed. The lower metal pattern 2273a formed on the uppermost metal layer of the peripheral circuit area PERI may not be connected to a separate contact in the peripheral circuit area PERI. Similarly, in the external pad bonding area PA, the upper metal layer of the cell area CELL corresponds to the lower metal pattern 2273a formed on the uppermost metal layer of the peripheral circuit area PERI. An upper metal pattern 2372a having the same shape as the lower metal pattern 2273a may be formed.

Lower bonding metals 2271b and 2272b may be formed on the second metal layer 2240b of the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 2271b and 2272b of the peripheral circuit area PERI may be electrically connected to the upper bonding metals 2371b and 2372b of the cell area CELL by a bonding method. .

In addition, in the bit line bonding area BLBA, the uppermost metal layer of the cell area CELL corresponds to the lower metal pattern 2252 formed on the uppermost metal layer of the peripheral circuit area PERI. An upper metal pattern 2392 having the same shape as the metal pattern 2252 may be formed. A contact may not be formed on the upper metal pattern 2392 formed on the uppermost metal layer of the cell region CELL.

The aforementioned word line voltages are applied to at least one memory block of the cell area CELL through the lower bonding metals 2271b and 2272b of the peripheral circuit area PERI and the upper bonding metals 2371b and 2372b of the cell area CELL. can be provided.

39 is a block diagram illustrating an electronic system including a semiconductor device according to example embodiments.

Referring to FIG. 39 , the electronic system 3000 may include a semiconductor device 3100 and a controller 3200 electrically connected to the semiconductor device 3100 . The electronic system 3000 may be a storage device including one or a plurality of semiconductor devices 3100 or an electronic device including the storage device. For example, the electronic system 3000 may be a solid state drive (SSD) device including one or a plurality of semiconductor devices 3100, a universal serial bus (USB), a computing system, a medical device, or a communication device. may be a device.

The semiconductor device 3100 may be a non-volatile memory device, for example, the non-volatile memory device described above with reference to FIGS. 11 to 23 . The semiconductor device 3100 may include a first structure 3100F and a second structure 3100S on the first structure 3100F. The first structure 3100F may be a peripheral circuit structure including a decoder circuit 3110 , a page buffer circuit 3120 , and a logic circuit 3130 . The second structure 3100S includes a bit line BL, a common source line CSL, word lines WL, first and second gate upper lines UL1 and UL2, and first and second gate lower lines. LL1 and LL2, and memory NAND strings CSTR between the bit line BL and the common source line CSL.

In the second structure 3100S, each of the memory NAND strings CSTR includes lower transistors LT1 and LT2 adjacent to the common source line CSL and upper transistors UT1 adjacent to the bit line BL. UT2), and a plurality of memory cell transistors MCT disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of lower transistors LT1 and LT2 and the number of upper transistors UT1 and UT2 may be variously modified according to embodiments.

In example embodiments, the upper transistors UT1 and UT2 may include string select transistors, and the lower transistors LT1 and LT2 may include ground select transistors. The lower gate lines LL1 and LL2 may be gate electrodes of the lower transistors LT1 and LT2, respectively. The word lines WL may be gate electrodes of the memory cell transistors MCT, and the upper gate lines UL1 and UL2 may be gate electrodes of the upper transistors UT1 and UT2, respectively.

In example embodiments, the lower transistors LT1 and LT2 may include a lower erase control transistor LT1 and a ground select transistor LT2 connected in series. The upper transistors UT1 and UT2 may include a string select transistor UT1 and an upper erase control transistor UT2 connected in series. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT1 performs an erase operation of erasing data stored in the memory cell transistors MCT using a gate induce drain leakage (GIDL) phenomenon. can be used for

The common source line CSL, the first and second lower gate lines LL1 and LL2, the word lines WL, and the first and second upper gate lines UL1 and UL2 have a first structure ( 3100F) may be electrically connected to the decoder circuit 3110 through first connection wires 3115 extending to the second structure 1100S. The bit lines BL may be electrically connected to the page buffer circuit 3120 through second connection lines 3125 extending from the first structure 3100F to the second structure 3100S.

In the first structure 3100F, the decoder circuit 1110 and the page buffer circuit 3120 may execute a control operation on at least one selected memory cell transistor among the plurality of memory cell transistors MCT. The decoder circuit 3110 and the page buffer circuit 3120 may be controlled by the logic circuit 3130 . The semiconductor device 3000 may communicate with the controller 3200 through the input/output pad 3101 electrically connected to the logic circuit 3130 . The input/output pad 3101 may be electrically connected to the logic circuit 3130 through an input/output connection wire 3135 extending from the first structure 3100F to the second structure 3100S.

The controller 3200 may include a processor 3210 , a NAND controller 3220 , and a host interface 1230 . According to example embodiments, the electronic system 3000 may include a plurality of semiconductor devices 3100 , and in this case, the controller 3200 may control the plurality of semiconductor devices 3000 .

The processor 3210 may control the overall operation of the electronic system 3000 including the controller 3200 . The processor 3210 may operate according to predetermined firmware and access the semiconductor device 3100 by controlling the NAND controller 3220 . The NAND controller 3220 may include a NAND interface 3221 that processes communication with the semiconductor device 3100 . Through the NAND interface 3221, a command for controlling the semiconductor device 3100, data to be written to the memory cell transistors MCT of the semiconductor device 1100, and memory cell transistors MCT of the semiconductor device 3100 ), data to be read from can be transmitted. The host interface 3230 may provide a communication function between the electronic system 1000 and an external host. When a control command is received from an external host through the host interface 3230, the processor 1210 may control the semiconductor device 1100 in response to the control command.

The present invention can be usefully applied to any electronic device having a storage device. For example, the present invention relates to a mobile phone having a storage device, a smart phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera ( Digital Camera), music player, portable game console, navigation system, etc.

As described above, although it has been described with reference to the preferred embodiments of the present invention, those skilled in the art can make the present invention various without departing from the spirit and scope of the present invention described in the claims below. It will be understood that it can be modified and changed accordingly.

Claims (29)

A plurality of word lines stacked on an upper surface of a substrate, a plurality of memory cells formed in channel holes extending in a direction perpendicular to the substrate, and a word extending in a first horizontal direction and dividing the word lines into a plurality of memory blocks. a non-volatile memory device including a memory cell array having line cut regions; and
A storage controller controlling an operation of the non-volatile memory device;
The storage controller
A first error correction code (ECC) for each of a plurality of sub data units included in user data in a write operation on memory cells of a target page connected to a target word line among the plurality of word lines. ') encoding to generate parity bits for each of the sub data units to form a plurality of ECC sectors, and outer cells to be stored in outer cells among the memory cells in the ECC sectors based on an error correction mode signal. an ECC engine including an ECC encoder configured to select bits, configure an outer ECC sector including the outer cell bits, and perform second ECC encoding on the outer ECC sector to generate outer parity bits; and
and a memory interface configured to transmit a codeword set including the ECC sectors and the outer parity bits to the nonvolatile memory device. According to claim 1,
The storage controller selects the outer cell bits based on a location index that divides the memory cells into outer cells and inner cells according to a relative distance from the word line cut region;
Each of the ECC sectors is a unit of the ECC encoding,
The outer cells are cells relatively close in distance from the word line cut region, and the inner cells are cells relatively far from the word line cut region;
The error correction mode signal is related to selection of inner cell bits to be stored in the outer cell bits and the inner cells,
The ECC encoder performs the first ECC encoding and the second ECC encoding using the same ECC. According to claim 1,
The storage device of claim 1 , wherein the ECC encoder sequentially performs the first ECC encoding on each of the sub data units. According to claim 1,
The ECC encoder performs the first ECC encoding for each of the sub data units and the second ECC encoding for the outer ECC sector in parallel. The method of claim 1, wherein the ECC engine
In a read operation for the target page, the codeword set is received and the ECC sectors are assigned based on a location index that divides the memory cells into outer cells and inner cells according to a relative distance from the word line cut region. constructs the outer ECC sector from ECC sectors, performs first ECC decoding on each of the ECC sectors, and performs second ECC decoding on the outer ECC sector based on the outer parity bits based on a result of the first ECC decoding. The storage device further comprising an ECC decoder that selectively performs decoding. According to claim 5,
The outer ECC sector includes data bits and parity bits read from the outer cells;
The ECC decoder
sequentially performing the first ECC decoding on each of the ECC sectors;
and performing second ECC decoding on the outer ECC sector based on the outer parity bits when an uncorrectable error is detected in at least one of the ECC sectors. The method of claim 5, wherein the ECC engine
In the write operation, the outer ECC sector is selected from the ECC sectors based on a location index that divides the memory cells into outer cells and inner cells according to a relative distance from the word line cut region, and the outer ECC sector is selected. The storage device further comprising a data selector provided to the ECC encoder. The method of claim 7, wherein the data selector
In the read operation, selectively selecting the outer ECC sector from the ECC sectors based on an error flag from the ECC decoder and providing the outer ECC sector to the ECC decoder;
The error flag indicates that an uncorrectable error is detected in at least one of the ECC sectors as a result of the first ECC decoding. According to claim 5,
The ECC decoder performs the first ECC decoding and the second ECC decoding using the same ECC. The method of claim 1 , wherein the non-volatile memory device
the memory cell array;
a voltage generator generating a plurality of word line voltages based on the control signal;
an address decoder coupled to the memory cell array through word lines and configured to provide the word line voltages to the memory cell array based on a row address;
a page buffer circuit coupled to the memory cell array through bit lines and configured to store the user data, the parity bits, and the outer parity bits in the memory cell array; and
and a control circuit controlling the page buffer circuit, the address decoder, and the voltage generator based on a command and an address from the storage controller. The method of claim 1 , wherein the non-volatile memory device
a memory cell region including a memory cell array including NAND strings each including the plurality of memory cells stacked in a vertical direction with respect to the substrate and a first metal pad; and
a peripheral circuit region including a second metal pad and connected to the memory cell region through the second metal pad and the first metal pad;
The peripheral circuit area is
a voltage generator for generating word line voltages based on the control signal;
an address decoder coupled to the memory cell array through word lines and configured to provide the word line voltages to the memory cell array based on a row address;
a page buffer circuit coupled to the memory cell array through bit lines and configured to store the user data, the parity bits, and the outer parity bits in the memory cell array; and
and a control circuit controlling the voltage generator, the address decoder, and the page buffer circuit based on a command and an address from the storage controller. A plurality of word lines stacked on an upper surface of a substrate, a plurality of memory cells formed in channel holes extending in a direction perpendicular to the substrate, and a word extending in a first horizontal direction and dividing the word lines into a plurality of memory blocks. a non-volatile memory device including a memory cell array having line cut regions; and
A storage controller controlling an operation of the non-volatile memory device;
In a write operation on memory cells of a target page connected to a target word line among the plurality of word lines, the storage controller divides the memory cells into outer cells and inner cells based on a relative distance from the word line cut region. Selecting outer cell bits to be stored in the outer cells from a plurality of sub data units included in user data based on a location index and an error correction mode signal to configure an outer ECC sector including the outer cell bits, First error correction code (ECC) encoding is performed on the outer ECC sector to generate outer parity bits, and second ECC encoding is performed on each of the sub data units to generate the outer parity bits. an ECC engine including an ECC encoder constituting a plurality of ECC sectors by generating parity bits in each of the ECC sectors; and
and a memory interface configured to transmit a codeword set including the ECC sectors and the outer parity bits to the nonvolatile memory device. According to claim 12,
Each of the ECC sectors is a unit of the ECC encoding,
The outer cells are cells relatively close in distance from the word line cut region, and the inner cells are cells relatively far from the word line cut region;
The error correction mode signal is related to selection of inner cell bits to be stored in the outer bits and the inner cells,
The ECC encoder performs the first ECC encoding and the second ECC encoding using the same ECC. 13. The method of claim 12, wherein the ECC engine
In a read operation for the target page, receiving the codeword set, constructing the outer ECC sector from the ECC sectors based on the location index, and performing first ECC decoding on each of the ECC sectors; , an ECC decoder that performs second ECC decoding on the outer ECC sector based on the outer parity bits. According to claim 14,
The ECC decoder sequentially performs the first ECC decoding for each of the ECC sectors;
The ECC decoder performs the first ECC decoding and the second ECC decoding using the same ECC. 13. The method of claim 12, wherein the ECC engine
and a data selector configured to configure the outer ECC sector by selecting the outer cell bits from the sub data units based on the location index in the write operation, and providing the outer ECC sector to the ECC encoder.
The data selector
In the read operation, the outer ECC sector is selected from the ECC sectors based on the location index and the outer ECC sector is provided to the ECC decoder. A plurality of word lines stacked on an upper surface of a substrate, a plurality of memory cells formed in channel holes extending in a direction perpendicular to the substrate, and a word extending in a first horizontal direction and dividing the word lines into a plurality of memory blocks. A method of operating a non-volatile memory device including a memory cell array having line cut regions and a storage device controlling the non-volatile memory device, the method comprising:
When an error correction code (ECC) encoder included in the storage controller writes memory cells of a target page connected to a target word line among the plurality of word lines, a plurality of user data are included. configuring a plurality of ECC sectors by generating parity bits for each of the sub data units by performing first ECC encoding on each of the sub data units;
configuring an outer ECC sector including the outer cell bits by selecting outer cell bits to be stored in outer cells among the memory cells from the ECC sectors;
generating, by the ECC encoder, outer parity bits by performing second ECC encoding on the outer ECC sector; and
and transmitting a codeword set including the ECC sectors and the outer parity bits to the non-volatile memory device. According to claim 17,
receiving a codeword set including the ECC sectors and the outer parity bits from the nonvolatile memory device in a read operation;
constructing the outer ECC sector from the ECC sectors based on a location index that divides the memory cells into outer cells and inner cells based on a relative distance from the word line cut region;
performing first ECC decoding on each of the ECC sectors by an ECC decoder included in the storage controller; and
and performing second ECC decoding on the outer ECC sector selectively based on the outer parity bits based on a result of the first ECC decoding. A plurality of word lines stacked on an upper surface of a substrate, a plurality of memory cells formed in channel holes extending in a direction perpendicular to the substrate, and a word extending in a first horizontal direction and dividing the word lines into a plurality of memory blocks. a non-volatile memory device including a memory cell array having line cut regions; and
A storage controller controlling an operation of the non-volatile memory device;
The storage controller
A first error correction code (ECC) for each of a plurality of sub data units included in user data in a write operation on memory cells of a target page connected to a target word line among the plurality of word lines. ') encoding is performed to generate parity bits for each of the sub data units to form a plurality of ECC sectors, and an inner cell to be stored in inner cells among the memory cells in the ECC sectors based on an error correction mode signal. An ECC engine including an ECC encoder that selects some of the bits, configures an inner ECC sector including the selected inner cell bits, and performs second ECC encoding on the inner ECC sector to generate inner parity bits. ; and
and a memory interface configured to transmit a codeword set including the ECC sectors and the inner parity bits to the nonvolatile memory device. According to claim 19,
The ECC engine selects some of the inner cell bits based on a location index that divides the memory cells into inner cells and outer cells according to a relative distance from the word line cut region;
Each of the ECC sectors is a unit of the ECC encoding,
The inner cells are cells relatively far from the word line cut region, and the outer cells are cells relatively short from the word line cut region;
The error correction mode signal is related to selection of outer cell bits to be stored in the inner cell bits and the outer cells,
The error occurrence probability of the inner cell bits is relatively lower than the error occurrence probability of the outer cell bits,
The ECC encoder performs the first ECC encoding and the second ECC encoding using the same ECC. According to claim 19,
The ECC engine
configuring a first inner ECC sector by selecting first inner cell bits related to a first location index from among the inner cells;
Selecting second inner cell bits related to a second location index from among the inner cells to configure a second inner ECC sector;
The ECC encoder is
generating first inner parity bits by performing the second ECC encoding on the first inner ECC sector;
and generating second inner parity bits by performing the second ECC encoding on the second inner ECC sector. According to claim 21,
The ECC encoder sequentially performs the first ECC encoding on each of the sub data units and the second ECC encoding on each of the first inner ECC sector and the second inter ECC sector. . According to claim 21,
Wherein the ECC encoder performs the first ECC encoding for each of the sub data units and the second ECC encoding for each of the first inner ECC sector and the second inter ECC sector in parallel. Device. 20. The method of claim 19, wherein the ECC engine
In the read operation for the target page,
Receiving the codeword set, constructing the inner ECC sector from the ECC sectors based on a location index that divides the memory cells into inner cells and outer cells according to their relative distance from the word line cut region;
performing first ECC decoding on the inner ECC sector based on the inner parity bits to correct a correctable error of the inner ECC sector;
an ECC decoder for correcting a correctable error of each of the ECC sectors by performing a second ECC decoding on each of the ECC sectors;
The storage device of claim 1 , wherein an error occurrence probability of the inner cell bits is relatively lower than an error occurrence probability of the outer cell bits. According to claim 24,
The inner ECC sector includes data bits read from the inner cells;
The ECC decoder
The storage device characterized in that the first ECC decoding and the second ECC decoding are sequentially performed. 20. The method of claim 19, wherein the ECC engine
In the read operation for the target page,
Receiving the codeword set, constructing the inner ECC sector from the ECC sectors based on a location index that divides the memory cells into inner cells and outer cells according to their relative distance from the word line cut region;
performing first ECC decoding on the inner ECC sector based on the inner parities to correct a correctable error of the inner ECC sector;
an ECC decoder to perform a second ECC decoding on some of the ECC sectors to correct at least one correctable error in some of the ECC sectors;
The ECC decoder
If an uncorrectable error is detected in some of the ECC sectors,
Perform third ECC decoding on all of the ECC sectors;
The storage device of claim 1 , wherein an error occurrence probability of the inner cell bits is relatively lower than an error occurrence probability of the outer cell bits. The method of claim 26,
The unit of the first ECC decoding and the unit of the second ECC decoding are the same,
The storage device, characterized in that the third ECC decoding unit is larger than the second ECC decoding unit. A plurality of word lines stacked on an upper surface of a substrate, a plurality of memory cells formed in channel holes extending in a direction perpendicular to the substrate, and a word extending in a first horizontal direction and dividing the word lines into a plurality of memory blocks. A method of operating a non-volatile memory device including a memory cell array having line cut regions and a storage device controlling the non-volatile memory device, the method comprising:
When an error correction code (ECC) encoder included in the storage controller writes memory cells of a target page connected to a target word line among the plurality of word lines, a plurality of user data are included. configuring a plurality of ECC sectors by generating parity bits for each of the sub data units by performing first ECC encoding on each of the sub data units;
configuring an inner ECC sector including some of the inner cell bits by selecting inner cell bits to be stored in inner cells among the memory cells from the ECC sectors;
generating, by the ECC encoder, inner parity bits by performing second ECC encoding on the inner ECC sector; and
and transmitting a codeword set including the ECC sectors and the inner parity bits to the non-volatile memory device. According to claim 28,
receiving a codeword set including the ECC sectors and the inner parity bits from the non-volatile memory device in a read operation;
constructing the inner ECC sector from the ECC sectors based on a location index that divides the memory cells into outer cells and inner cells based on a relative distance from the word line cut region;
performing, by an ECC decoder included in the storage controller, first ECC decoding on the inter-ECC sector based on the inner parity bits;
and performing, by the ECC decoder, second ECC decoding on each of the ECC sectors to which a result of the first ECC decoding is reflected.

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