KR20230071681A - Data transfer circuits of nonvolatile memory devices and nonvolatile memory devices including the same - Google Patents

Abstract

A data transmission circuit of a nonvolatile memory device includes a plurality of first repeaters, a plurality of second repeaters, and a plurality of signal lines. The plurality of first repeaters are connected to first circuit elements disposed in a data input/output path of the nonvolatile memory device. The plurality of second repeaters are connected to second circuit elements disposed apart from the first circuit elements in the data input/output path of the nonvolatile memory device. The plurality of signal lines connect the plurality of first repeaters and the plurality of second repeaters, and include a first group of signal lines and a second group of signal lines that are alternately disposed. The plurality of first repeaters include a first group of repeaters activated in a first operation mode and a second group of repeaters activated in a second operation mode whose operation section does not overlap with the first operation mode. The plurality of second repeaters are activated in the first operation mode, a third group of repeaters connected to the first group of repeaters through signal lines of the first group, and activated in the second operation mode, , and a fourth group of repeaters connected through the second group of repeaters and the second group of signal lines. The second group of signal lines are floated in the first operating mode, and the first group of signal lines are floated in the second operating mode.

Description

Data transmission circuit of non-volatile memory device and non-volatile memory device including the same

The present invention relates to a semiconductor memory device, and more particularly, to a data transfer circuit of a non-volatile memory device and a non-volatile memory device including the same.

Semiconductor memory devices for storing data can be largely classified into volatile memory devices and non-volatile memory devices. In a volatile memory device such as dynamic random access memory (DRAM), in which data is stored by charging or discharging cell capacitors, stored data is maintained while power is applied, but stored data is lost when power is cut off. Meanwhile, the non-volatile memory device may store data even when power is cut off. Volatile memory devices are mainly used as main memories of computers, etc., and non-volatile memory devices are used as large-capacity memories for storing programs and data in a wide range of application devices such as computers and portable communication devices.

Recently, a non-volatile memory device in which memory cells are stacked in three dimensions, such as a vertical NAND flash memory device, has been actively researched to improve the degree of integration of semiconductor memory devices.

Current consumption of signal lines transferring data in a non-volatile memory device is considerable.

One object of the present invention is to provide a data transmission circuit of a non-volatile memory device capable of reducing current consumption.

One object of the present invention is to provide a non-volatile memory device capable of reducing current consumption.

A data transfer circuit of a nonvolatile memory device according to example embodiments includes a plurality of first repeaters, a plurality of second repeaters, and a plurality of signal lines. The plurality of first repeaters are connected to first circuit elements disposed in a data input/output path of the nonvolatile memory device. The plurality of second repeaters are connected to second circuit elements disposed apart from the first circuit elements in the data input/output path of the nonvolatile memory device. The plurality of signal lines connect the plurality of first repeaters and the plurality of second repeaters, and include a first group of signal lines and a second group of signal lines that are alternately disposed. The plurality of first repeaters include a first group of repeaters activated in a first operation mode and a second group of repeaters activated in a second operation mode whose operation section does not overlap with the first operation mode. The plurality of second repeaters are activated in the first operation mode, a third group of repeaters connected to the first group of repeaters through signal lines of the first group, and activated in the second operation mode, , and a fourth group of repeaters connected through the second group of repeaters and the second group of signal lines. The second group of signal lines are floated in the first operating mode, and the first group of signal lines are floated in the first operating mode.

A nonvolatile memory device according to example embodiments includes a memory cell array including a plurality of memory cells, a page buffer circuit, a data input/output circuit, a data transfer circuit, and a control circuit. The page buffer circuit is connected to the memory cell array through a plurality of bit lines. The data input/output circuit exchanges data with an external memory controller. The data transfer circuit is connected between the data input/output circuit and the page buffer circuit, provides the data provided from the data input/output circuit to the page buffer circuit in a first operation mode, and operates in the first operation mode. In a second operation mode in which sections do not overlap, the data provided from the page buffer circuit is provided to the data input/output circuit. The control circuit controls the page buffer circuit and the data transfer circuit. The data transmission circuit transmits data among a plurality of signal lines included therein in each of the first operation mode and the second operation mode in response to a first power gating control signal and a second power gating signal from the control circuit. Float some signal lines that do not transmit.

A data transfer circuit of a nonvolatile memory device according to example embodiments includes a plurality of first repeaters, a plurality of second repeaters, and a plurality of signal lines. The plurality of first repeaters are connected to first circuit elements disposed in a data input/output path of the nonvolatile memory device. The plurality of second repeaters are connected to second circuit elements disposed apart from the first circuit elements in the data input/output path of the nonvolatile memory device. The plurality of signal lines connect the plurality of first repeaters and the plurality of second repeaters, and include a first group of signal lines and a second group of signal lines that are alternately disposed. The plurality of first repeaters include a first group of repeaters activated in a first operation mode and a second group of repeaters activated in a second operation mode whose operation section does not overlap with the first operation mode. The plurality of second repeaters are activated in the first operation mode, a third group of repeaters connected to the first group of repeaters through signal lines of the first group, and activated in the second operation mode, , and a fourth group of repeaters connected through the second group of repeaters and the second group of signal lines. In the second operation mode, the repeaters of the first group float output nodes connected to the signal lines of the first group in response to a first power gating signal. In the first operation mode, the repeaters of the fourth group float output nodes connected to the signal lines of the second group in response to a second power gating signal.

According to embodiments of the present invention, in the first operation mode, while data is transferred to the page buffer circuit through the signal lines of the first group, the repeaters of the second group and the repeaters of the fourth group are used to transmit the data to the first group. The signal lines of the second group alternately arranged with the signal lines are floated, and in the second operation mode, the read data is transferred to the data input/output circuit through the signal lines of the second group, while the repeaters of the first group and the second group By floating the first group of signal lines using three groups of repeaters, current consumption may be reduced by reducing capacitance of signal lines transferring data.

1 is a block diagram illustrating a non-volatile memory device according to example embodiments.
FIG. 2 is a block diagram illustrating a memory system including the nonvolatile memory device of FIG. 1 according to example embodiments.
3 schematically illustrates the structure of the non-volatile memory device of FIG. 1 according to embodiments of the present invention.
FIG. 4 is a block diagram illustrating an example of a memory cell array in the nonvolatile memory device of FIG. 1 .
FIG. 5 is a circuit diagram illustrating one of the memory blocks of FIG. 4 .
FIG. 6 shows an example of the structure of one cell string of the memory block of FIG. 5 .
FIG. 7 illustratively illustrates a connection between the memory cell array of FIG. 1 and a page buffer circuit according to example embodiments.
8 shows details of a page buffer according to embodiments of the present invention.
9 is a circuit diagram illustrating a cache unit according to example embodiments.
10 illustrates a data transfer circuit in the non-volatile memory device of FIG. 1 according to example embodiments.
11A is a circuit diagram showing the configuration of one of the repeaters of the first group in the data transfer circuit of FIG. 10 according to embodiments of the present invention.
FIG. 11B is a circuit diagram showing a configuration of one of repeaters of a fourth group in the data transmission circuit of FIG. 10 according to embodiments of the present invention.
12 illustrates the operation of the repeater of FIG. 11A in a second mode of operation according to embodiments of the present invention.
13 illustrates an operation of the data transfer circuit of FIG. 10 in a first operation mode according to embodiments of the present invention.
FIG. 14 illustrates data transferred to the page buffer circuit when the data transfer circuit operates as shown in FIG. 13 .
FIG. 15 shows a first power gating signal and a second power gating signal when the data transfer circuit synchronizes even-numbered data bits and odd-numbered data bits as shown in FIG. 14 .
16 illustrates the operation of the data transmission circuit of FIG. 10 in a second operating mode according to embodiments of the present invention.
FIG. 17 illustrates data transferred to the page buffer circuit when the data transfer circuit operates as shown in FIG. 16 .
FIG. 18 shows a first power gating signal and a second power gating signal when the data transfer circuit synchronizes even-numbered data bits and odd-numbered data bits as shown in FIG. 17 .
19 is a block diagram illustrating a nonvolatile memory device according to example embodiments.
20 is a block diagram illustrating a nonvolatile memory device according to example embodiments.
21 shows in detail the interface area of FIG. 20 according to embodiments of the present invention.
22 is a flowchart illustrating a method of operating a nonvolatile memory device according to example embodiments.
23 is a cross-sectional view illustrating a nonvolatile memory device according to example embodiments.
24 is a block diagram illustrating an electronic system including a semiconductor device according to example embodiments.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in more detail. The same reference numerals are used for the same components in the drawings, and redundant descriptions of the same components are omitted.

1 is a block diagram illustrating a non-volatile memory device according to embodiments of the present invention.

Referring to FIG. 1 , a nonvolatile memory device 50 may include a memory cell array 100 and a peripheral circuit 200 . The peripheral circuit 200 may include a page buffer circuit 210 , a control circuit 220 , a voltage generator 230 , an address decoder 240 , a data transfer circuit 300 and a data input/output circuit 250 . Although not shown in FIG. 1 , the peripheral circuit 200 may further include an input/output interface, column logic, a pre-decoder, and a temperature sensor.

The memory cell array 100 may be connected to the address decoder 240 through a string select line SSL, a plurality of word lines WLs, and a ground select line GSL. Also, the memory cell array 100 may be connected to the page buffer circuit 210 through a plurality of bit lines BLs. The memory cell array 100 may include a plurality of non-volatile memory cells connected to a plurality of word lines WLs and a plurality of bit lines BLs.

In an embodiment, the memory cell array 100 may be a three-dimensional memory cell array formed on a substrate in a three-dimensional structure (or vertical structure). In this case, the memory cell array 200 may include vertical memory cell strings including a plurality of memory cells stacked on each other.

The control circuit 220 receives the control signal CTRL, the command signal CMD, and the address signal ADDR from the memory controller (20 in FIG. 2), and receives the control signal CTRL, the command signal CMD, and the address signal. An erase loop, a program loop, and a read operation of the nonvolatile memory device 50 may be controlled based on (ADDR).

For example, the control circuit 220 may include control signals CTLs for controlling the voltage generator 230 and a page buffer control signal PBCTL for controlling the page buffer circuit 210 based on the command signal CMD. ) and the first power gating signal PGS1 and the second power gating signal PGS2 for controlling the data transfer circuit 300 are generated, and the row address R_ADDR and the column address are generated based on the low address signal ADDR. (C_ADDR). The control circuit 220 may provide the row address R_ADDR to the address decoder 240 and the column address C_ADDR to the data input/output circuit 250 . The control circuit 220 may include a status signal generator 225 that generates a status signal (or ready/busy) signal RnB indicating an operating state of the nonvolatile memory device 50 .

The address decoder 240 may be connected to the memory cell array 100 through a string select line SSL, a plurality of word lines WLs, and a ground select line GSL. During a program operation or a read operation, the address decoder 240 determines one of a plurality of word lines WLs as a selected word line based on the row address R_ADDR provided from the control circuit 450, and Word lines other than the selected word line among the lines WLs may be determined as non-selected word lines.

The voltage generator 230 generates word line voltages VWLs necessary for the operation of the nonvolatile memory device 50 using the power PWR based on the control signals CTLs provided from the control circuit 220. can do. The word line voltages VWLs generated by the voltage generator 230 may be applied to the plurality of word lines WLs through the address decoder 240 .

For example, during an erase operation, the voltage generator 230 may apply an erase voltage to a well of a memory block and a ground voltage to all word lines of the memory block. During the erase verify operation, the voltage generator 230 may apply the erase verify voltage to all word lines of one memory block or may apply the erase verify voltage in units of word lines.

For example, during a program operation, the voltage generator 230 may apply a program voltage to selected word lines and a program pass voltage to non-selected word lines. Also, during the program verify operation, the voltage generator 230 may apply a program verify voltage to selected word lines and apply a verify pass voltage to non-selected word lines. Also, during a read operation, the voltage generator 230 may apply read voltages to selected word lines and apply read pass voltages to unselected word lines.

The page buffer circuit 210 may be connected to the memory cell array 100 through a plurality of bit lines BLs. The page buffer circuit 210 may include a plurality of page buffers (PBs) and page buffer drivers (PBDs) 215 . The page buffer circuit 210 may temporarily store data to be programmed in a selected page during a program operation, and may temporarily store data read from the selected page during a read operation. The page buffer driver 215 transfers program data provided from the data transfer circuit 300 to the number of page buffers PBs during a program operation, and transfers data provided from a plurality of page buffers PBs during a read operation. It can be provided to the data transfer circuit 300 .

In the embodiment, page buffer units (eg, PBU0 to PBUn of FIG. 7 ) included in each of the plurality of page buffers PB and cache latches included in each of the plurality of page buffers PB (For example, CL0 to CLn of FIG. 7 ) may be spaced apart from each other to have a separated structure. Accordingly, a degree of freedom for wirings disposed above the page buffer units may be improved and layout complexity may be reduced. Also, since the cache latches are arranged adjacent to the data input/output lines, a distance between the carry latches and the data input/output lines is reduced, thereby improving data input/output speed.

The data transfer circuit 300 may include first repeaters 310 , second repeaters 350 and signal lines 380 .

The first repeaters 310 are connected to the data input/output circuit 250, the second repeaters 350 are connected to the page buffer driver 215 of the page buffer circuit 210, and the signal lines 380 are The first repeaters 310 and the second repeaters 350 may be connected to each other.

The first repeaters 310 may include a first group of repeaters activated in a first operation mode and a second group of repeaters activated in a second operation mode. The second repeaters 350 are activated in the first operation mode, and the repeaters of the third group connected through the signal lines of the first group among the repeaters and signal lines 380 of the first group and the second operation mode, and may include a fourth group of repeaters connected through the second group of repeaters and signal lines 380 through the second group of signal lines.

The signal lines of the first group and the signal lines of the second group may be alternately arranged.

The signal lines of the second group are floated in the first operating mode to reduce the capacitance of each of the signal lines of the first group, and the signal lines of the first group are floated in the second operating mode to reduce the capacitance of each of the signal lines of the first group. By reducing the capacitance of , current consumed in the signal lines 380 during data transmission in the first operation mode and the second operation mode may be reduced.

In the second operation mode, the repeaters of the first group float output nodes connected to the signal lines of the first group in response to the first power gating signal PGS1, and the repeaters of the third group float the output nodes connected to the signal lines of the first group in response to the first power gating signal (PGS1). An input node connected to the signal lines of the first group may be floated in response to PGS1).

In the first operation mode, the repeaters of the second group float output nodes connected to the signal lines of the second group in response to the second power gating signal PGS2, and the repeaters of the fourth group float the second power gating signal (PGS2). In response to PGS2), input nodes connected to the fourth group of signal lines may be floated.

In an embodiment, the first operation mode may correspond to a write operation, and the second operation mode may correspond to a read operation. Also, the first operation mode and the second operation mode may not overlap each other. That is, the operation period of the first operation mode and the operation period of the second operation mode may not overlap each other (may not overlap).

Although the data transfer circuit 300 has been described as being connected between the data input/output circuit 250 and the page buffer circuit 210 in FIG. 1 , the data transfer circuit 300 is a data input/output path within the non-volatile memory device 50. It is disposed between the disposed first circuit element and the second circuit element, and may transmit data between the first circuit element and the second circuit element.

When the data transmission circuit 300 is disposed between a first circuit element and a second circuit element arranged in a data input/output path in the nonvolatile memory device 50, the first operation mode is performed from the first circuit element to the second circuit element. may correspond to an operation of transferring data to , and the second operation mode may correspond to an operation of transferring data from the second circuit element to the first circuit element.

The data input/output circuit 250 may be connected to the page buffer circuit 210 through the data transmission circuit 300 . During a program operation, the data input/output circuit 250 receives the program data DATA from the memory controller (20 in FIG. 2) and converts the program data DATA based on the column address C_ADDR provided from the control circuit 220. may be provided to the page buffer circuit 210 through the data transfer circuit 300 . During a read operation, the data input/output circuit 250 provides the read data DATA stored in the page buffer circuit 210 through the data transmission circuit 300 based on the column address C_ADDR provided from the control circuit 220. receive and provide read data DATA to the memory controller 20 .

The data input/output circuit 250 may include a serial/parallelizer (SERDES) 255. The serializer/parallelizer 255 parallelizes the program data DATA and provides it to the data transfer circuit 300 in a write operation, and serializes the read data DATA provided from the data transfer circuit 300 in a read operation to a memory memory. It can be provided to the controller 20.

FIG. 2 is a block diagram illustrating a memory system including the nonvolatile memory device of FIG. 1 according to example embodiments.

Referring to FIG. 2 , the memory system 10 may include a memory controller 20 and a nonvolatile memory device (NVM) 50 .

The memory controller 20 controls the operation of the nonvolatile memory device 50 by applying a control signal CTRL, a command CMD, and an address ADDR to the nonvolatile memory device 50, and 50) and data (DATA) can be sent/received. The nonvolatile memory device 50 may apply the status signal RnB to the memory controller 20 to indicate an operating state of the nonvolatile memory device 50 . For example, when the state signal RnB is at a high level, it indicates that the nonvolatile memory device 50 is in a state in which a command can be received from the memory controller 20 .

3 schematically illustrates the structure of the non-volatile memory device of FIG. 1 according to embodiments of the present invention.

Referring to FIG. 2 , the nonvolatile memory device 50 may include a first semiconductor layer L1 and a second semiconductor layer L2, and the first semiconductor layer L1 is a second semiconductor layer L2. may be stacked in a vertical direction (VD) with respect to Specifically, the second semiconductor layer L2 may be disposed below the first semiconductor layer L1 in a vertical direction VD, and thus, the second semiconductor layer L2 may be disposed close to the substrate. there is.

In one embodiment, the memory cell array 100 of FIG. 1 may be formed on the first semiconductor layer L1, and the peripheral circuit 200 of FIG. 1 may be formed on the second semiconductor layer L2. Accordingly, the nonvolatile memory device 50 may have a structure in which the memory cell array 100 is disposed above the peripheral circuit 200, that is, a COP (Cell Over Periphery) structure. The COP structure can effectively reduce an area in a horizontal direction and improve the degree of integration of the nonvolatile memory device 50 .

In one embodiment, the second semiconductor layer L2 may include a substrate, and the peripheral circuit 200 is formed on the second semiconductor layer L2 by forming transistors and metal patterns for wiring the transistors on the substrate. can form After the peripheral circuit 200 is formed on the second semiconductor layer L2, the first semiconductor layer L1 including the memory cell array 100 may be formed, and the word lines of the memory cell array 100 ( Metal patterns may be formed to electrically connect the peripheral circuit 200 formed in the second semiconductor layer L2 to the WL) and the bit lines BL. For example, bit lines BL may extend in a first horizontal direction HD1 , and word lines WL may extend in a second horizontal direction HD2 .

With the development of semiconductor processes, as the number of stages of memory cells disposed in the memory cell array 100 increases, that is, as the stacked number of word lines WL increases, the area of the memory cell array 100 decreases. Accordingly, the area of the peripheral circuit 200 is also reduced. According to the present embodiment, in order to reduce the area occupied by the page buffer circuit 210, the page buffer circuit 210 has a structure in which the page buffer unit and the cache latch are separated, and the page buffer units are respectively included in the page buffer unit. Sensing nodes may be commonly connected to a combined sensing node.

FIG. 4 is a block diagram illustrating an example of a memory cell array in the nonvolatile memory device of FIG. 1 .

Referring to FIG. 4 , the memory cell array 100 includes a plurality of memory blocks (BLK1 to BLKz, where z is a natural number greater than or equal to 3) disposed along a plurality of directions HD1 , HD2 , and VD. In an embodiment, memory blocks are selected by address decoder 240 shown in FIG. For example, the address decoder 240 may select a memory block BLK corresponding to a block address from among the memory blocks BLK1 to BLKz.

FIG. 5 is a circuit diagram illustrating one BLKi of the memory blocks BLK1 to BLKz of FIG. 4 .

The memory block BLKi shown in FIG. 5 represents a three-dimensional memory block formed on the substrate SUB in a three-dimensional structure. For example, a plurality of memory cell strings included in the memory block BLKi may be stacked in a direction PD perpendicular to the substrate SUB.

Referring to FIG. 5 , the memory block BLKi includes a plurality of memory cell strings (or NAND strings, NS11 to NS33) connected between the bit lines BL1, BL2, and BL3 and the common source line CSL. can include Each of the plurality of memory cell strings NS11 to NS33 may include a string select transistor SST, a plurality of memory cells MC1 , MC2 , ..., MC8 , and a ground select transistor GST.

The string select transistor SST may be connected to corresponding string select lines SSL1 , SSL2 , and SSL3 . The plurality of memory cells MC1 , MC2 , ..., MC8 may be connected to corresponding word lines WL1 , WL2 , ... , WL8 , respectively. The ground select transistor GST may be connected to corresponding ground select lines GSL1 , GSL2 , and GSL3 . The string select transistor SST may be connected to corresponding bit lines BL1 , BL2 , and BL3 , and the ground select transistor GST may be connected to the common source line CSL.

Word lines (eg, WL1) having the same height may be commonly connected, and ground select lines GSL1, GSL2, and GSL3 and string select lines SSL1, SSL2, and SSL3 may be separated from each other.

FIG. 6 shows an example of the structure of one cell string of the memory block of FIG. 5 .

Referring to FIGS. 5 and 6 , the cell string NS11 may be provided with a pillar PL extending in a direction perpendicular to the substrate SUB and contacting the substrate SUB. The ground select line GSL1, the word lines WL1 to WL8, and the string select line SSL1 shown in FIG. 6 may be formed of conductive materials parallel to the substrate SUB, for example, metal materials. can The pillar PL may contact the substrate SUB by passing through conductive materials forming the ground select line GSL1 , the word lines WL1 to WL8 , and the string select line SSL1 .

In Fig. 6, a cross-sectional view along the cutting line A-A' is also shown. Exemplarily, a cross-sectional view of the first memory cell MC1 corresponding to the first word line WL1 is shown. The pillar PL may include a cylindrical body BD. An air gap AG may be provided inside the body BD.

The body BD may include P-type silicon and may be a region in which a channel is formed. The pillar PL may further include a cylindrical tunnel insulating layer TI surrounding the body BD and a cylindrical charge trapping layer CT surrounding the tunnel insulating layer TI. A blocking insulating layer BI may be provided between the first word line WL1 and the pillar PL. The body BD, the tunnel insulating layer TI, the charge trapping layer CT, the blocking insulating layer BI, and the first word line WL1 are formed in a direction perpendicular to the substrate SUB or an upper surface of the substrate SUB. It may be a formed charge trapping transistor. The string select transistor SST, the ground select transistor GST, and other memory cells may have the same structure as the first memory cell MC1.

FIG. 7 illustratively illustrates a connection between the memory cell array of FIG. 1 and a page buffer circuit according to example embodiments.

Referring to FIG. 7 , the memory cell array 100 may include first to n+1 th NAND strings NS0 to NSn, and each of the 1st to n+1 th NAND strings NS0 to NSn A ground select transistor GST connected to the ground select line GSL, a plurality of memory cells MC connected to the plurality of word lines WL0 to WLm, respectively, and a string select transistor SST connected to the string select line SSL ), and the ground select transistor GST, the plurality of memory cells MC, and the string select transistor SST may be serially connected to each other. Here, m is a positive integer.

The page buffer circuit 210 may include first to n+1 th page buffer units PBU0 to PBUn. The first page buffer unit PB0 is connected to the first NAND string NS0 through the first bit line BL0, and the n+1 th page buffer unit PBUn includes the n+1 th bit line BLn. It can be connected to the n+1th NAND string NSn through Here, n is a positive integer. For example, n may be 7, and the page buffer circuit 210 may have a structure in which 8-stage page buffer units PBU0 to PBUn are arranged in a row. For example, the first to n+1th page buffer units PBU0 to PBUn may be arranged in a line along the extension direction of the first to n+1th bit lines BL0 to BLn.

The page buffer circuit 210 may further include first to n+1th cache latches CL0 to CLn respectively corresponding to the first to n+1th page buffer units PBU0 to PBUn. The page buffer circuit 210 may have a structure in which eight-stage cache latches CL0 to CLn are arranged in a row. For example, the first to n+1th cache latches CL0 to CLn may be arranged in a row along the extension direction of the first to n+1th bit lines BL0 to BLn.

Sensing nodes of each of the first to n+1 th page buffer units PBU0 to PBUn may be connected in common to the combined sensing node SOC. In addition, the first to n+1th cache latches CL0 to CLn may be commonly connected to the combined sensing node SOC. Accordingly, the first to n+1th page buffer units PBU0 to PBUn may be connected to the first to n+1th cache latches CL0 to CLn through the combined sensing node SOC.

8 shows details of a page buffer according to embodiments of the present invention.

Referring to FIG. 8 , the page buffer PB may correspond to an example of the page buffer PB of FIG. 1 . The page buffer (PB) may include a page buffer unit (PBU) and a cache unit (CU). Since the cache unit CU includes cache latches C-LATCH and CL, and the cache latch CL is connected to the data input/output line, the cache unit CU may be disposed adjacent to the data input/output line. Accordingly, the page buffer unit (PBU) and the cache unit (CU) may be spaced apart from each other, and the page buffer (PB) may have a page buffer unit (PBU)-cache unit (CU) separation structure.

The page buffer unit (PBU) may include a main unit (MU). The main unit MU may include main transistors in the page buffer PB. The page buffer unit PBU may further include a bit line select transistor TR_hv connected to the bit line BL and driven by the bit line select signal BLSLT. The bit line select transistor TR_hv may be implemented as a high voltage transistor. Accordingly, the bit line select transistor TR_hv may be in a well area different from the main unit MU, that is, in a high voltage unit (HVU). can be placed.

The main unit (MU) consists of a sensing latch (S-LATCH) (SL), a force latch (F-LATCH) (FL), an upper bit latch (M-LATCH) (ML) and a lower bit latch (L-LATCH) (LL). ) may be included. Depending on embodiments, the sensing latch SL, the force latch FL, the upper bit latch ML, or the lower bit latch LL may be referred to as a “main latch”. The main unit MU may further include a precharge circuit PC capable of controlling a precharge operation of the bit line BL or the sensing node SO based on the bit line clamping control signal BLCLAMP. , and may further include a transistor PM' driven by the bit line setup signal BLSETUP.

The sensing latch SL may store data stored in the memory cell or a result of sensing the threshold voltage of the memory cell during a read or program verify operation. Also, the sensing latch SL may be used to apply a program bit line voltage or a program inhibit voltage to the bit line BL during a program operation. The force latch FL may be used to improve threshold voltage distribution during a program operation. Specifically, the force latch FL stores force data. The force data may be initially set to '1' and then reversed to '0' when the threshold voltage of the memory cell enters a forcing region that is less than the target region. By using force data, a bit line voltage may be controlled during a program execution operation and a program threshold voltage distribution may be formed more narrowly.

The upper bit latch ML, the lower bit latch LL, and the cache latch CL may be used to store externally input data during a program operation, and may be referred to as “data latches”. When 3-bit data is programmed in one memory cell, the 3-bit data may be stored in the upper bit latch ML, the lower bit latch LL, and the cache latch CL, respectively. The upper bit latch ML, the lower bit latch LL, and the cache latch CL may retain stored data until the programming of the memory cell is completed. In addition, the cache latch CL may receive data read from the memory cell during a read operation from the sensing latch SL and output the data to the outside through a data input/output line.

Also, the main unit MU may further include first to fourth transistors NM1 to NM4. The first transistor NM1 may be connected between the sensing node SO and the sensing latch SL, and may be driven by the ground control signal SOGND. The second transistor NM2 may be connected between the sensing node SO and the force latch FL, and driven by the forcing monitoring signal MON_F. The third transistor NM3 may be connected between the sensing node SO and the upper bit latch ML, and may be driven by the upper bit monitoring signal MON_M. The fourth transistor NM4 may be connected between the sensing node SO and the lower bit latch LL, and may be driven by the lower bit monitoring signal MON_L.

Also, the main unit MU may further include fifth and sixth transistors NM5 and NM6 connected in series between the bit line select transistor TV_hv and the sensing node SO. The fifth transistor NM5 can be driven by the bit line shut-off signal BLSHF, and the sixth transistor NM6 can be driven by the bit line connection control signal CLBLK. Also, the main unit MU may further include a precharge transistor PM. The precharge transistor PM is connected to the sensing node SO, is driven by the load signal LOAD, and precharges the sensing node SO to a precharge level in the precharge period.

In this embodiment, the main unit MU may further include a pair of pass transistors, that is, first and second pass transistors TR and TR' connected to the sensing node SO. Depending on embodiments, the first and second pass transistors TR and TR′ may be referred to as “first and second sensing node connection transistors”. The first and second pass transistors TR and TR′ may be driven according to the pass control signal SO_PASS. Depending on the embodiment, the pass control signal SO_PASS may also be referred to as a “sensing node connection control signal”. Specifically, the first pass transistor TR is connected between the first terminal SOC_U and the sensing node SO, and the second pass transistor TR′ is connected between the sensing node SO and the second terminal SOC_D. can be connected to

For example, when the page buffer unit PBU is the second page buffer unit PBU1 of FIG. 7 , the first terminal SOC_U may be connected to one end of a pass transistor included in the first page buffer unit PBU0. And, the second terminal SOC_D may be connected to one end of a pass transistor included in the third page buffer unit PBU3. Thus, the sensing node SO may be electrically connected to the coupling sensing node SOC through pass transistors included in each of the third to n+1th page buffer units PBU2 to PBUn.

During a program operation, the page buffer PB verifies whether a selected memory cell among memory cells included in a NAND string connected to the bit line BL has been programmed. Specifically, the page buffer PB stores data sensed through the bit line BL in the sensing latch SL during the program verify operation. An upper bit latch ML and a lower bit latch LL in which target data is stored are set according to the sensed data stored in the sensing latch SL. For example, when the sensed data indicates that programming is complete, the upper bit latch ML and the lower bit latch LL are switched to program inhibit settings for the selected memory cell in a subsequent program loop. The cache latch CL may temporarily store input data provided from the outside. During program operation, target data stored in the cache latch CL may be stored in the upper bit latch ML and the lower bit latch LL.

9 is a circuit diagram illustrating a cache unit (CU) according to example embodiments.

8 and 9 together, the cache unit CU may include a monitor transistor NM7 and a cache latch CL, and the cache latch CL includes first and second inverters INV1 and INV2. ), a dump transistor 132, and transistors 131, 133 to 135. The monitor transistor NM7 is driven according to the cache monitoring signal MON_C and can control a connection between the coupling sensing node SOC and the cache latch CL.

The first inverter INV1 is connected between the first node ND1 and the second node ND2, the second inverter INV2 is connected between the second node ND2 and the first node ND1, The first and second inverters INV1 and INV2 may constitute a latch. Transistor 131 has a gate coupled to the coupled sensing node SOC. The dump transistor 132 may be driven by the dump signal Dump_C and transfer data stored in the cache latch CL to a main latch in the page buffer unit PBU, for example, a sensing latch SL. . The transistor 133 can be driven by the data signal DI, the transistor 134 can be driven by the data inversion signal nDI, and the transistor 135 can be driven by the write control signal DIO_W. can When the write control signal DIO_W is activated, voltage levels of the first and second nodes ND1 and ND2 may be determined according to the data signal DI and the data inversion signal nDI.

The cache unit CU may be connected to the data input/output line RDi through transistors 136 and 137 . The transistor 136 has a gate connected to the second node ND2 and may be turned on or off according to the voltage level of the second node ND2. The transistor 137 may be driven by the read control signal DIO_R. When the read control signal DIO_R is activated and the transistor 137 is turned on, the voltage level of the data input/output line RDi may be determined as '1' or '0' according to the state of the cache latch CL.

10 illustrates a data transfer circuit in the non-volatile memory device of FIG. 1 according to example embodiments.

Referring to FIG. 10 , the data transmission circuit 300 includes first repeaters 310 connected to the serial/parallelizer 255 of the data input/output circuit 250, and the page buffer driver 215 of the page buffer circuit 210. ) may include second repeaters 350 and a plurality of signal lines 380 connected to.

The signal lines 380 may connect the first repeaters 310 and the second repeaters 350 to each other.

The first repeaters 310 include a first group of repeaters 311, 312, 313, and 314 activated in a first operation mode and a second group of repeaters 321, 322, and 323 activated in a second operation mode. , 324). The second repeaters 350 include the third group of repeaters 351, 352, 353, and 354 activated in the first operation mode and the fourth group of repeaters 361, 362, and 363 activated in the second operation mode. , 364).

The repeaters 311, 312, 313, and 314 of the first group and the repeaters 351, 352, 353, and 354 of the third group are connected to the power supply voltage VDD and the ground voltage VSS, and provide first power gating. It can operate in response to signal PGS1. The repeaters 321, 322, 323, and 324 of the second group and the repeaters 361, 362, 363, and 364 of the fourth group are connected to the supply voltage VDD and the ground voltage VSS, and are connected to the second power gating. It can operate in response to signal PGS2.

The signal lines 380 are the first group of signal lines (connecting the first group of repeaters 311, 312, 313, 314 and the third group of repeaters 351, 352, 353, 354 to each other). A second group of signal lines connecting SL1, SL3, SL5, and SL7, the second group of repeaters 321, 322, 323, and 324 and the fourth group of repeaters 361, 362, 363, and 364 to each other. SL2 , SL4 , SL6 , and SL8 may be included. The first group of signal lines SL1 , SL3 , SL5 , and SL7 and the second group of signal lines SL2 , SL4 , SL6 , and SL8 may be alternately disposed.

Since the first group of signal lines SL1, SL3, SL5, and SL7 and the second group of signal lines SL2, SL4, SL6, and SL8 are formed using metal, between the signal lines SL1 and SL2 A capacitance C1 is generated, a capacitance C2 is generated between the signal lines SL2 and SL3, a capacitance C3 is generated between the signal lines SL3 and SL4, and a capacitance C3 is generated between the signal lines SL4 and SL4. A capacitance C4 is generated between the signal lines SL5), a capacitance C5 is generated between the signal lines SL5 and SL6, a capacitance C6 is generated between the signal lines SL6 and SL7, and a signal line A capacitance C7 may be generated between the SL7 and SL8.

Each of the first group of signal lines SL1, SL3, SL5, and SL7 floats in the second operating mode, and each of the second group of signal lines SL2, SL4, SL6, and SL8 floats in the first operating mode. As a result, the same effect as that of serial connection of capacitances that may occur between adjacent signal lines passing data may occur. Since total capacitance is reduced when capacitances are connected in series, current consumption in signal lines transmitting data can be reduced.

Although FIG. 10 shows eight signal lines SL1, SL2, SL3, SL4, SL5, SL6, SL7, and SL8 as the signal lines 380 for convenience of description, the number of signal lines 380 is Not limited to this. In an embodiment, the number of signal lines 380 may include thousands.

11A is a circuit diagram showing the configuration of one of the repeaters of the first group in the data transfer circuit of FIG. 10 according to embodiments of the present invention.

11A shows the configuration of the repeater 311 among the first group of repeaters 311, 312, 313, and 314, but each of the repeaters 312, 313, and 314 and the third group of repeaters 351 and 352 , 353, and 354 may each have the same configuration as that of the repeater 311.

Referring to FIG. 11A , the repeater 311 includes a first inverter 410, a second inverter 420, a first discharge transistor 431, a second discharge transistor 433, and a precharge transistor 435. can include

The first inverter 410 is connected between the power supply voltage VDD and the first node N11, and connected between the power supply voltage VDD and the second node N12 corresponding to the output of the first inverter 410. It may include a PMOS transistor 411 and an NMOS transistor 413 connected between the second node N12 and the first node N11. Gates of the PMOS transistor 411 and the NMOS transistor 413 are commonly connected to the input node NI1 so that the input data bit IN_DB1 may be applied.

The first discharge transistor 431 is implemented as an NMOS transistor including a drain connected to the first node N11, a source connected to the ground voltage VSS, and a gate receiving the first power gating signal PGS1. It can be. The first discharge transistor 431 may discharge (pull-down) the first node N11 to the ground voltage VSS level in response to the first power gating signal PGS1 having a logic high level.

The precharge transistor 435 may be implemented as a PMOS transistor including a source connected to the power supply voltage VDD, a drain connected to the second node N12, and a gate receiving the first power gating signal PGS1. there is. The precharge transistor 435 may precharge (pull-up) the second node N12 to the power supply voltage VDD level in response to the first power gating signal PGS1 having a logic low level.

The second inverter 420 is connected between the power supply voltage VDD and the third node N13, and the PMOS transistor connected between the power supply voltage VDD and the output node NO1 connected to the signal line SL1. 421 and an NMOS transistor 423 connected between the output node NO1 and the third node N13. The gates of the PMOS transistor 421 and the NMOS transistor 423 may be commonly connected to the second node N12, and the second inverter 420 inverts the voltage level of the second node N12 to output the output node. (NO1) can provide the input data bit (IN_DB1).

The second discharge transistor 433 is implemented as an NMOS transistor including a drain connected to the third node N13, a source connected to the ground voltage VSS, and a gate receiving the first power gating signal PGS1. It can be. The second discharge transistor 433 may pull down the third node N13 to the ground voltage VSS level in response to the first power gating signal PGS1 having a logic high level.

The first power gating signal PSG1 may have a logic high level in the first operating mode and a logic low level in the second operating mode. When the first power gating signal PSG1 has a logic high level, the first discharge transistor 431 pulls down the first node N11 to the ground voltage VSS level, and the second discharge transistor 433 ) pulls down the third node N13 to the ground voltage VSS level. Accordingly, the first inverter 410 inverts the input data bit IN_DB1, and the second inverter 420 inverts the voltage level of the second node N12 to generate the input data bit IN_DB1 at the output node NO1. can provide.

FIG. 11B is a circuit diagram showing a configuration of one of repeaters of a fourth group in the data transmission circuit of FIG. 10 according to embodiments of the present invention.

11B shows the configuration of the repeater 361 among the repeaters 361, 362, 363, and 364 of the fourth group, but the repeaters 362, 363, and 364 respectively and the repeaters 321 and 322 of the second group , 323, and 324 may each have the same configuration as that of the repeater 361.

Referring to FIG. 11B, the repeater 361 includes a first inverter 440, a second inverter 450, a first discharge transistor 461, a second discharge transistor 463, and a precharge transistor 465. can include

The first inverter 440 is connected between the power supply voltage VDD and the first node N21, and is connected between the power supply voltage VDD and the second node N22 corresponding to the output of the first inverter 440. It may include a PMOS transistor 441 and an NMOS transistor 443 connected between the second node N22 and the first node N21. The gates of the PMOS transistor 441 and the NMOS transistor 443 are commonly connected to the input node NI2 so that the output data bit OUT_DB1 may be applied.

The first discharge transistor 461 is implemented as an NMOS transistor including a drain connected to the first node N11, a source connected to the ground voltage VSS, and a gate receiving the second power gating signal PGS2. It can be. The first discharge transistor 461 may pull down the first node N21 to the ground voltage VSS level in response to the second power gating signal PGS2 having a logic high level.

The precharge transistor 465 may be implemented as a PMOS transistor including a source connected to the power supply voltage VDD, a drain connected to the second node N22, and a gate receiving the second power gating signal PGS2. there is. The precharge transistor 465 may pull up the second node N22 to the power supply voltage VDD level in response to the second power gating signal PGS1 having a logic low level.

The second inverter 450 is connected between the power supply voltage VDD and the third node N23, and the PMOS transistor 451 and the signal line SL2 connected between the power voltage VDD and the output node NO1. ) and an NMOS transistor 453 connected between the output node NO2 and the third node N23. Gates of the PMOS transistor 451 and the NMOS transistor 453 may be commonly connected to the second node N22, and the second inverter 450 inverts the voltage level of the second node N22 to output the node. (NO2) can provide the output data bit (OUT_DB1).

The second discharge transistor 463 is implemented as an NMOS transistor including a drain connected to the third node N23, a source connected to the ground voltage VSS, and a gate receiving the second power gating signal PGS2. It can be. The second discharge transistor 463 may pull down the third node N13 to the ground voltage VSS level in response to the second power gating signal PGS2 having a logic high level.

The second power gating signal PSG2 may have a logic high level in the second operating mode and a logic low level in the first operating mode. When the second power gating signal PSG2 has a logic high level, the first discharge transistor 461 pulls down the first node N21 to the ground voltage VSS level, and the second discharge transistor 463 ) pulls down the third node N23 to the ground voltage VSS level. Accordingly, the first inverter 440 inverts the output data bit OUT_DB1, and the second inverter 450 inverts the voltage level of the second node N22 to generate the output data bit OUT_DB1 at the output node NO2. can provide.

12 illustrates the operation of the repeater of FIG. 11A in a second mode of operation according to embodiments of the present invention.

Referring to FIG. 12 , since the first power gating signal PGS1 has a logic low level in the second operation mode, the first discharge transistor 431 and the second discharge transistor 433 are turned off, The precharge transistor 435 pulls up the second node N12 to the power supply voltage VDD level. The PMOS transistor 421 of the second inverter 420 is turned off in response to the logic high level of the second node N12. Accordingly, the signal line SL1 connected to the output node NO1 is in a floating state. That is, the repeater 311 may float the signal line SL1 connected to the output node NO1 in response to the first power gating signal PGS1 in the second operation mode.

Similarly, the repeater 361 of FIG. 11B may float the signal line SL2 connected to the output node in response to the second power gating signal PGS2 in the first operation mode.

13 illustrates an operation of the data transfer circuit of FIG. 10 in a first operation mode according to embodiments of the present invention.

Referring to FIG. 13 , in the first operation mode, the first power gating signal PGS1 has a logic high level and the second power gating signal PGS2 has a logic low level. Accordingly, the first group of signal lines SL1, SL3, and SL5 connecting the first group of repeaters 311, 312, 313, and 314 and the third group of repeaters 351, 352, 353, and 354 to each other , SL7) is data bits EDB11, ODB11, EDB12, ODB12 from the first group repeaters 311, 312, 313, 314 to the third group repeaters 351, 352, 353, 354, respectively. Each can be delivered (DT: Data Delivery).

In addition, the second group of repeaters 321, 322, 323, and 324 and the fourth group of repeaters 361, 362, 363, and 364 generate a logic low level in response to the second power gating signal PGS2. The second group of signal lines SL2 connected to the output node of each of the four groups of repeaters 361, 362, 363, and 364 and the input node of each of the second group of repeaters 321, 322, 323, and 324. , SL4, SL6, SL8) can be plotted. Accordingly, the capacitance of each of the signal lines SL1 , SL3 , SL5 , and SL7 of the first group carrying the respective data bits EDB11 , ODB11 , EDB12 , and ODB12 may be reduced.

That is, the capacitance of the signal line SL13 may have a value (first value) corresponding to the serial connection of C1 and C2, and the capacitance of the signal line SL35 may correspond to the first value and the parallel connection of C3 and C4. It may have a value corresponding to the parallel connection of the value (second value), and the capacitance of the signal line (SL5) corresponds to the parallel connection of the second value and the value (third value) corresponding to the parallel connection of C5 and C6. It may have a corresponding value, and the capacitance of the signal line SL7 may have a value corresponding to the parallel connection of the third value and C7.

FIG. 14 illustrates data transferred to the page buffer circuit when the data transfer circuit operates as shown in FIG. 13 .

13 and 14, the even-numbered data bits EDB1 transmitted to the page buffer circuit 210 through signal lines SL1 and SL5 and the page buffer circuit (through signal lines SL3 and SL7) 210) may be asynchronous with each other.

FIG. 15 shows a first power gating signal and a second power gating signal when the data transfer circuit synchronizes even-numbered data bits and odd-numbered data bits as shown in FIG. 14 .

Referring to FIG. 15 , during the period T1 of the first operating mode, the second power gating signal PGS2 may have a logic low level, and during the first sub period T11 and the second sub period T12 The first power gating signal PGS1 may have a logic high level. Accordingly, the second group of signal lines are connected to the output nodes of the fourth group of repeaters 361, 362, 363, and 364 and the input nodes of the second group of repeaters 321, 322, 323, and 324, respectively. Each of SL2 , SL4 , SL6 , and SL8 may be floated. In addition, the first group of signal lines SL1, SL3, SL5, and SL7 transmit data bits EDB11, ODB11, EDB12, and ODB12 from each of the repeaters 311, 312, 313, and 314 of the first group. It may be asynchronously provided to each of the repeaters 351, 352, 353, and 354 of the third group.

16 illustrates the operation of the data transmission circuit of FIG. 10 in a second operating mode according to embodiments of the present invention.

Referring to FIG. 16 , in the second operation mode, the first power gating signal PGS1 has a logic low level and the second power gating signal PGS2 has a logic high level. Accordingly, the second group of signal lines SL2, SL4, and SL6 connecting the fourth group of repeaters 361, 362, 363, and 364 and the second group of repeaters 321, 322, 323, and 324 to each other , SL8) is data bits EDB21, ODB21, EDB22, ODB22 from each of the repeaters 361, 362, 363, and 364 of the fourth group to each of the repeaters 321, 322, 323, and 324 of the second group. Each can be delivered (DT: Data Delivery).

In addition, the repeaters 311, 312, 313, and 314 of the first group and the repeaters 351, 352, 353, and 354 of the third group control the logic low level in response to the first power gating signal PGS1. A first group of signal lines SL1 connected to the output node of each of the repeaters 311, 312, 313, and 314 of the first group and the input node of each of the repeaters 351, 352, 353, and 354 of the third group. , SL3, SL5, SL7) can be plotted. Accordingly, the capacitance of each of the signal lines SL2 , SL4 , SL6 , and SL8 of the second group carrying the respective data bits EDB21 , ODB21 , EDB22 , and ODB22 may be reduced.

FIG. 17 illustrates data transferred to the page buffer circuit when the data transfer circuit operates as shown in FIG. 16 .

16 and 17, the even data bits EDB2 transmitted to the data input/output circuit 250 through the signal lines SL2 and SL6 and the data input/output circuit (through the signal lines SL4 and SL8) 250) may be asynchronous with each other.

FIG. 18 shows a first power gating signal and a second power gating signal when the data transfer circuit synchronizes even-numbered data bits and odd-numbered data bits as shown in FIG. 17 .

Referring to FIG. 18 , during the period T2 of the second operation mode, the first power gating signal PGS1 may have a logic low level, and during the first sub period T21 and the second sub period T22 The second power gating signal PGS2 may have a logic high level. Accordingly, the signal lines of the first group are connected to the output node of each of the repeaters 311, 312, 313, and 314 of the first group and the input node of each of the repeaters 351, 352, 353, and 354 of the third group. Each of (SL1, SL3, SL5, SL7) can be floated. In addition, the signal lines SL2, SL4, SL6, and SL8 of the second group transmit data bits EDB21, ODB21, EDB22, and ODB22 from the repeaters 361, 362, 363, and 364, respectively, of the fourth group. It may be asynchronously provided to the repeaters 321, 322, 323, and 324 of the second group.

19 is a block diagram illustrating a nonvolatile memory device according to example embodiments.

19 shows an internal layout of the non-volatile memory device 500.

Referring to FIG. 19 , a semiconductor memory device 500 may include a memory cell array 510 including a plurality of memory planes 511 , 512 , 513 , and 514 . A peripheral area may be formed adjacent to one side of the memory cell array 510 . The peripheral area may include a data path logic 530 , a repeater area 540 , a first area 550 , a second area 560 , and the like. An interface region 520 may be formed adjacent to one side of the peripheral region.

A parallelizer 531 and a serializer 537 may be disposed in the data path logic 530 . The parallelizer 531 and the serializer 537 may collectively be referred to as SERDES, and may receive data from the input/output pads 525 and 527 included in the interface area 520, or may receive data from the input/output pads ( 525, 527) is a component for outputting data.

In an embodiment, the memory cell array 500 may be provided on the first semiconductor layer L1 of FIG. 3 and the peripheral area may be provided on the second semiconductor layer L2 of FIG. 3 .

Referring to FIG. 19 , data transfer from the repeater area 540 is indicated by arrows. First, when data is input through the data input/output pad in the interface area 220, the data is transferred to the data path logic 530. The data is processed by the server and passed to the repeater area 540. The repeater area 540 transfers data to a repeater 553 in the first area 550 or a repeater 563 in the second area 560 . The repeaters 553 and 563 transfer the received data to the memory planes 510 , 511 , 512 and 513 . Data from the memory planes 510 , 511 , 512 , and 513 may be transferred to the data input/output pad of the interface area 520 in a reverse direction of the above-described process.

20 is a block diagram illustrating a nonvolatile memory device according to example embodiments.

Referring to FIG. 20 , a nonvolatile memory device 600 includes a memory cell array 610 including a plurality of memory planes 611 , 612 , 613 , and 614 , a peripheral area, and an interface area 620 . The peripheral area is positioned between the memory cell array 600 and the interface area 620 and may include a data path logic area 630 , a first area 650 , a second area 660 , and the like.

The first region 650 may include a control circuit 651 and a repeater 653 , and the second region 660 may include a voltage generator 661 and a repeater 663 .

The interface area 620 may include sub-death areas 621 and 623 . A serializer and a parallelizer may be provided in the subdeath regions 621 and 623 . In FIG. 20 , arrows indicate data movement paths. That is, the data received through the input/output pads 625 and 627 in the interface area are processed by the serializer and parallelizer in the subdesk areas 621 and 623, and are processed by the repeaters through the signal lines SLs1 and SLs2, respectively. It is passed to (653, 663). The repeaters 653 and 663 may transfer the transferred data to the memory planes 611 , 612 , 613 and 614 .

The repeaters, the signal lines SLs1 and SLs2, and the repeaters 653 and 663 provided in the subdeath regions 621 and 623 may have the structure of FIG. 10 . Accordingly, repeaters connected to signal lines that do not transmit data may float the signal lines in response to the power gating signal, thereby reducing current consumption.

21 shows in detail the interface area of FIG. 20 according to embodiments of the present invention.

Referring to FIG. 21 , an interface area 620 may include sub-desk areas 621 and 623 . The input/output pads 625 and 627 may include data input/output pads 670 , 671 , 672 , 673 , 674 , 675 , 676 and 677 . Also, the subdeath areas 621 and 623 may include a plurality of subdeaths 680 , 681 , 682 , 683 , 684 , 685 , 686 and 687 .

Each of the subdesses 680, 681, 682, 683, 684, 685, 686, and 687 is provided in an area adjacent to the data input/output pads 670, 671, 672, 673, 674, 675, 676, and 677, It may be connected to a corresponding data input/output pad.

The subdeath regions 621 and 623 may include repeaters 691 and 692, respectively. Also, the interface area 20 may further include a repeater 693.

Among data input to the data input/output pads 670, 671, 672, and 673, data to be transferred to the memory planes 613 and 614 is processed by the adjacent subdesses 680, 681, 682, and 683. and can be transmitted to the repeater 692 through the repeater 693. The data is transferred to the memory planes 613 and 614 through the repeater 663 again.

Among the data input to the data input/output pads 670, 671, 672, and 673, data to be transferred to the memory planes 611 and 612 is processed by the subs 680, 681, 682, and 683 located adjacent to each other. and can be transmitted to the repeater 691. The data may be transferred to the memory planes 611 and 612 through the repeater 653 again.

22 is a flowchart illustrating a method of operating a nonvolatile memory device according to example embodiments.

1 to 18 and 22 , the nonvolatile memory device 50 receives a write command and write data from the memory controller 20 (S110).

The control circuit 220 includes a first group of repeaters (which are disposed between the data input/output circuit 250 and the page buffer 210 and connected to each other through the first group of signal lines SL1, SL3, SL5, and SL7). 311, 312, 313, 314 and a third group of repeaters 351, 352, 353, 354 are used to provide the write data to the memory cell array 100 through the page buffer, while the data input/output circuit A second group of repeaters 321, 322, 323, and 324 disposed between 250 and the page buffer 210 and connected to each other through second group signal lines SL2, SL4, SL6, and SL8 And the outputs of the repeaters 361, 362, 363, and 364 of the fourth group are set to a high impedance state to float the signal lines SL2, SL4, SL6, and SL8 of the second group (S120).

The nonvolatile memory device 50 receives a read command from the memory controller 20 (S130).

The control circuit 220 uses the second group of repeaters 321, 322, 323, and 324 and the fourth group of repeaters 361, 362, 363, and 364 to read data from the memory cell array 100. While providing to the data input/output circuit 250, the outputs of the first group repeaters 311, 312, 313, 314 and the third group repeaters 351, 352, 353, 354 are set to a high impedance state. Thus, the first group of signal lines SL1, SL3, SL5, and SL7 are floated (S140).

Accordingly, a data transmission circuit of a nonvolatile memory device according to embodiments of the present invention and a nonvolatile memory device including the same transfers data to a page buffer circuit through a first group of signal lines in a first operation mode, while second The second group of signal lines alternately disposed with the first group of signal lines are floated using the group of repeaters and the fourth group of repeaters, and reading is performed through the second group of signal lines in the second operation mode. While transferring data to the data input/output circuit, the signal lines of the first group are floated using the repeaters of the first group and the repeaters of the third group to reduce the capacitance of the signal lines passing data, thereby reducing current consumption. can

23 is a cross-sectional view illustrating a nonvolatile memory device according to example embodiments.

Referring to FIG. 23 , the nonvolatile memory device 2000 may have a chip to chip (C2C) structure. The C2C structure fabricates an upper chip (first chip) including a cell region (CELL) on a first wafer, and a lower chip (first chip) including a peripheral circuit region (PERI) on a second wafer different from the first wafer. 2), and then connecting the upper chip and the lower chip by a bonding method. For example, the bonding method may refer to a method of electrically connecting the bonding metal formed on the uppermost metal layer of the upper chip and the bonding metal formed on the uppermost metal layer of the lower chip to each other. For example, when the bonding metal is formed of copper (Cu), the bonding method may be a Cu-to-Cu bonding method, and the bonding metal may also be formed of aluminum (Al) or tungsten (W).

Each of the peripheral circuit area PERI and the cell area CELL of the nonvolatile memory device 2000 may include an external pad bonding area PA, a word line bonding area WLBA, and a bit line bonding area BLBA. there is.

The peripheral circuit region PERI includes a first substrate 2210, an interlayer insulating layer 2215, a plurality of circuit elements 2220a, 2220b, and 2220c formed on the first substrate 2210, and a plurality of circuit elements 2220a. , 2220b, 2220c) to include first metal layers 2230a, 2230b, and 2230c connected to each other, and second metal layers 2240a, 2240b, and 2240c formed on the first metal layers 2230a, 2230b, and 2230c. can In an embodiment, the first metal layers 2230a, 2230b, and 2230c may be formed of tungsten having a relatively high electrical resistivity, and the second metal layers 2240a, 2240b, and 2240c may be made of copper having a relatively low electrical resistivity. can be formed

In this specification, only the first metal layers 2230a, 2230b, and 2230c and the second metal layers 2240a, 2240b, and 2240c are shown and described, but are not limited thereto, and the second metal layers 2240a, 2240b, and 2240c At least one or more metal layers may be further formed. At least some of the one or more metal layers formed on the second metal layers 2240a, 2240b, and 2240c are made of aluminum having a lower electrical resistivity than copper forming the second metal layers 2240a, 2240b, and 2240c. can be formed

The interlayer insulating layer 2215 covers the plurality of circuit elements 2220a, 2220b, and 2220c, the first metal layers 2230a, 2230b, and 2230c, and the second metal layers 2240a, 2240b, and 2240c on the first substrate. 2210, and may include an insulating material such as silicon oxide, silicon nitride, or the like.

Lower bonding metals 2271b and 2272b may be formed on the second metal layer 2240b of the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 2271b and 2272b of the peripheral circuit area PERI may be electrically connected to the upper bonding metals 2371b and 2372b of the cell area CELL by a bonding method. , The lower bonding metals 2271b and 2272b and the upper bonding metals 2371b and 2372b may be formed of aluminum, copper, or tungsten.

The cell area CELL may provide at least one memory block. The cell region CELL may include a second substrate 2310 and a common source line 2320 . On the second substrate 2310, a plurality of word lines 2331, 2332, 2333, 2334, 2335, 2336, 2337, 2338, and 2330 are provided along the third direction D3 perpendicular to the upper surface of the second substrate 2310. ) can be stacked. String select lines and a ground select line may be disposed on upper and lower portions of the word lines 2330 , and a plurality of word lines 2330 may be disposed between the string select lines and the ground select line.

In the bit line bonding area BLBA, the channel structure CH extends in a direction VD perpendicular to the upper surface of the second substrate 2310 to form word lines 2330, string select lines, and ground select lines. can penetrate The channel structure CH may include a data storage layer, a channel layer, and a buried insulating layer, and the channel layer may be electrically connected to the first metal layer 2350c and the second metal layer 2360c. For example, the first metal layer 2350c may be a bit line contact, and the second metal layer 2360c may be a bit line. In one embodiment, the bit line 2360c may extend along the second direction D2 parallel to the upper surface of the second substrate 2310 .

In the example of FIG. 23 , an area where the channel structure CH and the bit line 2360c are disposed may be defined as a bit line bonding area BLBA. The bit line 2360c may be electrically connected to the circuit elements 2220c providing the page buffer 2393 in the peripheral circuit area PERI in the bit line bonding area BLBA. For example, the bit line 2360c is connected to upper bonding metals 2371c and 2372c in the peripheral circuit area PERI, and the upper bonding metals 2371c and 2372c are connected to circuit elements 2220c of the page buffer 2393. It may be connected to the connected lower bonding metals 2271c and 2272c.

In the word line bonding area WLBA, the word lines 2330 may extend along a second horizontal direction HD2 perpendicular to the first horizontal direction HD1 and parallel to the upper surface of the second substrate 310. , may be connected to a plurality of cell contact plugs 2341, 2342, 2343, 2344, 2345, 2346, 2347; 2340. The word lines 2330 and the cell contact plugs 2340 may be connected to each other at pads provided by extending different lengths from at least some of the word lines 2330 along the first horizontal direction HD1. . A first metal layer 2350b and a second metal layer 2360b may be sequentially connected to upper portions of the cell contact plugs 2340 connected to the word lines 2330 . The cell contact plugs 2340 are connected to peripheral circuits in the word line bonding area WLBA through the upper bonding metals 2371b and 2372b of the cell area CELL and the lower bonding metals 2271b and 2272b of the peripheral circuit area PERI. It may be connected to the area PERI.

The cell contact plugs 2340 may be electrically connected to circuit elements 2220b forming the address decoder or row decoder 2394 in the peripheral circuit area PERI. In one embodiment, the operating voltage of the circuit elements 2220b forming the row decoder 2394 may be different from the operating voltage of the circuit elements 2220c forming the page buffer 2393. For example, the operating voltage of the circuit elements 2220c forming the page buffer 2393 may be higher than the operating voltage of the circuit elements 2220b forming the row decoder 2394 .

A common source line contact plug 2380 may be disposed in the external pad bonding area PA. The common source line contact plug 2380 is formed of a conductive material such as metal, metal compound, or polysilicon, and may be electrically connected to the common source line 2320 . A first metal layer 2350a and a second metal layer 2360a may be sequentially stacked on the common source line contact plug 2380 . For example, an area where the common source line contact plug 2380, the first metal layer 2350a, and the second metal layer 2360a are disposed may be defined as an external pad bonding area PA.

Meanwhile, input/output pads 2205 and 2305 may be disposed in the external pad bonding area PA. A lower insulating film 2201 covering a lower surface of the first substrate 2210 may be formed under the first substrate 2210, and a first input/output pad 2205 may be formed on the lower insulating film 2201. The first input/output pad 2205 is connected to at least one of the plurality of circuit elements 2220a, 2220b, and 2220c arranged in the peripheral circuit area PERI through the first input/output contact plug 2203, and the lower insulating layer 2201 ) may be separated from the first substrate 2210. In addition, a side insulating layer may be disposed between the first input/output contact plug 2203 and the first substrate 2210 to electrically separate the first input/output contact plug 2203 from the first substrate 2210 .

An upper insulating layer 2301 covering the upper surface of the second substrate 2310 may be formed on the second substrate 2310, and second input/output pads 2305 may be disposed on the upper insulating layer 2301. The second input/output pad 2305 may be connected to at least one of the plurality of circuit elements 2220a, 2220b, and 2220c disposed in the peripheral circuit area PERI through the second input/output contact plug 2303. In one embodiment, the second input/output pad 2305 may be electrically connected to the circuit element 2220a.

Depending on the embodiment, the second substrate 2310 and the common source line 2320 may not be disposed in the region where the second input/output contact plug 2303 is disposed. Also, the second input/output pad 2305 may not overlap the word lines 2380 in the third direction D3. The second input/output contact plug 2303 is separated from the second substrate 2310 in a direction parallel to the top surface of the second substrate 2310, and penetrates the interlayer insulating layer 2315 of the cell region CELL to form the second input/output contact plug. It can be connected to pad 2305.

According to embodiments, the first input/output pad 2205 and the second input/output pad 2305 may be selectively formed. For example, the non-volatile memory device 2000 includes only the first input/output pad 2205 disposed on the first substrate 2201, or the second input/output pad 2205 disposed on the second substrate 2301 ( 2305) may be included. Alternatively, the memory device 2000 may include both the first input/output pad 2205 and the second input/output pad 2305 .

In each of the external pad bonding area PA and the bit line bonding area BLBA included in the cell area CELL and the peripheral circuit area PERI, the metal pattern of the uppermost metal layer exists in a dummy pattern, or The top metal layer may be empty.

In the nonvolatile memory device 2000, in the external pad bonding area PA, the cell area is formed on the uppermost metal layer of the peripheral circuit area PERI corresponding to the upper metal pattern 2372a formed on the uppermost metal layer of the cell area CELL. A lower metal pattern 2273a having the same shape as the upper metal pattern 2372a of the cell may be formed. The lower metal pattern 2273a formed on the uppermost metal layer of the peripheral circuit area PERI may not be connected to a separate contact in the peripheral circuit area PERI. Similarly, in the external pad bonding area PA, the upper metal layer of the cell area CELL corresponds to the lower metal pattern 2273a formed on the uppermost metal layer of the peripheral circuit area PERI. An upper metal pattern 2372a having the same shape as the lower metal pattern 2273a may be formed.

Lower bonding metals 2271b and 2272b may be formed on the second metal layer 2240b of the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 2271b and 2272b of the peripheral circuit area PERI may be electrically connected to the upper bonding metals 2371b and 2372b of the cell area CELL by a bonding method. .

In addition, in the bit line bonding area BLBA, the uppermost metal layer of the cell area CELL corresponds to the lower metal pattern 2252 formed on the uppermost metal layer of the peripheral circuit area PERI. An upper metal pattern 2392 having the same shape as the metal pattern 2252 may be formed. A contact may not be formed on the upper metal pattern 2392 formed on the uppermost metal layer of the cell region CELL.

The aforementioned word line voltages are applied to at least one memory block of the cell area CELL through the lower bonding metals 2271b and 2272b of the peripheral circuit area PERI and the upper bonding metals 2371b and 2372b of the cell area CELL. can be provided.

A page buffer circuit including the page buffer PB of FIG. 8 may be provided in the peripheral circuit area PERI by using at least a portion of the plurality of circuit elements 2220a, 2220b, and 2220c.

24 is a block diagram illustrating an electronic system including a semiconductor device according to example embodiments.

Referring to FIG. 24 , the electronic system 3000 may include a semiconductor device 3100 and a controller 3200 electrically connected to the semiconductor device 3100 . The electronic system 3000 may be a storage device including one or a plurality of semiconductor devices 3100 or an electronic device including the storage device. For example, the electronic system 3000 may be a solid state drive (SSD) device including one or a plurality of semiconductor devices 3100, a universal serial bus (USB), a computing system, a medical device, or a communication device. may be a device.

The semiconductor device 3100 may be a non-volatile memory device, for example, the non-volatile memory device described above with reference to FIGS. 1 to 21 . The semiconductor device 3100 may include a first structure 3100F and a second structure 3100S on the first structure 3100F. The first structure 3100F may be a peripheral circuit structure including a decoder circuit 3110 , a page buffer circuit 3120 , and a logic circuit 3130 . The second structure 3100S includes a bit line BL, a common source line CSL, word lines WL, first and second gate upper lines UL1 and UL2, and first and second gate lower lines. LL1 and LL2, and memory cell strings CSTR between the bit line BL and the common source line CSL.

In the second structure 3100S, each of the memory cell strings CSTR includes lower transistors LT1 and LT2 adjacent to the common source line CSL and upper transistors UT1 adjacent to the bit line BL. UT2), and a plurality of memory cell transistors MCT disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of lower transistors LT1 and LT2 and the number of upper transistors UT1 and UT2 may be variously modified according to embodiments.

In example embodiments, the upper transistors UT1 and UT2 may include string select transistors, and the lower transistors LT1 and LT2 may include ground select transistors. The lower gate lines LL1 and LL2 may be gate electrodes of the lower transistors LT1 and LT2, respectively. The word lines WL may be gate electrodes of the memory cell transistors MCT, and the upper gate lines UL1 and UL2 may be gate electrodes of the upper transistors UT1 and UT2, respectively.

In example embodiments, the lower transistors LT1 and LT2 may include a lower erase control transistor LT1 and a ground select transistor LT2 connected in series. The upper transistors UT1 and UT2 may include a string select transistor UT1 and an upper erase control transistor UT2 connected in series. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT1 performs an erase operation of erasing data stored in the memory cell transistors MCT using a gate induce drain leakage (GIDL) phenomenon. can be used for

The common source line CSL, the first and second lower gate lines LL1 and LL2, the word lines WL, and the first and second upper gate lines UL1 and UL2 have a first structure ( 3100F) may be electrically connected to the decoder circuit 3110 through first connection wires 3115 extending to the second structure 1100S. The bit lines BL may be electrically connected to the page buffer circuit 3120 through second connection lines 3125 extending from the first structure 3100F to the second structure 3100S.

In the first structure 3100F, the decoder circuit 1110 and the page buffer circuit 3120 may execute a control operation on at least one selected memory cell transistor among the plurality of memory cell transistors MCT. The decoder circuit 3110 and the page buffer circuit 3120 may be controlled by the logic circuit 3130 . The semiconductor device 3000 may communicate with the controller 3200 through the input/output pad 3101 electrically connected to the logic circuit 3130 . The input/output pad 3101 may be electrically connected to the logic circuit 3130 through an input/output connection wire 3135 extending from the first structure 3100F to the second structure 3100S.

The controller 3200 may include a processor 3210 , a NAND controller 3220 , and a host interface 1230 . According to example embodiments, the electronic system 3000 may include a plurality of semiconductor devices 3100 , and in this case, the controller 3200 may control the plurality of semiconductor devices 3000 .

The processor 3210 may control the overall operation of the electronic system 3000 including the controller 3200 . The processor 3210 may operate according to predetermined firmware and access the semiconductor device 3100 by controlling the NAND controller 3220 .

The NAND controller 3220 may include a NAND interface 3221 that processes communication with the semiconductor device 3100 . Through the NAND interface 3221, a control command for controlling the semiconductor device 3100, data to be written to the memory cell transistors MCT of the semiconductor device 1100, and memory cell transistors of the semiconductor device 3100 ( Data to be read from the MCT) may be transmitted. The host interface 3230 may provide a communication function between the electronic system 1000 and an external host. When a control command is received from an external host through the host interface 3230, the processor 1210 may control the semiconductor device 1100 in response to the control command.

A nonvolatile memory device or storage device according to an embodiment of the present invention may be mounted using various types of packages.

As described above, although it has been described with reference to the preferred embodiments of the present invention, those skilled in the art can make the present invention various without departing from the spirit and scope of the present invention described in the claims below. It will be understood that it can be modified and changed accordingly.

Claims (10)

As a data transmission circuit of a non-volatile memory device,
a plurality of first repeaters connected to a first circuit element disposed in a data input/output path of the non-volatile memory device;
a plurality of second repeaters connected to second circuit elements disposed apart from the first circuit elements in the data input/output path of the nonvolatile memory device; and
a plurality of signal lines connecting the plurality of first repeaters and the plurality of second repeaters and including a first group of signal lines and a second group of signal lines which are alternately disposed;
The plurality of first repeaters include a first group of repeaters activated in a first operation mode and a second group of repeaters activated in a second operation mode whose operation section does not overlap with the first operation mode,
The plurality of second repeaters are activated in the first operation mode, and a third group of repeaters connected to the first group of repeaters through the first group of signal lines and activated in the second operation mode, , a fourth group of repeaters connected to the second group of repeaters through the second group of signal lines,
the second group of signal lines are floating in the first mode of operation;
The first group of signal lines are floating in the second operating mode. According to claim 1,
In the second operation mode, the repeaters of the first group float output nodes connected to the signal lines of the first group in response to a first power gating signal, and the repeaters of the third group float the output nodes connected to the signal lines of the first group. Floating an input node connected to the first group of signal lines in response to a signal;
In the first operation mode, the repeaters of the second group float output nodes connected to the signal lines of the second group in response to a second power gating signal, and the repeaters of the fourth group float the output nodes connected to the signal lines of the second group in response to a second power gating signal. A data transmission circuit for floating an input node connected to the fourth group of signal lines in response to a signal. The method of claim 1, wherein each of the repeaters of the first group and each of the repeaters of the third group
a first inverter connected between the power supply voltage and the first node;
a first discharge transistor connected between the first node and a ground voltage and having a gate receiving a first power gating signal;
a precharge transistor connected between the power supply voltage and a second node corresponding to the output of the first inverter and having a gate receiving the first power gating signal;
a second inverter connected between the second node and an output node and connected between the power supply voltage and a third node; and
a second discharge transistor coupled between the third node and the ground voltage and having a gate receiving the first power gating signal;
In the first operation mode, the first power gating signal has a logic high level and is responsive to the first power gating signal.
The first discharge transistor connects the first node to the ground voltage;
The second discharge transistor connects the third node to the ground voltage. The method of claim 3, wherein the first inverter
a first PMOS transistor connected between the power supply voltage and the second node; and
A first NMOS transistor connected between the second node and the first node;
The second inverter
a second PMOS transistor connected between the power supply voltage and the output node; and
A second NMOS transistor connected between the output node and the third node;
In the second operation mode, the first power gating signal has a logic low level;
In response to the first power gating signal having the logic low level in the second operation mode,
The precharge transistor precharges the second node to the power supply voltage level;
The first NMOS transistor and the second NMOS transistor are turned off,
The second PMOS transistor is turned off in response to a voltage level of the second node to float the output node connected to a corresponding signal line among the signal lines of the first group. The method of claim 1, wherein each of the repeaters of the second group and each of the repeaters of the fourth group
a first inverter connected between the power supply voltage and the first node;
a first discharge transistor connected between the first node and a ground voltage and having a gate receiving a second power gating signal;
a precharge transistor connected between the power supply voltage and a second node corresponding to the output of the first inverter and having a gate receiving the second power gating signal;
a second inverter connected between the second node and an output node and connected between the power supply voltage and a third node; and
a second discharge transistor coupled between the third node and the ground voltage and having a gate receiving the second power gating signal;
In the second operation mode, the second power gating signal has a logic high level and is responsive to the second power gating signal.
The first discharge transistor connects the first node to the ground voltage;
The second discharge transistor connects the third node to the ground voltage. The method of claim 5, wherein the first inverter
a first PMOS transistor connected between the power supply voltage and the second node; and
A first NMOS transistor connected between the second node and the first node;
The second inverter
a second PMOS transistor connected between the power supply voltage and the output node; and
A second NMOS transistor connected between the output node and the third node;
In the first operation mode, the second power gating signal has a logic low level;
In response to the second power gating signal having the logic low level in the first operating mode,
The precharge transistor precharges the second node to the power supply voltage level;
The first NMOS transistor and the second NMOS transistor are turned off,
The second PMOS transistor is turned off in response to a voltage level of the second node to float the output node connected to a corresponding signal line among the signal lines of the second group. a memory cell array including a plurality of memory cells;
a page buffer circuit connected to the memory cell array through a plurality of bit lines;
a data input/output circuit for exchanging data with an external memory controller;
It is connected between the data input/output circuit and the page buffer circuit, provides the data provided from the data input/output circuit to the page buffer circuit in a first operation mode, and provides the data provided from the page buffer circuit in a second operation mode. a data transfer circuit that provides data to the data input/output circuit; and
a control circuit for controlling the page buffer circuit and the data transmission circuit;
The data transmission circuit transmits data among a plurality of signal lines included therein in each of the first operation mode and the second operation mode in response to a first power gating control signal and a second power gating signal from the control circuit. A non-volatile memory device that floats some signal lines that do not transmit. The method of claim 7, wherein the data transfer circuit
a plurality of first repeaters connected to the data input/output circuit;
a plurality of second repeaters connected to the page buffer circuit; and
a plurality of signal lines connecting the plurality of first repeaters and the plurality of second repeaters and including a first group of signal lines and a second group of signal lines that are alternately disposed;
The plurality of first repeaters include a first group of repeaters activated in the first operation mode and a second group of repeaters activated in a second operation mode;
The plurality of second repeaters are activated in the first operation mode, a third group of repeaters connected to the first group of repeaters through signal lines of the first group, and activated in the second operation mode, , a fourth group of repeaters connected to the second group of repeaters through the second group of signal lines,
the second group of signal lines are floated in the first mode of operation;
The non-volatile memory device of claim 1 , wherein the signal lines of the first group float in the second operation mode. According to claim 8,
In the second operation mode, the repeaters of the first group float output nodes connected to the signal lines of the first group in response to a first power gating signal, and the repeaters of the third group float the output nodes connected to the signal lines of the first group. Floating an input node connected to the first group of signal lines in response to a signal;
In the first operation mode, the repeaters of the second group float output nodes connected to the signal lines of the second group in response to a second power gating signal, and the repeaters of the fourth group float the output nodes connected to the signal lines of the second group in response to a second power gating signal. A non-volatile memory device for floating an input node connected to the fourth group of signal lines in response to a signal. The method of claim 7, wherein the page buffer circuit,
a plurality of page buffer units disposed along a first horizontal direction; and
A plurality of cache latches disposed spaced apart from the page buffer units along the first horizontal direction, respectively corresponding to the plurality of page buffer units, and commonly connected to a joint sensing node;
Each of the plurality of page buffer units includes a pass transistor connected to each sensing node and driven according to a pass control signal;
The memory cell array is disposed on a first semiconductor layer,
the page buffer circuit, the data input/output circuit, the data transmission circuit, and the control circuit are disposed on a second semiconductor layer;
The first semiconductor layer and the second semiconductor layer are disposed in a vertical direction.

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