KR20230068264A - Semiconductor memory device capable of controlling floating state of adjacent wl and operating method thereof - Google Patents

Abstract

A semiconductor memory device according to an embodiment of the present invention includes first and second memory cells storing multi-bit data; a first word line connected to the first memory cell; and a second word line connected to the second memory cell and adjacent to the first word line. The period in which the first word line voltage is applied to read data stored in the first memory cell includes a first voltage level applied to read first bit data among multi-bit data stored in the first memory cell. section; a second period having a second voltage level lower than the first voltage level; and a third period of applying a third voltage level higher than the second voltage level in order to read second bit data among the multi-bit data stored in the first memory cell. In the second period, the second word line may be in a floating state.

Description

Semiconductor memory device capable of controlling the floating state of an adjacent word line and its operating method

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device capable of adjusting a floating state of an adjacent word line and an operating method thereof.

Semiconductor memory devices can be largely classified into volatile memory devices and non-volatile memory devices. Volatile memory devices have high reading and writing speeds, but cannot retain stored data any longer when power supply is cut off. On the other hand, nonvolatile memory devices can retain stored data even if power supply is interrupted. A nonvolatile memory device may be used to retain data regardless of power.

A representative example of a nonvolatile memory device is a flash memory. Flash memory is widely used in user terminals such as computers and smart phones, and storage media such as USB and memory cards. Flash memory can store one or more multi-bit data in one memory cell. A flash memory storing multi-bit data requires as many select read voltage levels as the number of program states.

The flash memory may have a pre-emphasis period in the middle of changing the level of the read voltage in order to rapidly change the level of the selected read voltage. The flash memory requires a different pre-emphasis voltage level for each pre-emphasis period. Flash memory may require a large number of e-fuses to set the pre-emphasis voltage level. As a result, the flash memory may increase in chip size. In addition, the flash memory may increase post-processing time after wafer fab-out due to the complexity of the e-fuse circuit.

Republic of Korea Patent Publication No. 10-2021-0099657 (2021-08-12)

The present invention is to solve the above problems, and an object of the present invention is to quickly change the read voltage level of a selected word line without an e-fuse by enabling an adjacent word line to be in a floating state in a pre-emphasis section of a read operation. It is to provide a semiconductor memory device and an operating method thereof.

A semiconductor memory device according to an embodiment of the present invention includes first and second memory cells storing multi-bit data; a first word line connected to the first memory cell; and a second word line connected to the second memory cell and adjacent to the first word line. The period in which the first word line voltage is applied to read data stored in the first memory cell includes a first voltage level applied to read first bit data among multi-bit data stored in the first memory cell. section; a second period having a second voltage level lower than the first voltage level; and a third period of applying a third voltage level higher than the second voltage level in order to read second bit data among the multi-bit data stored in the first memory cell. In the second period, the second word line may be in a floating state.

As an embodiment, the period for applying the first word line voltage may further include a pre-pulse period for applying the pre-pulse voltage to the first word line before the first period. The period for applying the 1 word line voltage may further include a pre-emphasis period having a pre-emphasis voltage level lower than the first voltage level between the pre-pulse period and the first period. In the pre-emphasis period, the second word line may be in a floating state. A time for the second word line to be in a floating state in the pre-emphasis section may be set longer than a time in the pre-emphasis section.

As an example embodiment, the period in which the first word line voltage for reading data stored in the first memory cell is applied may further include one or more third word lines adjacent to the second word line. In the second period, the third word line may be in a floating state.

As an example embodiment, the pre-pulse voltage may be lower than the first voltage level. A read pass voltage of the same level may be applied to the second word line in the first and third periods. Read pass voltages of different levels may be applied to the second word line in the first and third periods. A time period in which the second word line is in a floating state in the second period may be set longer than a time period in the second period.

A semiconductor memory device according to another embodiment of the present invention includes first and second memory cells storing multi-bit data; a first word line connected to the first memory cell; a second word line connected to the second memory cell and adjacent to the first word line; a voltage generator for generating a second word line voltage supplied to the second word line; and a word line connection circuit connected between the voltage generator and the second word line. The period in which the first word line voltage is applied to read data stored in the first memory cell includes a first voltage level applied to read first bit data among multi-bit data stored in the first memory cell. section; a second period having a second voltage level lower than the first voltage level; and a third period of applying a third voltage level higher than the second voltage level in order to read second bit data among the multi-bit data stored in the first memory cell. In the second period, the second word line voltage provided to the second word line may be blocked.

As an embodiment, the second word line voltage may be blocked by turning off the voltage generator in the second period. In the second period, the word line connection circuit is turned off, so that the second word line voltage may be blocked. The first and second memory cells may be flash memory cells stacked in a direction perpendicular to the substrate. The period for applying the first word line voltage may further include a pre-pulse period for applying the pre-pulse voltage to the first word line before the first period. The period for applying the first word line voltage may further include a pre-emphasis period having a pre-emphasis voltage level lower than the first voltage level between the pre-pulse period and the first period. . In the pre-emphasis period, the second word line voltage provided to the second word line may be blocked. Read pass voltages of the same level or different levels may be applied to the second word line in the first and third periods.

The present invention relates to a method of operating a semiconductor memory device. The semiconductor memory device includes first and second memory cells storing multi-bit data; a first word line connected to the first memory cell; and a second word line connected to the second memory cell and adjacent to the first word line. The method of operating the semiconductor memory device may include applying a first voltage to the first word line to read first bit data among multi-bit data stored in the first memory cell; applying a second voltage lower than the first voltage; and applying a third voltage higher than the second voltage to the first word line in order to read second bit data among the multi-bit data stored in the first memory cell. In the step of applying the second voltage, the second word line may be in a floating state.

As an example embodiment, applying a pre-pulse voltage to the first word line before applying the first voltage; and applying a pre-emphasis voltage lower than the first voltage between the applying of the pre-pulse voltage and the applying of the first voltage. In the step of applying the pre-emphasis voltage, the second word line may be in a floating state.

In the semiconductor memory device according to an embodiment of the present invention, an adjacent word line is made to float in the middle of a read voltage level change, and the voltage level of the adjacent word line is reduced to a selected word line voltage due to capacitive coupling. may have a waveform similar to According to the present invention, the read voltage level can be quickly changed without using a separate e-fuse, and the setup time of the selected word line can be reduced.

1 is a block diagram showing a data storage device according to an embodiment of the present invention.
FIG. 2 is a block diagram illustrating the semiconductor memory device shown in FIG. 1 as an example.
FIG. 3 is a timing diagram illustrating a read operation of the semiconductor memory device shown in FIG. 2 .
4 is a block diagram showing a flash memory according to an exemplary embodiment of the present invention by way of example.
FIG. 5 is a circuit diagram showing a memory block BLK1 of the memory cell array shown in FIG. 4 as an example.
FIG. 6 is a circuit diagram showing cell strings STR1 to STR3 connected to one bit line BL1 and a common source line CSL among the cell strings of the memory block BLK1 shown in FIG. 5 . .
FIG. 7 is a diagram showing a threshold voltage distribution of the memory cell shown in FIG. 6 as an example.
FIG. 8 is a block diagram showing a word line connection circuit of the flash memory shown in FIG. 4 as an example.
FIG. 9 is a timing diagram exemplarily illustrating a read operation method when a switch signal is turned on in the word line connection circuit shown in FIG. 8 .
FIG. 10 is a timing diagram illustrating another embodiment of a read operation method when a switch signal is turned on in the word line connection circuit shown in FIG. 8 .
FIG. 11 is a timing diagram exemplarily illustrating a read operation method when a switch signal is OFF in the word line connection circuit shown in FIG. 8 .
FIG. 12 is a timing diagram exemplarily illustrating a read operation method when a switch signal is OFF in the word line connection circuit shown in FIG. 10 .
FIG. 13 is a timing diagram illustrating another embodiment of a read operation of the flash memory shown in FIG. 4 .

Hereinafter, embodiments of the present invention will be described clearly and in detail to the extent that those skilled in the art can easily practice the present invention.

1 is a block diagram showing a data storage device according to an embodiment of the present invention. Referring to FIG. 1 , a data storage device 1000 includes a semiconductor memory device 1100 and a memory controller 1200 . The semiconductor memory device 1100 and the memory controller 1200 may be connected through data input/output lines (IOs), control lines (CTRL), and power lines (VCC and VSS). The data storage device 1000 may store data in the semiconductor memory device 1100 under the control of the memory controller 1200 .

The semiconductor memory device 1100 includes a memory cell array 1110 and a peripheral circuit 1115 . The memory cell array 1110 includes a plurality of memory cells, and multi-bit data may be stored in each memory cell.

The memory cell array 1110 may include a plurality of memory blocks. Each memory block may have a planar 2D structure or a vertical 3D structure. The memory cell array 1110 may be positioned next to or above the peripheral circuit 1115 in terms of the design layout structure. A structure in which the memory cell array 1110 is positioned over the peripheral circuit 1115 is referred to as a cell on peripheral (COP) structure.

The peripheral circuit 1115 may generate internal power of various levels and provide word line voltages to word lines WL connected to the memory cell array 1110 . The peripheral circuit 1115 may receive commands, addresses, and data from the memory controller 1200 and store data in the memory cell array 1110 through an internal operation. Also, the peripheral circuit 1115 may read data stored in the memory cell array 1110 and provide the data to the memory controller 1200 .

The peripheral circuit 1115 may include a word line connection circuit 1120 and a voltage generator 1150 . The word line connection circuit 1120 may be positioned between the word line WL and the voltage generator 1150 and may provide the word line voltage generated by the voltage generator 1150 to the word line WL. When the word line connection circuit 1120 is turned off, the word line WL may be in a floating state. The voltage generator 1150 may receive external power through power lines VCC and VSS and generate internal power necessary for internal operations such as reading or writing.

FIG. 2 is a block diagram illustrating the semiconductor memory device shown in FIG. 1 as an example. Referring to FIG. 2 , the selected word line WLs is connected to the selected memory cell MCs, and the adjacent word line WLs±1 is connected to the adjacent memory cell MCs±1. Here, MCs±1 means MCs+1 or MCs-1. And WLs±1 may mean WLs+1 or WLs-1. Also, WLs±1 may mean one adjacent word line group. For example, WLs±1, WLs±2, and WLs±3 may be included in one adjacent word line group.

A coupling capacitance (Cap) may exist between the selected word line WLs and the adjacent word line WLs±1. The coupling capacitance Cap may increase as the spacing between word lines narrows. Also, the coupling capacitance Cap may increase as a voltage change between word lines increases.

The word line connection circuit 1120 may connect the memory cell array 1110 and the voltage generator 1150 through the word line WL. The selected word line connection circuit 1121 may be connected to the selected word line WLs, and the adjacent word line connection circuit 1122 may be connected to the adjacent word line WLs±1. The word line connection circuit 1120 may include a switch circuit capable of disconnecting the word line connection by a switch signal SW. When the connection of the adjacent word line WLs±1 is blocked by the switch signal SW, the adjacent word line WLs±1 may be in a floating state.

The voltage generator 1150 may include a selected word line voltage generator 1151 and an adjacent word line voltage generator 1152 . The selected word line voltage generator 1151 is connected to the selected word line connection circuit 1121 and may provide the selected word line voltage V_WLs to the selected word line WLs. The adjacent word line voltage generator 1152 is connected to the adjacent word line connection circuit 1122 and may provide the adjacent word line voltage V_WLs±1 to the adjacent word line WLs±1. The voltage generator 1150 may be turned off by the voltage generating signal VG. When the adjacent word line voltage generator 1152 is turned off by the voltage generation signal VG, the adjacent word line WLs±1 may be in a floating state.

In the semiconductor memory device 1100 , adjacent word lines WLs±1 may be connected or disconnected by a switch signal SW or a voltage generation signal VG provided to the word line connection circuit 1120 or the voltage generator 1150 . there is. A state in which the adjacent word lines WLs±1 are connected is referred to as a biased state, and a state in which the adjacent word lines WLs±1 are connected is referred to as a floating state.

FIG. 3 is a timing diagram illustrating a read operation of the semiconductor memory device shown in FIG. 2 . 3 shows word line voltage levels provided to a selected word line WLs and an adjacent word line WLs±1 to read multi-bit data stored in the selected memory cells MCs.

In FIG. 3 , the adjacent word line (WLs±1) may be WLs+1 or WLs−1. Also, adjacent word lines may be formed as one adjacent word line group. For example, WLs±1, WLs±2, ..., WLs±k (where k is a natural number greater than or equal to 3) may be included in the adjacent word line group. Hereinafter, the adjacent word line will be described as WLs+1 or WLs-1.

In FIG. 3, (A) shows a state in which adjacent word lines (WLs±1) are connected, that is, a biased state. (B) shows a state in which the adjacent word line (WLs±1) is blocked, that is, a floating state.

Referring to the biased state (A) of FIG. 3 , the section in which the selected word line voltage is applied to the selected word line WLs includes first to third sections. In the first period T1 to T2, a first voltage level Vs1 is applied to read first bit data among multi-bit data. In the second period T2 to T4, a second voltage level Vs2 lower than the first voltage level Vs1 is applied. In the third period (T4 to T5), a third voltage level (Vs3) higher than the second voltage level (Vs2) is applied to read the second bit data. During a period in which the select read voltage is applied to the select word line WLs, the read pass voltage Vrdps may be provided to the adjacent word line WLs±1.

A voltage level of the selected word line WLs may be Vs1 at a time point T1. At the time point T2, Vs1 may be changed to Vs2. The time taken for the voltage level of the selected word line WLs to change from Vs1 to Vs2 may be T3-T2. As the distance between the selected word line WLs and the adjacent word line WLs±1 decreases, the coupling capacitance Cap between the selected word line WLs and the adjacent word line WLs±1 may increase. Also, as the voltage difference between Vs1 and Vs2 increases, the coupling capacitance Cap between the selected word line WLs and the adjacent word line WLs±1 may increase. That is, as the voltage difference between Vrdps and Vs1 (Vrdps-Vs1) is larger than the voltage difference between Vrdps and Vs2 (Vrdps-Vs2), the selected word line (WLs) is more affected by the coupling capacitance (Cap). can

The semiconductor memory device 1100 may block an adjacent word line connection circuit (refer to FIG. 2 1122 ) or turn off an adjacent word line voltage generator (refer to FIG. 2 1152 ). At this time, the adjacent word line (WLs±1) may be in a floating state (B) in the second period (T2 to T4). When the adjacent word line WLs±1 is in a floating state, the voltage level of the adjacent word line WLs±1 may have a waveform similar to that of the selected word line voltage due to capacitive coupling. Due to this, the selected word line WLs may be less affected by the coupling capacitance Cap.

When the adjacent word line (WLs±1) is in the floating state (B) in the second period (T2 to T4), the point at which the voltage level of the selected word line (WLs) changes from Vs1 to Vs2 is fast from T3 to T3'. It can be. Also, a word line setup time for changing the voltage level of the selected word line WLs from Vs1 to Vs3 may be reduced from T4-T2 to T4'-T2.

The semiconductor memory device 1100 may make the adjacent word line WLs±1 a floating state. When the adjacent word line (WLs±1) is in a floating state, the voltage level of the adjacent word line (WLs±1) has a waveform similar to that of the selected word line voltage (V_WLs) due to capacitive coupling. can have The selected word lines WLs may be less affected by the coupling capacitance Cap. According to the present invention, the voltage level setup time of the selected word lines WLs can be reduced during a read operation.

The semiconductor memory device 1100 according to an embodiment of the present invention may be applied to a nonvolatile memory (NVM) in which multi-bit data is stored and a read voltage level is changed during a read operation. Nonvolatile memory (NVM) may include FRAM, PRAM, MRAM, RRAM, flash memory, and the like. Hereinafter, the operating method of the semiconductor memory device 1100 described in FIGS. 1 to 3 will be described in detail, taking a vertical NAND flash memory (VNAND) having a vertical stacked structure among nonvolatile memories as an example.

4 is a block diagram showing a flash memory according to an exemplary embodiment of the present invention by way of example. Referring to FIG. 4 , a flash memory 2100 includes a memory cell array 2110, a word line connection circuit 2120, a page buffer circuit 2130, a data input/output circuit 2140, a voltage generator 2150, and control logic. (2160).

The memory cell array 2110 may include memory blocks 2111 (BLK1 to BLKn) for storing user data and an e-fuse memory block 2112 (BLKe) for storing e-fuse data. The eFuse data stored in the eFuse memory block 2112 may be loaded into the control logic 2160 when the flash memory 2100 is booted. The eFuse data may be used to set various operating voltages or operating times of the flash memory 2100 .

The memory block BLK1 may be formed in a direction perpendicular to the substrate. A gate electrode layer and an insulation layer may be alternately deposited on the substrate. An information storage layer may be formed between the gate electrode layer and the insulating layer. The information storage layer may include a tunnel insulation layer, a charge trap layer, and a blocking insulation layer. A gate electrode film of the memory block BLK1 may be connected to a ground selection line GSL, a plurality of word lines WL, and a string selection line SSL.

The word line connection circuit 2120 may connect the memory cell array 2110 and the voltage generator 2150 through the word line WL. The word line connection circuit 2120 may receive an operating voltage such as a select read voltage (Vrd) or a read pass voltage (Vrdps) from the voltage generator 2150 and may provide a word line voltage. The selected word line connection circuit 2121 may be connected to the selected word line WLs, and the adjacent word line connection circuit 2122 may be connected to the adjacent word line WLs-1.

The word line connection circuit 2120 may receive the switch signal SW from the control logic 2160 . The adjacent word line connection circuit 2122 may be connected or disconnected by the switch signal SW. When the adjacent word line connection circuit 2122 is blocked, the adjacent word line WLs-1 may be in a floating state.

The page buffer circuit 2130 may be connected to the memory cell array 2110 through the bit line BL. The page buffer circuit 2130 may temporarily store data to be programmed into the selected page or data read from the selected page. The page buffer circuit 2130 may include a page buffer connected to each bit line. Each page buffer may include a first latch for storing first bit data and a second latch for storing second bit data while reading multi-bit data.

The input/output circuit 2140 may be internally connected to the page buffer circuit 2130 through a data line and externally connected to a memory controller (refer to FIG. 1 , 1200) through the input/output lines IO1 to IOn. The input/output circuit 2140 may receive program data from the memory controller 1200 during a program operation and provide read data to the memory controller 1200 during a read operation.

The voltage generator 2150 may receive power from the memory controller 1200 and generate a word line voltage required to read or write data. The word line voltage may be provided to the word line through the word line connection circuit 2120 . The voltage generator 2150 may generate a program voltage Vpgm provided to selected word lines WLs (selected WL) and a pass voltage Vpass provided to unselected WL (WLu) during a program operation. there is. Also, the voltage generator 2150 may generate the selected read voltage Vrd provided to the selected word line WLs and the read pass voltage Vrdps provided to the unselected word line WLu during a read operation.

The voltage generator 2150 may include a select read voltage generator 2151 and a read pass voltage generator 2152 . The select read voltage generator 2151 may generate the select read voltage Vrd provided to the select word line WLs. The read pass voltage generator 2152 may generate a read pass voltage Vrdps provided to an adjacent word line WLs-1 during a read operation. Here, the read pass voltage Vrdps may be a voltage sufficient to turn on memory cells connected to the unselected word line WLu during a read operation.

The control logic 2160 performs programming, reading, and erasing of the flash memory 2100 using commands CMD, addresses ADDR, and control signals CTRL provided from the memory controller 1200. You can control the action. The address ADDR may include a block selection address BLK_ADDR for selecting a memory block and a page selection address for selecting one page. The control logic 2160 may include an eFuse register 2161 .

The e-fuse register 2161 may generate parameters for controlling various bias conditions of the operating voltage generated by the voltage generator 2150. The eFuse register 2161 may generate a parameter signal using eFuse data provided from the eFuse memory block 2112 during a booting operation of the flash memory 2100 . In addition, the e-fuse register 2161 may generate a switch signal SW provided to the word line connection circuit 2120 and a voltage generation signal VG provided to the voltage generator 2150 using e-fuse data. there is.

The flash memory 2100 may provide a first voltage level to the selected word line WLs to read first bit data among multi-bit data and then provide a second voltage level to read second bit data. there is. That is, the flash memory 2100 may change the read voltage level provided to the selected word line from the first voltage level to the second voltage level during a read operation.

The flash memory 2100 may provide the switch signal SW to the adjacent word line connection circuit 2122 to make the adjacent word line WLs-1 into a floating state when the read voltage is changed. When the read voltage is changed in the floating state, an adjacent word line may have a voltage waveform similar to that of the selected word line voltage due to capacitive coupling. Accordingly, according to the present invention, the selected word line WLs can be less affected by the coupling capacitance Cap. Meanwhile, the flash memory 2100 may turn off the read pass voltage generator 2152 to make the adjacent word line WLs-1 a floating state.

FIG. 5 is a circuit diagram showing a memory block BLK1 of the memory cell array shown in FIG. 4 as an example. In the memory block BLK1, a plurality of cell strings STR1 to STR3 are formed between the bit lines BL1 to BL3 and the common source line CSL. Each cell string includes a string select transistor SST, a plurality of memory cells MC1 to MC9, and a ground select transistor GST.

The string selection transistor (SST) is connected to the string selection line (SSL1 to SSL3). The ground selection transistor GST is connected to ground selection lines (GSL1 to GSL3). The string select transistor SST is connected to bit lines BL1 to BL3, and the ground select transistor GST is connected to a common source line (CSL).

A plurality of memory cells MC1 to MC9 are connected to a plurality of word lines WL1 to WL9. The first word line WL1 may be positioned on the ground select lines GSL1 to GSL3. The first memory cells MC1 at the same height from the substrate may be connected to the first weed line WL1. Fourth memory cells MC4 at the same height from the substrate may be connected to the fourth weed line WL4. Similarly, the sixth memory cells MC6 and the ninth memory cells MC9 may be connected to the sixth word line WL6 and the ninth word line WL9, respectively.

A selection word line WL5 may be positioned between the fourth word line WL4 and the sixth word line WL6 . Select memory cells MC5 located at the same height from the substrate may be connected to the select word line WL5. Here, the fourth word line WL4 and the sixth word line WL6 may be adjacent word lines, and the fourth memory cell MC4 and the sixth memory cell MC6 may be adjacent memory cells.

FIG. 6 is a circuit diagram showing cell strings STR1 to STR3 connected to one bit line BL1 and a common source line CSL among the cell strings of the memory block BLK1 shown in FIG. 5 . . Each of the cell strings STR1 to STR3 includes string select transistors SST selected by string select lines SSL1 to SSL3 and a plurality of memory cells MC1 to MC1 to control by a plurality of word lines WL1 to WL9. MC9), and ground selection transistors GST selected by the ground selection lines GSL1 to GSL3.

The fifth word line WL5 may be a selected word line (WLs; selected WL). The fifth memory cells MC5 may be selected memory cells MCs (selected MCs). The first to fourth word lines WL1 to WL4 may be unselected word lines WLu (unselected WL). The first to fourth memory cells MC1 to MC4 are unselected memory cells MCu (unselected MC). Similarly, the sixth to ninth word lines WL6 to WL9 may be unselected word lines, and the sixth to ninth memory cells MC6 to MC9 may be unselected memory cells.

A program may be performed in the direction of the fourth word line WL4 based on the selected word line WLs. This programming method is referred to as a top to bottom (T2B) program. A program may be performed in the direction of the sixth word line WL6 based on the selected word line WLs. Such a program method is referred to as a B2T (bottom to top) program. The program may be performed in both directions of the fourth word line WL4 and the sixth word line WL6 based on the selected word lines WLs.

Based on the selected word lines WLs, the fourth word line WL4 or the sixth word line WL6 to be programmed before and after is referred to as an adjacent word line. Fourth memory cells MC4 and sixth memory cells MC6 connected to adjacent word lines are adjacent memory cells.

During a read operation, the selected read voltage Vrd may be provided to the selected word lines WLs, and the read pass voltage Vrdps may be provided to the non-selected word lines WLu (WL1 to WL4 and WL6 to WL9). The selected word lines WLs may be adjacent to adjacent word lines WL4 and WL6, and the adjacent word lines WL4 and WL6 may be adjacent to next adjacent word lines WL3 and WL7, respectively. Adjacent memory cells MC4 and MC6 may be connected to adjacent word lines WL4 and WL6, respectively. Next adjacent memory cells MC3 and MC7 may be connected to the next adjacent word lines WL3 and WL7 .

FIG. 7 is a diagram showing a threshold voltage distribution of the memory cell shown in FIG. 6 as an example. The horizontal axis represents the threshold voltage (Vth), and the vertical axis represents the number of cells. 7 shows an example in which 3-bit data is stored in one memory cell. A 3-bit memory cell may have one of eight states (E0, P1 to P7) according to the threshold voltage distribution. Here, E0 represents an erase state, and P1 to P7 represent program states.

During a read operation, the selected read voltages Vrd1 to Vrd7 may be provided to the selected word lines WLs, and the pass voltage Vps or the read pass voltage Vrdps may be provided to the non-selected word lines WLu. The pass voltage Vps or the read pass voltage Vrdps may be a voltage sufficient to turn on the memory cell.

The first select read voltage Vrd1 has a voltage level between the erase state E and the first program state P1, and the second select read voltage Vrd2 corresponds to the first and second program states P1 and P2. In this way, the seventh select read voltage Vrd7 has a voltage level between the sixth and seventh program states P6 and P7.

When the first select read voltage Vrd1 is applied, the memory cells in the erase state E0 become on cells, and the memory cells in the first to seventh program states P1 to P7 become off cells. (off cell). When the second select read voltage Vrd2 is applied, the memory cells in the erase state E0 and the first program state P1 become on-cell, and the second to seventh program states P2 to The memory cell having P7) becomes an off cell. In this way, when the seventh select read voltage Vrd7 is applied, the memory cells in the erase state E0 and the first to sixth program states P1 to P6 become on cells. A memory cell in the seventh program state P7 becomes an off cell.

FIG. 8 is a block diagram showing a word line connection circuit of the flash memory shown in FIG. 4 as an example. Referring to FIG. 8 , the word line connection circuit 2120 may be connected to the memory cells MC5 and MC4 through the block select transistor BLK_TR. Here, the block select transistor BLK_TR may be controlled by the block select address BLK_ADDR. The block selection address BLK_ADDR may be provided from the address ADDR shown in FIG. 4 .

The word line connection circuit 2120 includes a selected word line connection circuit 2121 and an adjacent word line connection circuit 2122 . The select word line connection circuit 2121 is connected between the select read voltage generator 2151 and the block select transistor BLK_TR, and transmits the select read voltage Vrd to the select word lines WLs (eg WL5) during a read operation. can provide The adjacent word line connection circuit 2122 is connected between the read pass voltage generator 2152 and the block select transistor BLK_TR, and is connected to the adjacent word line WLs-1 (eg WL4) during a read operation to read pass voltage Vrdps. ) can be provided.

The selected word line connection circuit 2121 and the adjacent word line connection circuit 2122 may include a switch circuit (S/W) and a decoder (DEC). A resistance component and a capacitance component may exist in a signal line to which the switch circuit (S/W) and the decoder (DEC) are connected. One or more switch circuits (S/W) and decoders (DEC) may exist, and their positions and order may be variously changed.

The switch circuit (S/W) of the adjacent word line connection circuit 2122 may include various switches connected between the read pass voltage generator 2152 and the block select transistor BLK_TR. For example, the switch circuit (S/W) may be simply composed of a switch transistor. The switch transistor may be turned on or off according to the switch signal SW applied to the gate. When the switch circuit (S/W) of the adjacent word line connection circuit 2122 is turned off, the adjacent word line WL4 is cut off from the read pass voltage generator 2152 and enters a floating state.

The decoder DEC of the adjacent word line connection circuit 2122 may include various word line activation circuits (WL activation circuits) connected between the read pass voltage generator 2152 and the block select transistor BLK_TR. For example, the decoder DEC is a row decoder for activating one or more word lines among word lines connected to the memory block BLK1, or providing word line voltage to one or more word lines. It may be a power line decoder for The decoder DEC may inactivate the adjacent word line WL4 and put it into a floating state according to the switch signal SW.

During a read operation, the flash memory 2100 may provide the selected read voltage Vrd to the selected word lines WLs and the read pass voltage Vrdps to the unselected word lines WLu. When the voltage level of the selected word line WL5 is changed during a read operation, the flash memory 2100 puts the adjacent word line WL4 in a floating state using the switch signal SW and the voltage generation signal VG. can The flash memory 2100 may reduce a time for changing a read voltage of the selected word line WL5 or a time for setting up a word line voltage by using capacitive coupling.

FIG. 9 is a timing diagram exemplarily illustrating a read operation method when a switch signal is turned on in the word line connection circuit shown in FIG. 8 . In the timing diagram, the horizontal axis is time (T) and the vertical axis is voltage (V). 9 shows a case where the switch signal SW is ON. When the switch signal SW is ON, it means that the adjacent word line WLs±1 is connected to the read pass voltage generator 2152.

Referring to FIG. 9, the read operation of the flash memory (refer to FIG. 4, 2100) is performed in a pre-pulse period (T0 to T1) based on the read voltage provided to the selected word line (WLs). 1 pre-emphasis period (first pre-emphasis period, T1~T2), 1st read voltage period (Vs1, T2~T3), 2nd pre-emphasis period (T3~T4), And it can be divided into the second read voltage interval (Vs2, T4 ~ T5) and the like. After the second read voltage period, the pre-emphasis period and the read voltage period may be repeated.

In the pre-pulse period T0 to T1, the pre-pulse voltage Vpre may be applied to the selected word line WLs. Here, the pre-pulse voltage may be a pass read voltage (Vrdps) or a higher or lower voltage. For example, during a read operation, the flash memory 2100 may apply the pass read voltage Vrdps to all word lines and then apply the select read voltage to the selected word lines WLs.

A first pre-emphasis voltage Va may be applied to the first pre-emphasis period T1 to T2. The first pre-emphasis voltage Va may be lower than the pre-pulse voltage Vpre by a predetermined voltage level. Before applying the pre-pulse voltage Vpre and applying the first voltage level Vs1, the flash memory 2100 generates a difference between the two voltages Vpre in order to reduce the setup time of the selected word lines WLs. A first pre-emphasis voltage Va higher than -Vs1) may be applied. Here, Va > Vpre - Vs1.

A read voltage having a first voltage level Vs1 may be applied to the first read voltage period T2 to T3. The first voltage level Vs1 may be any one of the first to seventh selected read voltages (Vrd1 to Vrd7 in FIG. 7 ). For example, the first voltage level Vs1 may be the seventh select read voltage Vrd7. The first voltage level Vs1 may be higher than the first pre-emphasis voltage Va and lower than the pre-pulse voltage Vpre. In the first read voltage period T2 to T3, first bit data among the multi-bit data stored in the selected memory cells MCs may be stored in a latch of the page buffer circuit 2130 (see FIG. 4 ).

A second pre-emphasis voltage Vb may be applied to the second pre-emphasis period T3 to T4. The second pre-emphasis voltage Vb may be lower than the first pre-emphasis voltage Va. In order to reduce the setup time of the selected word line WLs, the flash memory 2100 applies two voltages before applying the first voltage level Vs1 and applying the read voltage of the second voltage level Vs2. A second pre-emphasis voltage Vb greater than the difference (Vs1-Vs2) may be applied. Here, Vb > Vs1 - Vs2.

A read voltage of the second voltage level Vs2 may be applied to the second read voltage period T4 to T5. The second voltage level Vs2 may be any one of the first to sixth selected read voltages (Vrd1 to Vrd6 in FIG. 7 ). For example, the second voltage level Vs2 may be the fourth select read voltage Vrd4. The second voltage level Vs2 may be higher than the second pre-emphasis voltage Vb and lower than the first voltage level Vs1. In the second read voltage period T4 to T5, second bit data among the multi-bit data stored in the selected memory cells MCs may be stored in a latch of the page buffer circuit (see FIG. 4 , 2130).

The flash memory 2100 turns on the word line connection circuit (see FIG. 8 2120) and the voltage generator (see FIG. 8 2150) in the first and second pre-emphasis periods T1 to T2 and T3 to T4 ( ON) signal can be provided. When an ON signal is provided, as shown in FIG. 9 , the flash memory 2100 may apply a biased read pass voltage (biased Vrdps) to an adjacent word line (WLs±1) during a read operation. .

In the first pre-emphasis period (T1 to T2), when the read pass voltage (Vrdps) is applied to the adjacent word line (WLs±1), the pre-pulse voltage (Vpre) during the time Ta-T1 It can be changed to the pre-emphasis voltage (Va). Likewise, in the second pre-emphasis intervals T3 to T4, the first voltage level Vs1 may be changed to the second pre-emphasis voltage Vb for a predetermined period of time.

FIG. 10 is a timing diagram illustrating another embodiment of a read operation method when a switch signal is turned on in the word line connection circuit shown in FIG. 8 . Referring to FIG. 10 , a flash memory (refer to FIG. 4 2100 ) may provide a waveform similar to a voltage applied to a selected word line WLs to an adjacent word line WLs±1 during a read operation.

A voltage level of Vc may be applied to the first pre-emphasis period T1 to T2. A Vd voltage level higher than the Vc voltage level may be applied to the first read voltage period T2 to T3. A Ve voltage level lower than the Vd voltage level may be applied to the second pre-emphasis sections T3 to T4. A Vf voltage level higher than the Ve voltage level may be applied to the second read voltage period T4 to T5. The voltage level of Vc to Vf applied to the adjacent word line WLs±1 is a voltage sufficient to turn on the memory cell connected to the unselected word line WLu, and may be higher than the pass voltage (Vps in FIG. 7 ). .

According to the reading method of the flash memory 2100 shown in FIG. 10 , coupling capacitance between the selected word line WLs and an adjacent word line WLs±1 can be reduced. The flash memory 2100 may reduce the change time of the read voltage of the selected word lines WLs by reducing the effect of the coupling capacitance during a read operation. In addition, when the voltage level of the selected word line WLs rapidly changes, a hot carrier injection (HCI) phenomenon in an adjacent memory cell can be effectively reduced.

In the first pre-emphasis period (T1 to T2), when the Vc voltage level is applied to the adjacent word line (WLs±1), the first pre-emphasis voltage is applied at the pre-pulse voltage (Vpre) during the time period Tb-T1. It can be changed to the persistence voltage (Va). The word line voltage change time Tb-T1 of FIG. 10 may be shorter than the word line voltage change time Ta-T1 of FIG. 9 .

The read method of the flash memory 2100 shown in FIG. 10 may be performed by the eFuse register 2161 of the control logic 2160 shown in FIG. 4 . The e-fuse register 2161 may set a parameter so that the voltage of the adjacent word line WLs±1 is similar to the voltage waveform of the selected word line WLs. The e-fuse register 2161 may provide a voltage generation signal VG to the read pass voltage generator 2152 or a switch signal SW to an adjacent word line connection circuit 2122 . The eFuse register 2161 may receive data for parameter setting from the eFuse block 2112 during a booting operation of the flash memory (refer to FIG. 4 2100 ).

FIG. 11 is a timing diagram exemplarily illustrating a read operation method when a switch signal is OFF in the word line connection circuit shown in FIG. 8 . When the switch signal SW is OFF, the adjacent word line WLs±1 may be in a floating state. Referring to FIG. 11 , in the first and second pre-emphasis periods T1 to T2 and T3 to T4, the adjacent word lines WLs±1 may be in a floating state.

In the first pre-emphasis period T1 to T2, the voltage level of the selected word line WLs may change from the pre-pulse voltage Vpre to the first pre-emphasis voltage Va. In this case, the voltage of the adjacent word line WLs±1 may have a waveform similar to that of the selected word line WLs due to capacitive coupling. In the first pre-emphasis period T1 to T2, a voltage difference between the selected word line WLs and the adjacent word line WLs±1 may be maintained similarly to that in the pre-pulse period T0 to T1.

Similarly, in the second pre-emphasis period T3 to T4, the voltage level of the selected word line WLs may change from the first voltage level Vs1 to the second pre-emphasis voltage Vb. At this time, the voltage of the adjacent word line WLs±1 may be affected by capacitive coupling. At T4, when the switch signal SW is turned on, the adjacent word line WLs±1 may become the pass read voltage Vrdps again.

In the first pre-emphasis period T1 to T2, when the adjacent word line WLs±1 is in a floating state, the first pre-emphasis voltage ( Va) can be changed. The word line voltage change time Tc-T1 of FIG. 11 may be shorter than the word line voltage change time Ta-T1 of FIG. 9 .

The flash memory 2100 may increase the floating time of the adjacent word line WLs±1 in the first and second pre-emphasis periods T1 to T2 and T3 to T4. For example, the floating time of the adjacent word lines WLs±1 may be increased to T1 to T2' or T3 to T4', respectively.

The adjustment of the floating time of the adjacent word line (WLs±1) in the first and second pre-emphasis periods (T1 to T2) is performed by setting parameters of the eFuse register 2161 of the control logic (see FIG. 4, 2160). can be done through The control logic 2160 may adjust the off-time of the adjacent word line voltage generator 2152 or the off-time of the adjacent word line connection circuit 2122 using a parameter set in the e-fuse register 2161 .

FIG. 12 is a timing diagram exemplarily illustrating a read operation method when a switch signal is OFF in the word line connection circuit shown in FIG. 10 . When the switch signal SW is OFF, the adjacent word line WLs±1 may be in a floating state. Referring to FIG. 12 , in the first and second pre-emphasis periods T1 to T2 and T3 to T4, the adjacent word lines WLs±1 may be in a floating state.

As described in FIG. 10 , the flash memory (refer to FIG. 4 2100 ) may provide a waveform similar to a voltage applied to the selected word line WLs to an adjacent word line WLs±1 during a read operation. That is, a Vd voltage level lower than the Vrdps voltage level may be applied to the first read voltage period T2 to T3. A Vf voltage level lower than the Vd voltage level may be applied to the second read voltage period T4 to T5. The Vd and Vf voltage levels may be higher than the pass voltage (see FIG. 7, Vps).

In the first pre-emphasis period T1 to T2, when the switch signal SW is turned off, the adjacent word line WLs±1 is in a floating state. At this time, when the voltage level of the selected word line WLs changes from the pre-pulse voltage Vpre to the first pre-emphasis voltage Va, the voltage of the adjacent word line WLs±1 is capacitively coupled. Therefore, it may have a waveform similar to that of the voltage of the selected word line WLs. In the first pre-emphasis period T1 to T2, a voltage difference between the selected word line WLs and the adjacent word line WLs±1 may be maintained similarly to that in the pre-pulse period T0 to T1.

In the second pre-emphasis period T3 to T4, when the switch signal SW is turned off, the adjacent word line WLs±1 is in a floating state. At this time, when the voltage of the selected word line is changed from the first voltage level (Vs1) to the second pre-emphasis voltage (Vb), the voltage of the adjacent word line (WLs±1) is reduced to the selected word line due to capacitive coupling. It may have a waveform similar to the voltage of (WLs). In the second pre-emphasis period T3 to T4, a voltage difference between the selected word line WLs and the adjacent word line WLs±1 may be maintained similarly to the first read voltage period T2 to T3. .

According to the reading method of the flash memory 2100 shown in FIG. 12 , coupling capacitance between the selected word line WLs and an adjacent word line WLs±1 can be reduced. Accordingly, the flash memory 2100 may reduce a time for changing a read voltage of the selected word line WLs or a time for setting up the word line. In addition, the flash memory 2100 can effectively reduce the occurrence of the HCI phenomenon in an adjacent memory cell when the voltage level of the selected word line WLs rapidly changes.

In the first pre-emphasis period (T1 to T2), when the adjacent word line (WLs±1) is in a floating state, the first pre-emphasis voltage ( Va) can be changed. The word line voltage change time Td-T1 of FIG. 12 may be shorter than the word line voltage change time Ta-T1 of FIG. 9 . The flash memory 2100 may increase the floating time of the adjacent word line WLs±1 in the first and second pre-emphasis periods T1 to T2 and T3 to T4. For example, the floating time of the adjacent word lines WLs±1 may be increased to T1 to T2' or T3 to T4', respectively.

The read method of the flash memory 2100 shown in FIG. 12 uses a capacitive coupling phenomenon, so it can be performed regardless of the e-fuse register 2161 of the control logic 2160 shown in FIG. 4 . The flash memory 2100 may generate a pre-emphasis effect in the floated adjacent word line WLs±1 by using a capacitive coupling phenomenon. According to the present invention, the pre-emphasis effect can be obtained without setting the parameters of the e-fuse register 2161 or having a circuit or element. In addition, the present invention can reduce the setup time of the selected word lines WLs.

FIG. 13 is a timing diagram illustrating another embodiment of a read operation of the flash memory shown in FIG. 4 . 13 shows an example in which the switch signal SW is both OFF and ON in the read voltage change period.

In the pre-pulse period T0 to T1, the read pass voltage Vrdps may be provided to the selected word line WLs. In this case, the first pre-pulse voltage Vpre1 lower than the read pass voltage Vrdps may be provided to the adjacent word line WLs±1. The flash memory 2100 may apply a first pre-pulse voltage Vpre1 lower than the read pass voltage Vrdps. Due to the difference in setup time between the selected word line (WLs) and the adjacent word line (WLs±1) in the pre-pulse period (T0 to T1), overshoot occurs in the adjacent word line (WLs±1). ) can be prevented from occurring. In addition, the flash memory 2100 prevents overshoot of an adjacent word line (WLs±1) due to a couple-up phenomenon between the selected word line (WLs) and the next adjacent word line (WLs+2). ) can also be suppressed.

In the first pre-emphasis period T1 to T2, the switch signal SW is in an off state, and the adjacent word line WLs±1 may be in a floating state. During the first pre-emphasis period T1 to T2, the flash memory 2100 applies a waveform similar to the voltage applied to the selected word line WLs to the adjacent word line WLs±1 by using capacitive coupling. can be provided to In the second pre-emphasis period T3 to T4, the switch signal SW is in an on state, and a biased voltage Ve may be provided to the adjacent word line WLs±1.

In the first pre-emphasis period (T1 to T2), when the adjacent word line (WLs±1) is in a floating state, the first pre-emphasis is generated at the first pre-pulse voltage (Vpre1) during the time period Te-T1. It can be changed to voltage (Va). The word line voltage change time (Te-T1) of FIG. 13 may be shorter than the word line voltage change time (Ta-T1) of FIG. 9 .

The flash memory 2100 according to an embodiment of the present invention may put the adjacent word line WLs±1 into a floating state or a bias state in a pre-emphasis period through a switch signal SW. The flash memory 2100 may generate a pre-emphasis effect in the floating adjacent word line WLs±1 by using a capacitive coupling phenomenon. According to the present invention, a pre-emphasis effect can be obtained and the setup time of the selected word lines WLs can be reduced without a separate parameter setting of the e-fuse register 2161 or a circuit or device.

The foregoing are specific examples for carrying out the present invention. In addition to the above-described embodiments, the present invention will also include embodiments that can be simply or easily changed in design. In addition, the present invention will also include techniques that can be easily modified and practiced using the embodiments. Therefore, the scope of the present invention should not be limited to the above-described embodiments and should not be defined, and should be defined by those equivalent to the claims of this invention as well as the claims to be described later.

Claims (10)

In the semiconductor memory device,
first and second memory cells that store multi-bit data;
a first word line connected to the first memory cell; and
A second word line connected to the second memory cell and adjacent to the first word line;
A period in which a first word line voltage for reading data stored in the first memory cell is applied,
a first period for applying a first voltage level to read first bit data among multi-bit data stored in the first memory cell;
a second period having a second voltage level lower than the first voltage level; and
a third period for applying a third voltage level higher than the second voltage level in order to read second bit data among the multi-bit data stored in the first memory cell;
The semiconductor memory device of claim 1 , wherein the second word line is in a floating state during the second period. According to claim 1,
The period in which the first word line voltage is applied is
and a pre-pulse period for applying a pre-pulse voltage to the first word line before the first period. According to claim 2,
The period in which the 1 word line voltage is applied is
and a pre-emphasis section having a pre-emphasis voltage level lower than the first voltage level between the pre-pulse section and the first section. According to claim 3,
The semiconductor memory device of claim 1 , wherein the second word line is in a floating state during the pre-emphasis period. According to claim 4,
The semiconductor memory device of claim 1 , wherein a time for the second word line to be in a floating state in the pre-emphasis section is set to be longer than a time in the pre-emphasis section. According to claim 2,
Further comprising one or more third word lines adjacent to the second word line;
The semiconductor memory device of claim 1 , wherein the third word line is in a floating state during the second period. According to claim 2,
The semiconductor memory device of claim 1 , wherein the pre-pulse voltage is lower than the first voltage level. According to claim 1,
The semiconductor memory device of claim 1 , wherein a read pass voltage of the same level is applied to the second word line in the first and third periods. According to claim 1,
The semiconductor memory device of claim 1 , wherein read pass voltages of different levels are applied to the second word line in the first and third periods. According to claim 1,
The semiconductor memory device of claim 1 , wherein a time period for the second word line to be in a floating state in the second period is set to be longer than a time period of the second period.

Images