KR20230068241A - Semiconductor device - Google Patents

Abstract

The present invention provides a semiconductor device. The semiconductor device includes a substrate, an epitaxial layer provided on the substrate and including a depression from which a portion of an upper surface is removed, a channel layer provided in the depression, a barrier layer provided on the channel layer in the depression, the A passivation layer covering an upper surface of the barrier layer and an upper surface of the epitaxial layer, and a source contact, a drain contact, and a gate contact provided between them disposed on the barrier layer.

Description

Semiconductor device {Semiconductor device}

The present invention relates to a semiconductor device, and more particularly, to providing a buried GaN HEMT (High Electron Mobility Transistor) device.

Nitride semiconductor is a direct transition type semiconductor that can realize various wavelengths from visible light to ultraviolet light, and has thermal stability, chemical stability, saturated electron velocity, and large energy bandgap, making it a light emitting device in the visible light region and an electronic device for high power and high frequency. The scope of application is expanding.

In particular, in the case of high-power GaN HEMT devices, semi-insulating epitaxy process technology and device isolation process to block leakage current between unit devices or large-area devices to reduce leakage current toward the substrate skill is required

An object to be solved by the present invention is to provide a semiconductor device capable of simultaneously reducing leakage current in the direction of a substrate of a GaN HEMT device and leakage current between devices.

The problem to be solved by the present invention is not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

In order to achieve the object to be solved, a semiconductor device according to embodiments of the present invention includes a substrate, an epitaxial layer provided on the substrate and including a depression portion from which an upper surface is partially removed, and a channel layer provided in the depression portion. , a barrier layer provided on the channel layer in the depression, a protective layer covering the upper surface of the barrier layer and the upper surface of the epitaxial layer, and A source contact, a drain contact, and a gate contact provided between them are included on the barrier layer.

Specific details of other embodiments are included in the detailed description and drawings.

According to embodiments of the present invention, when manufacturing a HEMT device, the epitaxial layer serves as a substrate capable of growing a buried channel layer and at the same time has a high resistance characteristic, thereby blocking leakage current. In addition, since the channel layer is provided in the depression formed in the epitaxial layer, an effect of blocking leakage current in the direction of the substrate and between devices can be obtained.

1 is a cross-sectional view illustrating a semiconductor device according to example embodiments.
FIG. 2A is an energy band graph of FIG. 1 cut along the line A-A'.
FIG. 2B is an energy band graph of FIG. 1 cut along line BB′.
3A to 3G are cross-sectional views illustrating a method of manufacturing a semiconductor device according to example embodiments.

In order to sufficiently understand the configuration and effects of the present invention, the present invention will be described in detail by describing preferred embodiments of the present invention with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and may be implemented in various forms and various modifications and changes may be applied. However, it is provided to complete the disclosure of the present invention through the description of the present embodiments, and to completely inform those skilled in the art of the scope of the invention to which the present invention belongs. In the accompanying drawings, for convenience of explanation, the size of the components is shown larger than the actual size, and the ratio of each component may be exaggerated or reduced. In addition, terms used in the embodiments of the present invention may be interpreted as meanings commonly known to those skilled in the art unless otherwise defined.

For convenience of explanation, the upper direction in the drawing will be referred to as the upper side, and the surface facing the upper direction in the drawing will be referred to as the upper side. In addition, the downward direction in the drawing will be referred to as the bottom, and the surface facing the downward direction in the drawing will be referred to as the bottom face. In addition, a direction from left to right in the drawing will be referred to as a horizontal direction.

In this specification, when a layer is referred to as being 'on' another layer, it may be directly formed on the top surface of another layer or a third layer may be interposed therebetween.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

1 is a cross-sectional view of a semiconductor device according to example embodiments.

Referring to FIG. 1 , a semiconductor device according to embodiments includes a substrate 10, an epitaxial layer 20, a channel layer 40, a barrier layer 50, a protective layer 60, source and drain contacts ( 70), and a gate contact 80.

The substrate 10 may be, for example, a sapphire substrate or a silicon carbide (SiC) substrate.

An epitaxial layer 20 may be provided on the substrate 10 . The epitaxial layer 20 may be formed by an epitaxial process. The epitaxial layer 20 may be formed of a material having excellent lattice matching with the substrate 10 and high resistance. The epitaxial layer 20 may have a concave portion 21 in which a portion of an upper surface is removed. The epitaxial layer 20 may include AlN, for example. The epitaxial layer 20 may have a thickness of about 0.5 μm to about 2 μm.

The channel layer 40 may be provided in the depression 21 of the epitaxial layer 20 . The channel layer 40 may form a heterojunction with the epitaxial layer 20 . The channel layer 40 may include GaN, for example. The thickness of the channel layer 40 may be about 50 nm to about 300 nm.

The barrier layer 50 may be disposed on the channel layer 40 within the depression 21 of the epitaxial layer 20 . The barrier layer 50 may form a heterojunction with the channel layer 40 . The barrier layer 50 may include AlGaN, for example. The barrier layer 50 may have a thickness of about 15 nm to about 25 nm.

The protective layer 60 may be disposed on the upper surface of the epitaxial layer 20 and the upper surface of the barrier layer 50 . The protective layer 60 may be formed by plasma enhanced chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD). The protective layer 60 may include, for example, an insulating film such as SiO2, SiNx, or Al2O3. The protective layer 60 may have a thickness of about 50 nm to about 100 nm.

The source and drain contacts 70 may be spaced apart from each other on the barrier layer 50 . The source and drain contacts 70 may form an ohmic junction with the barrier layer 50 . The source and drain contacts 70 may include at least one of Ti, Al, and Au.

A gate contact 80 may be disposed on the barrier layer 50 between the source and drain contacts 70 . The gate contact 80 may form a Schottky junction with the barrier layer 50 . The gate contact 80 may include at least one of Ni, Pd, and Au.

2A and 2B are energy band graphs for explaining characteristics of semiconductor devices according to example embodiments.

Referring to FIG. 2A , a high energy barrier may be formed between the channel layer 40 and the epitaxial layer 20 having characteristics of high heat dissipation and high resistance. Electrons in the channel layer 40 may not be able to move in the vertical direction due to the high energy band of the epitaxial layer 20 . Accordingly, leakage current from the channel layer 40 toward the substrate 10 (ie, the vertical direction) can be minimized.

Referring to FIG. 2B , an epitaxial layer 20 having high heat dissipation and high resistance is provided to surround the channel layer 40 . The epitaxial layer 20 may be present on both sides of the channel layer 40 and a high energy barrier may be formed between the epitaxial layer 20 and the channel layer 40 . Due to the high energy band of the epitaxial layer 20, electrons in the channel layer 40 may not be able to move in the horizontal direction. Accordingly, leakage current between adjacent channel layers can be minimized.

3A to 3G are cross-sectional views illustrating a method of manufacturing a semiconductor device according to example embodiments.

Referring to FIG. 3A , a substrate 10 may be prepared. An epitaxial layer 20 may be formed on the substrate 10 by an epitaxial process. In one example, an AlN epitaxial layer may be formed by an epitaxial process, and the crystallinity of the epitaxial layer 20 is about 250 arcsec in the [002] direction and about 450 arcsec in the [102] direction. can have The epitaxial layer 20 may have a thickness of about 0.5 μm or more.

Referring to FIG. 3B , a mask layer 30 may be formed on the epitaxial layer 20 . The mask layer 30 may be formed by a method such as CVD or PVD. The mask layer 30 may be, for example, SiO2 or SiNx. The mask layer 30 may have a thickness of about 50 nm to about 300 nm.

Referring to FIG. 3C , a depression 21 in which a portion of the upper surface of the epitaxial layer 20 is removed may be formed by an etching process using the mask layer 30 as a mask. The etching process may be, for example, a dry etching process. The depth of the depression 21 may be about 100 nm to about 300 nm. In the case of a unit device, the size of the width of the depression 21 may be about 5 μm to about 30 μm. In the case of a large-area multi-device, the size of the width of the depression 21 may be about 0.5 mm to about 3 mm.

After the etching process of FIG. 3C , a surface treatment process may be performed on the epitaxial layer 20 . The surface treatment process may use, for example, TMAH (Tetramethylammonium hydroxide).

Referring to FIG. 3D , the channel layer 40 and the barrier layer 50 may be sequentially formed in the depression 21 . A GaN layer may be formed as the channel layer 40 using an epitaxy process. Since the channel layer 40 is grown on the AlN epitaxial layer 20 in a heterojunction form, a minimum thickness (about 50 nm) for two-dimensional growth may be required due to stress caused by a difference in lattice constant. In addition, it can be grown within a maximum thickness (about 300 nm) in consideration of leakage current generated during manufacturing of a semiconductor device.

Referring to FIG. 3E , a protective layer 60 may be formed on the epitaxial layer 20 and the barrier layer 50 using a deposition process.

Referring to FIG. 3F , source and drain contacts 70 may be formed on the barrier layer 50 . In detail, after forming a mask of the source and drain contacts 70 region using photolithography, a portion of the protective layer 60 may be etched by an etching process. Subsequently, source and drain contacts 70 may be formed by depositing a metal material in ohmic contact with the barrier layer 50 .

Referring to FIG. 3G , a gate contact 80 may be formed on the barrier layer 50 between the source and drain contacts 70 . In detail, after forming the source and drain contacts 70, a mask of the gate contact 80 region may be formed using a photolithography process, and a portion of the protective layer 60 may be etched through an etching process. Subsequently, a gate contact 80 may be formed by depositing a metal material that makes Schottky contact with the barrier layer 50 .

Although the embodiments of the present invention have been described with reference to the accompanying drawings, those skilled in the art can implement the present invention in other specific forms without changing its technical spirit or essential features. You will understand that there is Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

10: substrate
20: epitaxial layer
30: mask layer
40: channel layer
50: barrier layer
60: protective layer
70: source and drain contacts
80: gate contact

Claims (1)

Board;
an epitaxial layer provided on the substrate and including a recessed portion from which a portion of an upper surface is removed;
a channel layer provided within the recessed portion;
a barrier layer provided on the channel layer within the depression;
a protective layer covering an upper surface of the barrier layer and an upper surface of the epitaxial layer; and
A semiconductor device comprising a source contact, a drain contact, and a gate contact provided between them disposed on the barrier layer.

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