KR20230068234A - Nonvolatile memory device having multi-stack memory block and method for operating thereof - Google Patents

Abstract

A nonvolatile memory device having a multi-stack memory block and an operating method thereof are disclosed. A nonvolatile memory device includes a memory cell array divided into a plurality of memory stacks arranged in a vertical direction and a control circuit performing a channel voltage equalization operation of the plurality of memory stacks, and an inter-stack region between the plurality of memory stacks. are disposed, and channel holes are passed through word lines of each of the plurality of memory stacks. The control circuit provides inter-stack word lines with some of the word lines adjacent to the inter-stack regions among the word lines of each of the plurality of memory stacks, and inter-stack the inter-stack word lines according to the size of the channel hole of the inter-stack word lines. Setup times for applying a pass voltage to word lines or recovery times for applying a ground voltage are differently controlled.

Description

Nonvolatile memory device having multi-stack memory block and method for operating the same

The present invention relates to semiconductor memory devices, and more particularly, to a non-volatile memory device having a multi-stack memory block equalizing channel potential by differently controlling operation times of word lines adjacent to an inter-stack region between memory stacks. and a method of operating a non-volatile memory device.

A system using semiconductor chips is a dynamic random access memory (DRAM) used as an operation memory or main memory of the system to store data or instructions used by a host in the system and/or to perform a computational operation. ) is widely used, and a storage device is used as a storage medium. The storage device includes non-volatile memory. As the capacity of a storage device increases, the number of memory cells and word lines stacked on a nonvolatile memory substrate increases, and the number of bits of data stored in a memory cell also increases. In order to improve the storage capacity and integration of a memory, a nonvolatile memory device in which memory cells are stacked in a three-dimensional structure, such as a 3D NAND flash memory device, has been studied.

In a 3D NAND flash memory device, a memory cell array including a plurality of cell strings each disposed between a plurality of bit lines and a source line in a vertical direction with respect to a substrate may be formed in a multi-stack memory block structure. The multi-stack memory block structure may include memory stacks having gate lines corresponding to word lines stacked and an inter-stack portion between the memory stacks. In this case, the inter-stack region may be formed to be relatively longer than the length between the gate lines of the memory stack due to a manufacturing process. Since the inter-stack region is included in the channel region of each cell string, equalizing channel potential or channel voltage is required in the inter-stack region as well. If channel potentials are not uniform in the inter-stack region, there is a problem in that hot carrier injection (HCI) occurs when channel boosting by word lines occurs in a program operation or a read operation.

Accordingly, a method of equalizing a channel potential of an inter-stack region between memory stacks is required.

An object of the present invention is to provide a nonvolatile memory device having a multi-stack memory block and an operating method thereof, which equalize channel potentials by differently controlling operation times of word lines adjacent to an inter-stack region between memory stacks.

A nonvolatile memory device according to embodiments of the present invention includes a memory cell array including a plurality of cell strings in which a plurality of memory cells are respectively disposed between a plurality of bit lines and a source line in a vertical direction, the memory cell array is divided into a plurality of memory stacks disposed in the vertical direction, inter-stack regions are disposed between the plurality of memory stacks, and word lines of the plurality of memory cells are arranged in each of the plurality of memory stacks in the vertical direction. direction, and a channel hole passes through the word lines of each of the plurality of memory stacks; and providing some of the word lines adjacent to the inter-stack regions among the word lines of each of the plurality of memory stacks as inter-stack word lines, and according to sizes of the channel holes of the inter-stack word lines, the and a control circuit performing channel voltage equalization of the plurality of memory stacks while differently controlling set-up points in which pass voltages are applied to inter-stack word lines, wherein the pass voltage is such that the plurality of memory cells are always turned on. set to a voltage that can be

A method of operating a nonvolatile memory device according to embodiments of the present invention includes a memory cell array including a plurality of cell strings in which a plurality of memory cells are disposed between a plurality of bit lines and a source line in a vertical direction, respectively. Dividing into memory stacks, inter-stack regions are disposed between the plurality of memory stacks, word lines of the plurality of memory cells are stacked in the vertical direction on each of the plurality of memory stacks, and the plurality of memory cells are stacked in the vertical direction. A channel hole passes through the word lines of each of the memory stacks of; providing some of the word lines adjacent to the inter-stack regions among the word lines of each of the plurality of memory stacks as inter-stack word lines; and performing a channel voltage equalization operation of the plurality of memory stacks while differently controlling setup times for applying pass voltages to the inter-stack word lines according to sizes of the channel holes of the inter-stack word lines. , the pass voltage is set to a voltage at which the plurality of memory cells are always turned on.

A method of operating a nonvolatile memory device according to embodiments of the present invention includes a memory cell array including a plurality of cell strings in which a plurality of memory cells are disposed between a plurality of bit lines and a source line in a vertical direction, respectively. Dividing into memory stacks, inter-stack regions are disposed between the plurality of memory stacks, word lines of the plurality of memory cells are stacked in the vertical direction on each of the plurality of memory stacks, and the plurality of memory cells are stacked in the vertical direction. A channel hole passes through the word lines of each of the memory stacks of; providing some of the word lines adjacent to the inter-stack regions among the word lines of each of the plurality of memory stacks as inter-stack word lines; and performing a channel voltage equalization operation of the plurality of memory stacks while differently controlling recovery time points for applying recovery voltages to the inter-stack word lines according to sizes of the channel holes of the inter-stack word lines. .

A nonvolatile memory device and a method of operating the nonvolatile memory device according to the present invention improve program operation performance and read operation performance by equalizing channel potential by differently controlling operation times of word lines adjacent to an inter-stack region between memory stacks. can improve

1 is a block diagram illustrating a memory system according to example embodiments.
2 is a block diagram illustrating a memory device according to example embodiments.
3 is a diagram illustrating the structure of a memory device according to example embodiments.
4 is a perspective view illustrating a memory block according to an exemplary embodiment of the present invention.
FIG. 5 is a cross-sectional view illustrating an embodiment of an inter-stack area included in the memory block of FIG. 4 .
FIG. 6 shows an equivalent circuit diagram of the memory block of FIG. 4 .
FIG. 7 illustratively illustrates a threshold voltage distribution when write data is written to the memory cells shown in FIG. 6 .
8 is a diagram illustrating program bias conditions according to embodiments of the present invention.
9A and 9B are diagrams for explaining program operations according to embodiments of the present invention.
FIG. 10 is a cross-sectional view illustrating another exemplary embodiment of an inter-stack area included in the memory block of FIG. 4 .
11 is a diagram for explaining a program operation according to embodiments of the present invention.
12 is a flowchart illustrating a method of operating a nonvolatile memory device according to example embodiments.
FIG. 13 is a diagram explaining a read operation related to threshold voltage distribution of the memory cells shown in FIG. 7 .
14 is a diagram for explaining a read operation according to example embodiments.
15 is a diagram illustrating a memory block according to another exemplary embodiment of the present invention.
16 is a block diagram illustrating a system including a nonvolatile memory device according to example embodiments.

1 is a block diagram illustrating a memory system 100 according to example embodiments.

Referring to FIG. 1 , a memory system 100 may include a memory controller 110 and at least one memory device 120 . In this embodiment, a number of conceptual hardware configurations included in the memory system 100 are shown, but are not limited thereto and other configurations are possible. The memory controller 110 controls the memory device 120 to write data into the memory device 120 in response to a write request from the host, or data stored in the memory device 120 in response to a read request from the host. The memory device 120 may be controlled to read .

In some embodiments, the memory system 100 may be an internal memory embedded in an electronic device. For example, the memory system 100 may be an embedded universal flash storage (UFS) memory device, an embedded multi-media card (eMMC), or a solid state drive (SSD). In some embodiments, the memory system 100 may be an external memory that is detachable from an electronic device. For example, the memory system 100 includes a UFS memory card, Compact Flash (CF), Secure Digital (SD), Micro Secure Digital (Micro-SD), Mini Secure Digital (Mini-SD), extreme Digital (xD) and It may include at least one of Memory Stick.

The memory device 120 may perform an erase, program, or read operation under the control of the memory controller 110 . The memory device 120 receives a command CMD and an address ADDR from the memory controller 110 through an input/output line. It transmits and receives data (DATA) for a program operation or a read operation with the memory controller 110 . Also, the memory device 120 may receive the control signal CTRL through the control line. The memory device 120 may include a memory cell array 122 and a control circuit 124 .

The memory cell array 122 includes a plurality of memory blocks, and each of the plurality of memory blocks may include a plurality of memory cells, for example, the plurality of memory cells may be flash memory cells. Hereinafter, embodiments of the present invention will be described in detail taking a case in which a plurality of memory cells are NAND flash memory cells as an example. The memory cell array 122 may include a three-dimensional memory cell array including a plurality of cell strings, which will be described in detail with reference to FIGS. 3 to 6 .

A three-dimensional memory cell array is monolithically formed on at least one physical level of memory cell arrays having an active region disposed over a silicon substrate and circuitry associated with operation of the memory cells formed on or within the substrate. do. The term "monolithic" means that the layers of each level of the array are stacked directly on top of the layers of each lower level of the array. In one embodiment according to the technical idea of the present invention, a 3D memory cell array includes cell strings arranged in a vertical direction such that at least one memory cell is located above another memory cell. The at least one memory cell may include a charge trap layer. U.S. Patent Publication No. 7,679,133, U.S. Patent Publication No. 8,553,466, U.S. Patent Publication No. 8,654,587, U.S. Patent Publication No. 8,559,235, and U.S. Patent Application Publication No. 2011/0233648 disclose that a three-dimensional memory array has a plurality of Those reciting suitable configurations for a three-dimensional memory array that is made up of levels and where wordlines and/or bitlines are shared between the levels, incorporated herein by reference.

As shown in FIG. 4 , a memory block in the memory cell array 122 may include a first memory stack ST1 and a second memory stack ST2 stacked in a vertical direction with respect to the substrate. An inter-stack portion (INT-ST) may be included between the first memory stack ST1 and the second memory stack ST2. According to embodiments, a memory block may include three or more memory stacks ST1 , ST2 , and ST3 as shown in FIG. 15 .

The control circuit 124 adjusts the threshold voltages of memory cells of a certain page disposed adjacent to the same position from the substrate of the 3D memory cell array 122 according to a program command from the memory controller 110 to have a plurality of target states. Program operations can be performed. The program operation is performed by program loops based on the voltage increment of the program voltage, and each of the program loops may include a program period and a verification period. The control circuit 124 may perform a read operation on a selected memory cell among memory cells included in the 3D memory cell array 122 according to a read command from the memory controller 110 .

The control circuit 124 may include an inter-stack word line manager 129 . The inter-stack word line manager 129 may store channel hole profile information about some of word lines adjacent to the inter-stack regions INT-ST defined in the manufacturing process of the nonvolatile memory device 120 . The inter-stack word line management unit 129 may include some word lines adjacent to the inter-stack regions INT-ST among word lines of each of a plurality of memory stacks in the memory cell array 122 based on the channel hole profile information. may be determined as inter-stack word lines.

According to an embodiment, the inter-stack word line management unit 129 controls setup times for applying pass voltages to the inter-stack word lines differently according to the size of the channel hole of the inter-stack word lines, and controls the channels of the plurality of memory stacks. A voltage equalization operation may be performed. When the inter-stack word line management unit 129 sets up the inter-stack word lines to pass voltages, first sets up inter-stack word lines having a large channel hole size and sets up inter-stack word lines having a small channel hole size later. can do.

Depending on the embodiment, the inter-stack word line management unit 129 controls recovery time points for applying the recovery voltage to the inter-stack word lines differently according to the size of the channel hole of the inter-stack word lines, and channels of the plurality of memory stacks. A voltage equalization operation may be performed. When the inter-stack word line management unit 129 recovers the inter-stack word lines with the recovery voltage, the inter-stack word line having a small channel hole size is recovered first, and the inter-stack word line having a large channel hole size is recovered later. can do.

In the example of FIG. 1 , the inter-stack word line manager 129 is shown as being included in the control circuit 124, but the inter-stack word line manager 129 according to an embodiment of the present disclosure is outside the control circuit 124. It may be implemented as a separate component in

2 is a block diagram illustrating a memory device 120 according to example embodiments. 2 shows a schematic configuration of a flash memory device. Note that the configuration of the flash memory device shown in FIG. 2 is provided as an example, and is not necessarily an actual flash memory device configuration. Further, the configuration of the exemplary flash memory device shown in FIG. 2 does not represent or suggest limitations to the present disclosure. For convenience of description, the memory device 120 may be interchanged with the flash memory device 120 .

1 and 2, the memory device 120 includes a memory cell array 122, a row decoder 394, a control circuit 124, a page buffer unit 393, an input/output circuit unit 126, and a voltage generator unit. (127) may be included. Although not shown, the memory device 120 may further include an input/output interface.

The memory cell array 122 may be connected to word lines WL, string select lines SSL, ground select lines GSL, and bit lines BL. The memory cell array 122 is connected to the row decoder 394 through word lines WL, string select lines SSL, and ground select lines GSL, and to the page buffer through bit lines BL. It can be connected to unit 393. The memory cell array 122 may include a plurality of memory blocks BLK1 to BLKn.

Each memory block BLK1 to BLKn may include a plurality of memory cells and a plurality of selection transistors. Memory cells may be connected to word lines WL, and select transistors may be connected to string select lines SSL or ground select lines GSL. Each of the memory cells may store one or more bits, and as an example, each memory cell may be a multi level cell (MLC), triple level cell (TLC), or quad level cell (Quad Level Cell). , QLC).

The row decoder 394 may be connected to the memory cell array 122 through a plurality of string select lines SSL, a plurality of word lines WL, and a plurality of ground select lines GSL. During a program operation or a read operation, the row decoder 394 determines one of the plurality of word lines WL as a selected word line based on the row address R_ADDR provided from the control circuit 124, and selects the other word lines. may be determined as unselected word lines. Also, during a program operation or a read operation, the row decoder 394 determines one of the plurality of string selection lines SSL as a selection string selection line based on the row address R_ADDR provided from the control circuit 124, , the remaining string selection lines may be determined as unselected string selection lines.

The control circuit 124 performs program, read, and erase operations on the memory cell array 122 based on the command CMD, address ADDR, and control signal CTRL transmitted from the memory controller 110. It can output various internal control signals for The control circuit 124 may provide a row address R_ADDR to the row decoder 394, may provide a column address to the input/output circuit unit 126, and may provide a voltage control signal CTRL_VOL to the voltage generator 127. can provide.

The page buffer unit 393 may operate as a write driver or a sense amplifier according to an operation mode. During a read operation, the page buffer unit 393 may sense the bit line BL of the selected memory cell according to the control of the control circuit 124 . The sensed data may be stored in latches provided inside the page buffer unit 393 . The page buffer unit 393 may transfer data stored in the latches to the input/output circuit unit 126 through the data line DL under the control of the control circuit 124 .

The data input/output circuit unit 126 may be connected to the page buffer unit 393 through data lines DL. During a program operation, the data input/output circuit unit 126 may receive program data from the memory controller 110 and provide the program data to the page buffer unit 393 based on a column address provided from the control circuit 124. . During a read operation, the data input/output circuit unit 126 may provide read data stored in the page buffer unit 393 to the memory controller 110 based on the column address provided from the control circuit 124 .

The voltage generator 127 may generate various types of voltages for performing program, read, and erase operations on the memory cell array 122 based on the voltage control signal CTRL_VOL. Specifically, the voltage generator 127 may generate the word line voltage VWL, eg, a program voltage, a verify voltage, a read voltage, a pass voltage, an erase voltage, an erase verify voltage, and the like.

The control circuit 124 may include an inter-stack word line manager 129 . The inter-stack word line management unit 129 may be configured to differently control operation times of word lines adjacent to an inter-stack region between memory stacks. The inter-stack word line management unit 129 refers to those implemented in hardware, firmware, software, or a combination thereof for controlling or managing inter-stack word lines. In the following embodiment, the inter-stack word line management unit 129 provides inter-stack word lines with some of the word lines adjacent to the inter-stack region among word lines of memory stacks based on channel hole profile information, and inter-stack word lines. Although it will be described as controlling the stack wordlines, embodiments of the present invention need not be so limited. For example, the inter-stack word line management unit 129 corresponds to a configuration included in the control logic circuit 220, and it may be described that the control logic circuit 220 controls the inter-stack word lines.

3 is a diagram illustrating the structure of a memory device according to example embodiments.

Referring to FIG. 3 , the memory device 120 may have a chip to chip (C2C) structure. In the C2C structure, an upper chip including a cell area (CELL) is fabricated on a first wafer, a lower chip including a peripheral circuit area (PERI) is fabricated on a second wafer different from the first wafer, and then the upper chip is fabricated. This may mean connecting the chip and the lower chip to each other by a bonding method. For example, the bonding method may refer to a method of electrically connecting the bonding metal formed on the uppermost metal layer of the upper chip and the bonding metal formed on the uppermost metal layer of the lower chip to each other. For example, when the bonding metal is formed of copper (Cu), the bonding method may be a Cu-Cu bonding method, and the bonding metal may also be formed of aluminum (Al) or tungsten (W).

Each of the peripheral circuit area PERI and the cell area CELL of the memory device 120 may include an external pad bonding area PA, a word line bonding area WLBA, and a bit line bonding area BLBA.

The peripheral circuit region PERI includes a first substrate 210 , an interlayer insulating layer 215 , a plurality of circuit elements 220a , 220b , and 220c formed on the first substrate 210 , and a plurality of circuit elements 220a. , 220b, 220c) to include the first metal layers 230a, 230b, 230c connected to each other, and the second metal layers 240a, 240b, 240c formed on the first metal layers 230a, 230b, 230c. can In one embodiment, the first metal layers 230a, 230b, and 230c may be formed of tungsten having a relatively high electrical resistivity, and the second metal layers 240a, 240b, and 240c may be made of copper having a relatively low electrical resistivity. can be formed

In this specification, only the first metal layers 230a, 230b, and 230c and the second metal layers 240a, 240b, and 240c are shown and described, but are not limited thereto, and the second metal layers 240a, 240b, and 240c At least one or more metal layers may be further formed. At least some of the one or more metal layers formed on the second metal layers 240a, 240b, and 240c are made of aluminum having a lower electrical resistivity than copper forming the second metal layers 240a, 240b, and 240c. can be formed

The interlayer insulating layer 215 covers the plurality of circuit elements 220a, 220b, and 220c, the first metal layers 230a, 230b, and 230c, and the second metal layers 240a, 240b, and 240c on the first substrate. 210, and may include an insulating material such as silicon oxide or silicon nitride.

Lower bonding metals 271b and 272b may be formed on the second metal layer 240b of the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 271b and 272b of the peripheral circuit area PERI may be electrically connected to the upper bonding metals 371b and 372b of the cell area CELL by a bonding method. , The lower bonding metals 271b and 272b and the upper bonding metals 371b and 372b may be formed of aluminum, copper, or tungsten.

The cell area CELL may provide at least one memory block. The cell region CELL may include the second substrate 310 and the common source line 320 . A plurality of word lines 331 to 338 330 may be stacked on the second substrate 310 along a direction (Z-axis direction) perpendicular to the upper surface of the second substrate 310 . String select lines and a ground select line may be disposed on upper and lower portions of the word lines 330 , and a plurality of word lines 330 may be disposed between the string select lines and the ground select line.

In the bit line bonding area BLBA, the channel structure CH extends in a direction (Z-axis direction) perpendicular to the top surface of the second substrate 310 to form word lines 330, string selection lines, and ground selection. line can pass through. The channel structure CH may include a data storage layer, a channel layer, and a buried insulating layer, and the channel layer may be electrically connected to the first metal layer 350c and the second metal layer 360c. For example, the first metal layer 350c may be a bit line contact, and the second metal layer 360c may be a bit line. In one embodiment, the bit line 360c may extend along a first direction (Y-axis direction) parallel to the upper surface of the second substrate 310 .

In the embodiment shown in FIG. 3 , an area where the channel structure CH and the bit line 360c are disposed may be defined as a bit line bonding area BLBA. The bit line 360c may be electrically connected to the circuit elements 220c providing the page buffer unit 393 in the peripheral circuit area PERI in the bit line bonding area BLBA. For example, the bit line 360c is connected to the upper bonding metals 371c and 372c in the peripheral circuit area PERI, and the upper bonding metals 371c and 372c are connected to the circuit elements 220c of the page buffer unit 393. It may be connected to the lower bonding metals 271c and 272c connected to .

In the word line bonding area WLBA, the word lines 330 extend along a second direction (X-axis direction) perpendicular to the first direction (Y-axis direction) and parallel to the upper surface of the second substrate 310 . and may be connected to the plurality of cell contact plugs 341 to 347; 340. The word lines 330 and the cell contact plugs 340 may be connected to each other through pads provided by extending at least some of the word lines 330 with different lengths in the second direction. A first metal layer 350b and a second metal layer 360b may be sequentially connected to upper portions of the cell contact plugs 340 connected to the word lines 330 . The cell contact plugs 340 are connected to the peripheral circuit through the upper bonding metals 371b and 372b of the cell area CELL and the lower bonding metals 271b and 272b of the peripheral circuit area PERI in the word line bonding area WLBA. It may be connected to the area PERI.

The cell contact plugs 340 may be electrically connected to the circuit elements 220b providing the row decoder 394 in the peripheral circuit area PERI. In an embodiment, operating voltages of the circuit elements 220b forming the row decoder 394 may be different from operating voltages of the circuit elements 220c forming the page buffer unit 393 . For example, the operating voltage of the circuit elements 220c forming the page buffer unit 393 may be higher than the operating voltage of the circuit elements 220b forming the row decoder 394 .

A common source line contact plug 380 may be disposed in the external pad bonding area PA. The common source line contact plug 380 is formed of a conductive material such as metal, metal compound, or polysilicon, and may be electrically connected to the common source line 320 . A first metal layer 350a and a second metal layer 360a may be sequentially stacked on the common source line contact plug 380 . For example, an area where the common source line contact plug 380, the first metal layer 350a, and the second metal layer 360a are disposed may be defined as an external pad bonding area PA.

Meanwhile, input/output pads 205 and 305 may be disposed in the external pad bonding area PA. Referring to FIG. 3 , a lower insulating film 201 covering a lower surface of the first substrate 210 may be formed under the first substrate 210 , and first input/output pads 205 may be formed on the lower insulating film 201 . can be formed. The first input/output pad 205 is connected to at least one of the plurality of circuit elements 220a, 220b, and 220c arranged in the peripheral circuit area PERI through the first input/output contact plug 203, and the lower insulating layer 201 ) may be separated from the first substrate 210 by. In addition, a side insulating layer is disposed between the first input/output contact plug 203 and the first substrate 210 to electrically separate the first input/output contact plug 203 from the first substrate 210 .

3, an upper insulating layer 301 covering the upper surface of the second substrate 310 may be formed on the second substrate 310, and second input/output pads 305 are disposed on the upper insulating layer 301. It can be. The second input/output pad 305 may be connected to at least one of the plurality of circuit elements 220a, 220b, and 220c disposed in the peripheral circuit area PERI through the second input/output contact plug 303. In one embodiment, the second input/output pad 305 may be electrically connected to the circuit element 220a.

According to example embodiments, the second substrate 310 and the common source line 320 may not be disposed in an area where the second input/output contact plug 303 is disposed. Also, the second input/output pad 305 may not overlap the word lines 330 in the third direction (Z-axis direction). Referring to FIG. 3 , the second input/output contact plug 303 is separated from the second substrate 310 in a direction parallel to the upper surface of the second substrate 310, and the interlayer insulating layer 315 of the cell region CELL It can be connected to the second input/output pad 305 through.

According to embodiments, the first input/output pad 205 and the second input/output pad 305 may be selectively formed. For example, the memory device 120 includes only the first input/output pad 205 disposed on the first substrate 210 or the second input/output pad 305 disposed on the second substrate 310. may contain only Alternatively, the memory device 120 may include both the first input/output pad 205 and the second input/output pad 305 .

In each of the external pad bonding area PA and the bit line bonding area BLBA included in the cell area CELL and the peripheral circuit area PERI, the metal pattern of the uppermost metal layer exists in a dummy pattern, or The top metal layer may be empty.

In the memory device 120 , the uppermost metal layer of the peripheral circuit area PERI corresponds to the upper metal pattern 372a formed on the uppermost metal layer of the cell region CELL in the external pad bonding area PA. A lower metal pattern 273a having the same shape as the upper metal pattern 372a of ) may be formed. The lower metal pattern 273a formed on the uppermost metal layer of the peripheral circuit area PERI may not be connected to a separate contact in the peripheral circuit area PERI. Similarly, in the external pad bonding area PA, the upper metal layer of the cell area CELL corresponds to the lower metal pattern 273a formed on the uppermost metal layer of the peripheral circuit area PERI. An upper metal pattern 372a having the same shape as the lower metal pattern 273a may be formed.

Lower bonding metals 271b and 272b may be formed on the second metal layer 240b of the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 271b and 272b of the peripheral circuit area PERI may be electrically connected to the upper bonding metals 371b and 372b of the cell area CELL by a bonding method. .

In addition, in the bit line bonding area BLBA, the uppermost metal layer of the cell area CELL corresponds to the lower metal pattern 252 formed on the uppermost metal layer of the peripheral circuit area PERI. An upper metal pattern 392 having the same shape as the metal pattern 252 may be formed. A contact may not be formed on the upper metal pattern 392 formed on the uppermost metal layer of the cell region CELL.

Meanwhile, the memory device 120 may form a memory cell array including a plurality of cell strings each disposed between a plurality of bit lines and a source line in a vertical direction with respect to the substrate in a multi-stack memory block structure. In the bit line bonding area BLBA of FIG. 3 , a plurality of word lines 331 to 338 (330) disposed between the string select lines and the ground select line may be divided into two memory stacks as shown. there is. An inter-stack region INT-ST (FIG. 4) may be included between the memory stacks. A channel structure CH is also formed in the inter-stack region INT-ST, which will be described in detail with reference to FIGS. 4 and 5 .

4 is a perspective view illustrating a memory block BLK1 according to an exemplary embodiment of the present invention. FIG. 5 is a cross-sectional view illustrating an embodiment of an inter-stack area INT-ST included in the memory block BLK1 of FIG. 4 . FIG. 4 shows a representative memory block BLK1 among the plurality of memory blocks BLK1 to BLKn of FIG. 2 . The memory block BLK1 includes NAND strings or cell strings formed in a three-dimensional or vertical structure. The memory block BLK1 includes structures extending along a plurality of directions X, Y, and Z.

Referring to FIG. 4 , the memory block BLK1 is formed in a vertical direction (Z direction) with respect to the substrate SUB. The substrate SUB has a first conductivity type (eg, p-type), and a common source line CSL doped with impurities of a second conductivity type (eg, n-type) is formed on the substrate SUB. It can be.

On the region of the substrate SUB between the common source lines CSL, a plurality of insulating materials IL extending along the second horizontal direction (Y direction) are sequentially provided along the vertical direction (Z direction). do. For example, the plurality of insulating materials IL may be formed to be spaced apart by a specific distance along the first horizontal direction (X direction). For example, the insulating materials IL may include an insulating material such as silicon oxide.

A channel structure (which is sequentially disposed on the substrate SUB between the common source lines CSL) along the second horizontal direction (Y direction) and penetrates the insulating materials IL along the vertical direction (Z direction). CH) is formed. For example, the channel structure CH may be connected to the substrate SUB by penetrating the insulating materials IL. Illustratively, each channel structure CH may be composed of a plurality of materials. A surface layer S of the channel structure CH may include a silicon material having a first conductivity type and may function as a channel region. In some embodiments, the channel structure (CH) may be referred to as a vertical channel structure or a pillar. Meanwhile, the inner layer I of each channel structure CH may include an insulating material such as silicon oxide or an air gap.

A charge storage layer (CS) is provided along the insulating layers IL, the channel structure CH, and the exposed surface of the substrate SUB. The charge storage layer CS may include a gate insulating layer (or referred to as 'tunneling insulating layer'), a charge trap layer, and a blocking insulating layer. For example, the charge storage layer CS may have an oxide-nitride-oxide (ONO) structure. In addition, a gate electrode GE such as a ground select line GSL, a string select line SSL, and word lines WL1 to WL8 is provided on the exposed surface of the charge storage layer CS.

Drain contacts or drains DR are respectively provided on the plurality of channel structures CH. For example, the drains DR may include a silicon material doped with impurities of the second conductivity type. Bit lines BL1 to BL3 are provided on the drains DR, extending in a first horizontal direction (X direction) and spaced apart from each other by a specific distance along a second horizontal direction (Y direction).

The memory block BLK1 may include a first memory stack ST1 and a second memory stack ST2 stacked in a vertical direction (Z direction). For example, the first memory stack ST1 may include word lines WL1 to WL4 , and the second memory stack ST2 may include word lines WL5 to WL8 . An inter-stack region INT-ST may exist between the first memory stack ST1 and the second memory stack ST2 to secure structural stability of the memory device 120 in the manufacturing process of the memory device 120 . .

Referring to FIG. 5 , a channel hole constituting a cell string in each channel structure (CH) may include a first sub-channel hole 510 and a second sub-channel hole 520 . The first sub-channel hole 510 formed in the first memory stack ST1 may include a channel layer 511 , an internal material 512 , and an insulating layer 513 . The second sub-channel hole 520 formed in the second memory stack ST2 may include a channel layer 521 , an internal material 522 , and an insulating layer 523 . The channel film 511 of the first sub-channel hole 510 and the channel film 521 of the second sub-channel hole 520 may be connected.

In the inter-stack region INT-ST, the second sub-channel hole 520 is formed at a junction between the channel film 511 of the first sub-channel hole 510 and the channel film 521 of the second sub-channel hole 520 . The size 502 of ) may be smaller than the size 501 of the first sub-channel hole 510 . Accordingly, an overlap margin may be secured at a connection portion between the channel film 511 of the first sub-channel hole 510 and the channel film 521 of the second sub-channel hole 520 . In order to increase the overlap margin in the manufacturing process, the inter-stack region INT-ST may be formed long in the vertical direction. Accordingly, the length L2 of the inter-stack region INT-ST may be formed to be relatively longer than the distance L1 between the word lines WL1 to WL4 and WL5 to WL8 of each memory stack ST1 and ST2. can

Meanwhile, in each of the word lines WL1 to WL4 and WL5 to WL8, the remaining area except for the area through which the sub-channel holes 510 and 520 pass through the corresponding gate electrode GE area is the corresponding word line WL1 to WL4 and WL5. It is displayed as a resistance value of ~WL8). As the size of the sub-channel holes 510 and 520 of the word lines WL1 to WL4 and WL5 to WL8 increases, the word line resistance value may increase, and the sub-channel hole of the word lines WL1 to WL4 and WL5 to WL8 may have a larger size. As the sizes of (510 and 520) are smaller, the word line resistance value may be smaller.

Illustratively, the size of the first sub-channel hole 510 of the fourth word line WL4 at the upper end of the first memory stack ST1 is greater than that of the other word lines WL1 to WL3 of the first memory stack ST1. can be relatively large. A resistance value of the fourth word line WL4 at the upper end of the first memory stack ST1 may be relatively large. The size of the second sub-channel hole 520 of the fifth word line WL5 at the lower end of the second memory stack ST2 may be relatively smaller than that of the other word lines WL6 to WL8 of the second memory stack ST2. there is. A resistance value of the fifth word line WL5 at the lower end of the second memory stack ST2 may be relatively small.

The first channel voltage VCH1 of the cell string of the first memory stack ST1 according to the difference in resistance between the fourth word line WL4 and the fifth word line WL5 adjacent to the inter-stack region INT-ST. The second channel voltage VCH2 of the cell string of the second memory stack ST2 may be boosted differently. As shown in FIG. 5 , the first channel voltage VCH1 associated with the fourth word line WL4 having a large resistance value is boosted small, and the second channel voltage VCH1 associated with a fifth word line WL5 having a small resistance value is boosted. The channel voltage VCH2 may be greatly boosted. Since the inter-stack area (INT-ST) is included in the channel area of each cell string, when the difference between the first channel voltage (VCH1) and the second channel voltage (VCH2) exceeds a certain range, a hot signal is generated due to the channel voltage difference. Carrier injection (HCI) may occur. Accordingly, a threshold voltage state of a memory cell adjacent to the inter-stack region INT-ST may be distorted.

Channel hole profile information may be obtained in a process of forming the first sub-channel hole 510 and the second sub-channel hole 520 constituting the channel hole of each cell string. The channel hole profile may be defined in the manufacturing process of the nonvolatile memory device 120, and the inter-stack word line management unit 129 defines word lines adjacent to the inter-stack region INT-ST defined in the manufacturing process. Channel hole profile information for can be stored. The inter-stack word line management unit 129 may determine some word lines having a large difference in resistance among word lines adjacent to the inter-stack region INT-ST as inter-stack word lines based on the channel hole profile information.

The inter-stack word line manager 129 may determine each word line adjacent to the inter-stack region INT-ST in each of the first and second memory stacks ST1 and ST2 as an inter-stack word line. Exemplarily, the inter-stack word line management unit 129 stores the fourth word line WL4 of the first memory stack ST1 and the fifth word line WL5 of the second memory stack ST2 as inter-stack words. lines can be determined. In order to prevent HCI caused by a difference between the first channel voltage VCH1 and the second channel voltage VCH2 in the inter-stack region INT-ST, the inter-stack word line manager 129 controls the inter-stack word lines, That is, operation timings of the fourth and fifth word lines WL4 and WL5 may be controlled. Channel potential equalization for the inter-stack region (INT-ST) can be implemented by controlling the operation timing of the WL4 and WL5 inter-stack word lines.

FIG. 6 shows an equivalent circuit diagram of the memory block of FIG. 4 .

Referring to FIG. 6 , the memory block BLK1 includes NAND strings NS11 to NS33, word lines WL1 to WL8, bit lines BL1 to BL3, ground select lines GSL1 to GSL3, and a string. It may include selection lines SSL1 to SSL3 and a common source line CSL. Although FIG. 5 illustrates that each of the cell strings NS11 to NS33 includes eight memory cells MCs connected to eight word lines WL1 to WL8, the present invention is not limited thereto.

Each cell string (eg, NS11) may include a string select transistor SST, a plurality of memory cells MC, and a ground select transistor GST connected in series. The string select transistor SST is connected to the corresponding string select line SSL1. The plurality of memory cells MC are respectively connected to corresponding word lines WL1 to WL8. The ground select transistor GST is connected to a corresponding ground select line GSL1. The string select transistor SST is connected to the corresponding bit lines BL1 to BL3, and the ground select transistor GST is connected to the common source line CSL.

Depending on exemplary embodiments, in each cell string, one or more dummy memory cells may be provided between the string select transistor SST and the memory cells MC. In each cell string, one or more dummy memory cells may be provided between the ground select transistor GST and the memory cells MC. In each cell string, one or more dummy memory cells may be provided between the memory cells MC. The dummy memory cells have the same structure as the memory cells MC, and may be unprogrammed (eg, program inhibited) or programmed differently from the memory cells MC. For example, when memory cells MC are programmed to have two or more threshold voltage distributions, dummy memory cells have one threshold voltage distribution range or fewer threshold voltage distributions than memory cells MC. can be programmed

FIG. 7 illustratively illustrates a threshold voltage distribution when write data is written into the memory cells MCs shown in FIG. 6 . In FIG. 7 , a horizontal axis represents threshold voltages of memory cells, and a vertical axis represents cell counts, that is, the number of memory cells.

Referring to FIGS. 6 and 7 , one or more bits may be programmed into the memory cell MC. According to the number of bits stored in the memory cell MC, the memory cell may be classified as SLC, MLC, TLC, or QLC. According to the number of bits stored in the memory cell MC, the memory cell may have a plurality of states. A plurality of states may be defined as a range of threshold voltages. In FIG. 7 , the memory cell MC is a QLC, and the threshold voltage of the memory cell MC can be programmed to one of 16 states S1 to S16. Each state S1 to S16 may correspond to a distribution range of threshold voltages Vth of memory cells.

8 is a diagram illustrating program bias conditions according to embodiments of the present invention. 8 , for convenience, cell strings NS11 and NS21 connected to the first bit line BL1 among the cell strings NS11 to NS33 ( FIG. 4 ) of the memory block BLK1 of FIG. 7 and the second bit line BL2 ) shows the cell strings NS12 and NS22 connected to.

Referring to FIG. 8 , the first bit line BL1 is a program permission bit line to which a relatively low program permission voltage (VPER, FIG. 9 ), for example, a ground voltage (VSS) is applied, and a second bit line ( BL2) is a program inhibit bit line to which a relatively high program inhibit voltage VINH (FIG. 9), for example, the power supply voltage VDD is applied.

Assuming that the NS21 cell string is selected from among the cell strings NS11 and NS21 connected to the first bit line BL1, during a program operation (PROGRAM. FIG. 9 ), the first string selection line SSL1 connected to the NS11 cell string A turn-off voltage of the ground voltage VSS level is applied, and a turn-on voltage VSSL1 equal to or higher than the threshold voltage Vth of each of the string select transistors SST is applied to the second string select line SSL2 connected to the cell string NS21, for example , the power supply voltage VDD may be applied.

A turn-off voltage of the ground voltage VSS level may be applied to the first and second ground select lines GSL1 and GSL2, and the ground voltage VSS may be applied to the source line CSL. A program voltage (VPGM, FIG. 9) (eg, 18V) is applied to the selected word line (eg, WL2), and a program pass voltage (VPASS1, FIG. 9) (eg, WL1, WL3) is applied to the non-selected word lines (eg, WL1, WL3). For example, 8V) is applied, and the program pass voltage VPASS1 (FIG. 9) is also applied to the inter-stack word lines (eg, WL4 and WL5). Although not shown, the non-selected word lines may include word lines WL6, WL7, and WL8. The program pass voltage VPASS1 may be set to a voltage at which a plurality of memory cells are always turned on.

In this program bias condition, 18V is applied to the gate of the memory cell A and the channel voltage is 0V. Since a strong electric field is formed between the gate and the channel of the memory cell A, the memory cell A is programmed. Meanwhile, since the channel voltage of the memory cell B is the power supply voltage VDD and a weak electric field is formed between the gate and the channel of the memory cell B, the memory cell B is not programmed. Since the channels of the memory cells C and D are in a floating state, the channel voltage rises to the boosted level by the program pass voltage VPASS1, and the memory cells C and D are not programmed.

9A and 9B are diagrams for explaining program operations according to embodiments of the present invention. 9A and 9B show the memory cell A programmed in the NS21 cell string of FIG. 8 , the selected word line WLs refers to the word line WL2, and the unselected word lines WLu refer to WL1 and WL3. , WL6, WL7, WL8 word lines, inter-stack word lines refer to WL4, WL5 word lines, select string select line (SSL) refers to SSL2 string select line, non-select string select line (SSL) ) refers to the SSL1 string select line, the selected ground select line (GSL) refers to the GSL2 ground select line, the unselected ground select line (GSL) refers to the GSL1 ground select line, and the program enable bit line (BL) may refer to the BL1 bit line, and the program inhibit bit line BL may refer to the BL2 bit line.

Referring to FIG. 9A , a plurality of program loops (LOOP1, LOOP2, LOOP3, ??) may be sequentially performed on the memory cells connected to the selected word lines (WLs) according to ISPP until the program is completed. As the program loop is repeated, the program voltages VPGM1, VPGM2, VPGM3, ?? may increase in stages. Each program loop (LOOPi, where i is a natural number) includes a program period (PROGRAM) for applying the program voltage (VPGM) to the selected word lines (WLs) to program the selected memory cell, and a selected word line (PROGRAM) to verify program success. A verification period VERIFY for applying the verification voltage VVFY to WLs may be included.

The program period PRGOGRAM may include an inter-stack word line setup period PIWLS, a channel precharge and bit line setup period PBLS, a program execution period PEXE, and a program recovery period PRCV.

The inter-stack word line setup period PIWLS controls the inter-stack word lines WL4 and WL5 adjacent to the inter-stack area INT-ST to perform a channel potential equalization operation for the inter-stack area INT-ST. can be done During the inter-stack word line setup period PIWLS, the program pass voltage VPASS1 may be applied to the inter-stack word lines WL4 and WL5. According to the information that the resistance value of the WL4 inter-stack word line among the WL4 and WL5 inter-stack word lines is greater than the resistance value of the WL5 inter-stack word line, the program pass voltage (VPASS1 ) is applied, and the program pass voltage VPASS1 may be applied to the WL5 inter-stack word line at a time point Ta2. That is, for channel potential equalization, the program pass voltage VPASS1 may be first applied to the WL4 inter-stack word line having a large resistance value and applied later to the WL5 inter-sector word line having a small resistance value.

The channel precharge and bit line setup period (PBLS) uses a gate induced drain leakage (GIDL) phenomenon to initialize or precharge channels of a plurality of unselected cell strings before a program loop (hereinafter, USIP (referred to as Unselect String Initial Precharge). In the channel pre-charge and bit line setup period (PBLS), the power supply voltage VDD, which is the program inhibit voltage VINH, is applied to the program inhibit bit line BL, and the program permission voltage level, which is the program permission voltage level, is applied to the program permission bit line BL. A ground voltage VSS may be applied. A first turn-on voltage VSSL1 may be applied to the select string select line SSL, and a turn-off voltage, that is, a ground voltage VSS may be applied to the non-select string select line SSL. The turn-on voltage VGSL may be applied to the ground select lines GSL, and the power supply voltage VDD may be applied as the precharge voltage VPC to the source line CSL.

In the channel precharge and bit line setup period (PBLS), the channels of the plurality of unselected cell strings are initialized according to the GIDL phenomenon induced through the selection string selection transistor (SST) connected to the selection string selection line (SSL), and It may be initialized according to the GIDL phenomenon induced through the ground selection transistor GST connected to the selection lines GSL. Thereafter, the first turn-on voltage VSSL1 is maintained in the select string select line SSL, the turn-off voltage is applied to the non-select string select lines SSL, and the source line CSL and the ground select lines ( A ground voltage (VSS) may be applied to the GSL.

In the program execution period PEXE, the program pass voltage VPASS1 is applied to the selected word lines WLs and non-selected word lines WLu, and after a lapse of a certain time, the program voltage VPGM is applied to the selected word lines WLs. ) can be applied.

The program recovery period PRCV grounds bit lines BL, string select lines SSL, selected word lines WLs, unselected word lines WLu, and inter-stack word lines WL4 and WL5. It can be recovered with the voltage (VSS). At this time, among the inter-stack word lines WL4 and WL5, the WL5 inter-sector word line having a small resistance value is recovered to the ground voltage (VSS) at the time point Tb1, and the WL4 inter-stack word line having a large resistance value is recovered to the ground voltage VSS at the time point Tb1. At this point, it can be recovered to the ground voltage (VSS). That is, in the program recovery period PRCV, the WL5 inter-sector word line having a low resistance value may be program recovered first, and the WL4 inter-stack word line having a large resistance value may be program recovered later.

According to an embodiment, the program recovery period PRCV, as shown in FIG. 9B , sets the selected word line WLs, the non-selected word line WLu, and the inter-stack word lines WL4 and WL5 to a recovery voltage ( VRCV) to recover. The control circuit 124 of the nonvolatile memory device 120 determines the recovery voltage ( VRCV) can be determined. The recovery voltage VRCV may be set to an external power voltage applied to the nonvolatile memory device 120 or an internal power voltage generated from an external power voltage inside the nonvolatile memory device 120 . At this time, among the inter-stack word lines WL4 and WL5, the WL5 inter-sector word line having a small resistance value is recovered with the recovery voltage VRCV at the time point Tb1, and the WL4 inter-stack word line having a large resistance value is recovered at the time Tb2. At this point, it can be recovered with the recovery voltage VRCV. That is, in the program recovery period PRCV, the WL5 inter-sector word line having a low resistance value may be program recovered first, and the WL4 inter-stack word line having a large resistance value may be program recovered later.

9A and 9B, in the program period PRGOGRAM, in the inter-stack word line setup period PIWLS, the program pass voltage VPASS1 is first applied to the inter-stack word line WL4 having a large resistance value, and the inter-stack word line WL5 having a small resistance value The WL5 inter-sector word line, which is applied later to the inter-sector word line and has a small resistance value in the program recovery period (PRCV), is first recovered to the ground voltage (VSS) or recovery voltage (VRCV), and the WL4 inter-sector word line with a large resistance value is first recovered. Channel potential equalization of the inter-stack region INT-ST may be implemented by allowing the stack word line to be recovered later with the ground voltage VSS or the recovery voltage VRCV.

9A, the verification period VERIFY may include an inter-stack word line setup period PIWLS, a verify read period RVFY, and a read recovery period RRCV. In the inter-stack word line setup period PIWLS, similar to the inter-stack word line setup period PIWLS of the program period PRGOGRAM, the read pass voltage VPASS2 is applied first to the WL4 inter-stack word line having a large resistance value. can be applied later to the WL5 inter-sector wordline, which is applied and has a small resistance value. At time Tc1, the read pass voltage VPASS2 may be applied to the inter-stack word line WL4, and at time Tc2, the read pass voltage VPASS2 may be applied to the inter-stack word line WL5.

In the verification read period RVFY, the read pass voltage VPASS2 for turning on the memory cell is always applied to the unselected word line WLu regardless of the program state of the memory cell, and the verification voltage (VPASS2) is applied to the selected word line WLs. VVFY) may be applied, the turn-on voltage VGSL may be applied to the selected ground select line GSL, and the turn-off voltage, that is, the ground voltage VSS may be applied to the unselected ground select line GSL.

The read recovery period RRCV grounds the bit lines BL, the string select lines SSL, the selected word line WLs, the unselected word line WLu, and the inter-stack word lines WL4 and WL5. It can be recovered with the voltage (VSS). In the read recovery period (RRCV), similar to the program recovery period (PRCV) of the program period (PRGOGRAM), the WL5 inter-sector word line with a small resistance value is read-recovered first, and the WL4 inter-stack word line with a large resistance value is read later. Read recovery can be performed. At time Td1, the WL5 inter-stack word line may be recovered to the ground voltage VSS, and at time Td2, the WL4 inter-stack word line may be recovered to the ground voltage VSS.

According to an embodiment, the read recovery period RRCV, as shown in FIG. 9B , is a recovery voltage ( VRCV) to recover. Among the inter-stack word lines WL4 and WL5, the WL5 inter-sector word line having a small resistance value is recovered with the recovery voltage VRCV at time Td1, and the WL4 inter-stack word line having a large resistance value is recovered at time Td2. It can be recovered as the voltage VRCV. That is, in the read recovery period RRCV, the WL5 inter-sector word line having a low resistance value may be recovered first, and the WL4 inter-stack word line having a large resistance value may be recovered later.

9A and 9B, in the verification period VERIFY, in the inter-stack word line setup period PIWLS, the program pass voltage VPASS1 is first applied to the WL4 inter-stack word line having a large resistance value, and WL5 having a small resistance value. It is applied to the inter-sector word line later, and in the read recovery period (RRCV), the WL5 inter-sector word line with a small resistance value is first recovered to the ground voltage (VSS), and the WL4 inter-stack word line with a large resistance value is grounded later. By allowing the voltage to be recovered, the channel potential of the inter-stack region INT-ST can be equalized.

FIG. 10 is a cross-sectional view illustrating another embodiment of an inter-stack area INT-ST included in the memory block BLK1 of FIG. 4 . 11 is a diagram for explaining a program operation according to embodiments of the present invention. The programming method of FIG. 11 shows a timing diagram of inter-stack word lines WL3, WL4, WL5, and WL6 of FIG. 10, and selected word lines (WLs) and unselected word lines described in FIG. 9 for simplicity of the drawing. (WLu), a select/unselect string select line (SSL), a select/unselect ground select line (GSL), and a program enable/inhibit bit line (BL) are omitted.

10 and 11, in the inter-stack word line setup period PIWLS of the program period PRGOGRAM, the program pass voltage VPASS1 is applied to the inter-stack word line WL4 of the first memory stack ST1 at a time point Ta1. ) is applied, the program pass voltage VPASS1 is applied to the WL3 inter-stack word line of the first memory stack ST1 at the time Ta2, and the WL5 inter-stack word line of the second memory stack ST2 is applied at the time Ta3. The program pass voltage VPASS1 may be applied to , and the program pass voltage VPASS1 may be applied to the WL6 inter-stack word line of the second memory stack ST2 at a time point Ta4 . That is, in the inter-stack word line setup period PIWLS of the program period PRGOGRAM, the program pass voltage VPASS1 is the WL4 adjacent to the inter-stack area INT among WL3 and WL4 inter-stack word lines having a large resistance value. The inter-stack word line may be applied first, and the WL6 inter-sector word line distant from the inter-stack area INT among the WL5 and WL6 inter-stack word lines having a low resistance may be applied later.

In the program recovery period PRCV, the WL3 inter-stack word line of the first memory stack ST1 is recovered to the ground voltage VSS or the recovery voltage VRCV at a time Tb1, and at a time Tb2 the first memory stack ST1 The WL4 inter-stack word line of ) is recovered to the ground voltage (VSS) or the recovery voltage (VRCV), and the WL6 inter-stack word line of the second memory stack (ST2) is recovered to the ground voltage (VSS) or the recovery voltage at the time Tb3. (VRCV), and at the time point Tb4, the WL5 inter-stack word line of the second memory stack ST2 may be recovered to the ground voltage VSS or the recovery voltage VRCV. That is, in the program recovery period PRCV, among WL3 and WL4 inter-stack word lines having high resistance values, the WL3 inter-sector word lines far from the inter-stack area INT are first program recovered, and WL5 and WL6 having low resistance values Among the inter-stack word lines, a WL5 inter-sector word line close to the inter-stack area INT may be program recovered later.

In the inter-stack word line setup period PIWLS of the verification period VERIFY, the read pass voltage VPASS2 is applied to the inter-stack word line WL4 of the first memory stack ST1 at time Tc1, and at time Tc2 1 The read pass voltage VPASS2 is applied to the WL3 inter-stack word line of the memory stack ST1, and the read pass voltage VPASS2 is applied to the WL5 inter-stack word line of the second memory stack ST2 at a time point Tc3. At the time Tc4, the read pass voltage VPASS2 may be applied to the WL6 inter-stack word line of the second memory stack ST2. That is, in the inter-stack word line setup period PIWLS of the verification period VERIFY, the read pass voltage VPASS2 is the WL4 adjacent to the inter-stack area INT among WL3 and WL4 inter-stack word lines having a large resistance value. The inter-stack word line may be applied first, and the WL6 inter-sector word line distant from the inter-stack area INT among the WL5 and WL6 inter-stack word lines having a low resistance may be applied later.

In the read recovery period RRCV of the verification period VERIFY, the WL3 inter-stack word line of the first memory stack ST1 is recovered to the ground voltage VSS or the recovery voltage VRCV at time Td1, and at time Td2 The WL4 inter-stack word line of the first memory stack ST1 is recovered to the ground voltage VSS or the recovery voltage VRCV, and the WL6 inter-stack word line of the second memory stack ST2 is recovered to the ground voltage at time Td3. (VSS) or the recovery voltage (VRCV), and at the time Td4, the WL5 inter-stack word line of the second memory stack (ST2) may be recovered to the ground voltage (VSS) or the recovery voltage (VRCV). That is, in the read recovery period RRCV of the verification period VERIFY, among the WL3 and WL4 inter-stack word lines having high resistance values, the WL3 inter-sector word line farther from the inter-stack area INT is first read-recovered, Among the WL5 and WL6 inter-stack word lines having low resistance values, the WL5 inter-sector word line close to the inter-stack area INT may be read-recovered later.

12 is a flowchart illustrating a method of operating a nonvolatile memory device according to example embodiments.

Referring to FIG. 12 , in step S1210, a memory cell array including a plurality of cell strings in which a plurality of memory cells are disposed between a plurality of bit lines and a source line in a vertical direction is divided into a plurality of stacks. A memory cell array or memory block may be divided into two memory stacks as described with reference to FIG. 5 or three memory stacks as described with reference to FIG. 15 . Meanwhile, although not shown in the drawings, it will be appreciated that a memory block may be divided into four or more memory stacks in a similar manner.

In step S1220, the inter-stack word line management unit 129 transmits channel hole profile information about some of the word lines adjacent to the inter-stack regions INT-ST defined in the manufacturing process of the nonvolatile memory device 120. and some of word lines adjacent to the inter-stack region INT-ST among word lines of memory stacks based on the channel hole profile information may be determined as inter-stack word lines.

In step S1230, the inter-stack wordlines determined by the inter-stack wordline manager 129 may be sequentially set up according to the resistance values of the inter-stack wordlines. When setting up inter-stack word lines to pass voltages, the inter-stack word line management unit 129 may set up large inter-stack word lines first and set up inter-stack word lines having small resistance values later. In the inter-stack word line setup period PIWLS, as shown in FIG. 9 , the inter-stack word line management unit 129 controls the WL4 inter-stack word line having a large resistance value adjacent to the inter-stack region INT-ST. can be set up first, and the WL5 inter-sector wordline with a small resistor value can be set up later. As shown in FIG. 11 , the inter-stack word line management unit 129 first sets up the WL4 inter-stack word line adjacent to the inter-stack area INT among the WL3 and WL4 inter-stack word lines having a large resistance value. And, among the WL5 and WL6 inter-stack word lines having a small resistance value, the WL6 inter-sector word line distant from the inter-stack area INT can be set up later.

In step S1240, channel voltages of cell strings may be initialized or equalized as the inter-stack word lines of step S1230 are sequentially set up according to resistance values.

In step S1250, a program or read operation may be performed on the selected cell string. A program or read operation for a selected string may be performed according to the bias conditions of the program execution period PEXE or verification read period RVFY described in FIG. 9 and the read period RD described in FIG. 14 .

In step S1260, inter-stack word lines may be recovered in a recovery operation performed after a program or read operation. When the inter-stack word line management unit 129 recovers the inter-stack word lines with the ground voltage VSS or the recovery voltage VRCV, the inter-stack word line having a low resistance value is recovered first, and the inter-stack word line having a high resistance value is recovered first. - Stack wordlines can be recovered later. In the program recovery period (PRCV) and the read recovery period (RRCV), as shown in FIGS. 9A and 9B , the inter-stack wordline management unit 129 inter-stack area among WL3 and WL4 inter-stack wordlines. In (INT), the WL3 inter-sector word line having a small resistance value may be recovered first, and the WL4 inter-sector word line having a large resistance value may be recovered later. As shown in FIG. 11, the inter-stack word line management unit 129 first recovers the WL3 inter-sector word line far from the inter-stack area INT among the WL3 and WL4 inter-stack word lines having a large resistance value. And, among the WL5 and WL6 inter-stack word lines having a small resistance value, the WL5 inter-sector word line close to the inter-stack area INT can be recovered later.

FIG. 13 is a diagram explaining a read operation related to threshold voltage distribution of the memory cells shown in FIG. 7 .

Referring to FIGS. 2, 7, and 13 , when each of the memory cells is a QLC, the state of each of the memory cells may correspond to one of 16 states S1 to S16. Memory cells connected to one word line WL may include a least significant bit (LSB) page, a first middle bit (CSB1) page, a second middle bit (CSB2) page, and a most significant bit (MSB) page.

The control circuit 124 performs an operation of finding the valley positions (VR1 to VR15) of the threshold voltage of the memory cell and an operation of inferring the optimal read voltages (VRD1 to VRD15) based on the valley positions (VR1 to VR15). , A page read operation is performed on each of the least significant bit (LSB) page, the first middle bit (CSB1) page, the second middle bit (CSB2) page, and the most significant bit (MSB) page using read voltages (VRD1 to VRD15). can do.

In a read operation for the least significant bit (LSB) page, the eleventh and twelfth states S11 and S12 may be determined by applying the eleventh read voltage VRD11 to the selected word line WL, and then the sixth The sixth and seventh states S6 and S7, the fourth and fourth read voltages VRD6, the fourth read voltage VRD4, and the first read voltage VRD1 are sequentially applied to the selected word line WL, respectively. Five states S4 and S5 and first and second states S1 and S2 may be determined.

In a read operation for the first middle bit CSB1 page, the memory device 120 outputs a thirteenth read voltage VRD13, a ninth read voltage VRD9, a seventh read voltage VRD7, and a third read voltage VRD3. ) are sequentially applied to the selected word line WL to achieve the 13th and 14th states S13 and S14, the ninth and tenth states S9 and S10, the seventh and eighth states S7, S8) and the third and fourth states S3 and S4 can be determined.

In the read operation for the second middle bit CSB2 page, the memory device 120 selects the fourteenth read voltage VRD14, the eighth read voltage VRD8, and the second read voltage VRD2, respectively, to the word line WL. ), it is possible to determine the fourteenth and fifteenth states S14 and S15, the eighth and ninth states S8 and S9, and the second and third states S2 and S3.

In a read operation for a most significant bit (MSB) page, the memory device 120 applies a fifteenth read voltage VRD15, a twelfth read voltage VRD12, a tenth read voltage VRD10, and a fifth read voltage VRD5, respectively. by applying to the selected word line WL, the fifteenth and sixteenth states S15 and S16, the twelfth and thirteenth states S12 and S13, the tenth and eleventh states S10 and S11 and the fifth And sixth states S5 and S6 can be determined.

14 is a diagram for explaining a read operation according to example embodiments. The read operation of FIG. 14 will be similar to the verification period (VERIFY) of the program operation of FIG. 9 described above.

Referring to FIGS. 8, 10, and 14 , the read period READ may include an inter-stack word line setup period PIWLS, a read period RD, and a read recovery period RRCV. Similar to the inter-stack word line setup period (PIWLS) of the verification period (VERIFY), the inter-stack word line setup period (PIWLS) is similar to the inter-stack word line setup period (PIWLS) where the read pass voltage (VPASS2) has a large resistance value. Among them, the WL4 inter-stack word line adjacent to the inter-stack area INT is applied first and the WL6 inter-sector word farther from the inter-stack area INT among the WL5 and WL6 inter-stack word lines having a small resistance value. It can be applied later on the line. At the time Te1, the read pass voltage VPASS2 is applied to the WL4 inter-stack word line of the first memory stack ST1, and at the time Te2, the read pass voltage VPASS2 is applied to the WL3 inter-stack word line of the first memory stack ST1 ( VPASS2) is applied, the read pass voltage VPASS2 is applied to the WL5 inter-stack word line of the second memory stack ST2 at time Te3, and the WL6 inter-stack word of the second memory stack ST2 is applied at time Te4. A read pass voltage VPASS2 may be applied to the line.

In the read period RD, the read pass voltage VPASS2 for always turning on the memory cell is applied to the unselected word line WLu regardless of the program state of the memory cell, and the read pass voltage VPASS2 of FIG. 12 is applied to the selected word line WLs. The voltage VRD may be applied, the turn-on voltage VGSL may be applied to the selected ground select line GSL, and the turn-off voltage, that is, the ground voltage VSS may be applied to the unselected ground select line GSL.

The read recovery period RRCV may recover the selected word line WLs, the unselected word line WLu, and the inter-stack word lines WL4 and WL5 or the recovery voltage VRCV. Similar to the read recovery period (RRCV) of the verification period (VERIFY), the read recovery period (RRCV) is a WL3 inter-sector far from the inter-stack area (INT) among the WL3 and WL4 inter-stack word lines having a large resistance value. The word line is read-recovered first, and among the WL5 and WL6 inter-stack word lines having a small resistance value, the WL5 inter-sector word line close to the inter-stack area INT may be read-recovered later. At time Tf1, the WL3 inter-stack word line of the first memory stack ST1 is recovered to the ground voltage VSS or the recovery voltage VRCV, and at time Tf2, the WL4 inter-stack word line of the first memory stack ST1 is recovered. The ground voltage (VSS) or the recovery voltage (VRCV) is recovered, and the WL6 inter-stack word line of the second memory stack (ST2) is recovered to the ground voltage (VSS) or the recovery voltage (VRCV) at the time point Tf3, and the Tf4 At this point, the WL5 inter-stack word line of the second memory stack ST2 may be recovered with the ground voltage VSS or the recovery voltage VRCV.

15 is a diagram illustrating a memory block according to another exemplary embodiment of the present invention. Hereinafter, suffixes (eg, a in BLK1a) attached to the same reference numeral in different drawings are for distinguishing a plurality of circuits having similar or identical functions.

Referring to FIGS. 2 and 15 , the memory block BLK1a may include three memory stacks ST1 , ST2 , and ST3 . Inter-stack regions 1510 and 1520 may be included between the memory stacks ST1 , ST2 , and ST3 .

The inter-stack word line management unit 129 may store channel hole profile information about word lines adjacent to the inter-stack regions 1510 and 1520 defined in a manufacturing process step. The inter-stack word line management unit 129 selects one word line adjacent to the inter-stack regions 1510 and 1520 among word lines of each of the memory stacks ST1 , ST2 , and ST3 based on the channel hole profile information. It can be determined by the stack word lines 1512 and 1522. According to an embodiment, the inter-stack word line management unit 129 selects word lines 2 adjacent to the inter-stack regions 1510 and 1520 among word lines of the memory stacks ST1 , ST2 , and ST3 based on the channel hole profile information. Each may be determined as the inter-stack word lines 1514 and 1524.

The inter-stack word line management unit 129 applies pass voltages to the inter-stack word lines 1512, 1522, 1514, and 1524 according to the resistance values of the inter-stack word lines 1512, 1522, 1514, and 1524. A channel voltage equalization operation of a plurality of memory stacks may be performed while differently controlling set-up times. When the inter-stack word line management unit 129 sets up the inter-stack word lines 1512, 1522, 1514, and 1524 to pass voltages, first sets up the inter-stack word line having a large resistance value, and first sets up the inter-stack word line having a small resistance value. Inter-stack wordlines can be set up later.

The inter-stack word line manager 129 applies a ground voltage (VSS) to the inter-stack word lines 1512, 1522, 1514, and 1524 according to resistance values of the inter-stack word lines 1512, 1522, 1514, and 1524. ) or recovery time points at which the recovery voltage VRCV is applied may be differently controlled, and the channel voltage equalization operation of the plurality of memory stacks may be performed. When the inter-stack word line management unit 129 recovers the inter-stack word lines 1512, 1522, 1514, and 1524 with the ground voltage VSS or the recovery voltage VRCV, the inter-stack word having a small resistance value A line may be recovered first, and an inter-stack word line having a large resistance value may be recovered later.

16 is a block diagram illustrating a system 3000 including a nonvolatile memory device according to example embodiments.

Referring to FIG. 16, a system 3000 includes a camera 3100, a display 3200, an audio processor 3300, a modem 3400, DRAMs 3500a and 3500b, flash memories 3600a and 3600b, I It may include /O devices 3700a and 3700b and an application processor (Application Processor, 3800, hereinafter referred to as “AP”). The system 3000 is implemented as a laptop computer, a mobile phone, a smart phone, a tablet personal computer (PC), a wearable device, a healthcare device, or an Internet Of Things (IoT) device. It can be. Also, the system 3000 may be implemented as a server or a personal computer.

The camera 3100 may capture a still image or a moving image under user control, and may store or transmit the captured image/video data to the display 3200 . The audio processing unit 3300 may process audio data included in the flash memory devices 3600a and 3600b or contents of the network. The modem 3400 modulates and transmits a signal for wired/wireless data transmission and reception, and can demodulate it to restore the original signal at the receiving side. The I/O devices 3700a and 3700b are digital inputs such as USB (Universal Serial Bus), storage, digital cameras, SD (Secure Digital) cards, DVDs (Digital Versatile Disc), network adapters, and touch screens. and/or devices that provide an output function.

The AP 3800 may control overall operations of the system 3000. The AP 3800 may control the display 3200 to display a portion of content stored in the flash memory devices 3600a and 3600b on the display 3200 . When a user input is received through the I/O devices 3700a and 3700b, the AP 3800 may perform a control operation corresponding to the user input. The AP 3800 may include a controller 3810 and an interface 3830, and may include an accelerator block, which is a dedicated circuit for AI (Artificial Intelligence) data calculation, or an accelerator chip separate from the AP 3800. (3820). A DRAM 3500b may be additionally mounted on the accelerator block or accelerator chip 3820 . Accelerator is a functional block that specializes in performing specific functions of the AP (3800). Accelerator is a functional block that specializes in graphic data processing, GPU, and AI calculation and inference. It can include the Neural Processing Unit (NPU), and the Data Processing Unit (DPU), a block that specializes in data transfer.

The system 3000 may include a plurality of DRAMs 3500a and 3500b. The AP 3800 controls the DRAMs 3500a and 3500b through command and mode register (MRS) settings that conform to the JEDEC (Joint Electron Device Engineering Council) standard, or provides company-specific functions such as low voltage/high speed/reliability and CRC ( In order to use Cyclic Redundancy Check (Cyclic Redundancy Check)/ECC (Error Correction Code) functions, DRAM interface rules can be set and communicated. For example, the AP 3800 can communicate with the DRAM 3500a through an interface conforming to JEDEC standards such as LPDDR4 and LPDDR5, and the accelerator block or accelerator chip 3820 is for an accelerator having a higher bandwidth than the DRAM 3500a. In order to control the DRAM 3500b, a new DRAM interface protocol can be established and communicated.

Although only the DRAMs 3500a and 3500b are shown in FIG. 16, they are not limited thereto, and if the bandwidth, response speed, and voltage conditions of the AP 3800 or the accelerator chip 3820 are satisfied, PRAM, SRAM, MRAM, RRAM, FRAM, or Hybrid RAM is shown. Any memory, such as the memory of The DRAMs 3500a and 3500b have a relatively smaller latency and bandwidth than the I/O devices 3700a and 3700b or the flash memories 3600a and 3600b. The DRAMs 3500a and 3500b are initialized when the system 3000 is powered on, and the operating system and application data are loaded and used as a temporary storage place for the operating system and application data or used as an execution space for various software codes. .

In the DRAMs 3500a and 3500b, addition/subtraction/multiplication/division operations, vector operations, address operations, or FFT (Fast Fourier Transform) operations may be performed. In addition, a function for execution used for inference may be performed within the DRAMs 3500a and 3500b. Here, inference may be performed in a deep learning algorithm using an artificial neural network. The deep learning algorithm may include a training step of learning a model through various data and an inference step of recognizing data with the learned model. As an embodiment, an image captured by a user through the camera 3100 is signal-processed and stored in the DRAM 3500b, and the accelerator block or accelerator chip 3820 is used for data stored in the DRAM 3500b and inference. It is possible to perform AI data operation that recognizes data using a function to be used.

The system 3000 may include a plurality of storage or a plurality of flash memories 3600a and 3600b having a larger capacity than the DRAMs 3500a and 3500b. The accelerator block or accelerator chip 3820 may perform a training step and AI data calculation using the flash memory devices 3600a and 3600b. In an embodiment, the flash memories 3600a and 3600b perform an inference with a training step performed by the AP 3800 and/or the accelerator chip 3820 using an arithmetic unit included in the memory controller 3610. AI data calculations can be performed more efficiently. The flash memories 3600a and 3600b may store pictures taken through the camera 3100 or data transmitted through a data network. For example, augmented reality/virtual reality, high definition (HD), or ultra high definition (UHD) content may be stored.

The flash memories 3600a and 3600b may include the inter-stack word line manager 129 described with reference to FIGS. 1 to 15 . The inter-stack word line management unit 129 may store channel hole profile information about word lines adjacent to an inter-stack region defined in a manufacturing process step. The inter-stack word line management unit 129 may determine some word lines adjacent to the inter-stack region among word lines of each of the memory stacks as inter-stack word lines based on the channel hole profile information. The inter-stack word line management unit 129 controls setup times for applying pass voltages to the inter-stack word lines differently according to the size of the channel hole of the inter-stack word lines, and equalizes the channel voltages of the plurality of memory stacks. can do. When the inter-stack word line management unit 129 sets up the inter-stack word lines to pass voltages, first sets up inter-stack word lines having a large channel hole size and sets up inter-stack word lines having a small channel hole size later. can do. The inter-stack word line management unit 129 performs a channel voltage equalization operation of a plurality of memory stacks while differently controlling recovery time points for applying ground voltage to the inter-stack word lines according to the size of the channel hole of the inter-stack word lines. can do. When the inter-stack word line manager 129 recovers the inter-stack word lines to the ground voltage, the inter-stack word line having a small channel hole size is recovered first and the inter-stack word line having a large channel hole size is recovered later. can do.

Although the present invention has been described with respect to a limited number of embodiments shown in the drawings, this is merely exemplary, and various changes and modifications from this to those of ordinary skill in the art, and other implementations equivalent thereto. It will be appreciated that examples are possible. Accordingly, the appended claims are intended to cover all such changes and modifications as fall within the true spirit and scope of this invention.

Claims (20)

A memory cell array including a plurality of cell strings in which a plurality of memory cells are disposed between a plurality of bit lines and a source line in a vertical direction, the memory cell array being divided into a plurality of memory stacks disposed in the vertical direction inter-stack regions are disposed between the plurality of memory stacks, word lines of the plurality of memory cells are stacked in the vertical direction on each of the plurality of memory stacks, and each of the plurality of memory stacks Channel holes pass through the word lines; and
Some of the word lines adjacent to the inter-stack regions among the word lines of each of the plurality of memory stacks are provided as inter-stack word lines, and the inter-stack word lines are provided according to sizes of the channel holes of the inter-stack word lines. - A control circuit performing a channel voltage equalization operation of the plurality of memory stacks while differently controlling setup times at which pass voltages are applied to stack word lines;
The pass voltage is set to a voltage at which the plurality of memory cells are always turned on. According to claim 1,
When setting up the inter-stack word lines to the pass voltage, the control circuit first sets up an inter-stack word line having a large channel hole size among the inter-stack word lines, and selects an inter-stack word line having a small channel hole size among the inter-stack word lines. A non-volatile memory device that sets up the stack wordlines later. According to claim 1,
The control circuit performs a channel voltage equalization operation of the plurality of memory stacks while differently controlling recovery time points for applying recovery voltages to the inter-stack word lines according to the size of the channel hole of the inter-stack word lines. volatile memory device. According to claim 3,
The recovery voltage is set to a ground voltage, an external power voltage applied to the nonvolatile memory device, or an internal power voltage generated from the external power voltage inside the nonvolatile memory device. According to claim 3,
When recovering the inter-stack word lines with the recovery voltage, the control circuit first recovers an inter-stack word line having a small channel hole size among the inter-stack word lines, and first recovers an inter-stack word line having a large channel hole size. A non-volatile memory device that recovers the stack wordlines at a later time. According to claim 1,
The plurality of memory stacks include a first memory stack, a second memory stack stacked on the first memory stack, and a first inter-stack region disposed between the first memory stack and the second memory stack,
The control circuit sets up a first inter-stack word line at an upper portion of the first memory stack adjacent to the first inter-stack region to the pass voltage at a first time point, and sets up a second inter-stack word line at a lower portion of the second memory stack adjacent to the first inter-stack region. A nonvolatile memory device that sets up a word line to the pass voltage at a second point in time after the first point in time. According to claim 6,
The control circuit performs a program, verification read, or read operation on a cell string selected from among the plurality of cell strings after the second point in time. According to claim 7,
The control circuit recovers the second inter-stack word line to a recovery voltage at a third point in time after the program, the verify read, or the read operation, and the first inter-stack word line at a fourth point in time after the third point in time. A nonvolatile memory device recovering a word line with the recovery voltage. According to claim 8,
The recovery voltage is set to a ground voltage, an external power voltage applied to the nonvolatile memory device, or an internal power voltage generated from the external power voltage inside the nonvolatile memory device. According to claim 1,
The plurality of memory stacks include a first memory stack, a second memory stack stacked on the first memory stack, and a first inter-stack region disposed between the first memory stack and the second memory stack,
The control circuit sets up a first inter-stack word line of an upper portion of the first memory stack adjacent to the first inter-stack region to the pass voltage at a first time point, and sets up a second inter-stack word line below the first inter-stack word line. An inter-stack word line is set up at the pass voltage at a second time point after the first time point, and a third inter-stack word line at the lower end of the second memory stack is set up at a third time point after the second time point. and setting up a fourth inter-stack word line above the third inter-stack word line to the pass voltage at a fourth point in time after the third point in time. According to claim 10,
The control circuit performs a program, verification read, or read operation on a cell string selected from among the plurality of cell strings after the fourth point in time. According to claim 11,
The control circuit recovers the second inter-stack word line to a recovery voltage at a fifth point in time after the program, the verify read, or the read operation, and the first inter-stack word line at a sixth point in time after the fifth point in time. The word line is recovered to the recovery voltage, the fourth inter-stack word line is recovered to the recovery voltage at a seventh time point after the sixth time point, and the third inter-stack word line is recovered at an eighth time point after the seventh time point. - A nonvolatile memory device that recovers a stack word line with the recovery voltage. Dividing a memory cell array including a plurality of cell strings in which a plurality of memory cells are disposed between a plurality of bit lines and a source line in a vertical direction into a plurality of memory stacks, wherein between the plurality of memory stacks inter-stack regions are disposed, word lines of the plurality of memory cells are stacked in the vertical direction in each of the plurality of memory stacks, and a channel hole passes through the word lines of each of the plurality of memory stacks;
providing some of the word lines adjacent to the inter-stack regions among the word lines of each of the plurality of memory stacks as inter-stack word lines; and
performing a channel voltage equalization operation of the plurality of memory stacks while differently controlling setup times for applying pass voltages to the inter-stack word lines according to sizes of the channel holes of the inter-stack word lines;
The pass voltage is set to a voltage at which the plurality of memory cells are always turned on. 14. The method of claim 13, wherein the method of operating the nonvolatile memory device comprises:
and storing, in the nonvolatile memory device, channel hole profile information for some of the word lines adjacent to the inter-stack regions defined in the manufacturing process of the nonvolatile memory device. method. 15. The method of claim 14, wherein the method of operating the nonvolatile memory device comprises:
and determining some of the word lines adjacent to the inter-stack regions as the inter-stack word lines based on the channel hole profile information. According to claim 13,
The step of performing the channel voltage equalization operation of the plurality of memory stacks,
The step of setting up an inter-stack word line having a large channel hole among the inter-stack word lines to the pass voltage first and setting an inter-stack word line having a small channel hole to the pass voltage later. A method of operating a nonvolatile memory device that According to claim 13,
The plurality of memory stacks include a first memory stack, a second memory stack stacked on the first memory stack, and a first inter-stack region disposed between the first memory stack and the second memory stack,
The step of performing the channel voltage equalization operation of the plurality of memory stacks,
setting up a first inter-stack word line at an upper portion of the first memory stack adjacent to the first inter-stack region to the pass voltage at a first time point; and
and setting up a second inter-stack word line at the lower end of the second memory stack to the pass voltage at a second point in time after the first point in time. 18. The method of claim 17, wherein the method of operating the nonvolatile memory device comprises:
The method of operating a nonvolatile memory device further comprising performing a program, verify read, or read operation on a cell string selected from among the plurality of cell strings after the second point in time. According to claim 13,
The plurality of memory stacks include a first memory stack, a second memory stack stacked on the first memory stack, and a first inter-stack region disposed between the first memory stack and the second memory stack,
The step of performing the channel voltage equalization operation of the plurality of memory stacks,
setting up a first inter-stack word line of an upper portion of the first memory stack adjacent to the first inter-stack region to a pass voltage at a first time point;
setting up a second inter-stack word line under the first inter-stack word line to the pass voltage at a second time point after the first time point;
setting up a third inter-stack word line at a lower end of the second memory stack adjacent to the first inter-stack region to the pass voltage at a third point in time after the second point in time; and
and setting up a fourth inter-stack word line above the third inter-stack word line to the pass voltage at a fourth time point after the third time point. 20. The method of claim 19, wherein the method of operating the nonvolatile memory device comprises:
The method of operating a nonvolatile memory device further comprising performing a program, verify read, or read operation on a cell string selected from among the plurality of cell strings after the fourth point in time.

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