KR20230056521A - Sub-sampling phase locked loop with compensated loop bandwidth and integrated circuit including the same - Google Patents

Abstract

A sub-sampling phase-locked loop comprises a slope generation and sampling circuit, first and second transconductance circuits, a static transconductance bias circuit, a loop filter, and a voltage-controlled oscillator. The slope generation and sampling circuit generates a sampling voltage based on a reference clock signal and an output clock signal. The first and second transconductance circuits generate first and second output control voltages, respectively, based on the sampling voltage, a reference voltage, and a control current. The static transconductance bias circuit generates the control current and includes a switched capacitor resistor. The loop filter is connected to the output terminals of the first and second transconductance circuits. The voltage-controlled oscillator generates an output clock signal based on the first and second output control voltages. The sub-sampling phase-locked loop may have enhanced performance.

Description

Sub-sampling phase-locked loop with loop bandwidth compensated and an integrated circuit including the same

The present invention relates to a semiconductor integrated circuit, and more particularly, to a sub-sampling phase-locked loop with a compensated loop bandwidth and an integrated circuit including the sub-sampling phase-locked loop.

Despite improvements in the speed and data transfer rate of peripheral devices such as memory, communication devices, or graphics devices, the operating speed of peripheral devices has not been able to catch up with the operating speed of processors, and there is always a speed gap between new processors and their peripheral devices. Differences have existed. Therefore, in a high-performance digital system, significant speed improvement of peripheral devices has been required.

For example, in an I/O method in which data is transmitted in synchronization with a clock signal, such as data transmission between a memory device and a memory controller, it is very important to achieve temporal synchronization between the clock signal and data as the bus load increases and the transmission frequency increases. do. Circuits that can be used for this purpose include a Phase Locked Loop (PLL) and a Delay Locked Loop (DLL). These phase locked loops and delay locked loops are used in various application circuits.

One object of the present invention is to provide a sub-sampling phase-locked loop having a loop bandwidth in which an effect of a PVT (process, voltage, temperature) variation is compensated for.

Another object of the present invention is to provide an integrated circuit including the subsampling phase locked loop.

In order to achieve the above object, a subsampling phase locked loop according to embodiments of the present invention includes a slope generation and sampling circuit, a first transconductance (Gm) circuit, a second transconductance circuit, and a constant transconductance bias. (bias) circuit, loop filter and voltage controlled oscillator. The slope generation and sampling circuit generates a sampling voltage based on a reference clock signal and an output clock signal. The first transconductance circuit generates a first output control voltage based on the sampling voltage, reference voltage and control current. The second transconductance circuit generates a second output control voltage based on the sampling voltage, the reference voltage and the control current. The static transconductance bias circuit generates the control current and includes a switched capacitor resistor. The loop filter is connected to an output terminal of the first transconductance circuit and an output terminal of the second transconductance circuit. The voltage controlled oscillator generates the output clock signal based on the first output control voltage and the second output control voltage.

In order to achieve the above other object, an integrated circuit according to embodiments of the present invention includes a subsampling phase locked loop and an internal circuit. The subsampling phase locked loop generates an output clock signal based on a reference clock signal. The internal circuit operates based on the output clock signal. The subsampling phase locked loop includes a slope generating and sampling circuit, a first transconductance (Gm) circuit, a second transconductance circuit, a constant transconductance bias circuit, a loop filter and a voltage controlled oscillator. The slope generating and sampling circuit generates a sampling voltage based on the reference clock signal and the output clock signal. The first transconductance circuit generates a first output control voltage based on the sampling voltage, reference voltage and control current. The second transconductance circuit generates a second output control voltage based on the sampling voltage, the reference voltage and the control current. The static transconductance bias circuit generates the control current and includes a switched capacitor resistor. The loop filter is connected to an output terminal of the first transconductance circuit and an output terminal of the second transconductance circuit. The voltage controlled oscillator generates the output clock signal based on the first output control voltage and the second output control voltage.

In order to achieve the above object, a subsampling phase locked loop according to embodiments of the present invention includes a slope generation and sampling circuit, a constant transconductance bias circuit, a first transconductance (Gm) circuit, 2 Includes a transconductance circuit, loop filter and voltage controlled oscillator. The slope generation and sampling circuit includes a first resistor and a first capacitor, and generates a sampling voltage having a slope inversely proportional to the resistance of the first resistor and the capacitance of the first capacitor based on a reference clock signal and an output clock signal. generate The static transconductance bias circuit includes a switched capacitor resistor including a second capacitor and generates a control current proportional to a capacitance of the second capacitor. The first transconductance circuit generates a first output control voltage proportional to the resistance of the second resistor and the capacitance of the second capacitor based on the sampling voltage, the reference voltage and the control current. The second transconductance circuit generates a second output control voltage based on the sampling voltage, the reference voltage and the control current. The loop filter is connected to the output terminal of the first transconductance circuit and the output terminal of the second transconductance circuit, and includes the second resistor. The voltage controlled oscillator generates the output clock signal based on the first output control voltage and the second output control voltage. The first transconductance circuit and the second transconductance circuit form a proportional path and an integral path, respectively. Loop bandwidth is independent of the resistance of the first resistor, the capacitance of the first capacitor, the resistance of the second resistor, and the capacitance of the second capacitor, and is proportional only to the gain of the proportional path.

In the sub-sampling phase-locked loop and integrated circuit according to the embodiments of the present invention as described above, the static transconductance bias circuit is implemented by including the switched capacitor resistor, and the first transconductance circuit and the integration path are disposed on the proportional path. A second transconductance circuit disposed thereon, and the loop filter may be implemented by including a resistor connected to an output terminal of the first transconductance circuit. The influence of the distribution of resistors and capacitors included in the slope generation and sampling circuit on the loop bandwidth may be offset by the capacitor included in the switched capacitor resistor and the resistor included in the loop filter. Therefore, it is possible to have a loop bandwidth in which the influence of PVT fluctuation is compensated, that is, to be relatively insensitive to PVT fluctuation and to have an insensitive loop bandwidth, and thus to have improved performance.

1 is a block diagram illustrating a subsampling phase locked loop according to embodiments of the present invention.
2 is a circuit diagram illustrating an example of a slope generating and sampling circuit included in a subsampling phase locked loop according to embodiments of the present invention.
3A, 3B, 3C, and 3D are diagrams for explaining the operation of the slope generation and sampling circuit of FIG. 2 .
4 is a circuit diagram illustrating an example of a static transconductance bias circuit included in a subsampling phase locked loop according to embodiments of the present invention.
5A, 5B and 5C are diagrams for explaining the operation of the static transconductance bias circuit of FIG. 4 .
6 is a diagram illustrating an example of a first transconductance circuit, a second transconductance circuit, and a loop filter included in a subsampling phase locked loop according to embodiments of the present invention.
7A and 7B are diagrams for explaining the operation of the first transconductance circuit and the loop filter of FIG. 6 .
8 is a diagram illustrating performance of a subsampling phase locked loop according to embodiments of the present invention.
9 is a block diagram illustrating a sampling phase locked loop according to example embodiments.
10 is a flowchart illustrating a method of generating a clock signal according to embodiments of the present invention.
11 is a block diagram illustrating an integrated circuit according to example embodiments.
12 is a block diagram illustrating a digital processing system according to embodiments of the present invention.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in more detail. The same reference numerals are used for the same components in the drawings, and redundant descriptions of the same components are omitted.

1 is a block diagram illustrating a subsampling phase locked loop according to embodiments of the present invention.

Referring to FIG. 1, a sub-sampling phase locked loop (PLL) 100 includes a slope generation and sampling circuit 200, a first transconductance (Gm) circuit 300 , a second transconductance circuit 400, a constant transconductance bias circuit 500, a loop filter 600 and a voltage controlled oscillator (VCO) 700.

The slope generation and sampling circuit 200 generates the sampling voltage VSAMP based on the reference clock signal CLK_REF and the output clock signal CLK_VCO. The reference clock signal CLK_REF and the output clock signal CLK_VCO may respectively correspond to the input and output of the subsampling phase locked loop 100 . For example, the reference clock signal CLK_REF is generated using a crystal and has a fixed frequency. Accordingly, the frequency of the reference clock signal CLK_REF is the reference frequency (with respect to the frequency of the output clock signal CLK_VCO). For example, a target frequency) may be used.

The sampling voltage VSAMP may indicate a phase error between the reference clock signal CLK_REF and the output clock signal CLK_VCO. The slope generation and sampling circuit 200 generates a sampling voltage VSAMP representing the phase error based on a sampling operation, and uses a sampling based phase detector (PD) or phase frequency detector Detector; PFD).

In one embodiment, as will be described later with reference to FIGS. 3A , 3B and 3C , the sampling voltage VSAMP may have a relatively low first voltage level or a relatively high second voltage level. For example, when the phase of the reference clock signal CLK_REF leads the phase of the output clock signal CLK_VCO, that is, the phase of the output clock signal CLK_VCO lags behind the phase of the reference clock signal CLK_REF ( lag), a sampling voltage VSAMP having the first voltage level may be generated. When the phase of the reference clock signal CLK_REF lags behind the phase of the output clock signal CLK_VCO, that is, when the phase of the output clock signal CLK_VCO leads the phase of the reference clock signal CLK_REF , a sampling voltage VSAMP having the second voltage level may be generated.

The specific configuration and operation of the slope generating and sampling circuit 200 will be described later with reference to FIGS. 2 and 3 .

The static transconductance bias circuit 500 generates a control current ICTRL and provides it to the first transconductance circuit 300 and the second transconductance circuit 400 . The control current ICTRL may be used to drive the first transconductance circuit 300 and the second transconductance circuit 400 .

The static transconductance bias circuit 500 includes a switched capacitor resistor (SCR) 520 . For example, as described below with reference to FIG. 4 , the switched capacitor register 520 may include at least one capacitor and at least one switch.

A switched capacitor resistor is a type of switched capacitor and is the simplest switched capacitor. A switched capacitor is an electronic circuit element that implements a filter and works by moving charge in and out of the capacitor when the switches open and close. In general, signals that do not overlap in phase are used to control the switches, so not all switches may close simultaneously. A filter implemented with these components may be referred to as a "switched capacitor filter". Switched capacitors depend only on the ratio between capacitances to operate, and thus may be suitable for use in integrated circuits where it is not economical to construct with precisely specified resistors and capacitors.

A detailed configuration and operation of the static transconductance bias circuit 500 will be described later with reference to FIGS. 4 and 5 .

The first transconductance circuit 300 generates a first output control voltage VCTRL1 based on the sampling voltage VSAMP, the reference voltage VREF, and the control current ICTRL. The second transconductance circuit 400 generates a second output control voltage VCTRL2 based on the sampling voltage VSAMP, the reference voltage VREF, and the control current ICTRL. For example, the first transconductance circuit 300 forms a proportional path of the subsampling phase locked loop 100, and the second transconductance circuit 400 forms the integral of the subsampling phase locked loop 100. (integral) pathways can be formed.

The loop filter 600 is connected to the output terminal of the first transconductance circuit 300 and the output terminal of the second transconductance circuit 400 . The loop filter 600 may include a resistor RLF and a capacitor CLF. The resistor RLF may be connected between the output terminal of the first transconductance circuit 300 and the ground voltage VSS. The capacitor CLF may be connected between the output terminal of the second transconductance circuit 400 and the ground voltage VSS. The loop filter 600 may have a structure in which the resistor RLF and the capacitor CLF are separated from each other. Depending on embodiments, the loop filter 600 may also remove glitches and eliminate jitter by preventing voltage overshoot.

The static transconductance bias circuit 500, the first transconductance circuit 300 and the second transconductance circuit 400 may form a charge pump. For example, the charge pump may source the current output from the power source (ie, the control current ICTRL) to an output terminal based on the sampling voltage VSAMP or sink the current from the output terminal to the ground. can For example, the loop filter 600 may increase/decrease voltages (ie, the first output control voltage VCTRL1 and the second output control voltage VCTRL2 ) according to the sourcing/sinking current.

Detailed configurations and operations of the first transconductance circuit 300, the second transconductance circuit 400, and the loop filter 600 will be described later with reference to FIGS. 6 and 7.

The voltage controlled oscillator 700 generates the output clock signal CLK_VCO based on the first output control voltage VCTRL1 and the second output control voltage VCTRL2. For example, the voltage controlled oscillator 700 may include a ring oscillator, an RC oscillator, a crystal oscillator, or a temperature compensated crystal oscillator, but is not limited thereto.

In one embodiment, the output frequency of the output clock signal CLK_VCO may be FVCO=Kp*VCTRL1+Ki*VCTRL2 (where Kp is the gain of the proportional path and Ki is the gain of the integral path).

The phase locked loop performs a function of generating an output clock signal having an output frequency different from the input frequency by multiplying the input frequency of the input clock signal. In this case, phase noise of the output frequency is generated by properly filtering the phase noise of the input frequency, and its performance may be influenced by the structure of the phase-locked loop. One of the factors that greatly affect the phase noise performance of the output frequency is the loop bandwidth (BW), which is determined by parameters that determine the transfer function of blocks included in the phase-locked loop. can

The sub-sampling phase-locked loop is a type of phase-locked loop, and may operate by sampling an output clock signal using an input clock signal (or a reference clock signal). The sub-sampling phase-locked loop can operate without using a divider when the ratio of the output frequency of the output clock signal divided by the input frequency of the input clock signal is an integer, and therefore can be widely used. .

In general, a subsampling phase locked loop is implemented by including a slope generator and a sampling circuit, and the slope generator and sampling circuit may be implemented by including a resistor and a capacitor. In this case, the loop bandwidth of the sub-sampling phase-locked loop can be expressed as a function of the resistance of the resistor and the capacitance of the capacitor of the slope generating circuit and the sampling circuit. Resistors and capacitors, as passive devices, have a relatively large dispersion when produced in a semiconductor process, and thus have a relatively large dispersion in the loop bandwidth of the subsampling phase-locked loop.

In the subsampling phase locked loop 100 according to embodiments of the present invention, the static transconductance bias circuit 500 is implemented by including the switched capacitor resistor 520 and the first transconductance circuit disposed on the proportional path. 300 and a second transconductance circuit 400 disposed on the integration path, and the loop filter 600 may be implemented by including a resistor RLF connected to an output terminal of the first transconductance circuit 300. can The effect of the distribution of the resistor and capacitor included in the slope generation and sampling circuit 200 on the loop bandwidth is offset by the capacitor included in the switched capacitor resistor 520 and the resistor RLF included in the loop filter 600. can Therefore, the sub-sampling phase locked loop 100 has a loop bandwidth in which the effect of PVT (process, voltage, temperature) variation is compensated, that is, is relatively insensitive to PVT variation and is insensitive, thereby improving performance. can have

2 is a circuit diagram illustrating an example of a slope generating and sampling circuit included in a subsampling phase locked loop according to embodiments of the present invention.

Referring to FIG. 2 , the slope generation and sampling circuit 202 may include a first circuit unit 210 and a second circuit unit 220 .

The first circuit unit 210 is connected between the power voltage VDD and the ground voltage VSS and operates based on the output clock signal CLK_VCO. The first circuit unit 210 may include transistors TS1 and TS2 and a resistor RS.

Transistor TS1, resistor RS, and transistor TS2 may be connected in series between power supply voltage VDD and ground voltage VSS. For example, the transistor TS1 is connected between the power supply voltage VDD and the node NS1, the resistor RS is connected between the node NS1 and the node NS2, and the transistor TS2 is connected to the node ( NS2) and the ground voltage VSS may be connected in series. The gate electrode of the transistor TS1 and the gate electrode of the second transistor TS2 may receive the output clock signal CLK_VCO.

In one embodiment, the transistor TS1 may be a P-type metal oxide semiconductor (PMOS) transistor, and the transistor TS2 may be an N-type metal oxide semiconductor (NMOS) transistor. However, the present invention may not be limited thereto.

The second circuit unit 220 is connected to the first circuit unit 210 and the ground voltage VSS, operates based on the reference clock signal CLK_REF, and outputs a sampling voltage VSAMP. The second circuit unit 220 includes switches SWS1 and SWS2 and capacitors CS1 and CS2 and may further include an inverter INV.

The inverter INV may generate an inverted reference clock signal /CLK_REF obtained by inverting the reference clock signal CLK_REF. Depending on embodiments, the inverter INV may be disposed outside the second circuit unit 220 or outside the slope generation and sampling circuit 202 .

The switch SWS1 is connected between the register RS and the node NS3, and may be connected between the node NS2 and NS3 connected to the register RS. A switch SWS2 may be connected between nodes NS3 and NS4. The sampling voltage VSAMP may be output through the node NS4. Capacitor CS1 may be connected between node NS3 and ground voltage VSS. Capacitor CS2 may be connected between node NS4 and ground voltage VSS.

The switch SWS1 may be turned on/off based on the reference clock signal CLK_REF. The switch SWS2 may be turned on/off based on the inverted reference clock signal /CLK_REF. For example, the switch SWS1 is turned on and closed when the reference clock signal CLK_REF has a first logic level (eg, a logic high level), and the reference clock signal CLK_REF has a second logic level. level (eg, logic low level), it can be turned off and opened (open). For example, the switch SWS2 is turned on and closed when the inverted reference clock signal /CLK_REF has the first logic level, and the inverted reference clock signal /CLK_REF has the second logic level. In this case, it can be turned off and opened (open). In other words, the switches SWS1 and SWS2 may be turned on/off complementarily.

In one embodiment, the switches SWS1 and SWS2 may be implemented by including at least one transistor.

3A, 3B, 3C, and 3D are diagrams for explaining the operation of the slope generation and sampling circuit of FIG. 2 .

Referring to FIG. 3A , the output clock signal CLK_VCO generated and output from the subsampling phase locked loop 100 may be a sine wave having an amplitude and a direct current (DC) voltage VDC. , may be sampled based on the reference clock signal CLK_REF by the slope generation and sampling circuit 202. When the output clock signal CLK_VCO and the reference clock signal CLK_REF are phase-aligned and there is no phase error, the voltage level of the sampling voltage VSAMP is equal to the DC voltage VDC of the output clock signal CLK_VCO. It may have a constant value such as a voltage level. For example, the voltage level of the DC voltage VDC may be the same as that of the reference voltage VREF applied to the first transconductance circuit 300 and the second transconductance circuit 400 .

Referring to FIG. 3B, when the phase of the reference clock signal CLK_REF leads the phase of the output clock signal CLK_VCO, that is, the phase of the output clock signal CLK_VCO is greater than the phase of the reference clock signal CLK_REF. In the case of lag, a first phase error PE1 exists between the output clock signal CLK_VCO and the reference clock signal CLK_REF, and the sampling voltage VSAMP is lower than the voltage level of the DC voltage VDC. 1 voltage level. For example, the first voltage difference VD1 between the voltage level of the sampling voltage VSAMP and the voltage level of the DC voltage VDC is the first phase error between the output clock signal CLK_VCO and the reference clock signal CLK_REF. (PE1). When the voltage level of the sampling voltage VSAMP is lower than that of the DC voltage VDC, the phase of the output clock signal CLK_VCO may be adjusted in the first direction based on the sampling voltage VSAMP.

Referring to FIG. 3C , when the phase of the reference clock signal CLK_REF lags the phase of the output clock signal CLK_VCO, that is, the phase of the output clock signal CLK_VCO is greater than the phase of the reference clock signal CLK_REF. In the case of leading, a second phase error PE2 exists between the output clock signal CLK_VCO and the reference clock signal CLK_REF, and the sampling voltage VSAMP has a voltage level higher than that of the DC voltage VDC. It can have 2 voltage levels. For example, the second voltage difference VD2 between the voltage level of the sampling voltage VSAMP and the voltage level of the DC voltage VDC is the second phase error between the output clock signal CLK_VCO and the reference clock signal CLK_REF. (PE2). When the voltage level of the sampling voltage VSAMP is higher than that of the DC voltage VDC, the phase of the output clock signal CLK_VCO moves in a second direction opposite to the first direction based on the sampling voltage VSAMP. can be regulated.

Referring to FIG. 3D , VNS2 represents the voltage of the node NS2 of FIG. 2 , SLP represents the slope of the sampling voltage VSAMP, and SLP=Y/X. The slope SLP of the sampling voltage VSAMP, which is a small signal voltage generated by the voltage VNS2 of the node NS2, is the slope generation and sampling circuit of FIG. 2 as shown in [Equation 1] below. It may be inversely proportional to the resistance of the resistor RS included in 202 and inversely proportional to the capacitance of the capacitors CS1 and CS2 included in the slope generating and sampling circuit 202 of FIG. 2 .

[Equation 1]

In the above [Equation 1], R1 represents the resistance of the resistor RS, and C1 represents the capacitance of the capacitors CS1 and CS2. For example, C1 may be determined based on at least one of the capacitors CS1 and CS2. For example, C1 may correspond to the capacitance of one of the capacitors CS1 and CS2 (eg, the capacitance of the capacitor CS1), or may correspond to the capacitance of both capacitors CS1 and CS2 (eg, the capacitance of the capacitor CS1). (average capacitance of CS1 and CS2).

Although the exemplary structure and operation of the slope generation and sampling circuit 202 have been described with reference to FIGS. 2 and 3, the present invention is not limited thereto, and the structure of the slope generation and sampling circuit 200 may vary according to embodiments. can be changed.

4 is a circuit diagram illustrating an example of a static transconductance bias circuit included in a subsampling phase locked loop according to embodiments of the present invention.

Referring to FIG. 4 , the static transconductance bias circuit 502 may include a first circuit unit 510 , a switched capacitor resistor 522 and a second circuit unit 530 .

The first circuit unit 510 may be connected between the power supply voltage VDD and the ground voltage VSS. The first circuit unit 510 may include transistors TB1 , TB2 , TB3 , and TB4 .

Transistors TB1 and TB2 may be connected in series between the power supply voltage VDD and the ground voltage VSS. For example, the transistor TB1 may be connected between the power supply voltage VDD and the node NB1, and the transistor TB2 may be connected between the node NB1 and the ground voltage VSS. Transistors TB3 and TB4 may be connected in series between the power supply voltage VDD and the node NB3. For example, transistor TB3 may be connected between power supply voltage VDD and node NB2 , and transistor TB4 may be connected between node NB2 and node NB3 . The gate electrode of the transistor TB1 and the gate electrode of the transistor TB3 may be connected to each other and to the node NB2. The gate electrode of the transistor TB2 and the gate electrode of the transistor TB4 may be connected to each other and connected to the node NB1.

In one embodiment, transistors TB1 and TB3 may each be PMOS transistors, and transistors TB2 and TB4 may each be NMOS transistors. However, the present invention may not be limited thereto.

The switched capacitor resistor 522 is connected between the first circuit unit 510 and the ground voltage VSS, and may be connected between the node NB3 connected to the first circuit unit 510 and the ground voltage VSS. The switched capacitor register 522 may operate based on the first phase signal PH1 and the second phase signal PH2. The switched capacitor resistor 522 may include switches SWB1 and SWB2 and a capacitor CGm.

A switch SWB1 may be connected between nodes NB3 and NB4. Capacitor CGm may be connected between node NB4 and ground voltage VSS. The switch SWB2 may be connected in parallel with the capacitor CGm between the node NB4 and the ground voltage VSS.

The switch SWB1 may be turned on/off based on the first phase signal PH1. The switch SWB2 may be turned on/off based on the second phase signal PH2. For example, the switch SWB1 is turned on and closed when the first phase signal PH1 has a first logic level (eg, a logic high level), and the first phase signal PH1 is closed. When it has 2 logic levels (eg, a logic low level), it can be turned off and opened (open). For example, the switch SWB2 is turned on and closed when the second phase signal PH2 has the first logic level, and is closed when the second phase signal PH2 has the second logic level. It can be turned off and open.

In one embodiment, the switches SWB1 and SWB2 may be implemented by including at least one transistor.

The second circuit unit 530 is connected to the power supply voltage VDD and the first circuit unit 510 and may output a control current ICTRL. The second circuit unit 530 may include a transistor TB5 .

Transistor TB5 may be connected between power supply voltage VDD and node NB5. The control current ICTRL may be output through the node NB5 . The gate electrode of the transistor TB5 may be connected to the gate electrode of the transistor TB1 and the gate electrode of the transistor TB3.

In one embodiment, transistor TB5 may be a PMOS transistor. However, the present invention may not be limited thereto.

Unlike the static transconductance bias circuit included in the conventional sub-sampling phase-locked loop, the static transconductance bias circuit 502 included in the sub-sampling phase-locked loop 100 according to the embodiments of the present invention is a switched capacitor resistor ( 522) may be further included.

5A, 5B and 5C are diagrams for explaining the operation of the static transconductance bias circuit of FIG. 4 .

Referring to FIG. 5A , the first phase signal PH1 and the second phase signal PH2 applied to the switched capacitor resistor 522 of FIG. 4 are illustrated.

The activation period TA1 of the first phase signal PH1 and the activation period TA2 of the second phase signal PH2 do not overlap, and thus the switches SWB1 and SWB2 are not simultaneously turned on (that is, not closed). may not be

Switched capacitor resistor 522 is the simplest switched capacitor. The switched capacitor register 522 is composed of one capacitor CGm and two switches SWB1 and SWB2, and converts the capacitor CGm according to a given frequency (that is, according to the phase signals PH1 and PH2). can be alternately connected to the input and output of the switched capacitor resistor 522. In each switching cycle, charge q may be transferred from the input to the output according to the switching frequency f. In a typical capacitor, it has a relationship of q = C * V (where C is the capacitance of the capacitor and V is the voltage across the capacitor), and based on this, the operation of the switched capacitor resistor 522 will be described.

First, in the switched capacitor register 522, while one (eg, SWB1) of the switches SWB1 and SWB2 is closed and the other one (SWB2) is open, the charge input to and stored in the capacitor CGm is q1 = CGm*V1, where V1 is the input voltage of the switched capacitor resistor 522. Next, while one (eg, SWB1) of the switches SWB1 and SWB2 is open and the other (SWB2) is closed, a portion of the charge (ie, q1) stored in the capacitor CGm is transferred to the capacitor CGm. The charge that is transferred out and then remains in the capacitor CGm may be q2=CGm*V2 (where V2 is the output voltage of the switched capacitor resistor 522). Accordingly, the charge transferred from the capacitor CGm to the output may be q3=q1-q2=CGm*(V1-V2). Charge q3 moves at the rate of the switching frequency f, so the charge transfer rate per unit time is ISCR=q*f=CGm*(V1-V2)*f, and the continuous movement of charge from one node to another is the current Since it corresponds to , it is expressed as "I", which is the symbol of current. The voltage across the input to output of the switched capacitor resistor 522 is VSCR=V1-V2, so the equivalent resistance (i.e. voltage-current relationship) can be RSCR=VSCR/ISCR=1/(CGm*f) . Accordingly, the switched capacitor resistor 522 may operate as a resistor whose resistance varies according to the capacitance of the capacitor CGm and the switching frequency f.

Because the switched capacitor resistor 522 is easier to manufacture reliably in a wide range of values, it can be used as a replacement for simple resistors in integrated circuits. In addition, the switched capacitor resistor 522 may also have an advantage of being able to adjust the resistance by changing the switching frequency f (ie, it may be a programmable resistor).

Referring to FIG. 5B, the relationship between the current level of the control current ICTRL generated in the static transconductance bias circuit 502 of FIG. 4 and the capacitance of the capacitor CGm included in the switched capacitor resistor 522 of FIG. is foreshadowing As shown in FIG. 5B , the current level of the control current ICTRL may be proportional to the capacitance of the capacitor CGm. In other words, as the capacitance of the capacitor CGm increases, the current level of the control current ICTRL also increases, and as the capacitance of the capacitor CGm decreases, the current level of the control current ICTRL also decreases.

Referring to FIG. 5C, the current level of the control current ICTRL generated in the static transconductance bias circuit 502 of FIG. 4 over time is illustrated. As shown in FIG. 5C , the current level of the control current ICTRL may always be constant regardless of the passage of time. In other words, the static transconductance bias circuit 502 can operate as a constant current source.

Although the exemplary structure and operation of the static transconductance bias circuit 502 have been described with reference to FIGS. 4 and 5, the present invention is not limited thereto, and the structure of the static transconductance bias circuit 500 may vary according to embodiments. can be changed.

6 is a diagram illustrating an example of a first transconductance circuit, a second transconductance circuit, and a loop filter included in a subsampling phase locked loop according to embodiments of the present invention.

Referring to FIG. 6 , a first transconductance circuit (GmP) 302 corresponds to the first transconductance circuit 300 of FIG. 1, and a second transconductance circuit (GmI) 402 corresponds to the second transconductance circuit (GmI) 402 of FIG. Corresponds to the transconductance circuit 400, and the resistor RLF and the capacitor CLF may correspond to the resistor RLF and the capacitor CLF included in the loop filter 600 of FIG. 1, respectively.

The first transconductance circuit 302 includes a first input terminal (eg, a positive (+) input terminal) receiving the sampling voltage VSAMP and a second input terminal (eg, a positive (+) input terminal) receiving the reference voltage VREF. For example, it may include a negative (-) input terminal), be driven based on the control current ICTRL, and generate a first output control voltage VCTRL1. The resistor RLF may be connected between an output terminal of the first transconductance circuit 302 outputting the first output control voltage VCTRL1 and the ground voltage VSS. The first transconductance circuit 302 and the resistor RLF may form a proportional path of the subsampling phase locked loop 100 .

The second transconductance circuit 402 includes a first input terminal (eg, a positive (+) input terminal) receiving the reference voltage VREF and a second input terminal (eg, a positive (+) input terminal) receiving the sampling voltage VSAMP. For example, a negative (-) input terminal) may be driven based on the control current ICTRL, and the second output control voltage VCTRL2 may be generated. The capacitor CLF may be connected between an output terminal of the second transconductance circuit 402 outputting the second output control voltage VCTRL2 and the ground voltage VSS. The second transconductance circuit 402 and the capacitor CLF may form an integration path of the subsampling phase locked loop 100 .

Configurations of the first transconductance circuit 302 and the second transconductance circuit 402 are variously changed according to embodiments, and the present invention may not be limited to a transconductance circuit having a specific structure. In one embodiment, the first transconductance circuit 302 and the second transconductance circuit 402 may have the same configuration. In other embodiments, the first transconductance circuit 302 and the second transconductance circuit 402 may have different configurations.

In the loop filter included in the conventional sub-sampling phase-locked loop, a resistor and a capacitor are directly connected to each other, but unlike the loop filter 600 included in the sub-sampling phase-locked loop 100 according to the embodiments of the present invention, the dual It has a dual loop structure, and the resistor (RLF) and the capacitor (CLF) may be implemented separately from each other without being directly connected. In addition, the conventional sub-sampling phase-locked loop includes only one transconductance circuit, but unlike the sub-sampling phase-locked loop 100 according to the embodiments of the present invention, two transconductance circuits 302, 302, 402), each transconductance circuit capable of driving one of the discrete components (ie resistor RLF and capacitor CLF) of loop filter 600. For example, the first transconductance circuit 302 may drive the resistor RLF and the second transconductance circuit 402 may drive the capacitor CLF.

7A and 7B are diagrams for explaining the operation of the first transconductance circuit and the loop filter of FIG. 6 .

Referring to FIG. 7A , the voltage level of the first output control voltage VCTRL1 generated by the first transconductance circuit 302 of FIG. 6 and the resistance of the resistor RLF included in the loop filter 600 of FIG. 6 are exemplifies the relationship. As shown in FIG. 7A , the voltage level of the first output control voltage VCTRL1 may be proportional to the resistance of the resistor RLF. In other words, as the resistance of the resistor RLF increases, the voltage level of the first output control voltage VCTRL1 also increases, and as the resistance of the resistor RLF decreases, the voltage level of the first output control voltage VCTRL1 also decreases. can

Referring to FIG. 7B , the voltage level of the first output control voltage VCTRL1 generated by the first transconductance circuit 302 of FIG. 6 and the capacitance of the capacitor CGm included in the switched capacitor resistor 522 of FIG. 4 exemplifies the relationship between As described above with reference to FIG. 5B, the voltage level of the control current ICTRL used to drive the first transconductance circuit 302 is proportional to the capacitance of the capacitor CGm. 1 The voltage level of the output control voltage VCTRL1 may be proportional to the capacitance of the capacitor CGm. In other words, as the capacitance of the capacitor CGm increases, the voltage level of the first output control voltage VCTRL1 also increases, and as the capacitance of the capacitor CGm decreases, the voltage level of the first output control voltage VCTRL1 also decreases. can

Specifically, assuming that the resistor RLF has the same resistance, when the capacitor CGm has the first capacitance CGm1, the voltage level of the first output control voltage VCTRL1 is equal to the second capacitance of the capacitor CGm. In the case of having (CGm2), it is lower than the voltage level of the first output control voltage VCTRL1, and in this case, the first capacitance CGm1 may be smaller than the second capacitance CGm2. In addition, when the capacitor CGm has the second capacitance CGm2, the voltage level of the first output control voltage VCTRL1 is the first output control voltage (VCTRL1) when the capacitor CGm has the third capacitance CGm3. VCTRL1), and at this time, the second capacitance CGm2 may be smaller than the third capacitance CGm3. In other words, CGm1<CGm2<CGm3, and thus VCTRL1(CGm1)<VCTRL1(CGm2)<VCTRL1(CGm3).

As described above with reference to FIGS. 7A and 7B , the voltage level of the first output control voltage VCTRL1 is the resistance of the resistor RLF included in the loop filter 600 of FIG. 6 as shown in [Equation 2] below. , and may be proportional to the capacitance of the capacitor CGm included in the switched capacitor resistor 522 of the static transconductance bias circuit 502 of FIG. 4 .

[Equation 2]

In [Equation 2] above, R2 represents the resistance of the resistor RLF, and C2 represents the capacitance of the capacitor CGm.

When the sub-sampling phase-locked loop includes only a slope generating and sampling circuit (e.g., 202 in FIG. 2), that is, a conventional sub-sampling phase-locked loop does not include a switched capacitor resistor 520 and includes only one transconductance circuit. In a fixed loop, the loop bandwidth (LBWc) may satisfy the following [Equation 3].

[Equation 3]

In the above [Equation 3], R1 and C1 are the resistance of the register (eg, RS in FIG. 2) and capacitors (eg, CS1 in FIG. 2), respectively, described with reference to [Equation 1] above. , CS2), and Kp represents the gain of the proportional path including the transconductance circuit.

As described above, when the sub-sampling phase-locked loop includes only the slope generation and sampling circuit 202, the loop bandwidth LBWc of the sub-sampling phase-locked loop is the resistance of the resistor RS and the capacitors CS1 and CS2. ), where the resistor RS and the capacitors CS1 and CS2 have a large (eg, about 20%) dispersion when produced in a semiconductor process as passive devices, and thus the subsampling The loop bandwidth LBWc of the phase-locked loop may have a large distribution corresponding to the product of the resistance of the resistor RS and the capacitance of the capacitors CS1 and CS2.

In contrast, when the subsampling phase locked loop 100 includes a switched capacitor resistor 522, two transconductance circuits 302 and 402, and a loop filter 600 according to embodiments of the present invention, that is, The loop filter 600 is implemented in a dual loop structure, and two transconductance circuits 302 and 402 isolated from each other are separated components of the loop filter 600 (ie, a resistor RLF and a capacitor CLF). ) and the static transconductance bias circuit 502 is implemented by including the switched capacitor resistor 522, the loop bandwidth LBWp may satisfy the following [Equation 4] and [Equation 5] .

[Equation 4]

[Equation 5]

In the above [Equation 4] and [Equation 5], R1 and C1 represent the resistance of the resistor RS and the capacitance of the capacitors CS1 and CS2, respectively, described with reference to [Equation 1] above, R2 and C2 represent the resistance of the resistor (RLF in FIG. 6) and the capacitance of the capacitor (CGm in FIG. 4), respectively, described with reference to [Equation 2] above, and Kp includes the first transconductance circuit 302 represents the gain of the proportional path.

As described above, the loop bandwidth (LBWp) of the subsampling phase locked loop 100 according to embodiments of the present invention may be proportional only to the gain (Kp) of the proportional path. In particular, as expressed in [Equation 4] above, the effect of the distribution of the resistor RS and the capacitors CS1 and CS2 included in the slope generation and sampling circuit 202 on the loop bandwidth LBWp is the switched capacitor It can be offset by the capacitor CGm included in the resistor 522 and the resistor RLF included in the loop filter 600 . As described above, it is possible to reduce the effect of external factors such as PVT on the loop bandwidth, and the subsampling phase-locked loop 100 is a loop in which the effect of PVT variation is compensated, that is, a loop that is relatively insensitive to and insensitive to PVT variation. bandwidth, and thus can have improved performance.

8 is a diagram illustrating performance of a subsampling phase locked loop according to embodiments of the present invention.

Referring to FIG. 8, CASE1 represents a conventional sub-sampling phase locked loop including only a slope generation and sampling circuit, and CASE2 represents a switched capacitor resistor 522, two transconductance circuits 302 and 402, and a loop filter ( 600) shows a subsampling phase locked loop 100 according to embodiments of the present invention. Thirty-three samples were prepared for each case, and the loop bandwidth of each sample was normalized to 1 and shown. The loop bandwidth of a conventional sub-sampling phase-locked loop has a distribution of about 0.94 to 1.12 (ie, a distribution of about 18%), but the loop bandwidth of the sub-sampling phase-locked loop 100 according to embodiments of the present invention is about It can be seen that it has a dispersion of 0.98 to 1.04 (ie, a dispersion of about 6%), and the loop bandwidth characteristic is significantly improved.

9 is a block diagram illustrating a sampling phase locked loop according to example embodiments.

Referring to FIG. 9 , the sampling phase locked loop 800 includes a slope generating and sampling circuit 200, a first transconductance circuit 300, a second transconductance circuit 400, a static transconductance bias circuit 500, It includes a loop filter (600) and a voltage controlled oscillator (700) and a divider (900).

The sampling phase locked loop 800 of FIG. 9 may be substantially the same as the subsampling phase locked loop 100 of FIG. 1 except that a divider 900 is further included and the operation of some components is changed accordingly. can

The divider 900 may divide the output clock signal CLK_VCO to generate the divided clock signal CLK_DIV. For example, the frequency of the divided clock signal CLK_DIV may be lower than the frequency of the output clock signal CLK_VCO.

In one embodiment, divider 900 may be an integer divider. For example, a division ratio of the divider 900, that is, a value obtained by dividing the frequency of the output clock signal CLK_VCO by the frequency of the divided clock signal CLK_DIV may be an integer. In another embodiment, divider 900 may be a fractional divider. For example, a division ratio of the divider 900, that is, a value obtained by dividing the frequency of the output clock signal CLK_VCO by the frequency of the divided clock signal CLK_DIV may be a real number.

The slope generating and sampling circuit 200 may generate the sampling voltage VSAMP based on the reference clock signal CLK_REF and the divided clock signal CLK_DIV. In this case, the sampling voltage VSAMP may indicate a phase error between the reference clock signal CLK_REF and the divided clock signal CLK_DIV.

The first transconductance circuit 300, the second transconductance circuit 400, the static transconductance bias circuit 500, the loop filter 600, and the voltage controlled oscillator 700 of FIG. 9 are respectively the first transconductance circuit of FIG. The conductance circuit 300, the second transconductance circuit 400, the static transconductance bias circuit 500, the loop filter 600 and the voltage controlled oscillator 700 are substantially the same, and are described above with reference to FIGS. 2 to 8. can be implemented as

In the sampling phase locked loop 800 according to embodiments of the present invention, the static transconductance bias circuit 500 is implemented by including the switched capacitor resistor 520 and the first transconductance circuit ( 300) and a second transconductance circuit 400 disposed on the integration path, and the loop filter 600 may be implemented by including a resistor RLF connected to an output terminal of the first transconductance circuit 300. there is. The effect of the distribution of the resistor and capacitor included in the slope generation and sampling circuit 200 on the loop bandwidth is offset by the capacitor included in the switched capacitor resistor 520 and the resistor RLF included in the loop filter 600. can Accordingly, the sampling phase-locked loop 800 has a loop bandwidth in which the influence of the PVT fluctuation is compensated for, that is, is relatively insensitive to the PVT fluctuation and is insensitive, and thus can have improved performance.

In one embodiment, some or all of the components of the sub-sampling phase-locked loop 100 and the sampling phase-locked loop 800 may be implemented in the form of hardware. For example, some or all of the components of the sub-sampling phase-locked loop 100 and the sampling phase-locked loop 800 may be included in a computer-based electronic system. In another embodiment, some or all of the components of the subsampling phase locked loop 100 and the sampling phase locked loop 800 may be implemented in software, eg, in the form of instruction codes or program routines. For example, the instruction codes or program routines may be executed by a computer-based electronic system and stored in any storage unit located inside or outside the computer-based electronic system.

10 is a flowchart illustrating a method of generating a clock signal according to embodiments of the present invention.

1 and 10, in a clock signal generation method according to embodiments of the present invention, a static transconductance bias circuit 500 includes a switched capacitor register 520 while performing a sampling-based phase detection operation. implemented, and includes a first transconductance circuit (300) disposed on a proportional path and a second transconductance circuit (400) disposed on an integral path, wherein the loop filter (600) is the first transconductance circuit (300) It can be performed by the sub-sampling phase locked loop 100 according to embodiments of the present invention, which is implemented including a register RLF connected to the output terminal of . A method of generating a clock signal may be described as a method of operating a subsampling phase locked loop.

In the clock signal generation method according to the embodiments of the present invention, the sampling voltage VSAMP is generated based on the reference clock signal CLK_REF and the output clock signal CLK_VCO (step S100). For example, step S100 is performed by the slope generating and sampling circuit 200 and may be performed as described above with reference to FIGS. 2 and 3 .

A control current ICTRL is generated using the static transconductance bias circuit 500 including a switched capacitor resistor (SCR) 520 (step S200). For example, step S200 may be performed as described above with reference to FIGS. 4 and 5 .

A first output control voltage VCTRL1 is generated using the resistor RLF included in the first transconductance circuit (GmP) 300 and the loop filter 600 (step S300). For example, the first output control voltage VCTRL1 may be generated based on the sampling voltage VSAMP, the reference voltage VREF, and the control current ICTRL. For example, step S200 may be performed as described above with reference to FIGS. 6 and 7 .

A second output control voltage VCTRL2 is generated using the second transconductance circuit (GmI) 400 and the capacitor CLF included in the loop filter 600 (step S400). For example, the second output control voltage VCTRL2 may be generated based on the sampling voltage VSAMP, the reference voltage VREF, and the control current ICTRL. Steps S300 and S400 may be performed substantially concurrently.

An output clock signal CLK_VCO is generated based on the first output control voltage VCTRL1 and the second output control voltage VCTRL2 (step S500). For example, step S500 may be performed by the voltage controlled oscillator 700 .

The effect of the distribution of the resistor and capacitor included in the slope generation and sampling circuit 200 on the loop bandwidth is offset by the capacitor included in the switched capacitor resistor 520 and the resistor RLF included in the loop filter 600. can Therefore, it is possible to have a loop bandwidth in which the influence of PVT fluctuation is compensated, that is, to be relatively insensitive to PVT fluctuation and to have an insensitive loop bandwidth, and thus to have improved performance.

Meanwhile, embodiments of the present invention may be implemented in the form of a product including a computer readable program code stored in a computer readable medium. The computer readable program code may be provided to processors of various computers or other data processing devices. The computer-readable medium may be a computer-readable signal medium or a computer-readable recording medium. The computer-readable recording medium may be any tangible medium capable of storing or including a program in or connected to an instruction execution system, equipment, or device. For example, the computer-readable medium may be provided in the form of a non-transitory storage medium. Here, non-temporary means that the storage medium does not contain a signal and is tangible, but does not distinguish whether data is stored semi-permanently or temporarily in the storage medium.

11 is a block diagram illustrating an integrated circuit according to example embodiments.

Referring to FIG. 11 , an integrated circuit 2000 includes a phase locked loop (SPLL) 2100 and an internal circuit 2200 .

The phase locked loop 2100 may be a subsampling phase locked loop ( 100 in FIG. 1 ) and/or a sampling phase locked loop ( 800 in FIG. 9 ) according to embodiments of the present invention. The phase-locked loop 2100 performs a sampling-based phase detection operation, the loop filter 600 is implemented as a dual loop structure, and two transconductance circuits 300 and 400 separated from each other are implemented as a loop filter 600. Driving separate components (ie, resistor RLF and capacitor CLF), the static transconductance bias circuit 500 may be implemented including a switched capacitor resistor 520. Accordingly, the effect of the distribution of the resistor and the capacitor on the loop bandwidth is offset, and the effect of the PVT variation is compensated, that is, a loop bandwidth that is relatively insensitive and insensitive to the PVT variation can be obtained, and thus improved performance can be obtained.

The internal circuit 2200 may operate based on the output frequency signal output from the phase locked loop 2100 or may perform other specific operations.

12 is a block diagram illustrating a digital processing system according to embodiments of the present invention.

Referring to FIG. 12 , a digital processing system 3000 may include a master device 3100 and slave devices 3200 , 3300 , 3400 , 3500 , 3600 , 3700 , 3800 , and 3900 .

In one embodiment, the digital processing system 3000 is a personal computer (PC), laptop (laptop), mobile phone (mobile phone), smart phone (smart phone), tablet (tablet) PC (tablet) PC, MP3 player, personal digital assistant (PDA) ), EDA (enterprise digital assistant), PMP (portable multimedia player), digital camera, music player, portable game console, navigation device, wearable device , IoT (internet of things) device, IoE (internet of everything:) device, e-book (e-book), VR (virtual reality) device, AR (augmented reality) device, etc. to be implemented as any electronic system can

The master device 3100 may be a controller circuit or processor that actively controls each of the slave devices 3200 , 3300 , 3400 , 3500 , 3600 , 3700 , 3800 , and 3900 . For example, the master device 3100 is a baseband modem processor chip, a chip that can perform both the function of a modem and the function of an application processor (AP), an AP, or a mobile AP. It may be implemented, but may not be limited thereto.

The slave devices 3200 , 3300 , 3400 , 3500 , 3600 , 3700 , 3800 , and 3900 may be arbitrary devices that passively operate under the control of the master device 3100 . For example, the slave devices 3200, 3300, 3400, 3500, 3600, 3700, 3800, and 3900 may include a radio frequency integrated circuit (RFIC) 3200, a power management integrated circuit (PMIC) 3300, and a power supply module. (power supply module) 3400, a second RFIC 3500, a sensor 3600, a fingerprint recognition chip 3700, a touch screen controller 3800, and a digital display interface (DDI) or A display driver integrated circuit (ICC) chip 3900 may be included.

The RFIC 3200 may include at least one connection chip. For example, the connection chip includes a chip 3210 for cellular, a chip 3220 for wireless local area network (WLAN) communication, a chip 3230 for Bluetooth (BT) communication, and GNSS (global navigation satellite system) communication chip 3240, FM (frequency modulation) audio/video signal processing chip 3250, NFC (near field communication) chip 3260, and/or Wi- It may include a chip for Fi communication, but may not be limited thereto.

RFIC 3200 may include at least one phase locked loop 3270. The phase locked loop 3270 may be a subsampling phase locked loop ( 100 in FIG. 1 ) and/or a sampling phase locked loop ( 800 in FIG. 9 ) according to embodiments of the present invention. The phase-locked loop 3270 performs a sampling-based phase detection operation, the loop filter 600 is implemented as a dual loop structure, and two transconductance circuits 300 and 400 separated from each other are implemented as loop filters 600. Driving separate components (ie, resistor RLF and capacitor CLF), the static transconductance bias circuit 500 may be implemented including a switched capacitor resistor 520. Accordingly, the effect of the distribution of the resistor and the capacitor on the loop bandwidth is offset, and the effect of the PVT variation is compensated, that is, a loop bandwidth that is relatively insensitive and insensitive to the PVT variation can be obtained, and thus improved performance can be obtained.

Depending on embodiments, the phase-locked loop 3270 may be formed to correspond to each connection chip.

Embodiments of the present invention may be advantageously used in any electronic device or system that includes a subsampling phase locked loop. For example, embodiments of the present invention may be used in personal computers (PCs), server computers, data centers, workstations, laptops, cellular phones, and smart phones. phone), MP3 player, PDA (Personal Digital Assistant), PMP (Portable Multimedia Player), digital TV, digital camera, portable game console, navigation device, wearable device, IoT (Internet It can be more usefully applied to electronic systems such as Things of Things (IoT) devices, Internet of Everything (IoE) devices, e-books, VR (Virtual Reality) devices, AR (Augmented Reality) devices, and drones. there is.

Although the above has been described with reference to preferred embodiments of the present invention, those skilled in the art can variously modify and change the present invention without departing from the spirit and scope of the present invention described in the claims below. you will understand that you can

Claims (20)

a slope generation and sampling circuit for generating a sampling voltage based on the reference clock signal and the output clock signal;
a first transconductance (Gm) circuit for generating a first output control voltage based on the sampling voltage, reference voltage and control current;
a second transconductance circuit generating a second output control voltage based on the sampling voltage, the reference voltage and the control current;
a constant transconductance bias circuit that generates the control current and includes a switched capacitor resistor;
a loop filter connected to an output terminal of the first transconductance circuit and an output terminal of the second transconductance circuit; and
and a voltage controlled oscillator configured to generate the output clock signal based on the first output control voltage and the second output control voltage. 2. The method of claim 1, wherein the static transconductance bias circuit comprises:
A first circuit unit connected between the power supply voltage and the ground voltage;
the switched capacitor resistor coupled between the first circuit unit and the ground voltage and operating based on a first phase signal and a second phase signal; and
and a second circuit unit connected to the power supply voltage and the first circuit unit and outputting the control current. The method of claim 2, wherein the switched capacitor resistor,
a first switch connected between a first node and a second node connected to the first circuit unit and turned on/off based on the first phase signal;
a first capacitor connected between the second node and the ground voltage; and
and a second switch connected in parallel with the first capacitor between the second node and the ground voltage and turned on/off based on the second phase signal. According to claim 3,
The subsampling phase locked loop, characterized in that the current level of the control current generated in the static transconductance bias circuit is proportional to the capacitance of the first capacitor. According to claim 3,
An active period of the first phase signal and an active period of the second phase signal do not overlap. The method of claim 3, wherein the first circuit unit,
a first transistor and a second transistor connected in series between the power supply voltage and the ground voltage; and
A third transistor and a fourth transistor connected in series between the power supply voltage and the first node;
A gate electrode of the first transistor and a gate electrode of the third transistor are connected to each other, and a gate electrode of the second transistor and a gate electrode of the fourth transistor are connected to each other. The method of claim 6, wherein the second circuit unit,
A fifth transistor connected between a third node outputting the power supply voltage and the control current;
A gate electrode of the fifth transistor is connected to a gate electrode of the first transistor and a gate electrode of the third transistor. The method of claim 3, wherein the loop filter,
a first resistor coupled between an output terminal of the first transconductance circuit and the ground voltage; and
and a second capacitor connected between the output terminal of the second transconductance circuit and the ground voltage. According to claim 8,
A voltage level of the first output control voltage generated in the first transconductance circuit is proportional to a resistance of the first resistor and proportional to a capacitance of the first capacitor. According to claim 1,
the first transconductance circuit forms a proportional path of the subsampling phase locked loop;
The second transconductance circuit forms an integral path of the subsampling phase locked loop. According to claim 10,
The sub-sampling phase-locked loop, characterized in that the loop bandwidth of the sub-sampling phase-locked loop is proportional to the gain of the proportional path. According to claim 10,
the first transconductance circuit includes a first input terminal receiving the sampling voltage and a second input terminal receiving the reference voltage;
wherein the second transconductance circuit includes a first input terminal receiving the reference voltage and a second input terminal receiving the sampling voltage. According to claim 10,
The subsampling phase locked loop, characterized in that the first transconductance circuit and the second transconductance circuit have the same configuration. According to claim 10,
The sub-sampling phase locked loop, characterized in that the first transconductance circuit and the second transconductance circuit have different configurations. The method of claim 1, wherein the slope generation and sampling circuit,
a first circuit unit connected between a power supply voltage and a ground voltage and operating based on the output clock signal; and
and a second circuit part connected to the first circuit part and the ground voltage, operating based on the reference clock signal, and outputting the sampling voltage. 16. The method of claim 15, wherein the first circuit unit,
A first transistor, a first resistor, and a second transistor connected in series between the power supply voltage and the ground voltage;
A gate electrode of the first transistor and a gate electrode of the second transistor receive the output clock signal. The method of claim 16, wherein the second circuit unit,
a first switch coupled between the first register and a first node and turned on/off based on the reference clock signal;
a second switch connected between the first node and a second node outputting the sampling voltage, and turned on/off based on an inverted reference clock signal obtained by inverting the reference clock signal;
a first capacitor connected between the first node and the ground voltage; and
and a second capacitor connected between the second node and the ground voltage. 18. The method of claim 17,
A slope of the sampling voltage is inversely proportional to the resistance of the first resistor and inversely proportional to the capacitances of the first and second capacitors. a subsampling phase locked loop for generating an output clock signal based on the reference clock signal; and
an internal circuit that operates based on the output clock signal;
The subsampling phase locked loop,
a slope generation and sampling circuit for generating a sampling voltage based on the reference clock signal and the output clock signal;
a first transconductance (Gm) circuit for generating a first output control voltage based on the sampling voltage, reference voltage and control current;
a second transconductance circuit generating a second output control voltage based on the sampling voltage, the reference voltage and the control current;
a constant transconductance bias circuit that generates the control current and includes a switched capacitor resistor;
a loop filter connected to an output terminal of the first transconductance circuit and an output terminal of the second transconductance circuit; and
and a voltage controlled oscillator configured to generate the output clock signal based on the first output control voltage and the second output control voltage. A slope generation and sampling circuit including a first resistor and a first capacitor and generating a sampling voltage having a slope inversely proportional to the resistance of the first resistor and the capacitance of the first capacitor based on a reference clock signal and an output clock signal. ;
a constant transconductance bias circuit including a switched capacitor resistor including a second capacitor and generating a control current proportional to a capacitance of the second capacitor;
a first transconductance (Gm) circuit generating a first output control voltage proportional to a resistance of a second resistor and a capacitance of the second capacitor based on the sampling voltage, the reference voltage, and the control current;
a second transconductance circuit generating a second output control voltage based on the sampling voltage, the reference voltage and the control current;
a loop filter connected to an output terminal of the first transconductance circuit and an output terminal of the second transconductance circuit, and including the second resistor; and
a voltage controlled oscillator configured to generate the output clock signal based on the first output control voltage and the second output control voltage;
the first transconductance circuit and the second transconductance circuit form a proportional path and an integral path, respectively;
Loop bandwidth is independent of the resistance of the first resistor, the capacitance of the first capacitor, the resistance of the second resistor, and the capacitance of the second capacitor, and is proportional only to the gain of the proportional path. phase locked loop.

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