KR20230047282A - Pixel of display device - Google Patents

Abstract

An objective of the present invention is to provide a pixel of a display device which can prevent a flicker phenomenon when a driving frequency is changed and realize high resolution. According to one embodiment of the present invention, the pixel of a display device comprises: a light emitting device; a first transistor connected between first power and a second node, and controlling a driving current supplied to the light emitting device in response to a voltage of a first node connected to a gate electrode; a first capacitor including one electrode connected to the first node and the other electrode connected to a third node; a second transistor connected between the third node and a data line; a third transistor connected between the first node and the second node; a sixth transistor connected between the first power and a fifth node connected to one electrode of the first transistor; a seventh transistor connected between the second node and a fourth node connected to an anode of the light emitting device; and a ninth transistor connected between the fifth node and bias power. The gate electrodes of the sixth transistor, the seventh transistor, and the ninth transistor are connected to the same light emission control line.

Description

Pixel of display device {PIXEL OF DISPLAY DEVICE}

The present invention relates to a pixel of a display device.

As information technology develops, the importance of a display device as a connection medium between a user and information is being highlighted.

The display device includes a plurality of pixels. Each of the pixels includes a plurality of transistors, a light emitting element electrically connected to the transistors, and a capacitor. The transistors are turned on in response to signals provided through wiring, thereby generating a predetermined driving current. The light emitting element emits light in response to this drive current.

Recently, in order to improve the driving efficiency of the display device and minimize power consumption, a method of driving the display device by varying the driving frequency is used. In particular, for high-speed driving, a method of separately driving a threshold voltage compensating period and a data writing period of a driving transistor included in each pixel is used.

However, such a driving method may cause problems such as flicker and image quality unevenness when the driving frequency is varied, and this is supplemented by adding a power source and a transistor supplied to the pixel circuit.

When the number of power supplies and transistors supplied to the pixel circuit increases, it is difficult to implement a high resolution, and since the number of scan drivers increases, a non-display area (or dead space) of the display panel may increase.

An object of the present invention is to provide a pixel of a display device capable of implementing high resolution while preventing flicker when a driving frequency is varied.

A pixel of a display device for solving the above problems is connected between a light emitting element, a first power supply, and a second node, and controls a driving current supplied to the light emitting element in response to a voltage of a first node connected to a gate electrode. A first capacitor including a first transistor, one electrode connected to the first node and the other electrode connected to a third node, a second transistor connected between the third node and a data line, the first node and the A third transistor connected between a second node, a sixth transistor connected between the first power source and a fifth node connected to one electrode of the first transistor, and a sixth transistor connected between the second node and the anode of the light emitting element. A seventh transistor connected between a fourth node and a ninth transistor connected between the fifth node and a bias power supply.

A gate electrode of each of the sixth transistor, the seventh transistor, and the ninth transistor is connected to the same emission control line.

An eighth transistor connected between the fourth node and an anode initialization power supply may be further included, and a gate electrode of the eighth transistor may be connected to the emission control line.

The sixth transistor and the seventh transistor may be P-type thin film transistors, and the eighth transistor and the ninth transistor may be N-type thin film transistors.

A fourth transistor connected between the first node and the initialization power supply, and a fifth transistor connected between the reference power supply and the third node may be further included.

The second transistor, the third transistor, the fourth transistor, the fifth transistor, the eighth transistor, and the ninth transistor may be N-type thin film transistors.

The second transistor is turned on by the first scan signal, the third transistor is turned on by the second scan signal, the fourth transistor is turned on by the third scan signal, and the fifth transistor is turned on by the third scan signal. The transistor is turned on by the second scan signal, the sixth transistor is turned off by the emission control signal, the seventh transistor is turned off by the emission control signal, and the eighth transistor is turned off by the emission control signal. is turned on by the light emission control signal, and the ninth transistor is turned on by the light emission control signal.

A second capacitor including one electrode connected to the first power source and the other electrode connected to the third node may be further included.

The device may further include a fourth transistor connected between the first node and the initialization power supply, and a fifth transistor connected between the first power supply and the third node.

The method may further include an eighth transistor connected between the fourth node and the initialization power supply, and a gate electrode of the eighth transistor may be connected to the emission control line.

A fourth transistor connected between the first node and the initialization power supply, a fifth transistor connected between the reference power supply and the third node, and an eighth transistor connected between the fourth node and the initialization power supply; , a gate electrode of the eighth transistor may be connected to the emission control line.

During a period in which the emission control signal is supplied, the third scan signal, the second scan signal, and the first scan signal may be sequentially provided.

When the eighth transistor is turned on by the light emission control signal, the voltage of the anode initialization power supply is supplied to the fourth node, and when the ninth transistor is turned on by the light emission control signal, the A voltage of the bias power supply may be supplied to a fifth node.

When the fourth transistor is turned on by the third scan signal, the voltage of the initialization power supply may be supplied to the first node.

When the third transistor is turned on by the second scan signal, the first node and the second node may have a diode connection.

When the ninth transistor is turned on by the emission control signal, the voltage of the first node may be a difference between the voltage of the bias power supply and the threshold voltage of the first transistor.

When the second transistor is turned on by the first scan signal, a data signal may be provided from the data line to the third node.

In a pixel of a display device according to an exemplary embodiment of the present invention, a pixel circuit is configured to include an N-type transistor and a P-type transistor, and some of the transistors are collectively controlled with an emission control signal instead of a scan signal, thereby reducing flicker when the driving frequency is varied. can be prevented and at the same time, high resolution can be implemented.

1 is a block diagram illustrating a display device according to example embodiments.
2 is a circuit diagram illustrating a pixel according to an exemplary embodiment of the present invention.
3A to 3E are waveform diagrams for explaining the operation of the pixel shown in FIG. 2 in a display scan period.
4A to 4C are waveform diagrams for explaining an operation of a pixel shown in FIG. 2 in a self-scan period.
5 is a conceptual diagram for explaining an example of a method of driving a display device according to an image refresh rate.
6A is a block diagram illustrating a display device according to other exemplary embodiments of the present invention.
6B and 6C are circuit diagrams illustrating pixels according to another exemplary embodiment of the present invention.
7A is a block diagram illustrating a display device according to another exemplary embodiment of the present invention.
7B is a circuit diagram illustrating a pixel according to another exemplary embodiment of the present invention.
8A is a block diagram illustrating a display device according to another exemplary embodiment of the present invention.
8B is a circuit diagram illustrating a pixel according to another exemplary embodiment of the present invention.

Since the present invention may have various changes and various forms, specific embodiments are illustrated in the drawings and described in detail in the text. However, it should be understood that this is not intended to limit the present invention to the specific disclosed form, and includes all modifications, equivalents, and substitutes included in the spirit and scope of the present invention.

Like reference numerals have been used for like elements throughout the description of each figure. In the accompanying drawings, the dimensions of the structures are shown enlarged than actual for clarity of the present invention. Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. These terms are only used for the purpose of distinguishing one component from another. For example, a first element may be termed a second element, and similarly, a second element may be termed a first element, without departing from the scope of the present invention. Singular expressions include plural expressions unless the context clearly dictates otherwise.

In this application, the terms "include" or "have" are intended to designate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, but one or more other features It should be understood that it does not preclude the possibility of the presence or addition of numbers, steps, operations, components, parts, or combinations thereof.

In addition, when a part is said to be "connected" to another part, this includes not only the case where it is directly connected but also the case where it is connected with another element interposed therebetween.

Hereinafter, embodiments of the present invention will be described in more detail with reference to the accompanying drawings.

1 is a block diagram illustrating a display device according to example embodiments.

Referring to FIG. 1 , a display device 1000 may include a display panel 100, scan drivers 200, 300, and 400, a light emitting driver 500, a data driver 600, and a timing controller 700. there is.

The scan driver 200 , 300 , and 400 may be divided into configurations and operations of the first scan driver 200 , the second scan driver 300 , and the third scan driver 400 . However, the classification of the scan driving units 200, 300, and 400 is for convenience of description, and at least a part of the scan driving units 200, 300, and 400 may be integrated into one driving circuit, module, or the like, depending on the design. .

In an exemplary embodiment, the display device 1000 includes a first power supply VDD, a second power supply VSS, a third power supply VREF (or reference power supply), and a fourth power supply Vint (or initialization power supply). , a power supply unit (not shown) may be further included to supply voltages of the fifth power supply (Vaint) (or anode initialization power supply) and the sixth power supply (Vbs) (or bias power supply) to the display panel 100 . there is.

The power supply includes a low power supply (low power supply) and a high power supply that determines the gate-on level and gate-off level of the scan signal, control signal, and/or emission control signal. (High power) may be supplied to the scan driver 200 , 300 , 400 and/or the light emitting driver 500 . The low power supply may have a lower voltage level than the high power supply. However, this is exemplary, and the first power supply VDD, the second power supply VSS, the third power supply VREF (or reference power supply), the fourth power supply Vint (or initialization power supply), and the fifth power supply At least one of the (Vaint) (or anode initialization power supply) sixth power supply (Vbs) (or bias power supply), low power supply, and high power supply may be supplied from the timing controller 700 or the data driver 600.

Depending on the embodiment, the first power source VDD and the second power source VSS may generate voltages for driving the light emitting device. In one embodiment, the voltage level of the second power supply VSS may be lower than the voltage level of the first power supply VDD. For example, the voltage of the first power source VDD may be a positive voltage and the voltage of the second power source VSS may be a negative voltage.

The reference power source VREF may be a power source for initializing the pixel PX. For example, capacitors and/or transistors included in the pixel PX may be initialized by the voltage of the reference power supply VREF. The reference voltage VREF may be a positive voltage.

The initialization power source Vint may be a power source for initializing the pixel PX. For example, the driving transistor included in the pixel PX may be initialized by the voltage of the initialization power source Vint. The initialization power source Vint may be a negative voltage.

The anode initialization power source Vaint may be a power source for initializing the pixel PX. For example, the anode of the light emitting element included in the pixel PX may be initialized by the voltage of the anode initialization power supply Vaint. The anode initialization power supply (Vaint) may be a negative voltage.

The bias power source Vbs may be a power source for supplying a predetermined on-bias voltage to a source electrode of a driving transistor included in the pixel PX. The bias power supply (Vbs) may be a positive voltage. In an embodiment, the voltage of the bias power supply (Vbs) may be similar to the black grayscale data voltage.

The display device 1000 according to an embodiment may display images at various image refresh rates (drive frequencies, or screen refresh rates) according to driving conditions. The image refresh rate is the frequency at which a data signal is substantially written to the driving transistor of the pixel PX. For example, the video refresh rate is also referred to as a screen scan rate or a screen refresh rate, and represents the frequency at which a display screen is reproduced for one second.

In one embodiment, the output frequency of the data driver 600 for one horizontal line (or pixel row) and/or the output of the first scan driver 200 that outputs the write scan signal in response to the image refresh rate frequency can be determined. For example, a refresh rate for driving a video may be a frequency of about 60 Hz or more (eg, 120 Hz).

In an exemplary embodiment, the display device 1000 includes an output frequency of the scan driver 200 , 300 , and 400 for one horizontal line (or pixel row) and a data driver 600 corresponding thereto according to driving conditions. output frequency can be adjusted. For example, the display device 1000 may display images corresponding to various image refresh rates of 1 Hz to 120 Hz. However, this is just an example, and the display device 1000 may display an image even at an image refresh rate of 120 Hz or higher (eg, 240 Hz or 480 Hz).

The display panel 100 may include data lines DL, scan lines SL1 , SL2 , and SL3 , and pixels PXs respectively connected to the emission control line EL. The pixels PX supply voltages of the reference power supply VREF, the first power supply VDD, the second power supply VSS, the initialization power supply Vint, the anode initialization power supply Vaint, and the bias power supply Vbs from the outside. can receive In an exemplary embodiment, the pixels PX disposed in the ith row and the jth column (where i and j are natural numbers) include scan lines SL1i, SL2i, and SL3i corresponding to the ith pixel row, and the ith pixel row. It may be connected to emission control lines ELi corresponding to , and a data line DLj corresponding to the j th pixel column.

In an embodiment of the present invention, the signal lines SL1 , SL2 , SL3 , EL and DL connected to the pixel PX may be set in various ways corresponding to the circuit structure of the pixel PX.

The timing controller 700 receives a first drive control signal SCS1, a second drive control signal SCS2, a third drive control signal SCS3, and a fourth drive control signal ( ECS), and a fifth driving control signal DCS. The first drive control signal SCS1 is supplied to the first scan driver 200, the second drive control signal SCS2 is supplied to the second scan driver 300, and the third drive control signal SCS3 is supplied to the second scan driver 300. 3 may be supplied to the scan driver 400 , the fourth driving control signal ECS may be supplied to the light emitting driver 500 , and the fifth driving control signal DCS may be supplied to the data driver 600 . Also, the timing controller 700 may rearrange input image data supplied from the outside into image data RGB and supply the rearranged image data to the data driver 600 .

The first drive control signal SCS1 may include a first scan start pulse and clock signals. The first scan start pulse may control the first timing of the scan signal output from the first scan driver 200 . Clock signals may be used to shift the first scan start pulse.

The second drive control signal SCS2 may include a second scan start pulse and clock signals. The second scan start pulse may control the first timing of the scan signal output from the second scan driver 300 . Clock signals may be used to shift the second scan start pulse.

The third drive control signal SCS3 may include a third scan start pulse and clock signals. The third scan start pulse may control the first timing of the scan signal output from the third scan driver 400 . Clock signals may be used to shift the third scan start pulse.

The fourth driving control signal ECS may include a first emission control start pulse and clock signals. The first light emission control start pulse may control the first timing of the light emission control signal output from the light driving unit 500 . Clock signals may be used to shift the first emission control start pulse.

The fifth driving control signal DCS may include a source start pulse and clock signals. The source start pulse can control the starting point of data sampling. Clock signals may be used to control the sampling operation.

The first scan driver 200 receives the first driving control signal SCS1 from the timing controller 700 and transmits scan signals (eg, For example, a first scan signal) may be supplied. For example, the first scan driver 200 may sequentially supply the first scan signal to the first scan lines SL1. When the first scan signal is sequentially supplied, the pixels PXs are selected in units of horizontal lines (or in units of pixel rows), and a data signal may be supplied to the pixels PXs. That is, the first scan signal may be a signal used for writing data.

The first scan signal may be set to a gate-on level (eg, high voltage). A transistor included in the pixel PX and receiving the first scan signal may be set to a turn-on state when the first scan signal is supplied.

The first scan driver 200 may supply scan signals to the first scan lines SL1 in a display scan period of one frame. For example, the first scan driver 200 may supply at least one scan signal to each of the first scan lines SL1 during the display scan period.

The second scan driver 300 receives the second driving control signal SCS2 from the timing controller 700 and transmits the scan signal (eg, the second scan line SL2) based on the second driving control signal SCS2. For example, the second scan signal) may be supplied. For example, the second scan driver 300 may sequentially supply the second scan signal to the second scan lines SL2. The second scan signal may be supplied to initialize transistors and capacitors included in the pixels PX and/or to compensate for a threshold voltage (Vth). When the second scan signal is supplied, the pixels PX may perform threshold voltage compensation and/or initialization operations. The second scan signal may be set to a gate-on level (eg, high voltage). A transistor included in the pixel PX and receiving the second scan signal may be set to a turn-on state when the second scan signal is supplied.

The second scan driver 300 may supply scan signals to the second scan lines SL2 during the display scan period of one frame. For example, the second scan driver 300 may supply at least one scan signal to each of the second scan lines SL2 during the display scan period.

The third scan driver 400 receives the third drive control signal SCS3 from the timing controller 700 and transmits the scan signal (eg, the third scan line SL3) based on the third drive control signal SCS3. For example, a third scan signal) may be supplied. For example, the third scan driver 400 may sequentially supply the third scan signal to the third scan lines SL3. The third scan signal may be supplied to initialize driving transistors included in the pixels PXs and/or initialize capacitors included in the pixels PXs. When the third scan signal is supplied, the pixels PX may perform initialization of driving transistors and/or initialization of capacitors.

The third scan signal may be set to a gate-on level (eg, high voltage). A transistor included in the pixel PX and receiving the third scan signal may be set to a turn-on state when the third scan signal is supplied.

The light emitting driver 500 may receive the fourth driving control signal ECS from the timing controller 700 and supply the light emitting control signal to the light emitting control lines EL based on the fourth driving control signal ECS. .

When the emission control signal is supplied, the pixels PX may not emit light in units of horizontal lines (or in units of pixel rows).

In one embodiment, within one frame period, emission control signals supplied to the emission control line EL may be repeatedly supplied at predetermined intervals. Accordingly, when the image refresh rate is reduced, the number of repetitions of the operation of supplying the emission control signals within one frame period may be increased.

The data driver 600 may receive the fifth driving control signal DCS and image data RGB from the timing controller 700 . The data driver 600 may supply data signals to the data lines DL in response to the fifth driving control signal DCS. Data signals supplied to the data lines DL may be supplied to pixels PXs selected by a scan signal (eg, a first scan signal). To this end, the data driver 600 may supply data signals to the data lines DL in synchronization with the scan signal.

In one embodiment, the data driver 600 may supply data signals to the data lines DL for one frame period in response to the image refresh rate. For example, the data driver 600 may supply data signals in synchronization with scan signals supplied to the first scan lines SL1 .

2 is a circuit diagram illustrating a pixel according to an exemplary embodiment of the present invention. In FIG. 2 , for convenience of description, a pixel PX positioned on an i th horizontal line (or i th pixel row) and connected to a j th data line DLj is illustrated.

Referring to FIG. 2 , the pixel PX may include a light emitting element LD, first to ninth transistors T1 to T9, a first capacitor C1, and a second capacitor C2.

The first electrode of the light emitting element LD is connected to the second electrode (eg, drain electrode) (or the second node N2) of the first transistor T1 via the seventh transistor T7. , The second electrode of the light emitting element LD may be connected to the second power source VSS. Specifically, the first electrode of the light emitting element LD passes through the fourth node N4 to which one electrode of the seventh transistor T7 and one electrode of the eighth transistor T8 are connected in common to the first transistor ( It may be electrically connected to the second electrode of T1).

The first transistor T1 may be connected to the first power source VDD via the sixth transistor T6 and connected to the first electrode of the light emitting element LD via the seventh transistor T7. The first transistor T1 may generate a driving current and provide it to the light emitting element LD. A gate electrode of the first transistor T1 may be connected to the first node N1. The first transistor T1 may function as a driving transistor of the pixel PX. The first transistor T1 may control the amount of current flowing from the first power source VDD to the second power source VSS via the light emitting device LD in response to the voltage applied to the first node N1.

The first capacitor C1 may be connected between the first node N1 and the third node N3 corresponding to the gate electrode of the first transistor T1. The first capacitor C1 may store a voltage corresponding to a voltage difference between the first node N1 and the third node N3.

The second capacitor C2 may be connected between the first power source VDD and the third node N3. The second capacitor C2 may store a voltage corresponding to a voltage difference between the first power source VDD and the third node N3. As one electrode of the second capacitor C2 is connected to the first power source VDD, which is a constant voltage source, and the other electrode is connected to the third node N3, the second capacitor C2 is connected to the second transistor ( The data signal (or data voltage) written to the third node N3 through T2) may be maintained during the self-scan period in which the data signal is not written. That is, the second capacitor C2 can stabilize the voltage of the third node N3.

The second transistor T2 may be connected between the data line DLj and the third node N3. The second transistor T2 may include a gate electrode receiving a scan signal. For example, the gate electrode of the second transistor T2 may be connected to the first scan line SL1i to receive the first scan signal. The second transistor T2 is turned on when the first scan signal is supplied to the first scan line SL1i, thereby electrically connecting the data line DLj and the third node N3. Accordingly, the data signal (or data voltage) may be transferred to the third node N3.

The third transistor T3 includes a first node N1 corresponding to the gate electrode of the first transistor T1 and a second node N2 corresponding to the second electrode (or drain electrode) of the first transistor T1. ) can be connected. The third transistor T3 may include a gate electrode receiving a scan signal. For example, the gate electrode of the third transistor T3 may be connected to the second scan line SL2i to receive the second scan signal. The third transistor T3 is turned on when the second scan signal is supplied to the second scan line SL2i to electrically connect the first node N1 and the second node N2. When the third transistor T3 is turned on, the first transistor T1 may have a diode connection. When the first transistor T1 has a diode connection, the threshold voltage of the first transistor T1 may be compensated.

The fourth transistor T4 may be connected between the initialization power source Vint and the first node N1. The fourth transistor T4 may include a gate electrode receiving a scan signal. For example, the gate electrode of the fourth transistor T4 may be connected to the third scan line SL3i to receive the third scan signal. The fourth transistor T4 is turned on when the third scan signal is supplied to the third scan line SL3i, and electrically connects the initialization power source Vint and the first node N1. Accordingly, the voltage of the initialization power source Vint may be supplied to the first node N1. Accordingly, the voltage of the first node N1 may be initialized to the voltage of the initialization power source Vint.

The fifth transistor T5 may be connected between the reference power source VREF and the third node N3. The fifth transistor T5 may include a gate electrode receiving a scan signal. For example, the gate electrode of the fifth transistor T5 may be connected to the second scan line SL2i to receive the second scan signal. The fifth transistor T5 is turned on when the second scan signal is supplied to the second scan line SL2i, and electrically connects the reference power source VREF and the third node N3. Accordingly, the voltage of the reference power source VREF may be supplied to the third node N3. Accordingly, the voltage of the third node N3 may be initialized to the voltage of the reference power source VREF.

Meanwhile, since the gate electrodes of the third and fifth transistors T3 and T5 are connected to the same scan line (ie, the second scan line SL2i), they can be turned off or turned on at the same time.

The sixth transistor T6 may be connected between the first power source VDD and the first electrode (or fifth node N5) of the first transistor T1. The sixth transistor T6 may include a gate electrode receiving a light emitting control signal. For example, a gate electrode of the sixth transistor T6 may be connected to the emission control line ELi to receive an emission control signal. The sixth transistor T6 is turned off when an emission control signal is supplied to the emission control line ELi, and may be turned on in other cases. The turn-on sixth transistor T6 may connect the first electrode of the first transistor T1 to the first power source VDD.

The seventh transistor T7 may be connected between the second node N2 corresponding to the second electrode of the first transistor T1 and the anode (or fourth node N4) of the light emitting element LD. The seventh transistor T7 may include a gate electrode receiving a light emitting control signal. For example, a gate electrode of the seventh transistor T7 may be connected to the emission control line ELi to receive an emission control signal. The seventh transistor T7 is turned off when an emission control signal is supplied to the emission control line ELi, and may be turned on in other cases. The seventh transistor T7 in the turned-on state may electrically connect the second node N2 and the fourth node N4.

Meanwhile, since the gate electrodes of the sixth and seventh transistors T6 and T7 are connected to the same emission control line ELi, they can be turned off or turned on at the same time. When both the sixth and seventh transistors T6 and T7 are turned on, the light emitting element LD can emit light with a luminance corresponding to the voltage of the first node N1.

The eighth transistor T8 may be connected between the light emitting element LD (or the fourth node N4 ) and the anode initialization power supply Vaint. The eighth transistor T8 may include a gate electrode receiving a light emission control signal. For example, a gate electrode of the eighth transistor T8 may be connected to the emission control line ELi to receive an emission control signal. The eighth transistor T8 is turned on when an emission control signal is supplied to the emission control line ELi, thereby electrically connecting the anode initialization power source Vaint and the fourth node N4. Accordingly, the voltage of the fourth node N4 (or the anode of the light emitting element LD) may be initialized to the voltage of the anode initialization power supply Vaint.

When the voltage of the anode initialization power source Vaint is supplied to the anode of the light emitting element LD, the parasitic capacitor of the light emitting element LD may be discharged. As the residual voltage charged in the parasitic capacitor is discharged (removed), unintentional light emission may be prevented. Accordingly, black expression capability of the pixel PX may be improved.

The ninth transistor T9 may be connected between the first electrode (or the fifth node N5) of the first transistor T1 and the bias power supply Vbs. The ninth transistor T9 may include a gate electrode receiving a light emission control signal. For example, a gate electrode of the ninth transistor T9 may be connected to the emission control line ELi to receive an emission control signal. The ninth transistor T9 is turned on when an emission control signal is supplied to the emission control line ELi, thereby electrically connecting the fifth node N5 and the bias power source Vbs.

As described with reference to FIG. 1 , the ninth transistor T9 may supply a high voltage to the first electrode of the first transistor T1 based on the bias power supply Vbs having a positive voltage. Accordingly, the first transistor T1 may have an on-bias state.

Meanwhile, the period during which the second transistor T2 is turned on and the period during which the third transistor T3 is turned on do not overlap. For example, when the third transistor T3 is turned on, threshold voltage compensation of the first transistor T1 may be performed, and when the second transistor T2 is turned on, data writing may be performed. Accordingly, the threshold voltage compensating period and the data writing period may be separated from each other.

In low-frequency driving in which the length of one frame period is long, a hysteresis difference due to a gray level difference between adjacent pixels may be severely generated. Therefore, a difference in threshold voltage shift amounts of driving transistors of adjacent pixels may occur, and thus screen dragging (ghosting phenomenon) may be recognized.

In the display device according to example embodiments, a bias may be periodically applied with a constant voltage to the source electrode of the driving transistor (eg, the first transistor T1 ) using the ninth transistor T9 . Accordingly, the hysteresis deviation due to the gray level difference between adjacent pixels is eliminated, and screen drag caused by the deviation can be reduced (removed).

In one embodiment, the first, sixth, and seventh transistors T1, T6, and T7 are P-type low-temperature poly-silicon (LTPS) thin film transistors, and the second, third, fourth, and The fifth, eighth, and ninth transistors T2, T3, T4, T5, T8, and T9 may be N-type oxide semiconductor thin film transistors. Meanwhile, the gate electrodes of the sixth, seventh, eighth, and ninth transistors T6, T7, T8, and T9 are all connected to the emission control line ELi, but the sixth and seventh transistors T6 , T7) are P-type thin-film transistors, and the eighth and ninth transistors T8 and T9 are N-type thin-film transistors, so that the sixth and seventh transistors T6 correspond to the light emission control signal of the same level. , T7) and the eighth and ninth transistors T8 and T9 may operate oppositely.

3A to 3E are waveform diagrams for explaining the operation of the pixel shown in FIG. 2 in a display scan period.

Referring to FIGS. 2 and 3A , the pixel PX may receive signals for image display during the display scan period DSP. The display scan period DSP may include a period in which the data signal DVj actually corresponding to the output image is written.

The emission control signal EMi may be supplied to the emission control lines ELi from the first time point t1 to the seventh time point t7 of the display scan period DSP. Accordingly, from the first time point t1 to the seventh time point t7, the sixth and seventh transistors T6 and T7 are turned off, and the eighth and ninth transistors T8 and T9 are turned off. can be turned on

When the sixth and seventh transistors T6 and T7 are turned off, the pixel PX is in a non-emission state, and when the sixth and seventh transistors T6 and T7 are turned on, the pixel PX is in a non-emission state. (PX) can emit light.

While the emission control signal EMi is supplied, the third scan signal GIi is supplied to the third scan line SL3i in the first period P1a from the first time point t1 to the second time point t2. In the second period P2a from the third time point t3 to the fourth time point t4, the second scan signal GCi is supplied to the second scan line SL2i, and from the fifth time point t5 In the third period P3a up to the sixth time point t6, the first scan signal GWi may be supplied to the first scan line SL1i.

In this case, the first period P1a is a period for initializing the gate electrode of the first transistor T1, the second period P2a is a period for compensating the threshold voltage of the first transistor T1, and the third period (P3a) may be a period in which the data signal DVj is written, and the fourth period P4a may be a light emitting period (or a first light emitting period).

Referring to FIGS. 2 and 3B , during the first period P1a , the emission control signal EMi may be supplied and the third scan signal GIi may be supplied.

When the eighth transistor T8 is turned on, the voltage of the anode initialization power source Vaint may be supplied to the fourth node N4. That is, during the first period P1a, the anode of the light emitting element LD may be initialized.

When the ninth transistor T9 is turned on, the voltage of the bias power source Vbs may be supplied to the fifth node N5. Accordingly, the voltage of the bias power source Vbs having a positive voltage may be supplied to the first electrode (or source electrode) of the first transistor T1. That is, the on-bias voltage may be applied to the first transistor T1 during the first period P1a.

At the first time point t1, the third scan signal GIi transitions from the gate-off level to the gate-on level, and at the second time point t2, the third scan signal GIi transitions from the gate-on level to the gate-off level. It can be. Accordingly, since the fourth transistor T4 is turned on during the first period P1a, the voltage of the initialization power source Vint may be supplied to the first node N1. That is, the gate electrode of the first transistor T1 may be initialized during the first period P1a.

Referring to FIGS. 2 and 3C , the emission control signal EMi is maintained and the second scan signal GCi is supplied during the second period P2a.

When the eighth transistor T8 is maintained in a turned-on state, the voltage of the anode initialization power source Vaint may be supplied to the fourth node N4. That is, the anode of the light emitting element LD may be initialized even during the second period P2a.

At the third time point t3, the second scan signal GCi transitions from the gate-off level to the gate-on level, and at the fourth time point t4, the second scan signal GCi transitions from the gate-on level to the gate-off level. It can be.

Accordingly, since the third transistor T3 is turned on during the second period P2a, the first node N1 and the second node N2 may be electrically connected. When the third transistor T3 is turned on, the first transistor T1 may have a diode connection. When the first transistor T1 has a diode connection type, the threshold voltage of the first transistor T1 may be compensated. At this time, since the ninth transistor T9 is turned on, the voltage of the bias power source Vbs can be supplied to the first node N1 via the third transistor T3. That is, the pixel PX shown in FIG. 2 may compensate for the threshold voltage of the first transistor T1 with the voltage of the bias power supply Vbs having a constant voltage rather than the variable data voltage.

Also, since the fifth transistor T5 is turned on by the second scan signal GCi of the gate-on level during the second period P2a, the voltage of the reference power supply VREF to the third node N3 is can be supplied. That is, the third node N3 may be initialized during the second period P2a.

Referring to FIGS. 2 and 3D , during the third period P3a, the emission control signal EMi is maintained and the first scan signal GWi is supplied.

When the eighth transistor T8 is maintained in a turned-on state, the voltage of the anode initialization power source Vaint may be supplied to the fourth node N4. That is, the anode of the light emitting element LD may be initialized even during the third period P3a.

When the ninth transistor T9 is maintained in a turned-on state and the third transistor T3 is turned off, the voltage of the bias power source Vbs may be supplied to the fifth node N5. Accordingly, the voltage of the bias power source Vbs having a positive voltage may be supplied to the first electrode (or source electrode) of the first transistor T1 again. That is, the on-bias voltage may be re-applied to the first transistor T1 during the third period P3a.

At the fifth time point t5, the first scan signal GWi transitions from the gate-off level to the gate-on level, and at the sixth time point t6, the first scan signal GWi transitions from the gate-on level to the gate-off level. It can be. Accordingly, since the second transistor T2 is turned on during the third period P3a, the data line DLj and the third node N3 are electrically connected, so that the data signal DVj is output to the third node ( N3) can be supplied.

Since the first node N1 is connected to the third node N3 by the first capacitor C1, the voltage variation of the third node N3 (that is, "DATA - VREF") is connected to the first node N1. ) can be reflected. Here, DATA may be a voltage corresponding to the data signal DVj, and VREF may be a voltage of the reference power source VREF.

That is, the data signal DVj may be written into the pixel PX during the third period P3a.

Referring to FIGS. 2 and 3E , the first to third scan signals GWi, GCi, and GIi and the emission control signal EMi may not be supplied during the fourth period P4a.

When the emission control signal EMi is not supplied, the sixth and seventh transistors T6 and T7 are turned on, and the eighth and ninth transistors T8 and T9 are turned off. When both the sixth and seventh transistors T6 and T7 are turned on, the light emitting element LD can emit light with a luminance corresponding to the voltage of the first node N1. That is, during the fourth period P4a, the pixel PX may emit light.

As such, in the pixel PX shown in FIG. 2 , the sixth and seventh transistors T6 and T7 are P-type low-temperature poly-silicon (LTPS) thin film transistors, and the eighth and ninth transistors ( T8 and T9) are composed of N-type oxide semiconductor thin film transistors, and the gate electrodes of the sixth, seventh, eighth, and ninth transistors T6, T7, T8, and T9 are connected to the same emission control line Eli. by connecting to and controlling the initialization of the pixel PX, threshold voltage compensation, data writing, and bias power supply (Vbs) by using a smaller number of signal control lines (eg, scan lines, emission control lines). Voltage application can be performed. Meanwhile, since the number of signal control lines included in the pixel PX is reduced, a high-resolution display panel 100 can be implemented, and the number of scan drivers and/or light emitting drivers can be reduced in response to the reduced signal control lines. Therefore, the dead space of the display panel 100 can be minimized.

4A to 4C are waveform diagrams for explaining an operation of a pixel shown in FIG. 2 in a self-scan period.

Referring to FIGS. 2, 3A, and 4A, in order to maintain the luminance of an image output in the display scan period DSP, the first electrode of the first transistor T1 (or A voltage of the bias power source Vbs may be applied to the fifth node N5.

According to the video frame rate, one frame may include at least one self scan period (SSP). The self-scan period SSP may include an on-bias period of the fifth period P1b and a light emission period (or second light emission period) of the sixth period P2b.

The emission control signal EMi may be supplied to the emission control lines ELi from the eighth time point t8 to the ninth time point t9 of the self-scan period SSP. Accordingly, from the eighth time point t8 to the ninth time point t9, the sixth and seventh transistors T6 and T7 are turned off, and the eighth and ninth transistors T8 and T9 are turned off. can be turned on When the sixth and seventh transistors T6 and T7 are turned off, the pixel PX is in a non-emission state, and when the sixth and seventh transistors T6 and T7 are turned on, the pixel PX is in a non-emission state. (PX) can emit light.

Even while the emission control signal EMi is supplied in the self scan period SSP, the first to third scan signals GWi, GCi, and GIi may not be supplied.

Referring to FIGS. 2 and 4B , the emission control signal EMi is maintained during the fifth period P1b, and the first to third scan signals GWi, GCi, and GIi may not be supplied.

When the eighth transistor T8 is turned on, the voltage of the anode initialization power source Vaint may be supplied to the fourth node N4. That is, during the fifth period P1b, the anode of the light emitting element LD may be initialized.

When the ninth transistor T9 is turned on, the voltage of the bias power source Vbs may be supplied to the fifth node N5. Accordingly, the voltage of the bias power source Vbs having a positive voltage may be supplied to the first electrode (or source electrode) of the first transistor T1. That is, the on-bias voltage may be applied to the first transistor T1 during the fifth period P1b.

Referring to FIGS. 2 and 4C , the first to third scan signals GWi, GCi, and GIi and the emission control signal EMi may not be supplied during the sixth period P2b.

When the emission control signal EMi is not supplied, the sixth and seventh transistors T6 and T7 are turned on, and the eighth and ninth transistors T8 and T9 are turned off. When both the sixth and seventh transistors T6 and T7 are turned on, the light emitting element LD can emit light with a luminance corresponding to the voltage of the first node N1. That is, during the sixth period P2b, the pixel PX may emit light.

As such, in the self scan period SSP, the data driver ( 600 in FIG. 1 ) may not supply a data signal to the pixel PX. Accordingly, power consumption can be further reduced.

5 is a conceptual diagram for explaining an example of a method of driving a display device according to an image refresh rate.

1 to 5 , the pixel PX may perform the operations of FIGS. 3A to 3E in the display scan period DSP and the operations of FIGS. 4A to 4C in the self scan period SSP. can

In one embodiment, the length of the display scan period (DSP) and the self scan period (SSP) may be substantially the same. However, the number of self scan periods (SSPs) included in one frame period may be determined according to the image refresh rate (RR).

As shown in FIG. 5 , when the display device 1000 is driven at an image refresh rate (RR) of 120 Hz, one frame period includes one display scan period (DSP) and one self scan period (SSP). can do. Accordingly, when the display device 1000 is driven at the image refresh rate RR of 120 Hz, the pixels PX may alternately emit light and not emit light twice during one frame period.

Also, when the display device 1000 is driven at an image refresh rate (RR) of 80 Hz, one frame period may include one display scan period (DSP) and two consecutive self scan periods (SSP). Accordingly, when the display device 1000 is driven at the image refresh rate RR of 80 Hz, the pixels PX may alternately emit light and non-emit light three times during one frame period.

In a manner similar to the above, the display device 1000 may be driven at a driving frequency of 60 Hz, 48 Hz, 30 Hz, 24 Hz, or 1 Hz by adjusting the number of self scan periods (SSP) included in one frame period.

In addition, as the driving frequency decreases, the number of self-scan periods SSP increases, so that a constant amount of on-bias and/or off-bias is applied to each of the first transistors T1 included in each of the pixels PX. It may be applied periodically. Therefore, luminance reduction, flicker (blinking), and screen drag in low-frequency driving can be improved.

Hereinafter, other embodiments are described. In the following embodiments, descriptions of the same configurations as those of the previously described embodiments will be omitted or simplified, and will be mainly described based on differences.

6A is a block diagram illustrating a display device according to other exemplary embodiments of the present invention. 6B and 6C are circuit diagrams illustrating pixels according to another exemplary embodiment of the present invention.

The display device 1000_1 of FIG. 6A is only different from the display device 1000 of FIG. 1 in that the third power source VREF (or reference power source) is omitted among the power sources supplied to the display panel 100. , other configurations are substantially the same. That is, the display panel 100 of the display device 1000_1 shown in FIG. 6A includes the voltage of the first power supply VDD, the voltage of the second power supply VSS, the fourth power supply Vint (or initialization power supply), Voltages of the fifth power supply Vaint (or anode initialization power supply) and the sixth power supply Vbs (or bias power supply) may be provided.

In the pixel PX_1a of FIG. 6B , since the voltage supplied to one electrode of the 5' transistor T5' is the voltage of the first power source VDD, the voltage supplied to one electrode of the fifth transistor T5 is There is only a difference from the pixel PX of FIG. 2 , which is the voltage of the third power supply VREF (or reference power supply), but other configurations are substantially the same. Referring to FIGS. 3A and 6B , the 5' transistor T5' is turned on by the second scan signal GCi at the gate-on level during the second period P2a, so that the third node N3 The voltage of the first power source VDD may be supplied as .

In the pixel PX_1b of FIG. 6C , in that the voltage supplied to one electrode of the fifth transistor T5 is the voltage of the sixth power source Vbs (or bias power source), one electrode of the fifth transistor T5 is applied. There is a difference from the pixel PX of FIG. 2 in which the voltage supplied to the electrode is the voltage of the third power source VREF (or reference power source), but other configurations are substantially the same. Referring to FIGS. 3A and 6C , the fifth "transistor T5" is turned on by the second scan signal GCi at the gate-on level during the second period P2a, so that the third node N3 The voltage of the sixth power source Vbs (or bias power source) may be supplied as .

As such, instead of using a separate third power supply VREF (or reference power supply) to initialize the third node N3, the first power supply VDD is used as shown in FIG. 6B or as shown in FIG. 6C, When the sixth power supply Vbs (or bias power supply) is used, since the number of power lines disposed in the pixels PX can be reduced, a high-resolution display panel 100 (see FIG. 6A ) can be implemented.

7A is a block diagram illustrating a display device according to another exemplary embodiment of the present invention. 7B is a circuit diagram illustrating a pixel according to another exemplary embodiment of the present invention.

The display device 1000_2 of FIG. 7A is different from the display device 1000 of FIG. 1 in that the fifth power source Vaint (or anode initialization power source) is omitted among the power supplies supplied to the display panel 100. However, other configurations are substantially the same. That is, the display panel 100 of the display device 1000_1 shown in FIG. 7A includes the voltage of the first power supply VDD, the voltage of the second power supply VSS, the third power supply VREF (or reference power), Voltages of the fourth power source Vint (or initialization power source) and the sixth power source Vbs (or bias power source) may be provided.

In the pixel PX_2 of FIG. 7B , since the voltage supplied to one electrode of the 8′ transistor T8′ is the voltage of the fourth power source Vint (or initialization power source), one electrode of the eighth transistor T8′ There is a difference from that of the pixel PX of FIG. 2 in which the voltage supplied to the electrode is the voltage of the fifth power supply Vaint (or anode initialization power supply), but other configurations are substantially the same. Referring to FIGS. 3A and 7B , the 8′ transistor T8′ is turned on by the high level emission control signal EMi supplied from the first time point t1 to the seventh time point t7. , the voltage of the fourth power source Vint may be supplied to the fourth node N4. That is, the anode of the light emitting element LD may be initialized with the voltage of the initialization power source Vint from the first time point t1 to the seventh time point t7.

In this way, instead of using a separate fifth power supply Vaint (or anode initialization power supply) to initialize the fourth node N4 (or the anode of the light emitting element LD), as shown in FIG. 7B, the fourth power supply When Vint (or initialization power supply) is used, since the number of power lines disposed in the pixel PX can be reduced, a high-resolution display panel 100 (see FIG. 7A ) can be implemented.

8A is a block diagram illustrating a display device according to another exemplary embodiment of the present invention. 8B is a circuit diagram illustrating a pixel according to another exemplary embodiment of the present invention.

In the display device 1000_3 of FIG. 8A , among the power supplies supplied to the display panel 100, the third power source VREF (or reference power source) and the fifth power source (Vaint) (or anode initialization power source) are omitted. has only a difference from the display device 1000 of FIG. 1 , but other configurations are substantially the same. That is, the display panel 100 of the display device 1000_3 shown in FIG. 8A includes the voltage of the first power supply VDD, the voltage of the second power supply VSS, the fourth power supply Vint (or initialization power supply), And the voltage of the sixth power source Vbs (or bias power source) may be provided.

In the pixel PX_3 of FIG. 8B , the voltage supplied to one electrode of the 5' transistor T5' is the voltage of the first power source VDD, and the voltage supplied to one electrode of the 8' transistor T8' Given that the voltage is the voltage of the fourth power source Vint (or initialization power source), the voltage supplied to one electrode of the fifth transistor T5 is the voltage of the third power source VREF (or reference power source), The voltage supplied to one electrode of the eighth transistor T8 is different from that of the pixel PX of FIG. 2 , in which the voltage of the fifth power supply Vaint (or anode initialization power supply) is different, but other configurations are substantially the same. do.

Referring to FIGS. 3A and 8B , the 5' transistor T5' is turned on by the second scan signal GCi at the gate-on level during the second period P2a, so that the third node N3 The voltage of the first power source VDD is supplied to and the 8′ transistor T8′ operates by the high level emission control signal EMi supplied from the first time point t1 to the seventh time point t7. Since it is turned on, the voltage of the fourth power source Vint may be supplied to the fourth node N4.

As such, instead of using a separate third power source VREF (or reference power source) to initialize the third node N3, the first power source VDD is used as shown in FIG. 8B and the fourth node N4 is initialized. ) (or the anode of the light emitting element LD) instead of using a separate fifth power source (Vaint) (or anode initialization power source) to initialize the fourth power source (Vint) (or initialization power source) as shown in FIG. 8B. ) is used, since the number of power lines disposed in the pixel PX can be further reduced, a high-resolution display panel 100 (see FIG. 8A ) can be implemented.

Although the above has been described with reference to the embodiments of the present invention, those skilled in the art can variously modify and change the present invention without departing from the spirit and scope of the present invention described in the claims below. You will understand that you can.

100: display panel 200: first scan driver
300: second scan driver 400: third scan driver
500: light emitting driver 600: data driver
700: timing controller 1000: display device
C1, C2: Capacitor LD: Light-emitting element
PX: pixels
T1 to T9: Transistor

Claims (16)

light emitting device;
a first transistor connected between a first power supply and a second node and controlling a driving current supplied to the light emitting element in response to a voltage of the first node connected to a gate electrode;
a first capacitor including one electrode connected to the first node and the other electrode connected to a third node;
a second transistor coupled between the third node and a data line;
a third transistor connected between the first node and the second node;
a sixth transistor connected between the first power source and a fifth node connected to one electrode of the first transistor;
a seventh transistor connected between the second node and a fourth node connected to the anode of the light emitting element; and
A ninth transistor connected between the fifth node and a bias power supply;
A pixel of a display device wherein a gate electrode of each of the sixth transistor, the seventh transistor, and the ninth transistor is connected to a same emission control line. According to claim 1,
An eighth transistor connected between the fourth node and an anode initialization power supply;
A gate electrode of the eighth transistor is connected to the emission control line. According to claim 2,
The sixth transistor and the seventh transistor are P-type thin film transistors, and the eighth transistor and the ninth transistor are N-type thin film transistors. According to claim 2,
a fourth transistor coupled between the first node and an initialization power supply; and
The pixel of the display device further comprising: a fifth transistor connected between a reference power source and the third node. According to claim 4,
The second transistor, the third transistor, the fourth transistor, the fifth transistor, the eighth transistor, and the ninth transistor are N-type thin film transistors. According to claim 4,
The second transistor is turned on by the first scan signal,
The third transistor is turned on by the second scan signal,
The fourth transistor is turned on by the third scan signal,
The fifth transistor is turned on by the second scan signal,
The sixth transistor is turned off by the emission control signal,
The seventh transistor is turned off by the emission control signal,
An eighth transistor is turned on by the emission control signal,
The ninth transistor is turned on by the emission control signal. According to claim 1,
The pixel of the display device further comprising a second capacitor including one electrode connected to the first power supply and another electrode connected to the third node. According to claim 1,
a fourth transistor coupled between the first node and an initialization power supply; and
The pixel of the display device further comprising: a fifth transistor connected between the first power supply and the third node. According to claim 8,
An eighth transistor connected between the fourth node and the initialization power supply;
A gate electrode of the eighth transistor is connected to the emission control line. According to claim 1,
a fourth transistor coupled between the first node and an initialization power supply;
a fifth transistor connected between a reference power source and the third node; and
An eighth transistor connected between the fourth node and the initialization power supply;
A gate electrode of the eighth transistor is connected to the emission control line. According to claim 6,
A pixel of a display device in which the third scan signal, the second scan signal, and the first scan signal are sequentially provided while the emission control signal is supplied. According to claim 11,
When the eighth transistor is turned on by the emission control signal, a voltage of the anode initialization power supply is supplied to the fourth node;
The pixel of the display device to which the voltage of the bias power supply is supplied to the fifth node when the ninth transistor is turned on by the emission control signal. According to claim 12,
The pixel of the display device to which the voltage of the initialization power supply is supplied to the first node when the fourth transistor is turned on by the third scan signal. According to claim 12,
A pixel of a display device in which the first node and the second node have a diode connection when the third transistor is turned on by the second scan signal. According to claim 14,
When the ninth transistor is turned on by the emission control signal, the voltage of the first node is a difference between the voltage of the bias power supply and the threshold voltage of the first transistor. According to claim 12,
A pixel of a display device configured to provide a data signal from the data line to the third node when the second transistor is turned on by the first scan signal.

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