KR20230040954A - compact inverter system - Google Patents

Abstract

A compact inverter system includes a bus bar. The bus bar includes a terminal for connection to the positive terminal of the DC voltage supply. The compact inverter also includes a heat sink, a first transistor and a second transistor. The first transistor has a first terminal and a second terminal, between which a current is transmitted between the first terminal and the second terminal when the first transistor is activated, and a first gate terminal that controls the first transistor. A first terminal of the first transistor is thermally and electrically coupled to the bus bar. The second transistor has a first terminal and a second terminal, between which a current is transmitted when the second transistor is activated, and a second gate terminal that controls the second transistor. A first terminal of the second transistor is thermally and electrically connected to the heat sink. A first transistor and a second transistor are positioned between the bus bar and the heat sink. A first transistor is positioned between the second transistor and the bus bar. A second transistor is positioned between the first transistor and the heat sink.

Description

compact inverter system

[0001] Electric motors (eg, induction motors) are used in industrial fans, pumps, electric vehicles, and the like. An induction motor is an alternating current (AC) electric motor in which the current in the rotor required to produce torque is obtained by electromagnetic induction from the magnetic field of the stator windings. In electric vehicles, torque is applied to a shaft that propels the electric vehicle.

[0002] Microcontrollers or other data processing devices (eg, system on a chip) control the electric motors through power inverter systems. Essentially, a power inverter system converts direct current (DC) power from a battery, fuel cell or other source into AC power. The power inverter system can be operated in reverse to change AC power to DC power. A power inverter system may include one, three, six, nine, or more phases. Typically, each phase of the power inverter system includes at least one “high-side” switch coupled to at least one “low-side” switch. A pair of connected high-side and low-side switches is called a "half bridge".

[0003] The present disclosure will be described with reference to three-phase power inverter systems for converting DC power to AC power for electric motors of EVs, and it is understood that the present disclosure should not be limited thereto.

[0004] By referring to the accompanying drawings, the present technology may be better understood, and its many objects, features and advantages may become apparent to those skilled in the art.
[0005] FIG. 1A illustrates related components of an exemplary three-phase power inverter.
[0006] FIG. 1B illustrates an example timing diagram showing gate control signals used in the three-phase power inverter of FIG. 1A.
2AA and 2AB are isometric and inverse isometric views of an exemplary packaged switch.
[0008] Figures 2ba and 2bb are isometric and inverse isometric views of an exemplary packaged half bridge.
[0009] FIG. 3AA is a schematic diagram showing relevant components of the example of a packaged switch shown in FIGS. 2AA and 2AB when viewed from above.
[0010] FIG. 3ab is a schematic diagram illustrating relevant components of the example of a packaged switch shown in FIGS. 2AA and 2AB when viewed from the side.
[0011] FIG. 3Ac is a schematic diagram showing relevant components of the example of a packaged switch shown in FIGS. 2AA and 2AB when viewed from the back.
[0012] FIG. 3AD is a schematic diagram illustrating related components of an example switch controller.
[0013] FIGS. 3ae and 3af are schematic diagrams illustrating related components of example switches.
[0014] FIG. 3ag is a schematic diagram illustrating related components of an example gate driver.
[0015] FIG. 3BA is a schematic diagram illustrating related components of another exemplary packaged switch shown as viewed from above.
[0016] FIG. 3BB is a schematic diagram showing related components of the exemplary packaged switch shown in FIG. 3BA when viewed from the side.
[0017] FIG. 3BC is a schematic diagram showing related components of the exemplary packaged switch shown in FIG. 3BA when viewed from the back.
[0018] FIG. 3CA is a schematic diagram showing relevant components of another exemplary packaged switch shown as viewed from the side.
[0019] FIG. 3cb is a schematic diagram showing related components of the example packaged switch shown in FIG. 3ca when viewed from the back.
[0020] FIG. 3Da is a schematic diagram illustrating related components of another exemplary packaged switch shown as viewed from the side.
[0021] FIG. 3db is a schematic diagram showing related components of the exemplary packaged switch shown in FIG. 3da when viewed from the back.
[0022] FIG. 3ea is a schematic diagram illustrating related components of another exemplary packaged switch shown as viewed from the side.
[0023] FIG. 3EB is a schematic diagram illustrating related components of the exemplary packaged switch shown in FIG. 3EA when viewed from the back.
[0024] FIG. 3fa is a schematic diagram illustrating related components of another exemplary packaged switch shown as viewed from the side.
[0025] FIG. 3fb is a schematic diagram illustrating related components of the example packaged switch shown in FIG. 3fa when viewed from the back.
[0026] FIG. 3Ga is a schematic diagram showing related components of the example packaged half bridge shown in FIGS. 2BA and 2BB when viewed from the side.
[0027] FIG. 3GB is a schematic diagram showing related components of the example packaged half bridge shown in FIGS. 2BA and 2BB when viewed from the back.
[0028] FIG. 3HA is a schematic diagram showing related components of another exemplary packaged half bridge shown as viewed from the side.
[0029] FIG. 3HB is a schematic diagram showing related components of the exemplary packaged half bridge shown in FIG. 3HA when viewed from the back.
[0030] FIG. 3ia is a schematic diagram showing related components of another exemplary packaged half bridge shown as viewed from the side.
[0031] FIG. 3ib is a schematic diagram showing related components of the exemplary packaged half bridge shown in FIG. 3ia when viewed from the back.
[0032] FIG. 3Ka is a schematic diagram showing related components of another exemplary packaged half bridge shown as viewed from the side.
[0033] FIG. 3KB is a schematic diagram showing related components of the exemplary packaged half bridge shown in FIG. 3KA when viewed from the back.
[0034] FIG. 3LA is a schematic diagram illustrating related components of another exemplary packaged half bridge shown as viewed from the side.
[0035] FIG. 3lb is a schematic diagram showing related components of the exemplary packaged half bridge shown in FIG. 3la when viewed from the back.
[0036] FIG. 3J is a schematic diagram showing related components of another exemplary packaged half bridge shown as viewed from the side.
[0037] FIG. 4AA is a schematic diagram showing relevant components of an exemplary compact inverter system when viewed from the side.
[0038] Figure 4ab is a schematic diagram of the compact inverter system of Figure 4aa as viewed from the back.
[0039] Figures 4ac-4af are cross-sectional views of exemplary pipes that may be used in a compact inverter system.
[0040] FIG. 4BA is a schematic diagram showing related components of another exemplary compact inverter system when viewed from the side.
[0041] FIG. 4BB is a schematic diagram of the compact inverter system of FIG. 4BA when viewed from the rear.
[0042] FIG. 4BC illustrates exemplary signals received from or transmitted to the phase of the compact inverter system shown in FIG. 4BA.
[0043] FIG. 4ca is a schematic diagram showing related components of another exemplary compact inverter system when viewed from the side.
[0044] FIG. 4Da is a schematic diagram showing related components of another exemplary compact inverter system when viewed from the side.
[0045] FIG. 4db illustrates exemplary signals received from or transmitted to the phase of the compact inverter system shown in FIG. 4da.
[0046] FIG. 4E is a schematic diagram showing relevant components of another exemplary compact inverter system when viewed from above.
[0047] FIG. 4F is a schematic diagram showing related components of another exemplary compact inverter system when viewed from the side.
[0048] FIG. 4G is a schematic diagram showing related components of another exemplary compact inverter system when viewed from the side.
[0049] FIG. 4H is a schematic diagram showing related components of another exemplary compact inverter system when viewed from the side.
[0050] FIG. 4I is a schematic diagram showing related components of another exemplary compact inverter system when viewed from the side.
[0051] FIG. 4J is a schematic diagram showing related components of another exemplary compact inverter system when viewed from the side.
[0052] FIG. 4K is a schematic diagram showing related components of another exemplary compact inverter system when viewed from the side.
[0053] FIG. 4L is a schematic diagram showing relevant components of another exemplary compact inverter system when viewed from the side.
[0054] Figures 4ma and 4mb are schematic diagrams showing related components of a packaged half bridge as viewed from the back and side.
5 is an isometric view of an embossed sheet of thin metal from which an exemplary signal frame substrate may be formed.
[0056] FIG. 6 is a reverse isometric view of the embossed sheet shown in FIG. 5 after it has been cut.
[0057] FIG. 7 is an isometric view of the cut sheet shown in FIG. 6 after some non-isolated signal leads have been bent.
[0058] FIG. 8 is a plan view of the signal frame substrate of FIG. 7 with the leads of the gate driver circuit connected thereto.
[0059] FIG. 9A is a top view of an exemplary die substrate.
[0060] FIG. 9B shows an exemplary switch received on the surface of the die substrate shown in FIG. 9A.
[0061] FIG. 9C shows a partial cross-sectional view of the structure shown in FIG. 9B.
[0062] FIG. 10 is a top view of the die substrate of FIG. 9A aligned with the signal frame substrate shown in FIG. 8;
[0063] Figures 11A and 11B are isometric and inverse isometric views of an exemplary die clip.
[0064] FIGS. 11C and 11D are top and bottom views of the die clip shown in FIGS. 11A and 11B when aligned with the die substrate and signal frame substrate of FIG. 10 .
[0065] FIG. 11E is an isometric view partially showing the structure of FIGS. 11C and 11D as viewed from the side.
[0066] FIGS. 11F and 11G are top and isometric views of the structure shown in FIGS. 11C and 11D, with additional components.
[0067] FIGS. 12A and 12B are isometric and inverse isometric views of the structure shown in FIGS. 11F and 11G with a molded plastic body.
[0068] Figures 13A and 13B are side and isometric views of related components of an exemplary packaged half bridge.
[0069] FIGS. 14A and 14B are isometric and cross-sectional views, respectively, of an exemplary V+ bus bar used in the compact inverter system of FIG. 4DA.
[0070] FIGS. 15A and 15B are isometric and side views of the V+ bus bar of FIGS. 14A and 14B after it accommodates exemplary packaged half bridges.
[0071] FIG. 16A is an isometric view of an exemplary clamp that may be used in the compact inverter system of FIG. 4DA.
[0072] FIGS. 16B and 16C are cross-sectional views of the clamp shown in FIG. 16A.
[0073] FIGS. 17A and 17B are isometric and cross-sectional views of the structure shown in FIGS. 15A and 15B B, with the clamp of FIGS. 16A-16C.
[0074] FIGS. 18A-18C are isometric, side and cross-sectional views of the structure shown in FIGS. 17A and 17B with heat sinks added.
[0075] FIGS. 19A and 19B are isometric and side views of the structure shown in FIGS. 18A-18C, with additional clamps, half bridges and heat sinks.
[0076] FIGS. 20A-20C are isometric, top, and cross-sectional views of exemplary V-bus bars utilized in the compact inverter system of FIG. 4DA.
[0077] FIG. 20D is a side view of the exemplary V- bus bar shown in FIGS. 20A-20C having an array of decoupling capacitors housed therein.
[0078] FIG. 21 is a cross-sectional view of the structure shown in FIGS. 19A and 19B, with a V-bus and additional components.
[0079] Use of the same reference numbers in different drawings indicates similar or identical items.

[0080] 1A illustrates related components of an exemplary three-phase power inverter system (hereinafter inverter system) 100 . Each phase includes a half bridge: a high-side switch connected to a low-side switch. Each high-side switch includes a transistor THx connected in parallel with a diode DHx, and each low-side switch includes a transistor TLx connected in parallel with a diode DLx. Transistors TH1-TH3 and TL1-TL3 take the form of insulated-gate bipolar transistors (IGBTs).

[0081] High-side transistors TH1-TH3 are connected in series with low-side transistors TL1-TL3 through nodes N1-N3, respectively, which nodes N1-N3 are in turn connected to the electric motor. connected to individual terminals of wire windings (Wa-Wc) of The collectors of TH1-TH3 and the cathodes of DH1-DH3 are connected together and to a terminal of a battery that provides a positive voltage (V+) (e.g., 50 V, 100 V, 200 V, or more). Meanwhile, the emitters of transistors TL1-TL3 and the anodes of diodes DL1-DL3 are connected together and to the other terminal of the battery providing a return or negative voltage (V-).

[0082] High-side transistors TH1-TH3 and low-side transistors TL1-TL3 are controlled by microcontroller 110 through gate drivers H101-H103 and L101-L103, respectively. A gate driver accepts a low-power input signal from a device (e.g., a microcontroller) and operates on a transistor such as an IGBT or metal-oxide-semiconductor field-effect transistor (MOSFET). A circuit that generates a high-current output signal to control the gate.

[0083] Control of the transistors is relatively simple. The high-side gate drivers H101-H103 and the low-side gate drivers L101-L103 receive low-power driver control signals from the microcontroller 110 (i.e., pulse width modulation signals PWM-H1 to Receives PWM-H3 and PWM-L1 to PWM-L3)). The high-side gate drivers H101-H103 assert the high-current gate control signals VgH1-VgH3, respectively, when the PWM-H1 through PWM-H3 signals are asserted, respectively, so that a high - Activate the side transistors TH1-TH3 respectively. And the low-side gate drivers L101-L103 assert the high-current gate control signals VgL1-VgL3, respectively, when the PWM-L1 to PWM-L3 signals are asserted, respectively, so that the low-side Transistors TL1 to TL3 are respectively activated. Each of the transistors TH1-TH3 and TL1-TL3, when energized, conducts current to or from the connected winding W.

[0084] Through coordinated activation of the connected high-side and low-side transistors, the direction of current flow in winding W continuously and regularly flips-flops (current moves into the winding and then It suddenly reverses and flows out again). 1B illustrates an exemplary timing diagram for gate control signals VgH1-VgH3 and VgL1-VgL3. The interaction between the changing current in the wire windings (Wa-Wc) and the magnetic field of the rotor (not shown) of the motor coupled to the drive shaft (not shown) creates a force that propels the EV.

[0085] The microcontroller 110 controls the high-side transistors TH1 to TH3 and the low-side transistors TL1 to TL3 through PWM-H1 to PWM-H3 and PWM-L1 to PWM-L3 signals, respectively. Microcontrollers, such as microcontroller 110, include a central processing unit (CPU), a memory that stores instructions executable by the CPU, and peripherals, such as timers, input/output (I /O: input/output) ports, etc. The CPU programs the timers according to instructions stored in memory. Once programmed and started, these timers can autonomously generate the PWM-H1 to PWM-H3 and PWM-L1 to PWM-L3 signals. Gate drivers H101-H103 generate VgH1-VgH3 signals based on the PWM-H1 to PWM-H3 signals, and gate drivers L101-L103 generate VgH1-VgH3 signals based on the PWM-L1 to PWM-L3 signals. Generates VgL1-VLH3 signals. The CPU can reprogram the timers to adjust the duty cycle and/or period of the PWM signals, which in turn adjusts the rotational speed of the EV's drive shaft.

[0086] Prior art inverter systems are large, bulky, expensive, and inefficient. For example, a prior art inverter system capable of delivering 400 kW of peak power to an electric motor occupies a volume in excess of 11 liters. A "compact power inverter system" (hereinafter referred to as compact inverter system) is disclosed that solves many of the problems of prior art inverter systems. For example, a compact inverter system including ceramic decoupling capacitors, such as those described in FIG. 20D below, can deliver 400 kW of peak power, but occupy a volume of less than 0.25 liters. When thin film decoupling capacitors are used instead of ceramic decoupling capacitors, or when thin film decoupling capacitors are added together with ceramic decoupling capacitors, the size of compact inverters can be increased. Ultimately, the power density (power/volume) of the disclosed compact converter systems far exceeds that of prior art inverter systems.

Packaged Switch Modules

[0087] "Packaged switch modules" are disclosed. Compact inverter systems of the present disclosure use packaged switch modules, which can be used in a variety of other systems, such as AC-DC converters, DC-DC converter systems, rectifiers, photo voltaic conversion systems It is understood that it can be used in conversion systems, power charging stations, and the like.

[0088] As the name implies, packaged switch modules contain one or more “switch modules”. A switch module includes a “switch” and a “switch controller,” and it is understood that a switch module may include additional components. A switch monitors and/or controls switches (ie, activates or deactivates switches). A packaged switch module containing only one switch module is called a "packaged switch", and a packaged switch module containing two switch modules is called a "packaged half bridge".

[0089] Packaged switches and packaged half bridges have six sides; It can be in the shape of a cube with top, bottom, front, back, left and right sides. In one embodiment, the faces are substantially planar. 2AA and 2AB are isometric and inverse isometric views of an exemplary packaged switch 200 . 2BA and 2BB are isometric and reverse isometric views of an exemplary packaged half bridge 250 . Packaged switches and half bridges can be manufactured in small form factors. For example, the packaged switch 200 may measure 25 x 25 x 6 mm, and the packaged half bridge 250 may measure 25 x 25 x 12 mm. The sizes (eg, 25 x 25 x 6 mm) and shapes of all packaged switches described in this disclosure may be substantially similar. The sizes (eg, 25 x 25 x 12 mm) and shapes (eg, cubic) of all packaged half bridges described in this disclosure may be substantially similar.

[0090] Packaged switches and half bridges have solid glass, plastic or ceramic cases. For illustrative purposes only, it is assumed that the cases are plastic (eg, epoxy resin). 2AA and 2AB show packaged switch 200 with plastic case 202 and FIGS. 2BA and 2BB show packaged half bridge 250 with plastic case 252 . In most embodiments, the surfaces of plastic cases are substantially flat.

[0091] Plastic cases isolate, protect and/or support components such as switches, switch controllers, and the like. The plastic cases also support the "signal leads". A signal lead is an electrical connector or conductor consisting of a length of metal pad or “wire” designed to electrically connect two locations. Signal leads may be routed between internal components (eg, between a switch controller and a switch) or between internal components (eg, a switch controller) and external components (eg, a microcontroller, voltage regulator, etc.) Carries signals (eg, PWM signals, gate control signals, etc.) or voltages (eg, supply voltages or positive voltages, ground returns or negative voltages, etc.). 2AA and 2AB illustrate example signal leads 204 and 206. Signal lead 204 can carry a signal, such as a low-power PWM signal, to an internal component (eg, a switch controller), while signal lead 206 can carry a supply voltage to the same internal component or to a different internal component. there is. Packaged half bridge 250 has similar signal leads 204H, 204L, 206H and 206L.

[0092] In the illustrated embodiments, the signal leads have substantially planar surfaces. Unless otherwise noted, the signal lead surfaces are substantially flush with the plastic case surfaces of the packaged switch or packaged half bridge. However, in other embodiments, the flat surfaces may be substantially recessed below the surfaces of the plastic case, or the flat surfaces may substantially protrude above the surfaces of the plastic case. 2AA shows exemplary signal leads 204 and 206 having planar surfaces that are substantially flush with the top surface of packaged switch 200. FIG. 2AB also shows example signal leads having planar surfaces that are substantially flush with the front surface of the packaged switch 200 . Signal leads may provide terminals (ie, physical interfaces). The signal leads on the front of the packaged switch 200 provide terminals through which signals or voltages can be received or transmitted. For example, signal lead 204 provides a terminal capable of receiving a signal such as a low-power PWM signal from a microcontroller, while signal lead 206 is a power management integrated circuit (PMIC). Provides a terminal for receiving the supply voltage from In an alternative embodiment, the signal leads on the top may provide terminals for receiving or transmitting signals or voltages. For purposes of explanation, it is understood that only the front of the packaged switches provide signal lead terminals for receiving or transmitting signals and voltages, and that signal leads on the top may provide terminals in alternative embodiments. . 2BA and 2BB show similar signal leads 204 and 206 that are substantially flush with the front, top, and bottom surfaces of packaged half bridge 250 . For illustrative purposes, only the signal leads, such as signal leads 204H, 204L, 206H, and 206L in front of the packaged half bridges, provide terminals through which signals or voltages may be transmitted or received; It is understood that in some embodiments the signal leads on the top and bottom surfaces may provide terminals.

[0093] A switch includes one or more power transistors (IGBTs, MOSFETs, etc.). A power transistor has two current terminals (collector and emitter in an IGBT, source and drain in a MOSFET, etc.) and a control or gate terminal. Multiple power transistors in a switch can be connected in parallel and controlled by a common signal at their gates. Depending on the size (i.e., gate width and length), type (e.g. MOSFET), semiconductor material (e.g. GaN) and number (e.g. 3) of the transistors in the switch, the switch may fail without failure. It can transmit significant levels of current at high switching speeds. The power transistor can transmit current at high switching speeds (eg, up to 100 kHz for Si IGBTs, up to 500 kHz for SiC MOSFETs, up to 1.0 GHz for GaN MOSFETs, etc.). As will be discussed below, when thermally coupled to heat sinks, power transistors can transmit more current at higher switching speeds without failure.

[0094] The switches are sandwiched between discrete metal conductors called "die substrates" and "die clips". More specifically, the first current terminal (eg, collector or drain) and the second current terminal (eg, emitter or source) of each transistor in the switch are connected to a die substrate and a die clip, respectively ( eg sintered, soldered, brazed, etc.). The gate of each transistor in the switch is connected to and controlled by the switch controller.

Die board and die clip terminals

[0095] Die substrates and die clips conduct current. In addition to conducting current, the die substrate conducts heat. The die substrate has terminals for transferring heat out of the packaged switch or packaged half bridge. The same die board terminal can transmit current into or out of a packaged switch or packaged half-bridge. The die clip has at least one terminal for transmitting current into or out of the packaged switch or packaged half-bridge. This terminal may also transfer some heat out of the packaged switch or packaged half-bridge, but its primary purpose is to transmit current. In some embodiments, the die clip may have an additional terminal configured to transfer heat out of the packaged switch or packaged half bridge.

[0096] The die substrate terminals may extend through the surface of the packaged switch or packaged half bridge. Similarly, the die clip terminals may extend through the surface of the packaged switch or packaged half bridge. Unless otherwise noted, the die substrate terminals and die clip terminals have substantially planar surfaces that are substantially flush with the plastic case surfaces of the packaged switch or packaged half bridge. However, in other embodiments, these flat surfaces may be substantially recessed below the surfaces of the plastic case, or the flat surfaces may substantially protrude above the surfaces of the plastic case. 2AA shows an exemplary die substrate terminal 230 having a substantially planar surface that is substantially flush with the top surface of packaged switch 200 . 2AA also shows an example die clip terminal 232 having a substantially planar surface flush with the side surface of the packaged switch 200 . 2BA and 2BB show similar die substrate terminals 230H and 230L and die clip terminals 232H and 230L, with surfaces flush with the top, bottom, and side surfaces of packaged half bridge 250. ) is shown. The die clip terminals include several recesses that can mate with extensions of an external conductor (such as a V-bus bar or clamp described more fully below) to allow for better electrical connections. can do.

[0097] 2AA and 2AB show an exemplary die substrate terminal 230 and die clip terminal 232 having substantially planar surfaces that are substantially flush with the surfaces of plastic case 202 . 2BA and 2BB show a similar die substrate terminal 230 and die clip terminal 232 having substantially planar surfaces that are substantially flush with the surfaces of plastic case 252 . It should be understood that the die clip and die board terminals should not be limited to those shown in FIGS. 2aa, 2ab, 2ba and 2bb. In alternative embodiments, the die clip and die substrate terminals can take different shapes, shapes and sizes. The die clips and/or die substrates may be configured to have terminals having surfaces in planes that are substantially above or below parallel planes that include the surfaces of the plastic cases 202 or 252 .

[0098] Current can enter the packaged switch or half-bridge through the die-board terminals and subsequently exit through the die-clip terminals, or the current can flow in the reverse direction through the packaged switch or half-bridge but with current in the reverse direction. Flow may not be efficient. To illustrate, current enters the packaged switch 200 through the die substrate terminal 230, flows through the die substrate, the activated switch, the die clip, and then through the die clip terminal 232 into the packaged switch. (200) can be escaped. In a similar manner, current enters the packaged half bridge 250 through the high-side die board terminal 230H and flows through the high-side die board, the activated high-side switch, and the high-side die clip. Next, the packaged half bridge 250 may be exited through the high-side die clip terminal 232H. Current then enters the packaged half bridge 250 through the low-side die board terminal 230L, flows through the low-side die board, the activated low-side switch, the low-side die clip, and then the die The packaged half bridge 250 may be exited through the low-side die clip terminal 232L.

[0099] Die substrates and die clips, depending on their configuration (eg, thickness, terminal width and length, metal type, etc.), can transmit high levels of current to or from switches connected to them. . For example, a copper-based die substrate having a terminal 230 with a width of 24 mm and a length of 11.2 mm can transmit a current of 400 A or more, and a terminal 232 with a width of 1.6 mm and a length of 11.4 mm ) can transmit more than 400 A of current.

[00100] Switches get hot, especially when they conduct current at high switching rates. The die substrate is subjected to a large amount of heat (e.g., 10, 20, 50, 00, , 100, 300-750 W or more). The die substrate can be thick (eg, 0.1 mm - 6.0 mm thick), and the thicker the die substrate, the more thermal capacitance the die substrate provides to absorb the sudden increase in heat from the attached switch. can be important Die substrates can transfer even more heat out of packaged switches or packaged half bridges when their terminals are thermally connected to heat sinks. Like the die substrate, the die clip can be thick (eg, 0.1 mm - 6.0 mm thick), the thicker the die clip, the more thermal capacitance the die clip provides. In one embodiment as noted above, the die clip has a first terminal for conducting current into or out of the packaged switch or packaged half bridge, and a second terminal for conducting heat out of the packaged switch or packaged half bridge. can have terminals. The second terminal can transfer even more heat out of the packaged switch or packaged half bridge when the second terminal is thermally coupled to the heat sink. In general, the connection between a pair of components can be direct (eg, the surfaces of the components are in contact with each other), or the connection between a pair of components can be solder, a third metal component, may be indirect through a combination of solder and a third metal component, conductive adhesives, sintering material such as thermal and/or electrical intervening material such as silver, thermal grease, wire bond, etc. there is. Connections can conduct heat, current, or both between components.

Exemplary Packaged Switches

[00101] With continued reference to FIG. 2AA , FIGS. 3AA , 3AB and 3AC are schematic diagrams of an exemplary packaged switch 200 , showing some relevant components of the exemplary packaged switch 200 . 3AA, 3AB, and 3AC show the relative positions of certain components when viewing the packaged switch 200 from the top, side, and rear, respectively. The packaged switch 200 includes an exemplary switch module 300 as shown in FIG. 3AA. As will be described more fully below, a packaged half bridge may include a pair of switch modules, such as switch module 300 .

[00102] Switch module 300 includes switch controller 302 that controls switch 304 based on low-power PWM signals and/or other signals received from a microcontroller or similar processor-based device. Switch 304 is coupled to die substrate 312 and die clip 316 and positioned between die substrate 312 and die clip 316, both of which are represented by symbols. Die substrate 312 and die clip 316 conduct large currents. To indicate that the die substrate 312 is also configured to conduct relatively more heat out of the packaged switch 200, when compared to the amount of heat transferred out by the die clip 316, It is represented by a thicker line in the figures. Switch module 300 also includes temperature sensor circuitry (T_Sense) for sensing the temperature near switch 304, and current sensor circuitry (I_sense) for sensing the current sent by switch 304. A switch module may include fewer or more components than shown in the figures. For example, switch module 300 may also include a voltage sensor circuit that senses the voltage across the current terminals of switch 304 in another embodiment.

[00103] Figures 3aa, 3ab and 3ac show the relative positioning of components relative to each other. As can be seen in Figure 3ab, the die substrate 312, switch 304 and die clip 316 are stacked vertically between top (T) and bottom (B). Stacking these components reduces the height and, therefore, the volume of the packaged switch 200 . Switch controller 302 is positioned near the front (F) of the packaged switch 200, while switch 304 is positioned near the back (Bk) of the packaged switch 200.

[00104] For ease of illustration and description, die substrate terminal 230 is symbolically represented as a square in the figures. Depending on the view, the die clip terminal 232 is symbolically represented in the figures as a hexagon or as an octagon. For example, in the top and bottom views of FIGS. 3AA and 3AC , respectively, die clip terminal 232 is symbolically represented as a hexagon. In the side view of Figure 3ab, the die clip terminal 232 is represented as an octagon.

[00105] The die board terminal 230 is positioned in FIGS. 3A and 3AC to indicate that it is flush with the top surface of the packaged switch 200, and the die clip terminal 232 is positioned on the same level as the top surface of the packaged switch 200. It is positioned in Figures 3aa and 3ac to indicate that it is flush with the left surface of . The die clip terminal 232 is drawn with a center dot in FIG. 3AB to indicate that current enters or exits the packaged switch 200 through its left side ( drawn). 3BA, 3BB and 3BC show an alternative packaged switch 201, which is similar to packaged switch 200, but with die clip terminals 232 indicating that they are flush with the right side surface. is positioned in Figures 3ba and 3bc to The die clip terminal 232 in FIG. 3BB is drawn without a center dot to indicate that current enters or leaves the right side of the packaged switch 201. It is noted that in other embodiments, the die substrate terminals or die clip terminals may intentionally recess below or protrude above the packaged switch surface or packaged half bridge surface.

[00106] With continued reference to FIGS. 3AA, 3AB, and 3AC, FIG. 3AD shows an exemplary switch controller 302 that includes a gate driver 306, resistors R1 and R2, and diodes 308 and 310. it is a schematic A switch controller may include fewer or more components than shown in the figures. 3AD shows switch 304, but does not show die substrate 312 and die clip 316. Although not shown in this figure, the cathode of diode 308 is coupled to die substrate 312.

[00107] Prior art inverter systems mount gate drivers, such as gate drivers H101-H103 and L101-L103 in FIG. 1A, on large and expensive printed circuit boards (PCBs). Long conductive traces on these PCBs carry signals between the gate drivers and the power transistors (eg, IGBTs) external to the PCBs. Long traces between gate drivers and transistors increase parasitic induction and/or capacitance, which in turn increases undesirable power consumption and signal delay. Signals transmitted over longer traces are more susceptible to noise. In contrast, switch controller 302 including gate driver 306 is contained within a packaged switch or packaged half bridge and is positioned proximate switch 304 . Compared to prior art inverter systems, a shorter conductive line (eg, 5 mm or less) connects the control signal output of gate driver 306 and the gate(s) of switch 304. Shorter conductive lines reduce parasitic induction, signal delay, signal degradation due to noise, and/or other problems associated with gate drivers mounted on PCBs as described above. Gate driver 306 consumes less power while driving the gate. And the gate driver 306 can drive the gate of the switch 304 more quickly.

[00108] Typically, switch 304 includes one or more transistors such as IGBTs, MOSFETs, JFETs, BJTs, and the like. Switch 304 may include additional components such as diodes. Transistors and/or additional components within switch 304 may be made of any of many different types of semiconductor materials such as Si, SiC, GaN, GaO, and the like. 3ae and 3af are schematic diagrams illustrating example switches 304 . 3ae, switch 304 includes a power IGBT connected in parallel with diode D. Collector (c) and diode cathode are connected or attached (eg, sintered, soldered, etc.) to die substrate 312, while emitter (e) and diode anode are connected or attached (eg, to die clip 316). eg, sintering, soldering, etc.). In some embodiments, an IGBT has one emitter, but may have several emitter terminals. In such embodiments, each of the emitter terminals are attached to die clip 316 . 3af, switch 304 includes power MOSFETs (e.g., SiC MOSFETs, GaN MOSFETs, or MOSFETs made of other semiconductor materials such as GaO), with N1 and N2 coupled in parallel. ring Drains d of MOSFETs N1 and N2 are attached (eg, sintered, soldered, etc.) to die substrate 312, while sources s are attached to die clip 316 (eg, sintered, soldered, etc.). For example, sintering, soldering, etc.). In some embodiments, a MOSFET has one source, but may have several source terminals. In such embodiments, each of the source terminals are attached to die clip 316 . Each gate g is controlled by a high-current gate control signal Vg from driver 306. Switches other than switch 304 shown in the figures may be used in alternative embodiments.

[00109] With continued reference to FIGS. 3AA and 3AD , the components are connected to signal leads shown symbolically (eg, 204-208). Signal leads connect components inside the switch module (eg, gate driver 306 and resistor R1). The signal leads also connect components internal to the switch module (eg, gate driver 306 ) and components external to the switch module (eg, microcontroller, voltage regulator, etc.). Some signal leads are not shown in FIGS. 3AA and 3AD for ease of illustration. Some components of the switch module may be connected to signal leads through additional wires or conductors. For example, wire bonding or other type of connection method may be used to connect gate g of switch 304 to a signal lead, which in turn connects to resistor R2.

[00110] Some switch module components can take the form of packaged devices or bare semiconductor dies that can be purchased from original equipment manufacturers. Packaged devices have leads that are connected (eg, soldered) to signal leads. Bare semiconductor dies have pads that can be wire bonded to signal leads. Unless otherwise noted, switch module components are assumed to take the form of packaged devices with leads extending from them, which can be connected (eg, soldered) to individual signal leads. For example, gate driver 306 may take the form of a packaged integrated circuit having leads soldered to signal leads, such as signal leads 204 and 206 . I_Sense or I_Temp circuitry may also take the form of packaged integrated circuits with leads connected to signal leads via a flexible flat cable (FFC, such as a flex PCB, not shown). there is. FFC refers to any variety of flat as well as flexible electrical cable having flat conductors or traces formed on a flexible substrate. Resistors R1 and R2 and diodes 308 and 310 may be packaged components with leads connected to signal leads using solder.

[00111] The signal leads (eg, signal leads 204-208) may be constructed of a metal structure referred to as a "signal frame substrate", an example of which will be described more fully below. Signal leads may be fabricated using alternative methods. For example, a liquid crystal polymer may be injected into a mold to create a rigid substrate. Conductive traces may then be patterned on the substrate to form signal leads. However, for purposes of explanation, the remainder of the disclosure will assume the configuration of the signal leads from the signal frame substrate. Generally, a signal frame substrate resembles a "lead frame", a thin metal frame to which devices are attached during semiconductor package assembly. While on the signal frame substrate, the signal leads are not electrically isolated from each other. After the conductive leads, diode 308 and other components of the packaged gate driver 306 (or bare semiconductor die gate driver 306) are attached to the signal frame substrate, the bond is encapsulated in plastic. The plastic and signal frame substrates may be trimmed to create the packaged switch 200 or packaged half bridge 250 shown in Figures 2aa, 2ab, 2ba and 2bb, for example. More specifically, portions of the signal frame substrate and plastic are trimmed after molding to yield plastic cases (eg, cases 202 and 252) and signal leads (eg, 204 and 206). After trimming, the signal leads are isolated from each other, but held firmly in place by the plastic casing. Significantly, the signal frame substrate can be designed to accommodate many different combinations, types, shapes, arrangements, etc. of the components of a switch module.

[00112] With continued reference to FIGS. 3ae and 3af , the switches 304 are electrically and thermally coupled to the die substrates. In one embodiment, the first current terminal (e.g., collector, drain, etc.) of each transistor in switch 304 is sintered to die substrate 312 via a layer of a highly conductive sintered material such as silver. . In the illustrated embodiments, no dielectric is added between the switch 304 and the die substrate terminal so that there is no dielectric between the switch 304 and the die substrate terminal. The die board terminals are configured for direct or indirect connection to external devices. For example, die substrate terminal 230 may be connected to a "V+ bus bar", which in turn is connected to the V+ battery terminal directly or indirectly through a device such as a DC-DC converter. Generally, bus bars are metal elements used for high current distribution. The material composition and cross-sectional size of a bus bar or elements of a bus bar determine the maximum amount of current that can be safely carried. The V+ bus bar can also act as a heat sink with one or more channels through which a fluid (eg, air or liquid, such as a mixture of water and ethylene glycol) can flow. Alternatively, die board terminal 230 may be connected to an AC bus bar or "phase bus bar", which in turn is connected to the terminals of winding W. The phase bus bar (hereafter referred to as phase bar) may include a metal clamp that engages the die substrate terminals. A power cable may connect the metal clamp to the winding terminals. One end of the power cable is connected to the clamp, while the other end is connected to the winding terminal.

[00113] In FIG. 2AA, the die substrate terminal 230 has a flat surface exposed through the opening of the plastic case of the packaged switch 200. The packaged half bridge 250 of FIGS. 2BA and 2BB has similar die substrate terminals 230L and 230H. The dimensions (eg, width and length) of exposed terminal 230 are configured to conduct significant current and heat. In one embodiment, the die substrate terminals 230 face parallel to, but opposite to, the at least one surface of the die substrate 312 to which the first current terminal (e.g., collector, drain, etc.) is attached (i.e., 180 do).

[00114] Switches 304 are electrically and thermally connected to the die clips. For example, the second current terminal (e.g., emitter, source, etc.) of each transistor in switch 304 is sintered to die clip 316 via a layer of highly conductive sintered material such as silver. . In the illustrated embodiments, no dielectric is added between the switch 304 and the die clip terminal so that there is no dielectric between the switch 304 and the die clip terminal. The die clip terminals are configured to connect directly or indirectly to a device external to the packaged switch or packaged half-bridge. The die clip terminals 232 can be connected to the clamps mentioned above, which in turn are connected to the terminals of the windings via power cables. Alternatively, the die clip terminal 232 can be connected to the "V-bus bar", which in turn is connected to the V- battery terminal. In some embodiments, the V-bus bar can also act as a heat sink with one or more channels through which a fluid, such as air, can flow.

[00115] Still referring to FIG. 2AA , die clip terminal 232 has a substantially flat surface area exposed through an opening in the plastic case of packaged switch 200 . The packaged half bridge 250 of FIGS. 2BA and 2BB has similar die clip terminals 232L and 232H. The dimensions (eg, width and length) of exposed terminal 232 are configured to carry significant current.

[00116] The gate drivers of the switch module may receive signals from a microcontroller, individual microcontrollers, or similar processor-based device(s). For example, the gate driver circuit 306 of FIG. 3AD can receive a low-power PWM driver control signal similar to one of the PWM signals described with reference to FIG. 1A. Additionally, gate driver 306 may receive a low-power Reset signal from a microcontroller or other device. The gate driver circuit 306, after it receives the asserted Reset signal, asserts the high-current gate control signal (Vg) to switch in response to the assertion of the PWM signal it receives. (304) can be selectively activated. The distance between the output of the gate driver 306 and the gate or gates of the switch 304 should be reduced to mitigate adverse effects on the gate control signal Vg due to parasitic inductance, parasitic capacitance, noise, and the like. Gate drivers may also send signals to a microcontroller or similar processor-based device. For example, the gate driver circuit 306 disables the switch 304 (i.e., maintains the switch in a disabled state) and detects a fault such as excessive current conduction through the switch 304. Fault signals can be asserted when a fault is detected. A microcontroller or similar processor device may receive and process the Fault signal. Other components, such as the I_sense circuit and the Temp_sense circuit, may transmit signals indicating the current flow through the switch 304 and the temperature of the switch 304. If included, the voltage sensing circuit, if added, may likewise transmit a signal representative of the voltage across switch 304 . A microcontroller or similar processor-based device may receive and process signals provided by these other components. For example, the microcontroller can compare the signal representing the temperature to a first threshold and, if the threshold is exceeded, change the frequency or duty cycle of the PWM control signal provided to the gate driver circuit 306, or the microcontroller may continue to de-assert the PWM control signal provided to gate driver circuit 306 once the threshold is exceeded, which in turn keeps switch 304 in an inactive state.

[00117] 3AG illustrates an example gate driver 306 that includes a low-voltage input stage 320 in data communication with a high-voltage output stage 320 through a galvanic isolation circuit 324 . Galvanic isolation is used when two or more circuits must communicate but their grounds are at different potentials. Galvanic isolation circuits may use a transformer, capacitor, optocoupler or other device to achieve isolation between circuits. For illustrative purposes only, galvanic isolation circuit 324 uses a transformer device to implement galvanic isolation. The low-voltage input stage 322 is coupled to receive a first supply voltage (VDDI) and a first ground (GI) and includes a logic circuit 330 that receives PWM and Reset signals. The high-voltage output stage 322 is coupled to receive a second supply voltage (VDDO+), a third supply voltage (VDDO-) and a second ground (GO), and through a galvanic isolation circuit 324 a logic circuit ( and a logic circuit 332 that receives a control signal from 330). The high-voltage output stage 332 also includes a buffer 340 controlled by an output signal from the logic circuit 332 . The buffer asserts Vg when the control signal output of isolation circuit 324 is asserted. Other types of gate drivers 306 are contemplated.

[00118] Still referring to FIG. 3AA , I_sense produces a voltage signal Vi having a magnitude proportional to the current flow through switch 304 . I_sense may include an inductive current sensor that measures the magnetic field produced by current flow through the switch 304 in general and through the die clip in particular. As shown in Figure 3ac, the exemplary die clip 316 includes horizontal and vertical portions. The I_sense circuit can measure current flow through a narrowed portion (not shown) of the horizontal portion. I_sense conditions the signal output of the inductive current sensor for subsequent use by the microcontroller. The inductive sensor is galvanically isolated from transistor T.

[00119] T_sense may include a thermistor capable of generating a voltage signal (Vt) having a magnitude proportional to the temperature near switch 304 . A thermistor is a type of resistor whose resistance depends on temperature; The relationship between resistance and temperature is linear. T_sense conditions the thermistor's signal output for use by the microcontroller. The thermistor is galvanically isolated from transistor T.

[00120] Analog signals Vi and Vt from the I_sense and T_sense circuits, respectively, can be sent to a microcontroller for subsequent conversion to digital equivalents. Conductors, such as traces of flexible flat cabling (e.g., a flex PCB (not shown)), may be routed through the traces of the PCB (not shown) to the individual signal lead terminals of the microcontroller and switch module 300. It can be used to transmit signals including Vi, Vt and Fault between Other types of conductors may be used to transmit signals to the microcontroller. Unless noted otherwise, this disclosure assumes the use of a flexible flat cable such as a flex PCB. Flexible flat cabling can also be used to transmit other signals (eg, PWM and Reset) and voltages (eg, VDDI, VDDO+, GL, etc.) to the switch module 300 . A microcontroller can process digital equivalents of the signals it receives (eg, Fault, Vi and Vt) according to instructions stored in memory. The microcontroller may adjust the duty cycle and/or period of the driver control signals PWM based on the digital equivalents of Vi and Vt. In embodiments of packaged power modules that include circuitry to monitor the voltage across the switch, the analog signal Vv representing the voltage is sent to the microcontroller by the voltage monitoring circuitry for processing according to instructions stored in memory. can be provided.

[00121] 3ca and 3cb are schematic diagrams of an alternative packaged switch 203, showing some components of the alternative packaged switch 203. 3CA and 3CB show the relative positions of components of the packaged switch 203 when viewing the packaged switch 203 from the side and from the back, respectively. Like packaged switch 200 , packaged switch 203 includes a switch 304 controlled by switch controller 302 . The switch 304 is coupled (eg, sintered) to and between the die substrate 312 and the die clip 342 including the die clip terminals 344 . Die clip 342 and die clip terminal 344 are shown symbolically. Both die substrate 312 and die clip 342 are represented by thick lines to indicate that they are configured to carry significant current and significant heat. The shape and form of die clip 342 and terminal 344 of die clip 342 are substantially different from die clip 316 and terminal 232 of die clip 316 . The die substrate 312 and the die clip 342 may be substantially identical, and have substantially identical die substrate and die clip terminals 230 and 344, respectively.

[00122] 3ca and 3cb illustrate the relative positioning of components relative to each other. The die substrate 312, the switch 304, and the die clip 342 are stacked vertically between the top (T) and bottom (B) of the packaged switch 203. Switch controller 302 is positioned near the front (F) of packaged switch 203, while switch 304 is positioned near the rear (Bk). Die board terminal 230 is positioned in the figures to indicate that it is flush with the top surface of packaged switch 205, and die clip terminal 344 is likewise positioned flush with the bottom surface. is positioned to display

[00123] 3Da and 3DB are schematic diagrams of an alternative packaged switch 205, showing some of the components of the alternative packaged switch 205. 3Da and 3DB show the relative positions of components of the packaged switch 205 when viewing the packaged switch 205 from the side and from the back, respectively. Like packaged switch 200 , packaged switch 205 includes a switch 304 controlled by switch controller 302 . The switch 304 is coupled (eg, sintered) to and between the die substrate 312 and the die clip 346 including the die clip terminals 232 . Die clip 346 is shown symbolically. The die clip terminals 232 are flush with the back surface. Die clip 346 is represented by a thin line to indicate that it is primarily configured to transmit current and not heat. Die clips 316 and 346 are substantially different in shape and form, but have similar terminals 232 .

[00124] 3da and 3db illustrate the relative positioning of components relative to each other. The die substrate 312, the switch 304, and the die clip 346 are vertically stacked between the top (T) and bottom (B) of the packaged switch (205). Switch controller 302 is positioned near the front (F) of packaged switch 205, while switch 304 is positioned near the rear (Bk). Die board terminal 230 is positioned in the figures to indicate that it is flush with the top surface of packaged switch 203, and die clip terminal 324 indicates that it is flush with the back surface. is positioned in FIG. 3Da to be.

[00125] 3ea and 3eb are schematic diagrams of an alternative packaged switch 207, showing some components of the alternative packaged switch 207. 3ea and 3eb show the relative positions of components of the packaged switch 205 when viewing the packaged switch 205 from the side and from the back, respectively. Like packaged switch 200 , packaged switch 207 includes a switch 304 controlled by switch controller 302 . The switch 304 is coupled (eg, sintered) to and between the die substrate 312 and a die clip 345 comprising a pair of die clip terminals 232 and 344 . Die clip 345 and terminals 232 and 344 of die clip 345 are shown symbolically. As shown, die clip 345 includes first and second portions 348 and 350 and a third portion 354 extending perpendicularly from the first and second portions. Third portion 354 is drawn thinner to indicate that it is primarily configured to transmit current, while first and second portions 348 and 350 are drawn thinner to indicate that they are also configured to transfer heat. drawn with thick lines. However, second portion 350 will only conduct heat if second portion 350 is connected to an electrically isolated device, such as an electrically isolated heat sink. 3eb shows a current sensor circuit (I_sense) for sensing the current transmitted through the third portion 354.

[00126] 3ea and 3eb illustrate the relative positioning of components relative to each other. The die substrate 312, the switch 304, and the die clip 345 are stacked vertically between the top (T) and bottom (B) of the packaged switch 207. The switch controller 302 is positioned near the front (F) of the packaged switch 207. Switch 304 is positioned near the rear (Bk). Die board terminal 230 is positioned in the figures to indicate that it is flush with the top surface of packaged switch 207, and die clip terminal 232 indicates that it is flush with the left surface. 3B, and the die clip terminal 344 is positioned in the figures to indicate that it is flush with the bottom surface.

[00127] 3fa and 3fb are schematic diagrams of an alternative packaged switch 209, showing some components of the alternative packaged switch 209. 3fa and 3fb show the relative positions of components of the packaged switch 209 when viewing the packaged switch 209 from the side and from the back, respectively. Packaged switches 207 and 209 are substantially identical to each other. However, die clip terminals 232 in packaged switch 207 are positioned to indicate that they are flush with the left surface, while die clip terminals in packaged switch 209, as shown in Figure 3fb. 232 is positioned to indicate that it is flush with the right surface.

Exemplary Packaged Half Bridges

[00128] Packaged half bridges may include a pair of switch modules. With continued reference to FIGS. 2BA and 2BB , FIGS. 3GA and 3GB are schematic diagrams of an exemplary packaged half bridge 250 , illustrating several components of the exemplary packaged half bridge 250 . 3GA and 3GB show the relative positions of certain components of packaged half bridge 250 from side and rear views, respectively. The packaged half bridge 250 includes a pair of switch modules 300 as shown in FIG. 3AA. More specifically, the packaged half bridge 250 includes a high-side switch module 300H and a low-side switch module 300L. The switch modules face each other inside the packaged half bridge 250; High-side switch module 300H is flipped and positioned below low-side switch module 300L. For ease of illustration, most of the signal leads shown in Figs. 3aa have been omitted from Figs. 3ga and 3gb.

[00129] 3ga and 3gb illustrate the relative positioning of certain components of half bridge 250 relative to each other. Die substrates 312, switches 304 and die clips 316 are stacked between top (T) and bottom (B). Switch controllers 302 are likewise stacked between top (T) and bottom (B). Switch controllers 302 are positioned near the front (F) of packaged half bridge 250, while switches 304 are positioned near the back (Bk). The die substrate terminals 230L and 230H are accessible through the plastic case on the top (T) and bottom (B) of the packaged half bridge 250, respectively, and the die clip terminals 232L and 232H are, It is accessible through the plastic casing on the right and left surfaces of the packaged half bridge 250, respectively. Die substrate terminals 230L and 230H are positioned in the figures to indicate that they are flush with the top (T) and bottom (B) surfaces, respectively, and the die clip terminals 232L and 232H are, respectively, They are positioned in Fig. 3gb to indicate that they are flush with the right and left surfaces.

[00130] High-side switch 304H is connected to high-side die substrate 312H, which has terminal 230H for connection to a device external to packaged half bridge 250. For example, terminal 230H may be connected to a V+ bus bar, or terminal 230H may be connected to a phase bar or a component of a phase bar (eg, a clamp). High-side switch 304H is also connected to high-side die clip 316H, which has terminals 232H for connection to a device external to packaged half bridge 250. . For example, terminal 232H can be connected to a phase bar or a V- bus bar. Low-side switch 304L is connected to low-side die substrate 312L, which has terminal 230L for connection to a device external to packaged half bridge 250. For example, low-side die substrate terminal 230L can be connected to the same phase bar that high-side die clip terminal 232H is connected to, or low-side die substrate terminal 230L can be connected to a heat sink. there is. Low-side switch 304L is connected to die clip 316L, which has terminal 232L for connection to a device external to packaged half bridge 250. For example, terminal 232L can be connected to a V- bus bar or a phase bus bar.

[00131] 3ha and 3hb are schematic diagrams of an alternative packaged half bridge 251 , showing some components of the alternative packaged half bridge 251 . Half bridge 251 is similar to packaged half bridge 250, but die clip 316L is rotated 180 degrees as shown. 3ha and 3hb show the relative positions of certain components of the packaged half bridge 251 from the side and rear views, respectively. Die clip 316 may be slightly modified to accommodate 180 degree rotation. 3HB shows low-side die clip terminal 232L and high-side die clip terminal 232H positioned to indicate that they are flush with the left surface.

[00132] 3ia and 3ib are also schematic diagrams of an alternative packaged half bridge 253, showing some components of the alternative packaged half bridge 253. 3ia and 3ib show the relative positions of components of the packaged half bridge 253 from side and rear views, respectively. Packaged half bridge 253 is similar to packaged half bridge 250, but both die clip terminals 316 are rotated 180 degrees as shown. Figure 3ib shows the low-side die clip terminal 232L positioned to indicate that it is flush with the right surface and the high-side die clip terminal 232H positioned to indicate that it is flush with the left surface. show

[00133] 3KA and 3KB show an integrated die clip 315 similar to packaged half bridge 250 but with die clips 316H and 316L attached (eg, sintered) to switches 304H and 304L. Schematic diagrams showing side and back views of another packaged half bridge 255 replaced by . The die clip 315 has the same terminal 232 as the die clip terminal 232 of the die clip 316. The die clip terminal 232 is positioned in Figure 3kb to indicate that it is flush with the right side surface.

[00134] 3la and 3lb are schematic diagrams of another packaged half bridge 259, showing some of the components of another packaged half bridge 259. Half bridge 259 is similar to packaged half bridge 250, but die clips 316L and 316H are replaced with die clips 317L and 317H, respectively. 3la and 3lb show the relative positions of certain components of packaged half bridge 259 from side and rear views, respectively. 3lb shows low-side die clip terminal 232L and high-side die clip terminal 232L and high-side die clip terminal 232L and high-side die clip terminal 232H positioned to indicate that they are flush with the right side surface. The clip terminal 232H is shown. Die clips 317 and 316 are similar in many features. For example, like die clip 316, die clip 317 includes horizontal and vertical portions. 3la shows only the vertical portions of the die clips 317. There is at least one substantial difference between die clips 316 and 317; The horizontal portion of die clip 317 extends and is positioned between oppositely facing die clip terminals 232 and 233. Both die clip terminals 232 and 233 are accessible through the plastic casing of half bridge package 259. Die clip terminals 232 and 233 are flush with opposite side surfaces of packaged half bridge 259 as shown. Die clip terminals 232 and 233 may be similar in shape and size and may be configured to transmit high current into or out of packaged half bridge 259 .

width

[00135] 3J is a schematic diagram of another packaged half bridge 261 , showing some components of another packaged half bridge 261 . Half bridge 261 is similar to packaged half bridge 250, but die clips 316L and 316H are replaced with die clips 319L and 319H, respectively. 3J shows the relative positions of certain components of the packaged half bridge 261 as viewed from the side. 3J shows low-side die clip terminal 232L and high-side die clip terminal 232L and high-side die clip terminal 232L positioned to indicate that the high-side die clip terminal 232H is flush with the rear surface. The clip terminal 232H is shown.

Exemplary Compact Inverter Systems

[00136] Compact inverter systems have high power densities compared to prior art inverter systems. For example, compact inverter systems can deliver over 400 kW of peak power to an electric motor or other device while occupying a volume of less than 0.25 liters. Space is partially saved by arranging packaged switches, packaged half bridges, heat sinks, bus bars, etc. one on top of the other.

[00137] 4AA is a schematic diagram showing a side view of an exemplary compact inverter system 400 . Inverter system 400 includes packaged half bridges 250 as shown in FIG. 3GA. For ease of illustration, switch controllers, T_Sense circuits, I_sense circuits and signal leads are not shown.

[00138] The compact inverter system 400 includes three phases designated a-c. Phases a-c each include packaged half bridges 250ab50c connected to phase bars PBa-PBc, respectively, which in turn are in turn to windings Wa-Wc, respectively. Connected. Phase bars PB in compact inverter system 400 and other compact inverter systems described below may have different configurations to accommodate differences in compact inverter design. However, for ease of explanation, differences in the phase bars of the various compact inverter system embodiments are not discussed unless otherwise noted.

[00139] Die substrate terminals 230Lab30Lc are connected to heat sinks 402ad02c, respectively. The heat sinks 402ad02c are electrically isolated from each other. Each heat sink 402 has one or more channels (not shown in FIG. 4AA) through which an electrically isolated cooling fluid may flow. Die substrate terminals 230H are connected to V+ bus bar 404, which also has one or more channels (not shown in FIG. 4AA) through which electrically isolated cooling fluid can flow. ) as a heat sink with Figure 4ab is a rear view of phase-a. This figure shows example channels 40 of V+ bus bar 404 and heat sink 402a. To improve heat transfer, the channels 40 may each be positioned closer to the surface in contact with the die substrate terminals 230, as shown.

[00140] In general, heat sinks and/or V+ bus bars used in the disclosed compact inverter systems, such as those shown in FIGS. 4AA and 4AB, include channels 40 . Some V-bus bars may also include channels 40. Channels 40 are configured to hold conduits (eg, pipes), which in turn have their own channels through which cooling fluid can flow. For illustrative purposes, all heat sinks and V+ bus bars are assumed to have channels 40 comprising conduits. And all V-bus bars that also act as heat sinks are assumed to have channels 40 that also contain conduits. Additionally, it is assumed that the channels 40 are circular in cross section and the conduits are cylindrical pipes, and it is understood that the present disclosure should not be limited thereto. In alternative embodiments, channels 40 may be rectangular or square in cross section.

[00141] 4ac-4af are cross-sectional views of exemplary cylindrical pipes 420ad20d, respectively. The outer surfaces of pipes 420a - 420d contact surfaces of cylindrical channels of any one or more of the heat sinks, V+ bus bars, or specific V- bus bars disclosed herein. Each of the illustrated example pipes 420ad20c includes a thin layer (eg, aluminum oxide, aluminum nitride, silicon nitride, chemical vapor deposited diamond coating, etc.) of a dielectric material coating the outer surface of the pipe. For example, 0.1 - 1.0 mm) 422. In an alternative embodiment, a thin layer of dielectric coats the inner surface of the pipe. For purposes of explanation, this disclosure assumes that all of the thin layers of thin layers 422 are applied to the outer surface of the pipe to coat the outer surface of the pipe. In this embodiment, the outer surface of the dielectric layer 422 contacts the inner surface of the channels. During construction, the pipes may be cooled using, for example, liquid nitrogen. As the pipe warms, it expands inside its channel, ensuring better contact between the dielectric layer 422 and the cylindrical walls of the channel. A heat sink or bus bar with channels incorporated therein may be cooled simultaneously. Ideally, dielectric layer 422, if any, should be the only dielectric in the thermal path between switch 304 and the fluid in the pipe. In an alternative embodiment where a dielectric layer is applied to the inside wall of the pipe, that layer should be the only dielectric in the thermal path between the switch 304 and the fluid in the pipe.

[00142] The dielectric material of layer 422 should have a strength of 0-10 kV. Dielectric layer 422 is assumed to be 0.2 mm in Figures 4ac-4af. The thickness and material of the dielectric layer 422 affects the heat transfer of the pipe.

[00143] The table below contains the calculated heat transfer (W) for dielectric layer 422 of different materials and thicknesses. W is proportional to k A (T1-T2)/d, where k is the thermal conductivity, A is the area, T1-T2 = 70 is the temperature difference across the dielectric layer, and d is in microns. is the thickness 4000 volts across the dielectric is assumed.

[00144] Dielectric 422 directly engages the channel surface of the heat sink or bus bar within which the pipe is contained. Each pipe includes one or more channels through which cooling fluid can flow. The pipe channels have different cross-sectional shapes as shown. Pipes 420a and 420b contain a single channel, while pipes 420c and 420d contain multiple channels. The pipe 420a has a smooth inner wall. In an alternative embodiment, pipe 420a may have a rifled inner wall. Rippling is the process of machining helical grooves into the inner surface of a pipe for the purpose of creating or increasing fluid turbulence or molecular contact. Rippling is often described by its twist rate, which indicates the distance it takes for the rippling to complete one full revolution. In one embodiment, the inner wall of the rippled pipe 420a has a maximum inner diameter, a minimum inner diameter, one or more ribs each having an equal or unequal width, and a twist rate. The channel of pipe 420b is a “flower” shaped ring of small cylindrical sub-channels having substantially the same cross-section and in fluid communication with a centrally located cylindrical sub-channel, - the channel may be larger in cross section compared to the cross sections of the cylindrical sub-channels of the ring. Individual spoke sub-channels enable fluid communication between each cylindrical sub-channel of the ring and the centrally located cylindrical sub-channel. Each spoke sub-channel can have any one of many cross-sectional shapes. In the illustrated embodiment, each spoke sub-channel is substantially rectangular in cross section, but square or circular cross sections are also contemplated. Pipe 420c includes a plurality of small cylindrical channels of substantially similar dimensions. Pipe 420d is a hybrid of pipes 420b and 420c. Dielectric layer 422 electrically isolates each pipe and thus the fluid within the channel, channels, or sub-channels of the pipe. However, the dielectric layer 422 transfers heat to the cooling fluid flowing through the pipe channels. In an alternative embodiment, no dielectric (eg, layer 422) is present between the cooling fluid and the switch 304. However, in this alternative embodiment, the cooling fluid must be dielectric. The diameters of the pipes in the bus bar or heat sink need not be the same as each other. The number, position and/or diameter of pipes 420a - 420d may depend on one or more variables. For example, the number, position and/or diameter of the pipes may depend on the desired thermal capacitance of the heat sink or bus bar in which the pipes are incorporated. Alternatively, the number, position and/or diameter of the pipes may depend on the desired thermal resistance between the switch 304 and the fluid within one or more of the pipes. Alternatively, the number, position and/or diameter may depend on optimizing the thermal capacitance based on the desired thermal resistance, or vice versa.

[00145] Although not shown in schematic diagrams of compact inverter systems, all die substrate terminals 230 are connected to heat sinks, V+ bus bars, phase bars, or corresponding pedestals on V- bus bars. The pedestals may have substantially planar surfaces. More specifically, each pedestal may have a flat surface connected to a die substrate terminal. The pedestal surface is substantially similar in size and shape to the die substrate terminals to which the pedestal surface is connected. Heat and/or current is transferred between the die board terminal and the connected pedestal of the die board terminal. Although not required, a thin layer of thermally conductive and/or electrically conductive grease may connect the die substrate terminals to the pedestal surface to improve thermal and/or electrical conductivity therebetween. The pedestals may be configured to create an air gap between the signal leads of packaged switches or packaged half bridges and V- bus bars, heat sinks, phase bars, or V+ bus bars. The air gaps electrically isolate the signal leads from heat sinks, V- bus bars, phase bars, or V+ bus bars. In an alternative embodiment, a layer of dielectric material may be disposed in the air gaps to further ensure electrical isolation of the signal leads from the heat sinks, V- bus bars, phase bars, or V+ bus bars. Clamps to releasably connect packaged switches or packaged half-bridges to pedestals so that malfunctioning packaged switches or packaged half-bridges of a compact inverter system can be more easily replaced , bolts and other such fasteners may be used.

[00146] Turning to Figure 4aa, the phase bars PBa - PBc are shown symbolically. Phase bars PBa - PBc conduct current between windings Wa - Wc and packaged half bridges 250a - 250c, respectively. Phase bars PBa - PBc have terminals respectively connected to high-side die clip terminals 232Ha - 232Hc, and phase bars PBa - PBc have separate terminals respectively connected to heat sinks 402a - 402c. have The low-side die clip terminals 232La - 232c connect to the V- bus bar 401, which in turn couples to the V- battery terminal. Although the compact inverter system 400 is shown schematically, the half bridge 250, heat sink 402 and V+ bus bar 404 of each phase are shown in side view to illustrate the vertical positioning of these components relative to each other. . The V-bus bar 401 is positioned behind the packaged half bridges 250 in the figure and is shown symbolically.

[00147] 4AA includes current symbols representing current flow through inverter system 400 at an instant in time. More specifically, FIG. 4AA shows current flow through activated high-side switch 304H of phase-a, while low-side switches 304L of phases b and c are activated and V- Conducts current through bus bar 401 to V-. All other switches in the drawing are disabled. Significantly, all die substrate terminals 230 are thermally and electrically coupled to a V+ bus bar heat sink, heat sink 402a, heat sink 402b, or heat sink 402c. Although not shown, a plurality of decoupling capacitors may be coupled in parallel between the V+ bus bar 404 and the V- bus bar 401 .

[00148] 4BA is a schematic diagram showing a side view of another compact inverter system 406 . Each of the phases a-c of this system includes a packaged half bridge 250 as shown in FIG. 3ga, and a packaged half bridge 253 as shown in FIG. 3ia. For ease of illustration, switch controllers, T_Sense circuits, I_sense circuits and signal leads are not shown.

[00149] The packaged half bridges 250 and 253 of each phase are connected to an individual phase bar PB. The phase bars PBa - PBc respectively conduct current between the packaged half bridges of phases a - c and the windings Wa - Wc respectively. Each phase bar PB includes metal extensions 409-1 and 409-2. Die substrate terminals 230L1 and 230H2 are respectively connected to extensions 409-1 and 409-2 of the respective phases. And the metal heat sinks 402-1 and 402-2 are connected to the respective phase extensions 409-1 and 409-2, respectively. The phase bar extensions 409 are formed of a thermally and electrically conductive metal. Phase bar extensions 409-1 and 409-2 of each phase conduct heat from die substrate terminals 230L1 and 230H2, respectively, to heat sinks 402-1 and 402-2, respectively. . Phase bar PB also has extensions or terminals connected to die clip terminals 232H1 and 232L2 of each phase. The die substrate terminals 230H1 and 230L2 of each phase are connected to the V+ bus bar 415. Die clip terminals 232L1 and 232H2 of each phase are connected to the V- bus bar. Although not shown, a plurality of capacitors may be coupled in parallel between the V+ bus bar and the V- bus bar.

[00150] Figure 4bb is a rear view of phase-a. This figure shows example channels 40 in V+ bus bar 415 and heat sinks 402-1a and 402-2a that allow cooling fluid to flow. In the illustrated embodiment, the channels in the heat sinks are positioned closer to the surface in contact with the extensions 409 to improve heat dissipation. In alternative embodiments, channels may be positioned elsewhere. The V+ bus bar 415 of FIG. 4bb has more channels than the V+ bus bar heat sink shown in FIG. 4ab. Although a compact inverter system 406 is shown schematically, each phase's packaged half bridges 250 and 253, heat sinks 402 and V+ bus bar 415 allow vertical positioning of these components relative to each other. To illustrate, it is shown in Figures 4ba and 4bb.

[00151] 4CA is a schematic diagram showing a side view of another compact inverter system 411 . Compact inverter systems 406 and 411 are similar. However, one substantial difference exists; The phase bar PB of each phase in FIG. 4ca has no extensions 409 - 1 and 409 - 2 positioned between the half bridge packages and the heat sinks 40 . In this embodiment, each phase bar PB is coupled to die substrates 230L1 and 230H1 through heat sinks 402-1 and 402-2, respectively.

[00152] 4ba and 4ca include current symbols representing the current flow through the inverter systems 406 and 411 at an instant in time. More specifically, each figure shows when switches 304H1 and 304L2 of phase-a are activated and conduct current from V+ bus bar 415, and all switches of phases b and c ( 304L1 and 304H2) are activated and conduct current through the V- bus bar to V-. All other switches in this figure are inactive.

[00153] Figure 4bc shows the PWM and Reset signals received by phase-a of Figure 4ba. 4BC also shows the Fault, Vi and Vt outputs from phase-a. Each packaged half bridge 250 or 253 of the phase is controlled by separate sets of PWM and Reset signals. In an alternative embodiment, the high-side gate driver and the low-side gate driver of the packaged half bridges 250 and 253, respectively, may be controlled by a first PWM signal from the microcontroller, respectively, The low-side gate driver and high-side gate driver of half bridges 250 and 253 can be controlled by a second PWM signal from the microcontroller.

[00154] Each phase of the exemplary compact inverter systems of FIGS. 4AA, 4BA and 4CA has one or two packaged half bridges. Compact inverter systems should not be limited to this. Compact inverter systems can have phases with three, four or more packaged switches or packaged half bridges. Additional compact inverter systems can be stacked and connected in parallel. 4DA is a schematic diagram showing a side view of another compact inverter system 408. In this embodiment, phases a-c each have four packaged half bridges: two packaged half bridges 250-1 and 250-2 and two packaged half bridges 253-1 and 253 -2). For ease of illustration, the switch controllers, T_Sense circuits, I_sense circuits and signal leads are not shown in FIG. 4DA.

[00155] Phase bars PBa - PBc are shown symbolically. The phase bars PBa - PBc respectively conduct current between the packaged half bridges of phases a - c and the windings Wa - Wc respectively. Each phase bar includes metal extensions 411-1 and 411-2. The die substrate terminals 230L of the packaged half bridges 250 of each phase are connected to an extension 411-1, which in turn is connected to a metal heat sink 419-1. Connected. The die substrate terminals 230H of the packaged half bridges 253 are connected to the extension 411-2, and the extension 411-2 is eventually connected to the metal heat sink 419-2. The phase bar extensions 411 are formed of a thermally and electrically conductive metal. The phase bar extension 411-1 of each phase conducts the heat from the die substrate terminals 230L of the packaged half bridges 250 to the heat sinks 419-1, and the phase bar extension 411-1 of each phase Phase bar extension 411-2 conducts heat from die substrate terminals 230H of packaged half bridges 253 to heat sinks 419-2. The phase bar of each phase also includes terminals connected to die clip terminals 232H in packaged half bridges 250 and die clip terminals 232L in packaged half bridges 253. The die substrate terminals 230H of the packaged half bridges 250 and the die substrate terminals 230L of the packaged half bridges 253 of each phase are the three V+ bus bars shown in FIG. It is connected to the long version, V+ bus bar 417. Although not shown, a plurality of capacitors may be coupled in parallel between the V+ bus bar 417 and the V− bus bar 407 .

[00156] As shown, to releasably connect packaged half bridges 250, 253, V+ bus bar 417, extensions 411 and heat sinks 419 together, a threaded bolt ) or other such fasteners may be used. In an alternative embodiment, sintering may also be used to rigidly connect packaged half bridges 250, 253, V+ bus bar 417, extensions 411 and heat sinks 419 together. However, it will be assumed that the components are releasably connected and, consequently, malfunctioning packaged half bridges can be more easily replaced. In one embodiment, each phase bar PB may include a C-shaped clamp including extensions 411-1 and 411-2. The half bridges 250, 253 and V+ bus bar 417 of each phase are releasably connected together by C-shaped clamps and fasteners. In this embodiment, the die substrates 230 directly contact the surfaces of the extensions 411 or the surfaces of the V+ bus bar 417 . The heat sinks 419 of FIG. 4db are elongated versions of the heat sinks 402 of FIG. 4aa. Threaded bolts or other such fasteners may be used to connect heat sinks 419 to extensions 411 . In this embodiment, the surfaces of the metal heat sinks 409 are in direct contact with the surfaces of the extensions 411 . In another embodiment, packaged half bridges 250 and 253, V+ bus bar 417, extensions 411 and heat sinks 419 may be soldered or sintered together.

[00157] Although the compact inverter system 408 is shown schematically, each phase's packaged half bridges 250 and 253, heat sinks 419, PB extensions 411 and V+ bus bar 417 are connected to each other. Side views are shown to illustrate the vertical and horizontal positioning of these components for the

[00158] Figure 4db shows the PWM and Reset signals received by phase-a of Figure 4da. Figure 4db also shows the Fault, Vi and Vt outputs from phase-a. Each packaged half bridge 250 or 253 of the phase is controlled by separate and separate sets of PWM and Reset signals. In an alternative embodiment, the high-side gate drivers of packaged half bridges 250-1 and 250-2 and the low-side gate drivers of packaged half bridges 253-1 and 253-2 are micro While can be controlled by a single high-side PWM-H signal from the controller, the low-side gate drivers of packaged half-bridges 250-1 and 250-2 and of packaged half-bridges 253 High-side gate drivers can be controlled by a single low-side PWM-L signal from the microcontroller. In another embodiment, the high-side gate drivers of packaged half bridges 250-1 and 250-2 can be controlled by the first high-side PWM-H signal, while the packaged half bridges ( The low-side gate drivers of 253-1 and 253-2) are controlled by a second high-side PWM-H; And while the low-side gate drivers of the packaged half bridges 250-1 and 250-2 can be controlled by the first low-side PWM-L signal, the packaged half bridges 253-1 and 253 The high-side gate drivers of -2) are controlled by the second low-side PWM-L signal.

[00159] 4E is a schematic diagram showing a top view of another compact inverter system 430 that includes packaged half bridges 250 and 253. The compact inverter system 430 includes three phases a-c each connected to phase bars PBa-PBc. Each phase includes a packaged half bridge 250 and a packaged half bridge 253 connected between a metal heat sink 403 (shown transparently) and a V+ bus bar 405. More specifically, the die substrate terminals 230H (not shown) and 230L of each phase are connected to a V+ bus bar 405 and a corresponding heat sink 403, respectively. The phase bar PB of each phase is connected to heat sink 403 and high-side die clip terminals 232H. Low side-die clip terminals 232L are connected to V- bus bar 413. The heat sinks 403a - 403c are electrically isolated from each other, and each has one or more channels (not shown) through which an electrically isolated cooling fluid can flow. The V+ bus bar 405 acts as a heat sink with one or more channels (not shown) through which an electrically isolated cooling fluid can flow.

[00160] FIG. 4F is a schematic diagram showing a side view of another compact inverter system 410 using the packaged half bridges 251 shown in FIG. 3HA. There are many similarities between inverter systems 400 and 410. However, some differences exist. Phases a-c each include three packaged half bridges 251a - 251c. Low-side die substrate terminals 230L and high-side die substrate terminals 230H are connected to V- bus bar 412 and V+ bus bar 404, respectively. The V-bus bar 412 also acts as a heat sink with one or more channels (not shown in FIG. 4F) through which cooling fluid can flow. Although not shown, a plurality of decoupling capacitors may be coupled in parallel between the V+ bus bar and the V- bus bar. Phase bars PBa - PBc are connected to the die clip terminals 232 of phases a - c, respectively, as shown. Although inverter system 410 is shown schematically, each phase's half bridge 251, V+ bus bar 404 and V- bus bar 412 are shown in side view to illustrate the vertical positioning of these components relative to each other. do.

[00161] 4F includes current symbols representing current flow through inverter system 410 at an instant in time. More specifically, FIG. 4F shows that the high-side switch 304H of phase-a is activated and conducts current, while the low-side switches 304L of phases b and c are activated and conducts current. Shows the current flow through the inverter system 410 when All other switches in the drawing are disabled. Importantly, the active switches are thermally coupled to V+ bus bar 404 or V- bus bar 412.

[00162] FIG. 4G is a schematic diagram showing a side view of another compact inverter system 412 using packaged half bridges 251 as shown in FIG. 3HA. Each of the phases a-c includes a corresponding phase bar PB connected to die clip terminals 232 . The die substrate terminals 230L1 and 230H2 of each phase are connected to metal V- bus bars 412-1 and 412-2, respectively. V-bus bars 412-1 and 412-2 may include channels through which cooling fluid may flow. The die substrate terminals 230H1 and 230L2 of each phase are connected to the V+ bus bar 415. Although not shown, a plurality of decoupling capacitors may be coupled in parallel between the V- bus bar 412-1 and the V+ bus bar 415, and a plurality of decoupling capacitors may be coupled to the V- bus bar 412-2 and may be coupled in parallel between the V+ bus bars 415. Although the compact inverter system 412 is schematic, the half bridges 251, heat sink/bus bars 412, and heat sink/bus bars 415 of each phase are shown to illustrate the vertical positioning of these components relative to each other. A side view is shown.

[00163] 4G includes current symbols representing the current flow through inverter system 412 at an instant in time. More specifically, FIG. 4G shows that switches 304H1 and 304L2 of phase-a are activated and conduct current, while switches 304L1 and 304H2 of phases b and c are activated and current to V-. Shows the current flow through the inverter system 412 when conducting . All other switches in the drawing are disabled. Importantly, the activated switches are thermally and electrically coupled to V+ bus bar 415, V- bus bar 412-1, or V- bus bar 412-2.

[00164] 4H is a schematic diagram showing a side view of another compact inverter system 414 . Each of the phases a-c includes four packaged switches 203 as shown in FIG. 3ca. Heat sinks 418-a through 418-c are connected to phase bars PBa-PBc, respectively, which in turn are connected to windings Wa-Wc, respectively. The heat sinks 418-a through 418-c are electrically isolated from each other and have one or more channels (not shown) through which the electrically isolated cooling fluid can flow. The die substrate terminals 230 of each phase are connected to a heat sink 418 . The die clip terminals 344 of the packaged switches 203-1 and 203-2 of each phase are connected to the V+ bus bar 404, and the packaged switches 203-3 and 203 of each phase The die clip terminals 344 of -4) are connected to the V- bus bar 412. Bus bars 404 and 412 each include one or more channels through which cooling fluid flows. Although not shown, a plurality of decoupling capacitors may be coupled in parallel between the V+ bus bar 404 and the V− bus bar 412 .

[00165] Although a compact inverter system 414 is shown schematically, each phase of the packaged switches 203, V+ bus bar 404, heat sinks 418 and V- bus bar 412 have these relative to each other. A side view is shown to illustrate the vertical positioning of the components.

[00166] 4H includes current symbols representing the current flow through the inverter system 414 at an instant in time. More specifically, FIG. 4H shows that switches 203-1 and 203-2 of phase-a are activated and conduct current from V+ bus bar 404, while switches of phases b and c ( Shows current flow through inverter system 414 when 203-3 and 203-4) are activated and conduct current to V- through V- bus bar 412.

[00167] FIG. 4I is a schematic diagram illustrating a side view of another compact inverter system 416 using the packaged switches 207 shown in FIG. 3ea and the packaged switches 209 shown in FIG. 3FA. Each of the phases a-c includes a pair of packaged switches 209 and a pair of packaged switches 207. The die clip terminals 344 of each phase are connected to a corresponding heat sink 418. The heat sinks 418-a through 418-c are electrically isolated from each other and have one or more channels (not shown) through which the electrically isolated cooling fluid can flow. Because the heat sinks 418 are electrically isolated, no current flows through the heat sinks 418 . In each phase, terminals 230 in packaged switches 209 are connected to V+ bus bar 404, and terminals 230 in packaged switches 207 are connected to V- bus bar 412. connected to The phase bars PBa-PBc are connected to die clip terminals 232 of phases a-c, respectively. Although compact inverter system 416 is shown schematically, heat sinks 418, packaged switches 207 and 209, V+ bus bar 404 and V- bus bar 412 are components of these components relative to each other. Side views are shown to illustrate vertical and horizontal positioning. Although not shown, a plurality of decoupling capacitors may be coupled in parallel between the V+ bus bar 404 and the V− bus bar 412 .

[00168] 4I includes current symbols representing current flow through inverter system 416 at an instant in time. More specifically, FIG. 4i shows that switches 304 of packaged switches 209 of phase-b are activated and conduct current, while switches of packaged switches 207 of phases a and c Shows current flow through inverter system 416 when s 304 is activated and conducts current to V- through V- bus bar 412.

[00169] The packed switches of each of the inverters of FIGS. 4aa, 4ab and 4ba to 4i are oriented with their front faces F facing the same direction line. In other words, the fronts F of the packaged switches are included in respective planes that are substantially parallel to each other. In alternative embodiments, the packaged switches of each of the inverters of FIGS. 4AA, 4AB and 4BA to 4I include their front faces F substantially in one plane, and their rear faces ( Bk) can be rotated 90 degrees so that it is substantially contained in another plane parallel to one plane in which the fronts are contained. When rotated 90 degrees, the packaged switches can be positioned closer together, which can reduce the total volume occupied by the inverter in which the packaged switches are included. Moreover, to connect the signal lead terminals on the front (F) of each packaged switch to the individual terminals of a control printed circuit board (PCB), shorter, simpler (e.g., A straight FFC as opposed to an FFC with angled bends), cheaper and/or more compact FFCs or other connection devices may be used, on which control printed circuit boards (PCBs), one or more microcontrollers s and one or more power management integrated circuits are mounted as described more fully below. FFCs or other connection devices can carry voltages and signals between the packaged switch and the control PCB. A shorter and more compact FFC or other connection device can reduce delay and other transmission problems for signals transmitted between the packaged switch and the microcontroller on the control PCB. The phase bars (PBa - PBc) may require reconfiguration to accommodate the 90 degree rotation of the packaged switches.

[00170] To illustrate, FIG. 4J is a schematic diagram showing a side view of compact inverter system 423 . Similarities exist between compact inverter system 423 and compact inverter system 400 shown in FIG. 4AA. However, at least one substantial difference exists; The packaged half bridges 250 are rotated 90 degrees such that the backs Bk and fronts F of the packaged half bridges 250 face outward from the respective sides of the inverter system 423. do. In other words, the rears Bk are substantially included in one plane, and the fronts F are substantially included in another plane parallel to the one plane in which the rears Bk are included. In this configuration, packaged half bridges 250 can be positioned closer to each other, which can reduce the total volume occupied by inverter 423 when compared to inverter 400 . Moreover, to connect the signal lead terminals on the front (F) of the individual packaged half bridges 250 to the individual terminals of the control PCB, a shorter, simpler, cheaper and/or more compact design is required. A FFC or other connection device may be used.

[00171] 4K is a schematic diagram showing a side view of another compact inverter system 425 . Similarities exist between compact inverter system 406 and compact inverter system 425 shown in FIG. 4BA. There is at least one substantial difference; The packaged half bridges 250 and 253 have rears Bk and fronts F of the packaged half bridges 250 and 253 facing outward from the respective sides of the inverter system 423. rotated 90 degrees to

[00172] 4L is a schematic diagram showing a side view of another compact inverter system 426 . Similarities exist between compact inverter system 410 and compact inverter system 426 shown in FIG. 4F. There are at least two substantial differences; The packaged half bridges 251 are replaced with the packaged half bridges 250, and the packaged half bridges 250 have rears Bk and fronts F of the packaged half bridges 250. It is rotated 90 degrees to face outward from the individual sides of this inverter system 426 .

[00173] 4ma is a schematic diagram showing a rear view of a packaged half bridge 250 connected between heat sinks 427 and 428, respectively. For illustrative purposes, heat sinks 427 and 428 are connected to the V+ and V- terminals of the battery as shown, consequently heat sinks 427 and 428 also connect to the V- and V+ busses. will be referred to as bars 427 and 428 . For ease of illustration, the switch controllers, T_Sense circuits, I_sense circuits and signal leads of the packaged half bridge 250 are not shown.

[00174] Die substrate terminals 230L and 230H are connected to V- and V+ bus bars 427 and 428, respectively. Each bus bar has one or more channels through which an electrically isolated cooling fluid can flow. FIG. 4mb is a side view of the system shown in FIG. 4ma. This figure shows example channels 40 of V- and V+ bus bars 427 and 428, respectively. To enhance heat transfer, the channels may each be positioned closer to the surface in contact with the die substrate terminals 230, as shown. The channels 40 are configured to hold pipes like any one of the pipes shown in FIGS. 4ac-4af but shorter in length. Each pipe has its own channel or channels through which cooling fluid can flow.

[00175] Although not shown in the schematic diagram, the die substrate terminals 230 are connected to V+ and V- bus bars, phase bars, or corresponding pedestals on the bus bars. The pedestals may have substantially planar surfaces. More specifically, each pedestal may have a flat surface connected to a die substrate terminal. The pedestal surface may be substantially similar in size and shape to the die substrate terminals to which the pedestal surface is connected. Heat and/or current is transferred between the die board terminal and the connected pedestal of the die board terminal. Although not required, a thin layer of thermally conductive and/or electrically conductive grease may connect the die substrate terminals to the pedestal surface to improve thermal and/or electrical conductivity therebetween. The pedestals may be configured to create an air gap between the signal leads of packaged half bridge 250 and bus bars 427 and 428 . Air gaps electrically isolate the signal leads from the bus bars.

[00176] Although the system shown in FIG. 4MB is shown schematically, half bridge 250, V- bus bar 427 and V+ bus bar 428 are shown in side view to illustrate the vertical positioning of these components relative to each other.

Exemplary Packaged Switch 200

Exemplary Signal Frame Substrates

[00177] Packaged switches include switch modules, which in turn include components such as switches, gate drivers, etc. connected between die clips and die substrates. An exemplary packaged switch 200 includes the switch module 300 shown in FIG. 3AA.

[00178] During assembly, switch module components, such as gate drivers, are attached (bonded, soldered, etc.) to the signal frame substrate. 5 is an isometric view of an embossed sheet 500 of thin (eg 0.1 mma.0 mm) metal (eg copper) from which an exemplary signal frame substrate may be formed. For illustrative purposes only, the embossed sheet 500 is formed from a copper sheet that is 0.25 mm thick. Embossed sheet 500 is created by pressing a flat metal sheet between a female metal die and a counter male metal die. Embossing creates non-isolated signal leads. 6 is an isometric inverse view of the embossed sheet 500 after the embossed sheet 500 has been cut. Figure 6 more clearly shows the non-isolated signal leads 204, 206, 604 and 608. Signal leads, such as signal leads 204, 206, 604 and 608 of FIG. 6, are non-isolated because they are connected through unembossed portion 610. The non-isolated signal leads are contained in a plane parallel to the plane containing the unembossed portion 610, also referred to as the “negative layer”. Ultimately, the negative layer 610 will be removed by the trimming process mentioned above, which electrically isolates the signal leads from each other.

[00179] To create the signal frame substrate 700 shown in FIG. 7, some non-isolated signal leads may be bent. The signal frame substrate 700 includes a framing with alignment apertures 701 . The apertures assist in aligning the signal frame substrates, die substrates, and die clips during construction of the switch module 300 shown in FIG. 3AA.

[00180] With continued reference to FIGS. 3AA and 3AD , FIG. 8 shows the signal frame substrate after leads 802 of gate driver circuit 306 are connected (e.g., solder bonded) to individual non-isolated signal leads. It is a plan view of 700. Signal frame substrate 700 can house additional components of switch module 300 (eg, resistors R1 and R2 and diodes 308 and 310 in FIG. 3AD). For ease of illustration, additional components are not shown in FIG. 8 .

Exemplary Die Substrates and Die Clips

[00181] As can be seen in FIGS. 3A and 3AC , the switch module 300 includes a switch 304 , which is sandwiched between a die substrate 312 and a die clip 316 . Die substrates and die clips may be formed from separate thin sheets of metal, such as copper, using a punch press machine or similar tool. 9A is an isometric view of an exemplary die substrate 312 formed of a thin sheet of copper (eg, 0.1 mm - 6.0 mm). Certain types of switches (MOSFET-based switches) heat up faster than other types of switches (eg, IGBT-based switches). The thickness of the die substrate may depend on the type of switch to accommodate differences in rates at which the switches are heated. In one embodiment, a 1.6 mm thick die substrate may be used for switches using SiC MOSFETs, while a 4.0 mm thick die substrate may be used for switches using IGBTs. The die substrate 312 is connected between frames including apertures 901 configured for alignment with individual signal frame substrate apertures 701 as will be described more fully below. Die substrate 312 has planar surfaces facing oppositely. The switch can be mounted on one surface, while the oppositely facing surface forms the die substrate terminal 230 .

[00182] FIG. 9B shows die substrate 312 with switches 304 (ie, IGBT and diode D in FIG. 3ae ) sintered to surface 902 . For explanation purposes only, it will be assumed that all switches are sintered to die substrates and die clips. The switch may be sintered to the die clip before or after the switch is sintered to the die substrate, or vice versa. For illustrative purposes, after the switches are sintered to the die substrates, the die clips and switches are sintered together.

[00183] Sintering is the process of forming a solid mass by application of heat and/or pressure without melting the sintered material to its liquefaction point. Before the switch is sintered to the die substrate or die clip, a thin layer of sintering material (eg silver) is applied to the surface of the die substrate or die clip. Alternatively, a thin layer of sintering material is applied to the surface of the switch before the switch is sintered to the die substrate or die clip. During the sintering process, atoms in the sintering material diffuse across the boundaries of the items to be sintered, fusing the items to be sintered together and creating one solid piece. The sintering temperature need not reach the melting point of the sintering material, nor does sintering need to reach the melting point of the items to be sintered together (eg, the die substrate and the collector terminal of the IGBT). And as a result, sintering, unlike soldering, does not create bubbles or other voids that can adversely affect thermal and electrical conductivities between items (eg, a switch and a die substrate). In other words, sintering may provide a better thermal and electrical connection between the switch and its die substrate and/or die clip. Although other methods of attaching switches to die substrates or die substrates may be used, sintering is preferred because it creates a mechanically stronger bond, especially when compared to solder bonding. A strong bond is particularly important when it is subjected to the stresses of extreme environments (eg, thermal and mechanical stress). For example, the bond may be subjected to severe mechanical stress caused by road vibrations of moving electric vehicles. Moreover, since the melting point of the sintered material is higher than the temperature used in soldering, brazing, epoxy bonding, sintering, or other processes used in the construction of a packaged switch or packaged half bridge, such processes are It will not interfere with the sintered connection between the die substrates or between the switch and the die clip.

[00184] Returning to FIG. 9B , diode D includes an anode terminal 904 . The opposite facing cathode terminal (not shown) is sintered to the die substrate surface 902 through a thin layer of sintering material. In the illustrated embodiment, IGBT 905 has one emitter, but has several emitter terminals 906. The IGBT also includes a gate terminal 912. The oppositely facing collector terminal(s) (not shown) are sintered to the die substrate surface 902 through a thin layer of sintering material. FIG. 9C shows an enlarged cross-sectional view of the die substrate surface 902 and IGBT 905 taken along line A-A in FIG. 9B. A thin layer of sinter material 920 is positioned between and incorporated into the collector terminal of IGBT 905 and die substrate surface 902. The anode terminal 904 and emitter terminals 906 shown in FIG. 9B are configured to be connected (eg sintered) to a die clip. Gate 912 is configured for connection to the non-isolated signal-lead of signal frame substrate 700, which in turn is coupled to the output of gate driver 306. The connection type may depend on the characteristics of gate 912 . For example, gates formed from aluminum or a composite with base aluminum (eg, Al/Cu(0.5%)/Si(1%)) may be rapidly oxidized. Oxidation can render the solder bond unusable. If gate 912 is formed of aluminum or a composite with base aluminum, the connection may require a wire bond, one end of which is connected to gate 912 . If gate 912 is formed of silver, copper or gold, or a combination of these metals, a solder bond connection to gate 912 may be used.

[00185] The die substrate 312 may be coupled to the signal frame substrate 700 . FIG. 10 is a plan view of the die substrate 312 aligned with the signal frame substrate 700 shown in FIG. 8 . With the apertures 901 aligned with the apertures 701 , the die substrate 312 may be connected to the signal frame substrate 700 . For example, sidewalls of die substrate 312 may be soldered to bent signal leads 604 . This connection creates an electrical path between diode 308 (see FIG. 3ae) and collector c of IGBT 905. Gate 912 can be connected to gate driver 306 through a signal lead. For example, wire bonds and/or other conductors (eg, flat flexible cables) may be added to connect the gate 912 to the signal leads of the signal frame substrate 700. The signal lead of ) is in turn also connected to the output lead of the gate driver 306.

[00186] 11A and 11B are isometric and inverse isometric views of an exemplary die clip 316 formed from thin (eg, 0.1 mm - 4.0 mm) copper sheet. A die clip 316 is connected between frames containing alignment apertures 1101 . The die clip 316 includes pedestals 1104 that may be formed using a punch press or similar tool. In one embodiment, the recesses 1102 left by the creation of the pedestals 1104 may be filled with a thermally and electrically conductive material. Die clip 316 includes a surface that forms die clip terminal 232 . Additional die clip 316 includes a narrowed portion 1108 positioned between recesses 1102 and terminal 232 . An I_Sense circuit may be positioned over the narrow 1108 to measure current flow to or from the switch 304 when the switch 304 is connected to the die clip 316 .

[00187] With continued reference to FIGS. 10 , 11A and 11B , the end surfaces of the pedestals 1104 may be sintered to the respective emitter terminals 906 and anode terminal 904 . The end surfaces of the pedestals 1104 should be planar in shape and size substantially similar to the surfaces of the emitter terminals 906 but slightly smaller than the surfaces of the emitter terminals 906 . This ensures that the pedestals 1104 do not contact and possibly damage the IGBT 905 outside the areas occupied by the emitter terminals 906 . The size and shape of the end surfaces of the pedestals 1104 also increases the potential for unwanted hot spots to be created due to concentrated current flow through the narrow point connection between the pedestal 1104 and the emitter terminal 906. reduces When sintered together, the pedestals create an air gap between the IGBT 905 and the die clip 316. When an alternating current flows through the die clip, the alternating current creates an electromagnetic field that can adversely affect the operation of IGBT 905. The air gap reduces electromagnetic adverse effects on the operation of IGBT 905.

[00188] 11C and 11D show top and bottom views of the die clip 316, die substrate 312 and signal frame substrate 700 aligned. More specifically, apertures 1101 are aligned with individual die substrate apertures 901 and signal frame substrate apertures 701 . While aligned, the end surfaces of the pedestals 1104 of the die clip 316 are aligned with the individual terminals of the switch (e.g., the emitter terminals 906 of the IGBT 905 and the anode terminal of the diode 904). (904)). 11E is a partial isometric view showing sintered emitter terminals 906 and anode 904 relative to the ends of pedestals 1104 . In addition, the die clip 316 may be connected to the signal frame substrate 700 . For example, side surfaces of die clip 312 may be soldered to signal lead 608 .

[00189] The T_Sense circuit and I_Sense circuit of FIG. 3AA can be added to the partially configured switch module 300 shown in FIG. 11C. The FFC can be used to connect the T_Sense circuit and the I_Sense circuit to the signal leads of the signal frame substrate. An FFC can also be used to connect the output of gate driver 306 to the gate of a switch via a signal lead. FIG. 11F shows a partially constructed switch module 300 having a packaged I_sense circuit 1112 and a packaged T_sense circuit 1114 mounted on an FFC 1116. One portion of FFC 1116 is positioned over gate 912 . The I_sense circuit 1112 is positioned on another portion of the FFC 1116, which in turn is positioned over the narrowed section 1108 of the die clip 312. 11G is an isometric view of the switch module 300 shown in FIG. 11F.

[00190] The FFC 1116 includes conductive traces extending between the first terminal and the second terminal. The first trace terminals may be soldered to bent signal leads of the signal frame substrate 700, respectively. The second trace terminals may be soldered to individual leads of the packaged I_Sense circuit 1112 and the packaged T_sense circuit 1114 . In addition to sending output analog signals Vi and Vt from I_Sense circuit 1112 and T_sense circuit 1114, respectively, FFC 1116 may provide supply and ground voltages to these components.

[00191] FFC 1116 includes at least one trace, the second terminal of which is soldered to gate 912 of IGBT 905. This FFC trace can transmit the gate control signal (Vg) between gate driver 306 and gate 912 . The illustrated embodiment assumes that gate 912 is compatible with solder bonding, and consequently gate 912 is soldered to one or more traces of FFC 1116. In an alternative embodiment, gate 912 is wire bonded to the trace terminal of FFC 1116, which extends to but does not cover gate 912. Other methods are contemplated for connecting gate 912 to a signal lead that is also connected to gate driver 306.

[00192] The switch module 300 shown in FIG. 11F may be placed in a mold. Liquid plastic (e.g., epoxy resin) was then poured into the mold. Once cured, the liquid plastic forms a plastic body. The switch module 300 and cured plastic body are removed from the mold and trimmed. 12A is an isometric view of the switch module 300 with the molded plastic body 1200 after removal from the mold. In an alternative embodiment, transfer molding may be used to create the plastic body. In either embodiment, the bent signal leads of the signal frame substrate 700 , including signal leads 204 and 206 , are exposed through the front of the molded plastic body 1200 . 12A also shows die clip terminals 232 exposed through the side of molded plastic body 1200 . 12B is an inverse isometric view showing the negative layer 610 of the signal frame substrate 700. The portion of molded plastic body 1200 and negative layer 610 may be trimmed using any one of many different trimming tools or techniques (eg, grinding). The die substrate terminal 230 is exposed and the signal leads are isolated by a trimming process. 2AA and 2AB show the packaged switch after a trimming process.

Exemplary Packaged Half Bridge 250

[00193] Switch modules such as those shown in FIG. 11F can be stacked to create an exemplary packaged half bridge 250 . 13A and 13B are side and isometric views of the two switch modules 300 shown in FIG. 11F. More specifically, FIGS. 13A and 13B show a high-side switch module 300H and a low-side switch module 300L. The switch module 300H is flipped over and positioned over the switch module 300L inside a mold (not shown). Frames with apertures 701 , 901 and 1101 are not shown in FIGS. 13A and 13B for ease of illustration. However, these apertures can be used to align oppositely facing switch modules 300H and 300L while they are positioned inside the mold. Liquid plastic may be poured into a mold and allowed to harden to form a plastic body. Reversely facing switch modules 300H and 300L and the cured plastic body are removed from the mold and trimmed. Portions of the plastic body, and negative layers 610L and 610H may be removed using any one of many different trimming tools or techniques. Die substrate terminals 230H and 230L are exposed, and signal leads are isolated by a trimming process. The die substrate terminals 230H and 230L may protrude from the upper and lower plastic surfaces depending on the amount of the plastic body to be trimmed. 2ba and 2bb show the packaged half bridge after the trimming process.

Exemplary compact inverter system 408

[00194] Compact inverter systems include vertically stacked components. For example, FIG. 4DA includes packaged half bridges 250 and 253 stacked one on top of the other, heat sinks 419, phase bar extensions 411 and V+ bus bar 417. A compact inverter system 408 is shown.

[00195] 14A and 14B are isometric and cross-sectional views, respectively, of an exemplary V+ bus bar 417 that may be formed from a metal such as copper. V+ bus bar 417 conducts current between the packaged half bridges and the battery. Although not shown, a metal cable may connect the V+ terminal of the battery to one or more terminal structures of the V+ bus bar 417 . A DC-DC converter may be connected between the battery and the V+ bus bar 417 to increase or decrease the DC voltage supplied to the bus bar 417 . The width (W) and height (H) shown in the cross-sectional view 14b may vary depending on the embodiment. In the illustrated embodiment, H = 16 mm and W = 29 mm.

[00196] Pedestals on opposite facing surfaces of V+ bus bar 417 receive packaged half bridges 250 and 253. 14A and 14B show example pedestals 1402 having substantially planar surfaces 1405 for engaging die substrate terminals 230 of packaged half bridges 250 and 253. Each pedestal 1402 can be positioned between opposing short stop walls 1403 that can engage the left and right sides of a packaged half bridge 250 or 253. Stop walls 1403 inhibit lateral movement of packaged half bridges 250 or 253 when they are received by pedestals 1402 . In the illustrated embodiment, pedestal surfaces 1405 fully extend between stop walls 1403 . In an alternative embodiment, the pedestals 1402 are arranged so that the pedestals can engage die substrate terminals flush with or recessed below the plastic case surfaces of the packaged half bridges. It may have planar surfaces shaped similar to 230 but smaller than die substrate terminals 230 . For purposes of describing the exemplary inverter system 408, it is assumed that the packaged half bridges 250 and 253 have die substrate terminals 230 protruding slightly from their plastic case surfaces. Furthermore, it is assumed that the die substrate terminals 230 are directly connected to the pedestal surfaces 1405; in other embodiments, the die substrate terminals 230 are made of a thermally and electrically conductive material, such as solder. or indirectly to the pedestal surfaces 1405 via grease. When the die substrate terminals 230 are received by the surfaces 1405 of the pedestals 1402, the signal leads of the packaged half bridges (eg see signal leads in FIG. 2BA) and the V+ bus bar Air gaps are created between (417).

[00197] Referring to FIG. 14B, V+ bus bar 417 includes channels that receive pipes 420a shown in FIG. 4AC. Other pipes may be used in alternative embodiments, including pipes 420bd20d shown in Figures 4ad-4af, respectively. As noted above, the outer cylindrical surface of each pipe 420a is coated with a thin layer 422 of a dielectric material such as aluminum oxide. Dielectric layer 422 electrically insulates the fluid in pipe 420a from V+ bus bar 417. Dielectric layer 422 conducts significant heat between the fluid and V+ bus bar 417.

[00198] Still referring to FIGS. 4DA and 14A , FIG. 15A is an isometric view of V+ bus bar 417 with packaged half bridges 250 and 253 . Although not shown in this figure, die substrates 230H and 230L of packaged half bridges 250 and 253 are, respectively, the surfaces of respective pedestals 1402 on opposite sides of V+ bus bar 417. (1405) in direct contact. 15B is a side view revealing small air gaps between the signal leads of packaged half bridges 250 and 253 (eg, see signal leads in FIG. 2BA) and V+ bus bar 417. Partial air gaps separate signal leads and V+ bus bar 417 on the lower and upper surfaces of packaged half bridges 250 and 253, respectively. The length (L) shown in the side view of FIG. 15B may vary depending on the embodiment. In the illustrated embodiment, L=200 mm.

[00199] With continued reference to FIG. 4Da, the phase bars PBa - PBc of inverter system 408 conduct current between the packaged half bridges of phases a-c and windings Wa - Wc, respectively. . Each phase bar is connected between the die substrate terminals 230L and 230H of the packaged half bridges 250 and 253, respectively, and the heat sinks 419-1 and 419-2, respectively. 411-1 and 411-2). In one embodiment, each phase bar (PB) may include a C-shaped clamp and a metal cable. The clamp includes metal extensions 411-1 and 411-2 and a terminal structure. One end of the cable is connected to the terminal structure, while the other end of the cable is connected to the wire winding.

[00200] 16A, 16B and 16C are isometric and cross-sectional views of an exemplary C-shaped clamp 1604. Extensions 411-1 and 411-2 extend from common base 1602 as shown in FIG. 16A. Each extension 411 includes a pair of pedestals 1606 having surfaces 1607 configured to engage corresponding die substrate terminals 230L and 230H of packaged half bridges 250 and 253, respectively. includes In an alternative embodiment, the pedestals 1606 can engage die substrate terminals such that the pedestal surfaces are flush with, or slightly recessed below, the plastic surfaces of the packaged half bridges. may have planar surfaces 1607 shaped similar to but smaller than the die substrate terminals. Between the signal leads of packaged half bridges 250 and 253 (see, e.g., signal leads in FIG. Air gaps are created when accommodated by s 1607 .

[00201] With continued reference to FIG. 16A , clamp 1604 also includes a metal terminal structure 1610 mechanically connected to base 1602 by fasteners 1611 (eg, threaded bolts). Fasteners 1611 secure the electrical connection between base 1602 and terminal structure 1610 . The terminal structure 1610 includes a channel 1612 configured to receive one end of the metal cable described above. Fasteners 1614 extend through apertures in terminal structure 1610 and are configured to press the cable against the wall of channel 1612 to ensure an electrical connection therebetween.

[00202] Referring to FIG. 16B , clamp 1604 includes terminals 1615 connected to and extending from base 1602 . The terminals have substantially planar end surfaces 1619 that can engage and establish an electrical connection between the die clip terminals 232H and 232L of packaged half bridges 250 and 253, respectively. Clamp 1604 conducts significant current through terminals 1615 between the cable to which clamp 1604 is attached and packaged half bridges 250 and 253.

[00203] Clamp 1604 includes fasteners (eg, threaded bolts) 1620 at the lateral ends of extensions 411 . These fasteners extend through the apertures of the extensions 411 and are configured to secure the clamp 1604 to a dielectric block (not shown). With the dielectric block positioned between the tightened fasteners 1620 and the ends of the extensions 411, the clamp clamp 1604 and die substrate terminals relative to the pedestal surfaces 1405 and 1607 of the V+ bus bar 417. Each of the fields 230 is pressurized.

[00204] 17A shows packaged half bridge 250-2, V+ bus bar 417 and packaged half bridge 253-2 positioned between extensions 411-1 and 411-2 of clamp 1604. show Although not shown in this figure, die substrate terminals 230L and 230H of packaged half bridge 250 are clamp 1604 and respective pedestal surfaces 1607 and 1405 of V+ bus bar 417, respectively. The die substrate terminals 230L and 230H of the packaged half bridge 253 are releasably connected to the V+ bus bar 417 and the respective pedestal surfaces 1405 and 1607 of the clamp 1604, respectively. is releasably connected to the surfaces of With fasteners 1620 engaging the aforementioned dielectric block (not shown), clamp 1604 holds the die substrate terminals and pedestal surfaces in tight contact with each other. FIG. 17B is a cross-sectional view of the assembly shown in FIG. 17A. Although not explicitly shown in this figure, end surfaces 1619 of terminals 1615 engage respective die clip terminals 232H and 232L of packaged half bridges 250 and 253.

[00205] 4Da shows heat sinks 419-1 and 419-2 respectively connected to extensions 411-1 and 411-2 of each phase. With continued reference to FIG. 4DA , FIGS. 18A-18C are isometric, side, and side views of the assembly shown in FIGS. 17A and 17B , respectively, with exemplary heat sinks 419-1 and 419-2 added thereto. show a cross section Heat sinks 419-1 and 419-2 are substantially similar in this embodiment. Each of these heat sinks has channels that receive pipes, such as pipes 420a. Heat sinks 419-1 and 419-2 are releasably connected to clamp 1604. More specifically, fasteners (eg, threaded bolts, not shown) extend through the apertures and secure heat sinks 419 - 1 and 419 - 2 to clamp 1604 . The surfaces of heat sinks 419-1 and 419-2 and clamp 1604 are held in tight connection by these fasteners. Connections are made from packaged half bridges 250-2 and 253-2, respectively, to heat sinks 419-1 and 419 via extensions 411-1 and 411-2 of clamp 1604, respectively. -2) to enable heat transfer. In another embodiment, solder, sinter or thermal grease is used between heat sinks 419-1 and 419-2 and clamp extensions 411-1 and 411-2, respectively.

[00206] 19A and 19B show isometric and side views of the structure of FIGS. 18A-18C with additional clamps 1604, heat sinks 419 and packaged half bridges 250 and 253. Heat sinks 419-1a to 419-1c and 419-2a to 419-2c are similar to each other. Similarly, clamps 1604a - 1604c are similar to each other and to those shown in FIGS. 16A - 16C . Pipes 420a received by heat sinks 419-1a to 419-1c move fluid through them. Pipes 420a received by heat sinks 419-1a to 419-1c move fluid through them. Heat sinks 419-1a to 419-1c are isolated from each other to maintain electrical isolation. Similarly, sinks 419-2a through 419-2c are isolated from each other to maintain electrical isolation. However, heat sinks 419-1a to 419-1c are thermally coupled together by fluid in common pipes 420a. Similarly, heat sinks 419-2a to 419-2c are thermally coupled together by fluid in common pipes 420a.

[00207] 4da shows the V-bus bar 407. The die clip terminals 232L of the packaged bridges 250 and the die clip terminals 232H of the packaged half bridges 253 are connected to the V- bus bar 407 . Still referring to FIG. 4DA , FIGS. 20A , 20B and 20C show isometric, top and cross-sectional views of an exemplary V-bus bar 407 formed of a metal such as copper. Fasteners (eg, threaded bolts) 1616 mechanically connect terminal structures 1630 to the ends of base 1618 . Fasteners maintain electrical connection between terminal structures 1630 and base 1618 . Terminal structures 1630 have channels 1617 configured to receive ends of metal cables (not shown). The other ends of these metal cables may be connected directly or indirectly to a V- battery terminal (not shown). Fasteners 1622 (e.g., threaded bolts) extend through apertures in terminal structure 1630, engage the wall of channel 1617 and secure the metal cable received against the wall of channel 1617. It is configured to press the end. Fasteners 1622 ensure electrical connection between the metal cable and the V-bus bar 407. Openings 1634 are configured to receive PCBs each having an X x Y array of decoupling capacitors mounted thereon. 20D is a side view of V- bus bar 407 with PCBs 1636 received in openings 1634. Each PCB 1636 includes a 3×13 array of capacitors 1638. In the depicted embodiment, ceramic capacitors are mounted on PCBs 1636. In other embodiments, thin film or electrolytic capacitors may be used. In still other embodiments, a combination of capacitor types may be used. Ceramic capacitors are smaller than thin film capacitors, and the use of ceramic capacitors can be advantageous in that the ceramic capacitors can reduce the overall volume occupied by the exemplary compact inverter system 408. Each decoupling capacitor 1638 can be included in a package with a pair of leads, one of which is connected to V- bus bar 407 while the other is connected to V+ bus bar 417 . Traces on PCBs 1636 enable connections to V- bus bar 407 and V+ bus bar 417. Ceramic capacitor 1638 may fail and create a short between the terminals of ceramic capacitor 1638, which in turn creates a short between V- bus bar 407 and V+ bus bar 417 . PCB 1636 with ceramic capacitors 1638 should include one or more fused or fusible links, each of which should provide a bridge between V- bus bar 407 and V+ bus bar 417 if the ceramic capacitor fails. It is positioned to stop current flow. It is understood that the arrays of decoupling capacitors 1638 can provide a collective decoupling capacitance of 78 μF or greater, and that less or more decoupling capacitance may be used in other compact inverter system embodiments.

[00208] Decoupling capacitors 1638 prevent voltage spikes, ripple currents at the current terminals of switches (e.g., IGBTs) 304 in packaged half bridges 250 and 253. Or reduce other unwanted AC voltage components. Conductors connected between terminals of a battery or other voltage source and switches have parasitic inductance, or conductors between switches and windings of an electric motor have parasitic inductance. Narrow and long conductors have more parasitic inductance than shorter and wider conductors. Parasitic inductance also increases as the current carried by the conductor increases. Parasitic inductance presents several hazards to the switches 304. For example, in the process of turning switches 304 off, voltage spikes will occur at the current terminals of the switches due to the rapid decrease in current. These voltage spikes are due to the release of energy stored in the parasitic inductance of the conductors between the switch and the battery. Switch 304 may experience voltage spikes outside its normal operating range. Thus, it may be necessary to use a switch with a higher voltage level, but a switch with a higher voltage level may be less efficient and more expensive. Positioning the PCBs 1636 in the openings 1634 places the decoupling capacitors 1638 close (eg, 1 cm or less) to the current terminals of the switches in the packaged half bridges 250 and 253. place This ensures that more of the current emitted by the parasitic induction of the conductive line is received and stored by the decoupling capacitors 1638, which in turn reduces the voltage spike at the terminal of the switch. As a result of the proximity of decoupling capacitors 1638 to switches 304, smaller and more efficient switches 304 can be used in packaged half bridges 250 and 253.

[00209] As shown in FIGS. 20B and 20C , V- bus bar 407 has terminals 1640 connected to and extending from base 1618 . Terminals 1640-L have planar end surfaces for engaging die clip terminals 232L of packaged half bridges 250, and die clip terminals 232H of packaged half bridges 253 It has terminals 1640-H for engaging with. The V- bus bar 407 and the V+ bus bar must be electrically isolated from each other. 21 is a cross-sectional view of the assembly shown in FIG. 19 with a V-bus bar 407 added to it. An air gap exists between the extensions 411 of the clamp 1604a and the V-bus bar 407 to ensure electrical isolation between them. Although not visible in this figure, the end surfaces of terminals 1640 are releasably connected to corresponding die clip terminals 232L and 232H, respectively.

[00210] A compact inverter system may include one or more control PCBs, or may be connected to one or more control PCBs. For example, components such as one or more packaged power management integrated circuits (PMICs), one or more microcontrollers, etc., may be mounted (eg, soldered) onto the control PCBs. PMICs include voltage regulators that provide stable supply voltages to packaged switches or components of packaged half-bridges (eg, gate drivers). A microcontroller provides control signals (eg, PWM signals) to one or more packaged switches or packaged half bridges. The microcontroller also receives signals (eg, fault signals) from one or more packaged switches or packaged half bridges. The control PCB can be connected to the packaged switches or packaged half-bridges of the compact inverter system via individual FFCs. FFCs carry voltages and signals between the control PCB and packaged switches or packaged half bridges.

[00211] The control PCB may have several interfaces, each configured for connection to a respective first interface of a corresponding FFC. The second interfaces of the FFCs are configured for connection to individual packaged switches or packaged half bridges. In one embodiment, the second interfaces of the FFCs are connected to terminals of signal leads of individual packaged half bridges or packaged switches. 21 shows an exemplary control PCB 1650 with PMICs 1652 mounted thereon. Although not shown in this figure, one or more microcontrollers for controlling the packaged half bridges 250 and 253 may be mounted on the PCB 1650.

[00212] A number of methods and apparatus are disclosed. For example, a first apparatus is disclosed that includes a first device, which in turn includes a first case; a first metal structure comprising a first surface and a second surface; A first transistor comprising a first terminal and a second terminal, wherein when the first transistor is activated, a current is transmitted between the first terminal and the second terminal, the first transistor having a first control terminal that controls the first transistor. wherein the first terminal is sintered to the first surface; and a first opening through the first casing exposing the second surface. The first device includes a second metal structure including a first surface and a second surface; a second transistor comprising a first terminal and a second terminal, wherein a current is transmitted between the first terminal and the second terminal when the second transistor is activated, and the second transistor is a second control terminal for controlling the second transistor wherein the first terminal of the second transistor is sintered to the first surface of the second metal component; and a second opening penetrating the first case to expose a second surface of the second metal structure. The first device further includes a first metal element comprising a first surface and a second surface, the second terminal of the first transistor being sintered to the first surface of the first metal element; a second metal element comprising a first surface and a second surface, the second terminal of the second transistor being sintered to the first surface of the second metal element; a third opening penetrating the first case to expose a second surface of the first metal element; and a fourth opening penetrating the first case to expose the second surface of the second metal element. The first apparatus may further include a second device, which in turn may include a second case; a third metal structure comprising opposing first and second surfaces; a third transistor including a first terminal and a second terminal - when the third transistor is activated, current is transmitted between the first terminal and the second terminal, and the third transistor provides a third control terminal for controlling the third transistor. wherein the first terminals of the third transistors are sintered to the first surface of the third metal structure; a first opening through the second case exposing a second surface of the third metal structure; a fourth metal structure comprising opposing first and second surfaces; a fourth transistor including a first terminal and a second terminal, wherein a current is transmitted between the first terminal and the second terminal when the fourth transistor is activated, and the fourth transistor is a fourth control terminal for controlling the fourth transistor; wherein the first terminal of the fourth transistor is sintered to the first surface of the fourth metal structure; a second opening penetrating the second case to expose a second surface of the fourth metal structure; and a first bus bar directly connected to the second surface of the first metal structure and directly connected to the second surface of the third metal structure, wherein the first bus bar includes a channel through which a fluid can flow. The second device may also include a third metal element including a first surface and a second surface, the second terminal of the third transistor being connected to the first surface of the third metal element; a fourth metal element including a first surface and a second surface, the second terminal of the fourth transistor being connected to the first surface of the fourth metal element; a third opening penetrating the second case to expose a second surface of the third metal element; and a fourth opening penetrating the second case to expose the second surface of the fourth metal element.

[00213] A second apparatus is disclosed that includes a first device, which in turn includes a first device, the first device comprising: a first case; a first metal structure comprising a first surface and a second surface; A first transistor comprising a first terminal and a second terminal, wherein when the first transistor is activated, a current is transmitted between the first terminal and the second terminal, the first transistor having a first control terminal that controls the first transistor. wherein the first terminal is sintered to the first surface; a first opening through the first case exposing a second surface; a second metal structure comprising a first surface and a second surface; a second transistor comprising a first terminal and a second terminal, wherein a current is transmitted between the first terminal and the second terminal when the second transistor is activated, and the second transistor is a second control terminal for controlling the second transistor wherein the first terminal of the second transistor is sintered to the first surface of the second metal component; and a second opening penetrating the first case to expose a second surface of the second metal structure. The second device includes: a first bus bar connected to a second surface of the first metal structure, the first bus bar including channels through which fluid may flow; a heat sink coupled to the second surface of the second metal structure, the heat sink including channels through which fluid may flow; a first dielectric layer that electrically insulates the first bus bar from fluid flowing through the channel of the first bus bar; and a second dielectric layer electrically insulating the metallic heat sink from fluid flowing through a channel of the metallic heat sink. The second device may further include another bus bar electrically connected to the heat sink.

[00214] A third apparatus is disclosed that includes a first device, which in turn includes a first device, the first device comprising: a first case; a first metal structure comprising a first surface and a second surface; A first transistor comprising a first terminal and a second terminal, wherein when the first transistor is activated, a current is transmitted between the first terminal and the second terminal, the first transistor having a first control terminal that controls the first transistor. wherein the first terminal is sintered to the first surface; a first opening through the first case exposing a second surface; a second metal structure comprising a first surface and a second surface; a second transistor comprising a first terminal and a second terminal, wherein a current is transmitted between the first terminal and the second terminal when the second transistor is activated, and the second transistor is a second control terminal for controlling the second transistor wherein the first terminal of the second transistor is sintered to the first surface of the second metal component; a second opening penetrating the first case to expose a second surface of the second metal structure; a first circuit for controlling the first transistor; and a second circuit for controlling the second transistor.

[00215] A fourth apparatus is disclosed that includes a first device, which in turn includes a first device, the first device comprising: a first case; a first metal structure comprising a first surface and a second surface; A first transistor comprising a first terminal and a second terminal, wherein when the first transistor is activated, a current is transmitted between the first terminal and the second terminal, the first transistor having a first control terminal that controls the first transistor. wherein the first terminal is sintered to the first surface; a first opening through the first case exposing a second surface; a first metal element comprising a first surface and a second surface, the second terminal being sintered to the first surface of the first metal element; and a second opening penetrating the first case to expose a second surface of the first metal element.

[00216] A fifth apparatus is disclosed that includes a first device, which in turn includes a first device, the first device comprising: a first case; a first metal structure comprising a first surface and a second surface; A first transistor comprising a first terminal and a second terminal, wherein when the first transistor is activated, a current is transmitted between the first terminal and the second terminal, the first transistor having a first control terminal that controls the first transistor. wherein the first terminal is sintered to the first surface; a first opening through the first case exposing a second surface; The fifth device further includes a first bus bar thermally and electrically connected to the second surface of the first metal structure, the first bus bar including a channel through which a fluid can flow. The fifth device may further include a dielectric layer electrically insulating the fluid from the first bus bar.

[00217] A sixth apparatus is disclosed that includes a first device, which in turn includes a first device, the first device comprising: a first case; a first metal structure comprising a first surface and a second surface; A first transistor comprising a first terminal and a second terminal, wherein when the first transistor is activated, a current is transmitted between the first terminal and the second terminal, the first transistor having a first control terminal that controls the first transistor. wherein the first terminal is sintered to the first surface; a first opening through the first case exposing a second surface; and a first circuit for controlling the first transistor.

[00218] Although the invention has been described in connection with several embodiments, it is not intended that the invention be limited to the specific forms presented herein. On the contrary, it is intended to cover such alternatives, modifications and equivalents as may reasonably be included within the scope of the invention as defined by the appended claims.

Claims (20)

As a power inverter,
a bus bar, the bus bar comprising terminals for connection to the positive terminal of the DC voltage supply;
a first heat sink;
a first transistor comprising a first terminal and a second terminal, wherein a current is transmitted between the first terminal and the second terminal when the first transistor is activated, the first transistor controlling the first transistor a first gate terminal, wherein a first terminal of the first transistor is thermally and electrically connected to the bus bar;
a second transistor comprising a first terminal and a second terminal, wherein a current is transmitted between the first terminal and the second terminal when the second transistor is activated, the second transistor controlling the second transistor a second gate terminal, wherein the first terminal of the second transistor is thermally and electrically connected to the first heat sink;
Including,
the first transistor and the second transistor are positioned between the bus bar and the first heat sink;
the first transistor is positioned between the second transistor and the bus bar; and
the second transistor is positioned between the first transistor and the first heat sink;
power inverter. According to claim 1,
a second heat sink;
a third transistor comprising a first terminal and a second terminal, wherein a current is transmitted between the first terminal and the second terminal when the third transistor is activated, the third transistor controlling the third transistor a third gate terminal, wherein a first terminal of the third transistor is thermally and electrically connected to the bus bar;
a fourth transistor comprising a first terminal and a second terminal, wherein a current is transmitted between the first terminal and the second terminal when the fourth transistor is activated, the fourth transistor controlling the fourth transistor a fourth gate terminal, wherein a first terminal of the fourth transistor is thermally and electrically coupled to the second heat sink;
Including more,
the third transistor and the fourth transistor are positioned between the bus bar and the second heat sink;
the third transistor is positioned between the fourth transistor and the bus bar; and
the fourth transistor is positioned between the third transistor and the second heat sink;
power inverter. According to claim 2,
the first terminal of the first transistor is positioned between the bus bar and the second terminal of the first transistor;
the first terminal of the second transistor is positioned between the first heat sink and the second terminal of the second transistor;
the second terminal of the first transistor is positioned between the second terminal of the second transistor and the first terminal of the first transistor;
the second terminal of the second transistor is positioned between the second terminal of the first transistor and the first terminal of the second transistor;
the first terminal of the third transistor is positioned between the bus bar and the second terminal of the third transistor;
the first terminal of the fourth transistor is positioned between the second heat sink and the second terminal of the fourth transistor;
the second terminal of the third transistor is positioned between the second terminal of the fourth transistor and the first terminal of the third transistor;
The second terminal of the fourth transistor is positioned between the second terminal of the third transistor and the first terminal of the fourth transistor.
power inverter. According to claim 1,
a second bus bar connected to the second terminal of the first transistor and the first terminal of the second transistor;
A third bus bar comprising a terminal for connection to the negative terminal of the DC supply voltage
Including more,
The third bus bar is connected to the second terminal of the second transistor,
power inverter. As a power inverter,
a bus bar, the bus bar comprising a cylindrical channel through which fluid may flow;
a dielectric that electrically insulates the fluid from the bus bar;
a first transistor comprising a first terminal and a second terminal, wherein a current is transmitted between the first terminal and the second terminal when the first transistor is activated, the first transistor controlling the first transistor including a first gate terminal -
Including,
wherein the first terminal is thermally and electrically connected to the bus bar;
power inverter. According to claim 5,
a conduit positioned in the cylindrical channel and configured to convey the fluid between ends of the cylindrical channel;
wherein the dielectric is positioned between the outer surface of the conduit and the bus bar;
power inverter. According to claim 6,
wherein the cylindrical channel comprises a wall and the dielectric is in contact with the wall;
power inverter. According to claim 5,
a first heat sink including a first channel through which the fluid can flow;
A second transistor comprising a first terminal and a second terminal, wherein a current is transmitted between the first terminal and the second terminal when the second transistor is activated, the second transistor controlling the second transistor with a second gate terminal -
Including more,
a first terminal of the second transistor is thermally and electrically connected to the first heat sink;
power inverter. According to claim 8,
The first transistor and the second transistor are positioned between the bus bar and the first heat sink.
power inverter. According to claim 9,
wherein the first transistor is positioned between the second transistor and the bus bar, and the second transistor is positioned between the first transistor and the first heat sink.
power inverter. According to claim 9,
a third transistor comprising a first terminal and a second terminal, wherein a current is transmitted between the first terminal and the second terminal when the third transistor is activated, the third transistor controlling the third transistor including a third gate terminal;
a fourth transistor comprising a first terminal and a second terminal, wherein a current is transmitted between the first terminal and the second terminal when the fourth transistor is activated, the fourth transistor controlling the fourth transistor including a fourth gate terminal;
A second heat sink comprising a second channel through which the fluid can flow
Including more,
a first terminal of the third transistor is thermally and electrically coupled to the bus bar;
a first terminal of the fourth transistor is thermally and electrically connected to the second heat sink;
power inverter. According to claim 11,
wherein the first transistor, the second transistor, the third transistor, the fourth transistor and the bus bar are positioned between the first heat sink and the second heat sink.
power inverter. According to claim 9,
the first transistor is positioned between the second transistor and the bus bar, and the second transistor is positioned between the first transistor and the first heat sink;
wherein the third transistor is positioned between the fourth transistor and the bus bar, and the fourth transistor is positioned between the third transistor and the second heat sink.
power inverter. As a power inverter,
a bus bar, wherein the bus bar includes a channel;
a first transistor comprising a first terminal and a second terminal, wherein a current is transmitted between the first terminal and the second terminal when the first transistor is activated, the first transistor controlling the first transistor a first gate terminal, the first terminal being thermally and electrically connected to the bus bar;
A conduit positioned in the channel and configured to convey fluid between ends of the channel.
including,
power inverter. According to claim 14,
a first heat sink including a first channel through which the fluid can flow;
a second transistor comprising a first terminal and a second terminal, wherein a current is transmitted between the first terminal and the second terminal when the second transistor is activated, the second transistor controlling the second transistor a second gate terminal, wherein the first terminal of the second transistor is thermally and electrically connected to the first heat sink;
Including more,
power inverter. According to claim 15,
the first transistor and the second transistor are positioned between the bus bar and the first heat sink;
the first transistor is positioned between the second transistor and the bus bar; and
the second transistor is positioned between the first transistor and the first heat sink;
power inverter. According to claim 15,
a third transistor comprising a first terminal and a second terminal, wherein a current is transmitted between the first terminal and the second terminal when the third transistor is activated, the third transistor controlling the third transistor including a third gate terminal;
a fourth transistor comprising a first terminal and a second terminal, wherein a current is transmitted between the first terminal and the second terminal when the fourth transistor is activated, the fourth transistor controlling the fourth transistor including a fourth gate terminal;
A second heat sink comprising a second channel through which the fluid can flow
Including more,
a first terminal of the third transistor is thermally and electrically coupled to the bus bar;
a first terminal of the fourth transistor is thermally and electrically connected to the second heat sink;
power inverter. According to claim 17,
wherein the first transistor, the second transistor, the third transistor, the fourth transistor and the bus bar are positioned between the first heat sink and the second heat sink.
power inverter. According to claim 18,
the first transistor is positioned between the second transistor and the bus bar, and the second transistor is positioned between the first transistor and the first heat sink;
wherein the third transistor is positioned between the fourth transistor and the bus bar, and the fourth transistor is positioned between the third transistor and the second heat sink.
power inverter. According to claim 16,
a second bus bar connected to the second terminal of the first transistor;
A third bus bar connected to the second terminal of the second transistor
Including more,
power inverter.

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