KR20230025244A - Integrated circuit including standard cell and method for designing the same - Google Patents

Abstract

An integrated circuit according to an exemplary embodiment of the present disclosure includes: a plurality of standard cells including first and second standard cells disposed adjacent to each other in a first direction; and first to third metal layers sequentially stacked in a vertical direction. Within an area where at least one standard cell of the first standard cell and the second standard cell is disposed, power is provided to the plurality of standard cells, and at least one power segment formed as a pattern of the third metal layer extended in a second direction is disposed.

Description

Integrated circuit containing standard cell and method for designing same {INTEGRATED CIRCUIT INCLUDING STANDARD CELL AND METHOD FOR DESIGNING THE SAME}

The technical idea of the present disclosure relates to an integrated circuit, and more particularly, to an integrated circuit including a standard cell, and a method for designing the same.

An integrated circuit can be designed based on standard cells. As a semiconductor manufacturing process is miniaturized, the size of patterns in a standard cell may be reduced, and the size of the standard cell may also be reduced. Accordingly, the size or arrangement of patterns in a standard cell that affects metal resource utilization efficiency, size of a standard cell, and the like is becoming important.

The technical problem to be solved by the technical idea of the present disclosure is to provide an integrated circuit including a standard cell capable of efficiently using metal resources by including a power segment and a method for designing the same.

The technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the description below.

An integrated circuit including a plurality of standard cells according to an exemplary embodiment of the present disclosure includes a plurality of standard cells including first and second standard cells disposed adjacent to each other in a first direction, and sequentially stacked in a vertical direction. and providing power to the plurality of standard cells within a region where at least one of the first standard cell and the second standard cell is disposed, and providing power to the plurality of standard cells in a second direction. At least one power segment formed as a pattern of the third metal layer extending to may be disposed.

A method of designing an integrated circuit according to an exemplary embodiment of the present disclosure includes disposing a plurality of standard cells, disposing a plurality of power lines that are patterns for transmitting power to the plurality of standard cells on a plurality of tracks. and replacing some of the plurality of power lines with signal segments transmitting signals to the plurality of standard cells.

An integrated circuit including a plurality of cells according to an exemplary embodiment of the present disclosure includes a plurality of standard cells and a plurality of tracks formed with a plurality of patterns extending in a first direction and spaced apart from each other in a second direction. And, a first track of the plurality of tracks is configured to transmit power and is configured to transmit a signal and a power segment, which is a pattern formed on a part of the first track, and is formed on a part of the first track. It may be characterized by including a signal segment that is a pattern formed.

According to an integrated circuit including a standard cell and a method for designing the integrated circuit according to an exemplary embodiment of the present disclosure, an area of a standard cell may be reduced.

In addition, according to the integrated circuit including a standard cell and a method for designing the integrated circuit according to an exemplary embodiment of the present disclosure, metal resources included in the standard cell can be efficiently used.

Also, according to an integrated circuit including a standard cell and a method for designing the integrated circuit according to an exemplary embodiment of the present disclosure, IR drop characteristics and ElectroMigration (EM) characteristics may be improved.

Effects obtainable in the exemplary embodiments of the present disclosure are not limited to the effects mentioned above, and other effects not mentioned are common knowledge in the art to which exemplary embodiments of the present disclosure belong from the following description. can be clearly derived and understood by those who have That is, unintended effects according to the implementation of the exemplary embodiments of the present disclosure may also be derived by those skilled in the art from the exemplary embodiments of the present disclosure.

1A to 1D are diagrams for explaining an integrated circuit according to an exemplary embodiment of the present disclosure.
2 is a diagram for explaining a layout of an integrated circuit according to an exemplary embodiment of the present disclosure.
3 is a diagram for explaining a layout of an integrated circuit according to an exemplary embodiment of the present disclosure.
4A to 4C are views for explaining the layout of an integrated circuit according to an exemplary embodiment of the present disclosure.
5A and 5B are views for explaining the layout of an integrated circuit according to an exemplary embodiment of the present disclosure.
6A and 6B are views for explaining the layout of an integrated circuit according to an exemplary embodiment of the present disclosure.
7A and 7B are diagrams for explaining a layout of an integrated circuit according to an exemplary embodiment of the present disclosure.
8A to 8D are diagrams for explaining the layout of an integrated circuit according to an exemplary embodiment of the present disclosure.
9A and 9B are views for explaining the layout of an integrated circuit according to an exemplary embodiment of the present disclosure.
10 is a flowchart illustrating a method for designing an integrated circuit according to an exemplary embodiment of the present disclosure.
11A and 11B are diagrams for explaining the layout of an integrated circuit according to an exemplary embodiment of the present disclosure.
12A to 12C are views for explaining the layout of an integrated circuit according to an exemplary embodiment of the present disclosure.
13 is a flow chart illustrating a method for fabricating an integrated circuit according to an exemplary embodiment of the present disclosure.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

1A to 1D are diagrams for explaining an integrated circuit according to an exemplary embodiment of the present disclosure.

FIG. 1A is a plan view showing a part of the integrated circuit 10 constituting one chip or one functional block on a plane consisting of an X axis and a Y axis. In this specification, the X-axis direction and the Y-axis direction may be referred to as a first horizontal direction and a second horizontal direction, respectively, and the Z-axis direction may be referred to as a vertical direction. The plane made up of the X and Y axes can be referred to as the horizontal plane, and components arranged in the +Z-axis direction relative to other components can be referred to as being above other components, and relative to other components - Components disposed in the Z-direction may be referred to as being below other components.

Referring to FIG. 1A , the integrated circuit 10 may include a plurality of standard cells. A standard cell is a layout unit included in an integrated circuit, and may be designed to perform a predefined function, and may also be referred to as a cell. The integrated circuit 10 may include a number of various standard cells, and the standard cells may be arranged and arranged according to a plurality of rows.

Multiple standard cells are used repeatedly in integrated circuit design. Standard cells may be pre-designed according to a manufacturing technology and stored in a standard cell library, and integrated circuits may be designed by arranging and interconnecting standard cells stored in the standard cell library according to design rules.

For example, standard cells are used in central processing unit (CPU), graphics processing unit (GPU), and system-on-chip (SOC) designs, such as inverters, AND gates, NAND gates, OR gates, XOR gates, and NOR gates. It may contain various basic circuits often used in digital circuit design for electronic devices. Or, for example, standard cells may include other circuits often used in circuit blocks, such as flip-flops and latches.

Standard cells may include filler cells. A pillar cell may be placed adjacent to a functional cell to provide routing of signals provided to or output from the functional cell. Also, the filler cell may be a cell used to fill a space remaining after functional cells are disposed.

Standard cells may include an active region and a gate line. An active region and a gate line included in a standard cell may form a transistor. In an exemplary embodiment, the gate line may include a work function metal-containing layer and a gap-fill metal layer. For example, the work function metal-containing layer may include at least one of Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, and Pd, and gap fill The metal layer may be formed of a W layer or an Al layer. In an exemplary embodiment, the gate line may include a TiAlC/TiN/W stacked structure, a TiN/TaN/TiAlC/TiN/W stacked structure, or a TiN/TaN/TiN/TiAlC/TiN/W stacked structure. there is.

The integrated circuit 10 may include metal layers on which wires for interconnecting standard cells are formed. For example, a second metal layer M2 may be formed on the first metal layer M1. In an exemplary embodiment, the first metal layer M1 may include patterns extending in the X-axis direction, and the second metal layer M2 may include patterns extending in the Y-axis direction (uni- direction). In addition, a third metal layer may be further formed on the second metal layer M2.

The patterns formed on each of the metal layers may be made of metal, conductive metal nitride, metal silicide, or a combination thereof. In the drawings of this specification, only some layers may be shown for convenience of illustration, and vias may be displayed even though they are located under the pattern of the metal layer to indicate the connection between the pattern of the metal layer and the lower pattern. there is.

A first power line PL1 and a second power line PL2 supplying a voltage to each standard cell may be formed at the boundary of each of the plurality of rows. The first power line PL1 may provide a first supply voltage (eg, power supply voltage VDD) to each standard cell, and the second power line PL2 may provide a second supply voltage (eg, power supply voltage VDD) to each standard cell. For example, a ground voltage VSS) may be provided. The first power line PL1 and the second power line PL2 may be formed as conductive patterns extending in the X-axis direction and may be alternately disposed in the Y-axis direction.

FIG. 1B is a cross-sectional view taken along the line X1-X1' of FIG. 1A, and FIGS. 1C and 1D are cross-sectional views taken along the line Y1-Y1' of FIG. 1A. Although not shown in FIGS. 1B, 1C, and 1D , gate spacers may be formed on side surfaces of gate lines, and barrier films may be formed on surfaces of contacts and/or vias.

FIG. 1C illustrates an example in which a plurality of fins are formed in the active region, and FIG. 1D illustrates an example in which nanosheets are formed in the active region. However, the standard cell included in the integrated circuit according to the present disclosure is not limited to those shown in FIGS. 1C and 1D. For example, a gate-all-around (GAA) FET in which nanowires formed on the active region are surrounded by gate lines may be formed in the standard cell, and a plurality of nanowires are vertically stacked on the active region. A vertical GAA FET may be formed in which nanowires of are surrounded by a gate line. For example, a multi bridge channel (MBC) FET may be formed in a standard cell in which a plurality of nanosheets are stacked on an active region and a gate line surrounds the plurality of nanosheets. Also, for example, a negative capacitance (NC) FET may be formed in the active region. In addition to the above transistor examples, various transistors (CFET (complementary FET), NCFET (negative FET), CNT (carbon nanotube) FET, bipolar junction transistor, and other three-dimensional transistors) are formed on the gate line and active region It can be.

Referring to FIGS. 1B and 1C, the substrate 10' is a semiconductor such as silicon (Si) or germanium (Ge), or GaAs, AlGaAs, InAs, InGaAs, InSb, GaSb, InGaSb, InP, GaP, InGaP, Group III-V compounds such as InN, GaN, InGaN, and the like may be included. In an exemplary embodiment, the substrate 10' may be a Silicon-On-Insulator (SOI) substrate or a Germanium-On-Insulator (GOI) substrate. In an exemplary embodiment, the substrate 10' may be doped with a P-type impurity.

A first active region RX1 and a second active region RX2 may be formed on the substrate 10 ′. In an exemplary embodiment, the second active region RX2 may be formed on the substrate 10 (P-SUB) doped with P-type impurities, and the first active region RX1 may be formed on the substrate 10'. It may be formed in a well (N-well). The first active region RX1 may form a gate line GL2 and a P-type transistor, and the second active region RX2 may form a gate line GL2 and an N-type transistor.

An isolation trench DT may be formed between the first active region RX1 and the second active region RX2 . An isolation layer DTI may be formed by filling the isolation trench DT with an insulating material (eg, oxide). The first active region RX1 and the second active region RX2 may be separated from each other by the device isolation layer DTI. An isolation trench DT may be formed under the first power line PL1 and the second power line PL2 , and a device isolation layer DTI may be formed.

The plurality of first fins F1 and the plurality of second fins F2 may extend parallel to each other along the X-axis direction. An element insulating layer IL (eg, oxide) may be formed between each of the plurality of first fins F1 and the plurality of second fins F2 . In the first active region RX1 and the second active region RX2, the plurality of first fins F1 and the plurality of second fins F2 may protrude on the device insulating layer IL in a fin shape. . Although it is illustrated in FIG. 1C that three first fins F1 and three second fins F2 are formed, it is not limited thereto, and is formed in the first active region RX1 and the second active region RX2. The number of pins can vary widely.

The gate insulating layer GI and the gate line GL2 may be formed to extend in the Y-axis direction. The gate insulating film GI and the gate line GL2 are formed on the top surface and both sidewalls of each of the plurality of first fins F1 and the plurality of second fins F2, the top surface of the device insulating film IL, and the separation insulating layer ( DTI) can be covered.

First to sixth interlayer insulating films 11 to 16 may be formed on the plurality of first fins F1 and the plurality of second fins F2 . Active contacts and active vias may be formed through the first interlayer insulating layer 11 to connect the source/drain regions and the pattern of the first metal layer M1 .

The gate contact CB may pass through the second interlayer insulating layer 12 and be connected to the gate line GL2 , and the gate via V02 may pass through the third interlayer insulating layer 13 to connect the gate contact CB to the first interlayer insulating layer 13 . A routing wire (RT12) can be connected. The first routing wire RT12 may be formed as a pattern of the first metal layer M1, and the gate via V02 is a first via V0 electrically connected under the first metal layer M1. can be formed Accordingly, the first routing line RT12 may be electrically connected to the gate line GL2 through the gate via V02 and the gate contact CB.

The second via V12 connecting the first routing wire RT12 and the second routing wire RT2 may be formed as a second via V1 penetrating the fifth interlayer insulating layer 15 . The second routing wire RT2 may be formed as a pattern of the second metal layer M2, which is an upper layer of the first metal layer M1.

Referring to FIG. 1D , in an exemplary embodiment, a nanosheet as an active region may be formed on each of the first active region RX1 and the second active region RX2 . A first nanosheet stack NS1 may be formed on the first active region RX1 , and a second nanosheet stack NS2 may be formed on the second active region RX2 . Each of the first nanosheet stack NS1 and the second nanosheet stack NS2 may extend in the X-axis direction.

The first nanosheet stack NS1 and the second nanosheet stack NS2 may function as a channel of a transistor. For example, the first nanosheet stack NS1 may be doped with N-type impurities and form a P-type transistor. On the other hand, the second nanosheet stack NS2 may be doped with P-type impurities and form an N-type transistor. In an exemplary embodiment, the first nanosheet stack NS1 and the second nanosheet stack NS2 may be made of Si, Ge, or SiGe. In an exemplary embodiment, the first nanosheet stack NS1 and the second nanosheet stack NS2 may be made of InGaAs, InAs, GaSb, InSb, or a combination thereof.

Each of the first nanosheet stack NS1 and the second nanosheet stack NS2 includes a plurality of nanoparticles overlapping each other in a mutually perpendicular direction (Z-axis direction) on the upper surfaces of the first fins F1 and the second fins F2. Sheets NS11 to NS13 and NS21 to NS23 may be included. In this example, each of the first nanosheet stack NS1 and the second nanosheet stack NS2 is composed of three nanosheets, but the technical concept of the present invention is not limited to the examples. For example, each of the first nanosheet stack NS1 and the second nanosheet stack NS2 may include at least two nanosheets, and the number of nanosheets is not particularly limited.

The gate line GL2 covers the first nanosheet stack NS1 and the second nanosheet stack NS2 on the first fin F1 and the second fin F2 and covers the plurality of nanosheets NS11 to NS13, NS21 ~ NS23) can surround each. The plurality of nanosheets NS11 to NS13 and NS21 to NS23 may have a gate-all-around (GAA) structure surrounded by the gate line GL2. A gate insulating layer GI may be interposed between the first nanosheet stack NS1 and the second nanosheet stack NS2 and the gate line GL2.

2 is a diagram for explaining the layout of an integrated circuit according to an exemplary embodiment of the present disclosure.

Referring to FIG. 2 , an integrated circuit according to an exemplary embodiment of the present disclosure may include a plurality of standard cells. For example, the integrated circuit 20 may include a first standard cell 201 and a second standard cell 202 . The cell height of the first standard cell 201 and the cell height of the second standard cell 2020 may be different from each other.

Also, the integrated circuit 20 may include a plurality of metal layers, and FIG. 2 illustrates a second metal layer M2 and a third metal layer M3, which are some of them.

The integrated circuit 20 may include a plurality of tracks for each of a plurality of metal layers, and may include patterns extending in a predetermined direction along the plurality of tracks. For example, the integrated circuit 20 may include patterns 210 extending in the Y-axis direction from the second metal layer M2 and patterns extending in the X-axis direction from the third metal layer M3. (L1 to L5.5 and L1' to L3.5').

At least one of a power line that is a pattern for transmitting power and a signal line that is a pattern for transmitting a signal may be disposed on the plurality of tracks. For example, the first standard cell 201 in the third metal layer M3 may include signal lines L1 to L5. Also, the second standard cell 202 in the third metal layer M3 may include signal lines L1' to L3'.

The integrated circuit 20 includes a plurality of standard cells including first and second standard cells 201 and 202 disposed adjacent to each other in a first direction (eg, a Y-axis direction), and sequentially stacked in a vertical direction. The first to third metal layers M1 to M3 may be included. In addition, power is provided to a plurality of standard cells in an area where at least one standard cell of the first standard cell 201 and the second standard cell 202 is disposed, and power is provided in a second direction (eg, X-axis). direction), at least one power segment formed as a pattern of the third metal layer M3 may be disposed. The power line may represent a pattern extending longer in the second direction (eg, the X-axis direction) than the power segment. Widths of the patterns of the plurality of tracks in the second direction may be different from each other. Specifically, widths of patterns of second tracks among the plurality of tracks in the second direction may be different from widths of patterns of first tracks in the second direction.

In the third metal layer M3, the integrated circuit 20 provides power to a plurality of standard cells and transmits power segments 221, 223, 232, 241, and 243, which are patterns formed on a part of a track, and signals. and may include signal segments 222, 231, 233, and 242, which are patterns formed on a part of the track. The signal line may represent a pattern extending longer in the second direction (eg, the X-axis direction) than the signal segment.

Both a power segment and a signal segment may be formed in at least one of the plurality of tracks. For example, the power segments 221 and 223 and the signal segment 222 may be disposed on one track, and the power segment 232 and signal segments 231 and 233 may be disposed on the other track. and the power segments 241 and 243 and the signal segment 242 may be arranged on another track. Since the integrated circuit 20 includes a track on which both the power segment and the signal segment are arranged, space can be efficiently used, and therefore, the area of the integrated circuit can be reduced compared to the case where neither the power segment nor the signal segment is included. .

When only power lines or signal lines are formed in one track, the corresponding track may be referred to as a power track or a signal track. Also, when a power segment or a signal segment is formed in one track, the corresponding track may be referred to as a power-signal track. For example, when referring to tracks inside a standard cell in order, the signal tracks L1 to L5 and the power-signal track L5.5 are arranged in the area where the first standard cell 201 is arranged. can In addition, the signal tracks L1' to L3' and the power-signal track L3.5' may be disposed in the area where the second standard cell 202 is disposed. The number of tracks formed in the area where the plurality of cells are arranged is not limited as described above, and the number of tracks may vary.

A pitch (width in the Y-axis direction) of a signal line included in an integrated circuit, a pitch of a power line, a pitch of a signal segment, and/or a pitch of a power segment may be the same or different from each other. For example, as shown in FIG. 2, the pitch of the power segments 221, 223, 232, 241, 243 and the pitch of the signal segments 222, 231, 233, 242 may be greater than the pitch of the signal lines, , However, it is not limited thereto.

3 is a diagram for explaining a layout of an integrated circuit according to an exemplary embodiment of the present disclosure.

Referring to FIG. 3 , an integrated circuit 30 according to an exemplary embodiment of the present disclosure may include a first standard cell 301 and a second standard cell 302 . The integrated circuit 30 may include patterns 310 extending from the second metal layer M2 and patterns extending from the third metal layer M3.

A power-signal track L5.5 including a power segment and a signal segment may be formed inside a region where at least one standard cell of the first standard cell 301 and the second standard cell 302 is disposed. For example, unlike the power segment disposed at the boundary between the first standard cell 201 and the second standard cell 202 in the integrated circuit 20 of FIG. 2 , the integrated circuit of FIG. 3 has the first standard cell ( 301) and the second standard cell 302, the power segment 332 and the signal segment 331 formed as a pattern of the third metal layer M3 inside the region where the first standard cell 301 is disposed, not at the boundary. 333) may be included. Inside the standard cell, the pitch (width in the Y-axis direction) of the power segment 332 and the pitch (width in the Y-axis direction) of the signal segments 331 and 333 may be smaller than the pitch of the power line. It is not limited.

Accordingly, in the integrated circuit 30 according to the present disclosure, power is formed on the power-signal track L.5.5 of the third metal layer M3 and is formed inside the region where the first standard cell 301 is disposed. By including the segment 332 and the signal segments 331 and 333, it is possible to secure a wide space for routing electrically connecting a plurality of standard cells to each other. Accordingly, when a power segment is formed at the boundary of a standard cell, a larger number of signal lines, power lines, signal segments, and/or power segments may be included.

4A to 4C are views for explaining the layout of an integrated circuit according to an exemplary embodiment of the present disclosure.

Referring to FIG. 4A , an integrated circuit 40 according to an exemplary embodiment of the present disclosure may include a plurality of standard cells 401 to 404 . The standard cells 401 to 404 may include patterns extending from the second metal layer M2 and patterns extending from the third metal layer M3. Also, the integrated circuit 40 may include a plurality of power segments and a plurality of signal segments. A VDD voltage or a ground (GND) voltage may be applied to each of the plurality of power segments.

Standard cells 401-404 may have various cell heights. For example, the standard cells 401 and 403 may have a cell height of a first height, and the standard cells 402 and 404 may have a cell height of a second height. Also, the integrated circuit 40 may include standard cells composed of two different cell heights having a predetermined ratio, such as 9:13 (117:169). However, the cell height is not limited to the above and may vary.

Standard cells in the integrated circuit 40 may be arranged according to a predetermined rule. For example, as shown in FIG. 4A , when standard cells included in an integrated circuit have two heights, a first height and a second height, standard cells 401 and 403 having cell heights of the first height and the standard cells 402 and 404 having cell heights of the second height may be alternately arranged. In addition, although not shown in FIG. 4A, in the integrated circuit, two standard cells having a cell height of a first height are continuously arranged in the Y-axis direction, and then two standard cells having a cell height of a second height are adjacent to each other along the Y-axis. It can be arranged in such a way that it is arranged continuously in the direction. Also, standard cells having different cell heights may be arranged in a predetermined ratio in the integrated circuit. For example, in an integrated circuit, standard cells having a cell height of a first height and standard cells having a cell height of a second height may be sequentially arranged in the Y-axis direction to have a ratio of 2:2, 1:3, and the like. can However, the arrangement of standard cells is not limited to the above.

Referring to FIG. 4B , the integrated circuit 40 according to the exemplary embodiment of the present disclosure may include patterns extending from the first metal layer M1 . The number of tracks of the first metal layer M1 formed in the area where each of the standard cells 401 to 404 is disposed may vary according to the cell height of each of the standard cells 401 to 404 .

A direction in which patterns extend from the first metal layer M1 may be the same as a direction in which patterns extend from the third metal layer M3, and a direction perpendicular to a direction in which patterns extend from the second metal layer M2. can be For example, patterns in the first metal layer M1 and the third metal layer M3 may extend in the X-axis direction, and patterns in the second metal layer M2 may extend in the Y-axis direction.

The power lines 421 to 425 in the first metal layer M1 may be connected to power lines and/or power segments included in the third metal layer M3.

The power lines in the first metal layer M1 and/or the power lines and/or power segments in the third metal layer M3 may not be aligned in the direction in which the metal layers are stacked (eg, the Z-axis direction). can

FIG. 4C is a cross-sectional view of the integrated circuit shown in FIG. 4A taken along sections 411 and 412 .

Referring to FIG. 4C , patterns of a plurality of metal layers of the integrated circuit 40 according to an exemplary embodiment of the present disclosure may be connected by vias V1, V2, and V3, which are not shown in FIG. 4A. However, the integrated circuit 40 may include a plurality of metal layers. Referring to FIG. 4C as an example, the standard cell 404 may include patterns formed on the first metal layer M1 to the fourth metal layer M4.

The via V1 may connect between patterns disposed on the first metal layer M1 and patterns disposed on the second metal layer M2, and the via V2 may be disposed on the second metal layer M2. A connection may be made between the pattern and the patterns disposed on the third metal layer M3, and the via V3 may be formed between the pattern disposed on the third metal layer M3 and the patterns disposed on the fourth metal layer M4. can be connected. A power segment or power line may provide power to a lower standard cell through vias V1 to V3.

5A and 5B are views for explaining the layout of an integrated circuit according to an exemplary embodiment of the present disclosure.

FIG. 5B is a cross-sectional view of the integrated circuit shown in FIG. 5A taken along sections 511 and 512 . Referring to FIGS. 5A and 5B , an integrated circuit 50 according to an exemplary embodiment of the present disclosure may include a plurality of standard cells 501 to 504 . The integrated circuit 50 may include patterns extending from the second metal layer M2 and patterns extending from the third metal layer M3. Also, the integrated circuit 50 may include a plurality of power segments and a plurality of signal segments. A VDD voltage or a ground (GND) voltage may be applied to each of the plurality of power segments.

The standard cells 502 and 503 may illustratively have a cell height of a first height, and the standard cells 501 and 504 may illustratively have a cell height of a second height. For example, the first height may be smaller than the second height.

The area of the standard cells 501 and 504 having a relatively large cell height is larger than that of the standard cells 502 and 503, and accordingly, the number of patterns formed inside the standard cells 501 and 504 is greater than that of the standard cells 502 and 503. It may be more than the number of patterns formed inside. The amount of power required for the standard cells 501 and 504 having relatively high cell heights may be greater than the amount of power required for the standard cells 502 and 503 having relatively small cell heights. Depending on the amount of power required, the standard cell 504 may be insufficient to cover power by receiving power from the power segment. Accordingly, a power line 550 may be formed on the standard cell 504 and power may be provided from the power line 550 . In addition, the pitch 551 of the power line 550 is greater than the pitch (eg, 541) of the power segments (eg, 540) included in the standard cells 502 and 503 having relatively small cell heights. can

In addition, the standard cell 501 may not be a cell requiring as much power as the standard cell 504, and therefore, the power segment 520 may be disposed on the standard cell 501, and the power segment 520 power can be obtained from In addition, the size of the pitch 521 of the power segment 520 may be proportional to the amount of power required for the standard cell 501, and thus included in the standard cells 502 and 503, which may require a relatively small amount of power. may be greater than the pitch of the power segments.

Patterns of the plurality of metal layers of the integrated circuit may be connected through vias V2 and V3.

6A and 6B are views for explaining the layout of an integrated circuit according to an exemplary embodiment of the present disclosure.

FIG. 6B is a cross-sectional view of the integrated circuit 60 shown in FIG. 6A taken along sections 611, 612, and 613. Referring to FIG. Referring to FIG. 6A , an integrated circuit 60 according to an exemplary embodiment of the present disclosure may include a plurality of standard cells 601 to 604 . An area where the plurality of standard cells 601 to 604 are disposed may include patterns extending from the second metal layer M2 and patterns extending from the third metal layer M3. Also, the integrated circuit 60 may include a plurality of power segments and a plurality of signal segments. A VDD voltage or a ground (GND) voltage may be applied to each of the plurality of power segments.

A power segment may be included in an area where the plurality of standard cells 601 to 604 are disposed. The power segment may be located on the standard cell boundary or inside the standard cell. For example, the power segments 621 and 622 are located inside the area where the standard cells are arranged, and the power segments 631, 632, 641 and 642 are located on the boundaries of the standard cells.

When the power segments 621 and 622 are not located on the standard cell boundary but are included in an area where different standard cells are arranged based on the standard cell boundary, the power segments 621 and 622 are respectively different from each other. It may be connected to the pattern of the metal layer M2. In other words, the area where the standard cell 603 is disposed may include the power segment 621 disposed adjacent to the cell boundary with the standard cell 603, and the area where the standard cell 602 is disposed may include the cell boundary. It may include a power segment 622 disposed adjacent to, and the power segment 621 and the power segment 622 may be connected to different patterns formed on the second metal layer M2, respectively.

In addition, when there is a power segment located on the standard cell boundary, the corresponding power segment may be disposed adjacent to another power segment connected to the same pattern in the second metal layer M2.

Patterns of a plurality of metal layers of the integrated circuit 60 according to an exemplary embodiment of the present disclosure may be connected through vias V2 and V3, and the power segment supplies power to standard cells through the vias V2 and V3. can provide

7A to 7B are diagrams for explaining a layout of an integrated circuit according to an exemplary embodiment of the present disclosure.

Referring to FIG. 7A , an integrated circuit 70 according to an exemplary embodiment of the present disclosure may include a plurality of standard cells 701 to 704 . The standard cells 701 to 704 may include patterns extending from the second metal layer M2 and patterns extending from the third metal layer M3. Also, the integrated circuit 70 may include a plurality of power segments and a plurality of signal segments. A VDD voltage or a ground (GND) voltage may be applied to each of the plurality of power segments.

The integrated circuit 70 may not include a power segment if a power segment is not required, such as in the standard cells 703 and 704.

Referring to FIG. 7B , patterns of a plurality of metal layers of an integrated circuit according to an exemplary embodiment of the present disclosure may be connected through super vias.

Super vias may be vias capable of connecting patterns included in non-adjacent metal layers. For example, the super via may be a via capable of connecting a pattern included in the second metal layer M2 and a pattern included in the fourth metal layer M4, but is not limited thereto.

8A to 8D are diagrams for explaining the layout of an integrated circuit according to an exemplary embodiment of the present disclosure.

Referring to FIG. 8A , an integrated circuit 80 according to an exemplary embodiment of the present disclosure may include a plurality of standard cells 801 to 804 and may include patterns extending from the third metal layer M3. can Also, the integrated circuit 80 may include a plurality of power segments and a plurality of signal segments. A VDD voltage or a ground (GND) voltage may be applied to each of the plurality of power segments.

The integrated circuit may be configured such that power lines are placed on cell boundaries of standard cells 801 and 802 . Alternatively, the integrated circuit 80 may include a power line disposed inside a region in which each of the standard cells 803 and 804 are disposed, rather than on a cell boundary of the standard cells 803 and 804, and 804 can secure more space for routing than the standard cell 802.

Referring to FIG. 8B , the integrated circuit may be configured such that a power line is positioned at each cell boundary, such as in standard cells 811 and 812 . Unlike the standard cells 813 and 814, space can be secured in the standard cells 813 and 814 by reducing the pitch size of the power lines and eliminating some of the power lines. Accordingly, the standard cells 813 and 814 814) may include more signal lines than the standard cells 811 and 812.

Referring to FIGS. 8C and 8D , standard cells 851 to 854 and 861 to 864 may be arranged in various ways according to cell height.

For example, the arrangement of standard cells may vary based on the amount of power required for the standard cells. Standard cells with a large cell height may require a larger amount of power, and thus more power lines may be arranged to include standard cells with a larger cell height.

9A and 9B are diagrams for explaining the layout of an integrated circuit according to an exemplary embodiment of the present disclosure.

Referring to FIG. 9A , an integrated circuit according to an exemplary embodiment of the present disclosure may include a plurality of standard cells, and the plurality of standard cells are a power line of a first metal layer M1 and a third metal layer M3. ) may be supplied with power through a power line or power segment.

Some of the power lines of the first metal layer M1 may not be aligned with power lines/power segments of the third metal layer M3. For example, the power line/power segment of the third metal layer M3 may not be disposed on the power lines 921 and 923 of the first metal layer M1, that is, the third metal layer may be formed in a vertical direction. It may not be aligned with the power line/power segment of layer M3.

Accordingly, the power line 912 of the third metal layer M3 may be connected to the power lines 921 and 923 of the first metal layer M1, and also the power line 911 of the third metal layer M3. , 913) may also be connected to the power line 922 of the first metal layer M1.

Referring to FIG. 9B , some of the power lines of the first metal layer M1 may not be aligned with power lines/power segments of the third metal layer M3. The power lines 931 and 933 of the third metal layer M3 may be connected to the power line 942 of the first metal layer M1, and the power lines 933 and 935 of the third metal layer M3 may be It may be connected to the power line 944 of the first metal layer M1, and the power line 932 of the third metal layer M3 may be connected to the power lines 941 and 943 of the first metal layer M1. , The power line 934 of the third metal layer M3 may be connected to the power lines 943 and 945 of the first metal layer M1, but is not limited thereto.

10 is a flowchart illustrating a method for designing an integrated circuit according to an exemplary embodiment of the present disclosure.

Referring to FIG. 10 , in step S1010 , the method for designing an integrated circuit according to an exemplary embodiment of the present disclosure may include arranging a plurality of cells.

In step S1020, the method for designing an integrated circuit according to an exemplary embodiment of the present disclosure may include disposing a plurality of power lines in a pattern for delivering power to a plurality of standard cells on a plurality of tracks. can..

In step S1030, the method for designing an integrated circuit according to an exemplary embodiment of the present disclosure may include replacing some of a plurality of power lines with a signal segment that transmits a signal to a plurality of standard cells. . A portion to be replaced with a signal segment may be determined based on an amount of power required for a cell in which a power line to be replaced is disposed. For example, when the amount of power required for a cell is small, the entire power line may not be needed, and accordingly, a decision may be made to replace some of the power lines with signal segments.

In addition, a method for designing an integrated circuit is a pattern formed on a part of a track that transfers power to a plurality of standard cells through a dummy signal segment, which is a part not used for signal transmission among the arranged signal lines. A step of replacing and arranging the power segment may be further included. By replacing a potentially unnecessary dummy signal segment with a power segment, space in an area where standard cells are arranged can be efficiently used.

Additionally, a method for designing an integrated circuit may include positioning a power segment to abut a power line disposed adjacent to a dummy signal segment. Specifically, when there is a power segment and a power line disposed adjacent to the dummy signal segment, the pattern of the power segment may be extended so as to be in contact with the power line. Accordingly, metal resources included in the integrated circuit can be efficiently used. In addition, a power segment may be disposed on a dummy signal line by extending a metal of an existing power line.

Further, the method for designing an integrated circuit may further include merging adjacent power segments into one power segment when power segments disposed on different tracks are adjacently disposed.

Also, a method for designing an integrated circuit may include placing a power segment inside a plurality of cells.

Also, a method for designing an integrated circuit may include removing a dummy signal segment, which is a portion of an arranged signal line that is not used for signal transmission.

In addition, the method for designing the integrated circuit includes forming vias in the lower metal layer that connect a lower metal layer of the metal layer on which the dummy signal segments are disposed and an upper metal layer of the metal layer on which the dummy signal segments are disposed. can do.

11A and 11B are diagrams for explaining the layout of an integrated circuit according to an exemplary embodiment of the present disclosure.

FIG. 11B is a cross-sectional view of the integrated circuit 110 shown in FIG. 11A taken along sections 1111 and 1112 .

Referring to FIG. 11A , an integrated circuit 110 according to an exemplary embodiment of the present disclosure may include a plurality of standard cells 1101 to 1104 .

Referring to FIGS. 5A and 11A , a method for designing an integrated circuit 110 according to an exemplary embodiment of the present disclosure may determine dummy signal segments in standard cells 401 to 404 of FIG. 4A . For example, signal segments formed on axes 411 and 412 of FIG. 4A may be determined as dummy signal segments. A method for designing an integrated circuit may allow a power segment to be placed on a dummy signal segment since a dummy signal segment may be an unnecessary part on a standard cell. Specifically, a power line or an extended power segment may be formed instead of a dummy signal segment by extending the power segment pattern of FIG. 4A in the X-axis direction like the power segments 1121 and 1122 of FIG. 11A.

Also, as the power segments 1121 and 1122 are formed, patterns 1131 , 1132 , 1133 and 1134 may be additionally formed on the second metal layer M2 . By forming the patterns 1131 , 1132 , 1133 , and 1134 , resistance may be reduced, and IR drop characteristics and EM (electromigration) characteristics may be improved.

Patterns of a plurality of metal layers of the integrated circuit 110 according to an exemplary embodiment of the present disclosure may be connected through vias V2 and V3.

12A to 12C are views for explaining the layout of an integrated circuit according to an exemplary embodiment of the present disclosure. FIG. 12C is a cross-sectional view of the integrated circuit 120 shown in FIG. 12A taken along sections 1211, 1212, and 1213. Referring to FIG.

Referring to FIG. 12A , an integrated circuit 120 according to an exemplary embodiment of the present disclosure may include a plurality of standard cells 1301 to 1304 . The plurality of standard cells 1202, 1203, and 1204 may include a power segment inside the standard cell. The power segments may be arranged adjacent to the cell boundary, such as the power segments 1220, 1221, and 1223, and may be arranged to be included inside the standard cell without being adjacent to the cell boundary, such as the power segments 1222 and 1224. .

(A power segment 1320 formed on a power-signal track formed close to the standard cell 1302 at the cell boundary, and a power segment 1321 formed on a power-signal track formed close to the standard cell 1303)

Referring to FIGS. 12A and 12B , a method for designing an integrated circuit according to an exemplary embodiment of the present disclosure includes power segments 1220 and 1221 disposed adjacent to each other based on a cell boundary of FIG. 12A. It can be merged like the power segment 1230 of 12b. In this case, the via V2 connecting the power segments 1230 is formed in a long bar shape, and the power segments 1230 formed on the two tracks can be connected with one via. However, the shape of the via is not limited to the above, and may be formed in various shapes such as a square shape. Also, vias may be formed to connect power segments formed on two or more tracks.

Referring to FIG. 12C , patterns of a plurality of metal layers of the integrated circuit according to the exemplary embodiment of the present disclosure may be connected through vias V2 and V3.

13 is a flow chart illustrating a method for fabricating an integrated circuit according to an exemplary embodiment of the present disclosure.

Referring to FIG. 13 , the standard cell library D10 may include information about standard cells, for example, function information, characteristic information, and layout information. The standard cell library D10 may include data DC defining the layout of standard cells. The data DC may include data defining structures of standard cells that perform the same function and have different layouts. The data DC may include data defining structures of the standard cells described with reference to FIGS. 1 to 12C.

Steps S10 and S20 are steps of designing an integrated circuit (IC), and layout data D30 may be generated from RTL data D11. The integrated circuit (IC) may be the integrated circuit 10 of FIG. 1 . In step S10, a logic synthesis operation may be performed to generate netlist data D20 from RTL data D11. For example, a semiconductor design tool (eg, a logic synthesis module) refers to a standard cell library D10 from RTL data D11 written as VHDL (VHSIC Hardware Description Language) and HDL (Hardware Description Language) such as Verilog. By performing logic synthesis by doing so, it is possible to generate netlist data D20 including a bitstream or netlist. The standard cell library D10 performs the same function and may include data (DC) defining the structure of standard cells having different layouts. can be included in

In step S20, a Place & Routing (P&R) operation for generating layout data D30 from netlist data D20 may be performed. Layout data D30 may have a format such as, for example, GDSII, and may include geometric information of standard cells and interconnections.

For example, a semiconductor design tool (eg, a P&R module) may arrange a plurality of standard cells from the netlist data D20 by referring to the standard cell library D10. The semiconductor design tool may select one of the standard cell layouts defined by the netlist D103 by referring to the data DC, and may arrange the selected standard cell layout.

In step S20, an operation of generating interconnections may be further performed. The interconnection may electrically connect the output pin and the input pin of the standard cell, and may include, for example, a conductive pattern formed on at least one via and at least one metal layer.

In step S30, Optical Proximity Correction (OPC) may be performed. OPC may refer to an operation to form a pattern of a desired shape by correcting distortion phenomena such as refraction caused by the characteristics of light in photolithography included in a semiconductor process for manufacturing an integrated circuit (IC). , the pattern on the mask may be determined by applying OPC to the layout data D30. In an exemplary embodiment, the layout of the integrated circuit (IC) may be limitedly modified in step S30, and the limited modification of the integrated circuit (IC) in step S30 may be performed after optimizing the structure of the integrated circuit (IC). As a treatment, it may be referred to as design polishing.

In step S40, an operation of manufacturing a mask may be performed. For example, as OPC is applied to the layout data D30, patterns on a mask may be defined to form patterns formed on a plurality of layers, and at least one mask (or , photomask) can be fabricated.

In step S50, an operation of fabricating an integrated circuit (IC) may be performed. For example, an integrated circuit (IC) may be fabricated by patterning a plurality of layers using at least one mask fabricated in step S40. Step S50 may include steps S51, S53, and S55.

In step S51, a front-end-of-line (FEOL) process may be performed. FEOL may refer to a process of forming individual elements, eg, transistors, capacitors, resistors, and the like, on a substrate during the manufacturing process of an integrated circuit (IC). For example, FEOL includes planarization and cleaning of the wafer, forming trenches, forming wells, forming gate lines, forming source and drain regions, etc. can do.

In step S53, a middle-of-line (MOL) process may be performed. It may refer to a process of forming a connecting member for connecting individual devices produced through the FEOL process in a standard cell. For example, the MOL process may include forming an active contact on an active region, forming a gate contact on a gate line, forming a via on the active contact and the gate line, and the like.

In step S55, a back-end-of-line (BEOL) process may be performed. BEOL may refer to a process of interconnecting individual elements, eg, transistors, capacitors, resistors, and the like, in the manufacturing process of an integrated circuit (IC). For example, BEOL includes silicidation of gate, source and drain regions, adding dielectric, planarization, forming holes, forming metal layers, and forming vias between metal layers. A step of forming, a step of forming a passivation layer, and the like may be included. The integrated circuit (IC) can then be packaged in a semiconductor package and used as a component in various applications.

As above, exemplary embodiments have been disclosed in the drawings and specifications. Although the embodiments have been described using specific terms in this specification, they are only used for the purpose of explaining the technical idea of the present disclosure, and are not used to limit the scope of the present disclosure described in the claims. . Therefore, those of ordinary skill in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical scope of protection of the present disclosure should be determined by the technical spirit of the appended claims.

Claims (10)

a plurality of standard cells including first and second standard cells disposed adjacent to each other in a first direction; and
Including first to third metal layers sequentially stacked in a vertical direction,
Formed as a pattern of the third metal layer extending in a second direction and providing power to the plurality of standard cells within a region where at least one of the first standard cell and the second standard cell is disposed An integrated circuit, characterized in that at least one power segment (power segment) is disposed. According to claim 1,
and the power segment disposed at a cell boundary of the first standard cell and the second standard cell. According to claim 1,
The cell height of the first standard cell in the first direction is greater than the cell height of the second standard cell in the first direction;
A power line formed as a pattern of the third metal layer that supplies power to the plurality of standard cells and extends in the second direction is formed at a cell boundary of the first standard cell;
wherein the power line extends longer in the second direction than the at least one power segment. According to claim 1,
The at least one power segment includes a first power segment and a second power segment,
The first power segment is disposed adjacent to a cell boundary with the second standard cell in an area where the first standard cell is disposed;
The second power segment is disposed adjacent to the cell boundary in an area where the second standard cell is disposed;
The first power segment and the second power segment are each connected to different patterns formed on the second metal layer. According to claim 1,
The integrated circuit further comprises a via connecting a pattern included in a fourth metal layer, which is a higher metal layer than the third metal layer, and a pattern included in the second metal layer. According to claim 1,
An integrated circuit further comprising vias connecting two or more tracks included in the same metal layer. According to claim 1,
Each of the first metal layer and the third metal layer includes power lines transmitting power to the plurality of standard cells,
Some of the power lines included in the third metal layer are not aligned in a direction in which the power lines of the first metal layer and the metal layers are stacked. In the method of designing an integrated circuit,
arranging a plurality of standard cells;
arranging a plurality of power lines in a pattern for delivering power to the plurality of standard cells on a plurality of tracks; and
and replacing some of the plurality of power lines with a signal segment carrying a signal to the plurality of standard cells. According to claim 8,
The replacement step is
and determining the part based on an amount of power required for a cell in which the power line to be replaced is disposed. According to claim 8,
arranging signal lines for transmitting signals to the plurality of standard cells;
A dummy signal segment, which is a portion of the plurality of signal lines not used for signal transmission, is converted into a power segment, which is a pattern formed on a part of a track and transferring power to the plurality of standard cells. The method further comprising the step of replacing and disposing.

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