KR20230024322A - Display device - Google Patents

Abstract

The present invention relates to a display device capable of realizing low power consumption. According to the present invention, because a first thin-film transistor having a polycrystalline semiconductor layer and a second thin-film transistor having an oxide semiconductor layer are arranged in an active area, low power consumption can be realized, and because at least one opening arranged in a bending area has the same depth as any one of a plurality of contact holes arranged in the active area, the opening and the contact tholes can be formed in the same process, thereby simplifying the process. Because a high-potential supply line and a low-potential supply line overlap with a protective film made of inorganic insulating material therebetween, short circuit defects in the high-potential supply line and low-potential supply line can be prevented.

Description

Display device {DISPLAY DEVICE}

The present invention relates to a display device, and more particularly, to a display device capable of realizing low power consumption.

BACKGROUND OF THE INVENTION [0002] Video display devices, which implement various information on a screen, are a core technology in the information and communication era, and are developing toward a thinner, lighter, portable and high-performance direction. Accordingly, a flat panel display device capable of reducing the weight and volume, which are disadvantages of a cathode ray tube (CRT), is in the spotlight.

These flat panel displays include liquid crystal display devices (LCDs), plasma display panels (PDPs), organic light emitting display devices (OLEDs), and electrophoretic displays (electrophoretic displays). Display Device: ED), etc.

Such a flat panel display device is being developed as a product with excellent portability and/or wearability as personal electronic devices are actively developed. As such, a display device capable of realizing low power consumption is required in order to be applied to a portable or wearable device. However, it is difficult to implement low power consumption with the technologies related to display devices developed to date.

The present invention is to solve the above problems, and the present invention provides a display device capable of realizing low power consumption.

In order to achieve the above object, the present invention includes a first thin film transistor having a polycrystalline semiconductor layer in an active region; Since the second thin film transistor having an oxide semiconductor layer is disposed, low power consumption can be realized, and since at least one opening disposed in the bending region has the same depth as any one of the plurality of contact holes disposed in the active region, the opening and The process can be simplified as the contact hole can be formed in the same process, and since the high potential supply line and the low potential supply line are overlapped with an inorganic insulating material in between, short circuit defects between the high potential supply line and the low potential supply line can be prevented. can prevent

In the present invention, power consumption can be reduced by applying the second thin film transistor having an oxide semiconductor layer to the driving transistor of each sub-pixel and applying the first thin film transistor having a polycrystalline semiconductor layer as a switching element of each sub-pixel. Further, in the present invention, since the opening disposed in the bending area is formed through the same mask process as the plurality of contact holes disposed in the active area, the opening and the contact hole are formed to have the same depth. Accordingly, the present invention can simplify the structure and manufacturing process, thereby improving productivity. In addition, in the present invention, a passivation layer made of an inorganic insulating material and a first planarization layer made of an organic insulating material are disposed between the high-potential supply line and the low-potential supply line. Accordingly, the present invention can prevent the high potential supply line and the low potential supply line from being shorted by the passivation layer even if a pinhole is generated in the first planarization layer.

1 is a block diagram showing a display device according to the present invention.
FIG. 2 is a cross-sectional view illustrating the display device taken along line “I-I′” in FIG. 1 .
3A and 3B are plan views illustrating sub-pixels disposed in the active area shown in FIG. 1 .
4A and 4B are plan views illustrating embodiments of signal links disposed in the bending area shown in FIG. 1;
5A and 5B are circuit diagrams for explaining each sub-pixel of the display device shown in FIG. 1 .
FIG. 6 is a plan view illustrating the sub-pixels shown in FIG. 5B.
FIG. 7 is a cross-sectional view illustrating the organic light emitting display device taken along lines II-II', III-III', IV-IV', V-V', and VI-VI' in FIG. 6 .
8A is a cross-sectional view showing a comparative example not provided with the protective layer shown in FIG. 7 , and FIG. 8B is a cross-sectional view showing an embodiment provided with the protective layer shown in FIG. 7 .
9A and 9B are cross-sectional views illustrating other exemplary embodiments of the bending area shown in FIG. 7 .
10A to 10N are cross-sectional views illustrating a method of manufacturing the organic light emitting display device shown in FIG. 7 .

Hereinafter, embodiments according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a plan view showing a display device according to the present invention, and FIG. 2 is a cross-sectional view showing the display device according to the present invention.

The display device shown in FIGS. 1 and 2 includes a display panel 200 , a gate driver 202 and a data driver 204 .

The display panel 200 is divided into an active area AA disposed on the substrate 101 and a non-active area NA disposed around the active area AA. The substrate 101 is formed of a plastic material having flexibility to enable bending. For example, the substrate is polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polycarbonate (PC), polyethersulfone (PES), polyarylate (PAR), polysulfone (PSF), ciclic-olefin copolymer (COC) made of materials such as

The active area AA displays an image through unit pixels arranged in a matrix form. A unit pixel is composed of red (R), green (G), and blue (B) sub-pixels, or composed of red (R), green (G), blue (B), and white (W) sub-pixels. For example, as shown in FIG. 3A, red (R), green (G), and blue (B) sub-pixels are arranged in a row on the same virtual horizontal line, or as shown in FIG. 3B, red (R) , green (G) and blue (B) sub-pixels are spaced apart from each other and arranged in a virtual triangular structure.

Each sub-pixel includes at least one of a thin film transistor having an oxide semiconductor layer and a thin film transistor having a polycrystalline semiconductor layer. A thin film transistor having such an oxide semiconductor layer and a thin film transistor having a polycrystalline semiconductor layer have higher electron mobility than a thin film transistor having an amorphous semiconductor layer, enabling high resolution and low power implementation.

At least one of the data driver 204 and the gate driver 202 may be disposed in the non-display area NA.

The scan driver 202 drives the scan line of the display panel 200 . The scan driver 202 is configured using at least one of a thin film transistor having an oxide semiconductor layer and a thin film transistor having a polycrystalline semiconductor layer. At this time, the thin film transistor of the scan driver 202 is simultaneously formed in the same process as at least one thin film transistor disposed in each sub-pixel of the active area AA.

The data driver 204 drives the data lines of the display panel 200 . The data driver 204 is mounted on the substrate 101 in the form of a chip or mounted on the signal transmission film 206 in the form of a chip and attached to the non-active area NA of the display panel 200 . To be electrically connected to the signal transmission film 206, a plurality of signal pads PAD are disposed in the non-active area NA, as shown in FIGS. 4A and 4B. A signal line where driving signals generated from the data driver 204, the scan driver 202, the power supply (not shown), and the timing controller (not shown) are disposed in the active area AA through the signal pad PAD. supplied to

The non-active area NA includes a bending area BA capable of bending or folding the display panel 200 . The bending area BA corresponds to an area that is bent to position areas that do not perform a display function, such as the signal pad PAD, the scan driver 202, and the data driver 204, to the rear surface of the active area AA. As shown in FIG. 1 , the bending area BA is disposed within the upper side of the non-active area NA between the active area AA and the data driver 204 . In addition, the bending area BA may be disposed within at least one of the upper, lower, left, and right sides of the non-active area NA. Accordingly, the area occupied by the active area AA on the entire screen of the display device is maximized and the area corresponding to the non-active area NA is minimized.

The signal link LK disposed in the bending area BA connects the signal pad PAD and the signal line disposed in the active area AA. When the signal link LK is formed in a straight line along the bending direction BD, a crack or disconnection may occur in the signal link LK by receiving the greatest bending stress. Accordingly, the area of the signal link LK of the present invention is widened in a direction crossing the bending direction BD to minimize bending stress. To this end, the signal link LK is formed in a zigzag or sinusoidal shape as shown in FIG. 4A, or formed in a form in which a plurality of rhombus shapes with empty central areas are connected to each other in a row as shown in FIG. 4B.

The signal link LK disposed in the bending area BA connects the signal pad PAD and the signal line disposed in the active area AA. When the signal link LK is formed in a straight line along the bending direction BD, a crack or disconnection may occur in the signal link LK by receiving the greatest bending stress. Accordingly, the area of the signal link LK of the present invention is widened in a direction crossing the bending direction BD to minimize bending stress. To this end, the signal link LK is formed in a zigzag or sinusoidal shape as shown in FIG. 4A, or formed in a form in which a plurality of rhombus shapes with empty central areas are connected to each other in a row as shown in FIG. 4B.

Also, as shown in FIG. 2 , at least one opening 212 is disposed in the bending area BA so that the bending area BA can be easily bent. The opening 212 is formed by removing a plurality of inorganic insulating layers 210 that cause cracks disposed in the bending area BA. Specifically, when the substrate 101 is bent, continuous bending stress is applied to the inorganic insulating layer 210 disposed in the bending area BA. Since the inorganic insulating layer 210 has lower elasticity than organic insulating materials, cracks are easily generated in the inorganic insulating layer 210 . Cracks generated in the inorganic insulating layer 210 propagate to the active area AA along the inorganic insulating layer 210 , resulting in line defects and defective device driving. Accordingly, at least one planarization layer 208 made of an organic insulating material having higher elasticity than the inorganic insulating layer 210 is disposed in the bending area BA. Since the planarization layer 208 alleviates bending stress generated when the substrate 101 is bent, it is possible to prevent cracks from occurring. Since the opening 212 of the bending area BA is formed through the same mask process as at least one of the plurality of contact holes disposed in the active area AA, the structure and process can be simplified.

Such a display device capable of simplifying the structure and process may be applied to a display device requiring a thin film transistor, such as a liquid crystal display device or an organic light emitting display device. Hereinafter, an embodiment of the present invention in which a display device capable of simplifying a structure and process is applied to an organic light emitting display device will be described.

Each of the sub-pixels SP of the organic light emitting display device includes a pixel driving circuit and a light emitting element 130 connected to the pixel driving circuit, as shown in FIGS. 5A and 5B .

The pixel driving circuit is composed of a 2T1C structure having two thin film transistors (ST and DT) and one storage capacitor (Cst) as shown in FIG. 5A, but as shown in FIGS. It is composed of a 4T1C structure having transistors ST1, ST2, ST3, and DT and one storage capacitor Cst. Here, the pixel driving circuit is not limited to the structures of FIGS. 5A and 5B , and pixel driving circuits of various configurations may be used.

The storage capacitor Cst of the pixel driving circuit shown in FIG. 5A is connected between the gate node Ng and the source node Ns to maintain a constant voltage between the gate node Ng and the source node Ns during the light emission period. let it The driving transistor DT has a gate electrode connected to the gate node Ng, a drain electrode connected to the drain node Nd, and a source electrode connected to the light emitting element 130 . The driving transistor DT controls the magnitude of the driving current according to the voltage between the gate node Ng and the source node Ns. The switching transistor ST has a gate electrode connected to the scan line SL, a drain electrode connected to the data line DL, and a source electrode connected to the gate node Ng. The switching transistor ST1 is turned on in response to the scan control signal SC from the scan line SL1 to supply the data voltage Vdata from the data line DL to the gate node Ng. The light emitting element 130 is connected between the source node Ns connected to the source electrode of the driving transistor DT and the low potential supply line 162 and emits light according to the driving current.

In contrast to the pixel driving circuit shown in FIG. 5A , the pixel driving circuit shown in FIG. 5B has the source electrode of the first switching transistor ST1 connected to the data line DL connected to the source node Ns, and It has substantially the same configuration except for further including second and third switching transistors ST2 and ST3. Therefore, a detailed description of the same configuration will be omitted.

5B and 6 , the first switching transistor ST1 includes a gate electrode 152 connected to the first scan line SL1, a drain electrode 158 connected to the data line DL, and a source node. A semiconductor layer 154 forming a channel is provided between a source electrode 156 connected to (Ns) and the source and drain electrodes 156 and 158. The first switching transistor ST1 is turned on in response to the scan control signal SC1 from the first scan line SL1 to supply the data voltage Vdata from the data line DL to the source node Ns. .

The second switching transistor ST2 has a gate electrode GE connected to the second scan line SL2, a drain electrode DE connected to the reference line RL, and a source electrode connected to the gate node Ng. (SE) and a semiconductor layer (ACT) forming a channel between the source and drain electrodes (SE and DE). The second switching transistor ST2 is turned on in response to the scan control signal SC2 from the second scan line SL2 to supply the reference voltage Vref from the reference line RL to the gate node Ng. .

The third switching transistor ST3 has a gate electrode GE connected to the emission control line EL, a drain electrode DE connected to the high potential supply line 172, and a source connected to the drain node Nd. A semiconductor layer ACT forming a channel is provided between the electrode SE and the source and drain electrodes SE and DE. The third switching transistor ST3 is turned on in response to the light emission control signal EN from the light emission control line EL, and applies the high potential voltage VDD from the high potential supply line 172 to the drain node Nd. supply to

Each of the high-potential supply line 172 and the low-potential supply line 162 included in the pixel driving circuit is formed in a mesh shape so that at least two sub-pixels share it. To this end, the high-potential supply line 172 includes first and second high-potential supply lines 172a and 172b that cross each other, and the low-potential supply line 162 includes first and second low-potential supply lines that cross each other. Supply lines 162a and 162b are provided.

Each of the second high-potential supply line 172b and the second low-potential supply line 162b is disposed parallel to the data line DL, and is formed for each of at least two sub-pixels. The second high-potential supply line 172b and the second low-potential supply line 162b are disposed side by side side by side as shown in FIGS. 5A and 5B, or vertically overlapping each other as shown in FIG. 6. are placed side by side

The first high-potential supply line 172a is electrically connected to the second high-potential supply line 172b and disposed parallel to the scan line SL. The first high-potential supply line 172a is branched from the second high-potential supply line 172b to intersect the second high-potential supply line 172b between the second high-potential supply lines 172b. Accordingly, the first high potential supply line 172a can minimize the voltage drop (IR drop) of the high potential supply line 172 by compensating for the resistance of the second high potential supply line 172b.

The first low potential supply line 162a is electrically connected to the second low potential supply line 162b and disposed parallel to the scan line SL. The first low-potential supply line 162a is branched from the second low-potential supply line 162b to intersect the second low-potential supply line 162b between the second low-potential supply lines 162b. Accordingly, the first low-potential supply line 162a can minimize the voltage drop (IR drop) of the low-potential supply line 162 by compensating for the resistance of the second low-potential supply line 162b.

As such, since the high potential supply line 172 and the low potential supply line 162 are formed in a mesh shape, the number of the second high potential supply line 172b and the second low potential supply line 162b disposed in the vertical direction is reduced. It can be reduced, and since more sub-pixels can be arranged as the number is reduced, the aperture ratio and resolution increase.

Among the plurality of transistors included in the pixel driving circuit, one transistor includes a polycrystalline semiconductor layer, and the other transistors include an oxide semiconductor layer. The switching transistor ST of the pixel driving circuit shown in FIG. 5A is formed of the first thin film transistor 150 having the polycrystalline semiconductor layer 154 as shown in FIG. 7 , and the driving transistor DT is an oxide semiconductor layer. It is formed of the second thin film transistor 100 having (104). In addition, the first and third switching transistors ST1 and ST3 of the pixel driving circuit shown in FIGS. 5B and 6 are formed of one thin film transistor 150 having a polycrystalline semiconductor layer 154, and the second switching transistor ( ST2) and the driving transistor DT are formed of the second thin film transistor 100 having the oxide semiconductor layer 104. As described above, in the present invention, the second thin film transistor 100 having the oxide semiconductor layer 104 is applied to the driving transistor DT of each sub-pixel, and the first thin film transistor 150 having the polycrystalline semiconductor layer 154 Power consumption can be reduced by applying to the switching element ST of each sub-pixel.

The first thin film transistor 150 shown in FIGS. 6 and 7 includes a polycrystalline semiconductor layer 154, a first gate electrode 152, a first source electrode 156, and a first drain electrode 158. provide

A polycrystalline semiconductor layer 154 is formed on the lower buffer layer 112 . This polycrystalline semiconductor layer 154 includes a channel region, a source region, and a drain region. The channel region overlaps the first gate electrode 152 with the lower gate insulating layer 114 interposed therebetween to form a channel region between the first source and first drain electrodes 156 and 158 . The source region is electrically connected to the first source electrode 156 through the first source contact hole 160S. The drain region is electrically connected to the first drain electrode 158 through the first drain contact hole 160D. Since the polycrystalline semiconductor layer 154 has higher mobility than the amorphous semiconductor layer and the oxide semiconductor layer 104, energy consumption is low and reliability is excellent, the switching transistor ST and the scan line SL of each sub-pixel are driven. suitable for application to the gate driver 202 for A multi-buffer layer 140 and a lower buffer layer 112 are disposed between the polycrystalline semiconductor layer 154 and the substrate 101 . The multi-buffer layer 140 delays diffusion of moisture and/or oxygen penetrating into the substrate 101 . The multi-buffer layer 140 is formed by alternately stacking silicon nitride (SiNx) and silicon oxide (SiOx) at least once. The lower buffer layer 112 protects the polycrystalline semiconductor layer 154 and blocks various types of defects introduced from the substrate 101 . The lower buffer layer 112 may be formed of a-Si, silicon nitride (SiNx), or silicon oxide (SiOx).

The first gate electrode 152 is formed on the lower gate insulating layer 114 . The first gate electrode 152 overlaps the channel region of the polycrystalline semiconductor layer 154 with the lower gate insulating layer 114 interposed therebetween. The first gate electrode 152 is made of the same material as the storage lower electrode 182, for example, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), or nickel (Ni). ), neodymium (Nd) and copper (Cu), or may be a single layer or a multi-layer made of any one of these alloys, but is not limited thereto.

The first and second lower interlayer insulating films 116 and 118 positioned on the polycrystalline semiconductor layer 154 are formed of an inorganic film having a higher hydrogen particle content than the upper interlayer insulating film 124 . For example, the first and second lower interlayer insulating films 116 and 118 are made of silicon nitride (SiNx) formed by a deposition process using NH3 gas, and the upper interlayer insulating film 124 is made of silicon oxide (SiOx). Hydrogen particles included in the first and second lower interlayer insulating films 116 and 118 are diffused into the polycrystalline semiconductor layer 154 during the hydrogenation process to fill voids in the polycrystalline semiconductor layer 154 with hydrogen. Accordingly, since the polycrystalline semiconductor layer 154 can be stabilized, degradation of the characteristics of the first thin film transistor 150 can be prevented.

The first source electrode 156 includes a first source contact hole 160S penetrating the lower gate insulating layer 114 , the first and second lower interlayer insulating layers 116 and 118 , the upper buffer layer 122 , and the upper interlayer insulating layer 124 . It is connected to the source region of the polycrystalline semiconductor layer 154 through. The first drain electrode 158 faces the first source electrode 156, and includes the lower gate insulating layer 114, the first and second lower interlayer insulating layers 116 and 118, the upper buffer layer 122, and the upper interlayer insulating layer 124. It is connected to the drain region of the polycrystalline semiconductor layer 154 through the first drain contact hole 160D passing through. Since the first source and first drain electrodes 156 and 158 are formed of the same material on the same plane as the storage supply line 186, the first source and first drain electrodes 156 and 158 are the same as the storage supply line 186. It can be formed simultaneously through the mask process.

After the process of activating and hydrogenating the polycrystalline semiconductor layer 154 of the first thin film transistor 150, the oxide semiconductor layer 104 of the second thin film transistor 100 is formed. That is, the oxide semiconductor layer 104 is positioned over the polycrystalline semiconductor layer 154 . Accordingly, since the oxide semiconductor layer 104 is not exposed to the high-temperature atmosphere of the activation and hydrogenation process of the polycrystalline semiconductor layer 154, damage to the oxide semiconductor layer 104 can be prevented and reliability is improved.

The second thin film transistor 100 is disposed on the upper buffer layer 122 to be spaced apart from the first thin film transistor 150 . The second thin film transistor 100 includes a second gate electrode 102 , an oxide semiconductor layer 104 , a second source electrode 106 , and a second drain electrode 108 .

The second gate electrode 102 overlaps the oxide semiconductor layer 104 with the upper gate insulating pattern 146 therebetween. The second gate electrode 102 is formed of the same material as the first high voltage supply line 172a on the upper gate insulating pattern 146 on the same plane as the first high voltage supply line 172a. Accordingly, since the second gate electrode 102 and the first high voltage supply line 172a can be formed through the same mask process, the mask process can be reduced.

The oxide semiconductor layer 104 is formed on the upper buffer layer 122 to overlap the second gate electrode 102 to form a channel between the second source and second drain electrodes 106 and 108 . The oxide semiconductor layer 104 is formed of an oxide containing at least one metal selected from among Zn, Cd, Ga, In, Sn, Hf, and Zr. Since the second thin film transistor 100 including the oxide semiconductor layer 104 has higher charge mobility and lower leakage current characteristics than the first thin film transistor 150 including the polycrystalline semiconductor layer 154, it is turned on. It is preferable to apply to switching and driving thin film transistors (ST, DT) that maintain a short on time and a long off time.

The upper interlayer insulating film 124 and the upper buffer layer 122 adjacent to the upper and lower portions of the oxide semiconductor layer 104 are formed of an inorganic film having a lower content of hydrogen particles than the lower interlayer insulating films 116 and 118 . For example, the upper interlayer insulating film 124 and the upper buffer layer 122 are formed of silicon oxide (SiOx), and the lower interlayer insulating films 116 and 118 are formed of silicon nitride (SiNx). Accordingly, diffusion of hydrogen in the lower interlayer insulating films 116 and 118 and hydrogen in the polycrystalline semiconductor layer 154 into the oxide semiconductor layer 104 during the heat treatment process of the oxide semiconductor layer 104 can be prevented.

The second source and second drain electrodes 106 and 108 are formed of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), It may be a single layer or multiple layers made of any one of neodymium (Nd) and copper (Cu) or an alloy thereof, but is not limited thereto.

The second source electrode 106 is connected to the source region of the oxide semiconductor layer 104 through the second source contact hole 110S passing through the upper interlayer insulating film 124, and the second drain electrode 108 is connected to the upper interlayer interlayer. It is connected to the drain region of the oxide semiconductor layer 104 through the second drain contact hole 110D passing through the insulating layer 124 . The second source and second drain electrodes 106 and 108 are formed to face each other with the channel region of the oxide semiconductor layer 104 therebetween.

As shown in FIG. 7 , the storage capacitor Cst 180 is formed by overlapping the lower storage electrode 182 and the upper storage electrode 184 with the first lower interlayer insulating layer 116 interposed therebetween.

The storage lower electrode 182 is connected to either one of the second gate electrode 102 of the driving transistor DT and the second source electrode 106 of the driving transistor DT. The storage lower electrode 182 is positioned on the lower gate insulating layer 114 and is formed on the same layer as the first gate electrode 152 and made of the same material.

The storage upper electrode 184 is connected to the other one of the second gate electrode 102 of the driving transistor DT and the second source electrode 106 of the driving transistor DT through the storage supply line 186 . The storage upper electrode 184 is positioned on the first lower interlayer insulating layer 116 . The storage upper electrode 184 is formed of the same material on the same layer as the light blocking layer 178 and the first low potential supply line 162a. The storage upper electrode 184 is exposed through the storage contact hole 188 penetrating the second lower interlayer insulating film 118, the upper buffer layer 122, and the upper interlayer insulating film 124, and is connected to the storage supply line 186. do. Meanwhile, the storage upper electrode 184 is spaced apart from the light blocking layer 178 as shown in FIG. 7 , but may be integrally connected to each other.

The first lower interlayer insulating layer 116 disposed between the storage lower electrode 182 and the storage upper electrode 184 is formed of an inorganic insulating material such as SiOx or SiNx. The first lower interlayer insulating film 116 is preferably formed of SiNx having a higher dielectric constant than SiOx. Accordingly, the storage lower electrode 182 and the storage upper electrode 184 are overlapped with the first lower interlayer insulating layer 116 formed of SiNx having a high permittivity interposed therebetween, so that the capacitance value of the storage capacitor Cst is proportional to the permittivity. will increase

The light emitting element 130 includes an anode electrode 132 connected to the second source electrode 106 of the second thin film transistor 150, at least one light emitting stack 134 formed on the anode electrode 132, A cathode electrode 136 formed on the light emitting stack 134 is provided.

The anode electrode 132 is connected to the exposed pixel connection electrode 142 through the second pixel contact hole 144 penetrating the second planarization layer 128 . Here, the pixel connection electrode 142 is connected to the exposed second source electrode 106 through the first pixel contact hole 120 penetrating the passivation layer 166 and the first planarization layer 126 .

The anode electrode 132 is formed in a multilayer structure including a transparent conductive film and an opaque conductive film having high reflective efficiency. The transparent conductive film is made of a material having a relatively large work function value such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO), and the opaque conductive film is Al, Ag, Cu, Pb, Mo, It consists of a single-layer or multi-layer structure containing Ti or alloys thereof. For example, the anode electrode 132 has a structure in which a transparent conductive film, an opaque conductive film, and a transparent conductive film are sequentially stacked, or a transparent conductive film and an opaque conductive film are sequentially stacked. The anode electrode 132 is formed by the second planarization layer 128 so as to overlap not only the emission area provided by the bank 138 but also the circuit area where the first and second transistors 100 and 150 and the storage capacitor 180 (Cst) are disposed. By being placed on the light emitting area is increased.

The light emitting stack 134 is formed by stacking a hole related layer, an organic light emitting layer, and an electron related layer on the anode electrode 132 in the order or reverse order. In addition, the light emitting stack 134 may include first and second light emitting stacks facing each other with a charge generating layer interposed therebetween. In this case, one organic light emitting layer of the first and second light emitting stacks generates blue light, and the other organic light emitting layer of the first and second light emitting stacks generates yellow-green light, thereby generating the first and second light emitting stacks. White light is generated through Since the white light generated by the light emitting stack 134 is incident on a color filter (not shown) positioned above the light emitting stack 134, a color image can be implemented. In addition, a color image may be implemented by generating color light corresponding to each sub-pixel in each light emitting stack 134 without a separate color filter. That is, the emission stack 134 of the red (R) sub-pixel emits red light, the emission stack 134 of the green (G) sub-pixel emits green light, and the emission stack 134 of the blue (B) sub-pixel emits blue light. You may.

The bank 138 is formed to expose the anode electrode 132. The bank 138 may be formed of an opaque material (eg, black) to prevent light interference between adjacent sub-pixels. In this case, the bank 138 includes a light blocking material made of at least one of color pigments, organic black, and carbon.

The cathode electrode 136 is formed on the upper and side surfaces of the light emitting stack 134 to face the anode electrode 132 with the light emitting stack 134 interposed therebetween. The cathode electrode 136 is made of a transparent conductive layer such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO) when applied to a top emission type organic light emitting display.

This cathode electrode 136 is electrically connected to the low voltage supply line 162. The low voltage supply line 162 includes first and second low potential supply lines 162a and 162b crossing each other, as shown in FIGS. 5B and 6 . As shown in FIG. 7 , the first low potential supply line 162a is formed of the same material as the upper storage electrode 184 on the first lower interlayer insulating film 116 which is the same layer as the upper storage electrode 184. . The second low potential supply line 162b is formed of the same material as the pixel connection electrode 142 on the first planarization layer 126 which is the same layer as the pixel connection electrode 142 . The second low potential supply line 162b is formed to pass through the second lower interlayer insulating film 118, the upper buffer layer 122, the upper interlayer insulating film 124, the protective film 166, and the first planarization layer 126. It is electrically connected to the first low potential supply line 162a exposed through the 1 line contact hole 164.

The high voltage supply lines 172 supplying the high potential voltage VDD higher than the low potential voltage VSS supplied through the low voltage supply line 162 have first crossovers as shown in FIGS. 5B and 6 . and second high potential supply lines 172a and 172b. As shown in FIG. 7 , the first high potential supply line 172a is formed of the same material as the second gate electrode 102 on the upper gate insulating pattern 146 on the same layer as the second gate electrode 102 . do. The second high potential supply line 172b is formed of the same material as the second source and drain electrodes 106 and 108 on the upper interlayer insulating film 124 that is the same layer as the second source and drain electrodes 106 and 108 . The second high potential supply line 172b is electrically connected to the exposed first high potential supply line 172a through the second line contact hole 174 formed to pass through the upper interlayer insulating film 124 .

In this way, since the high potential supply line 172 and the low potential supply line 162 are formed in a mesh shape, the second high potential supply line 172b and the second low potential supply line 162b disposed in the vertical direction are provided with a protective film ( 166) and the first planarization layer 126 interposed therebetween. In this case, the protective film 166 may prevent the second high potential supply line 172b and the second low potential supply line 162b from being shorted through a pin hole formed in the first planarization layer 126. The first planarization layer 126 is disposed so as to contact the first planarization layer 126 on one of the lower and upper portions. This will be described in conjunction with FIGS. 8A and 8B.

As shown in FIG. 8A , pin holes 168 are generated in the first planarization layer 126 due to microbubbles generated when the first planarization layer 126 is applied on the second high potential supply line 172b. When the second low potential supply line 162b is formed on the first planarization layer 126 having the pin hole 168, the second low potential supply line 162b fills the pin hole 168 while the second low potential supply line 162b fills the second low potential supply line 162b. The potential supply line 162b and the second high-potential supply line 172b are shorted, resulting in deterioration in reliability such as occurrence of product fire.

On the other hand, as shown in FIG. 8B , a protective film 166 made of an inorganic insulating material is formed on the second high-potential supply line 172b. When the first planarization layer 126 is applied on the protective film 166, pin holes 168 are generated in the first planarization layer 126 due to microbubbles generated during application. When the second low potential supply line 162b is formed on the first planarization layer 126 having the pin hole 168, the second low voltage supply line 162b fills the pin hole 168. At this time, even if the second low voltage supply line 162b fills the pin hole 168, the second low voltage supply line 162b and the second high voltage supply line 172b are insulated from each other by the passivation layer 166. Accordingly, the present invention provides the second low potential supply line 162b and the second high potential supply line 162b and the second high potential supply line 162b by the protective film 166 disposed between the second high potential supply line 162b. It is possible to prevent the line 172b from being shorted.

A signal link 176 connected to at least one of the low-potential supply line 162, the high-potential supply line 172, the data line DL, the scan line SL, and the emission control line EL is shown in FIG. As shown in FIG. 7, the first and second openings 192 and 194 are disposed to cross the bending area BA. The first opening 192 exposes a side surface of the upper interlayer insulating layer 124 and a top surface of the upper buffer layer 122 . The first opening 192 is formed to have the same depth d1 as at least one of the second source contact hole 110S and the second drain contact hole 110D. The second opening 194 exposes side surfaces of the multi-buffer layer 140, the lower buffer layer 112, the lower gate insulating layer 114, the first and second lower interlayer insulating layers 116 and 118, and the upper buffer layer 122, respectively. is formed The second opening 194 is formed to have a deeper depth d2 than at least one of the first source contact hole 160S and the first drain contact hole 160D, or to have the same depth d2. is formed Accordingly, the multi-buffer layer 140, the lower buffer layer 112, the lower gate insulating layer 114, and the first and second lower interlayer insulating layers 116 and 118 are formed in the bending area BA by the first and second openings 192 and 194. , the upper buffer layer 122 and the upper interlayer insulating film 124 are removed. That is, since the plurality of inorganic insulating layers 140 , 112 , 114 , 116 , 118 , 122 , and 124 that cause cracks are removed from the bending area BA, the substrate 101 can be easily bent without cracks.

As shown in FIG. 7 , the signal link 176 disposed in the bending area BA may be formed together with the pixel connection electrode 142 through the same mask process as the pixel connection electrode 142 . In this case, the signal link 176 is made of the same material as the pixel connection electrode 142 and is formed on the same plane, that is, on the first planarization layer 126 and the substrate 101 . A second planarization layer 128 is disposed on the signal link 176 to cover the first planarization layer 126 and the signal link 176 formed on the substrate 101, or without the second planarization layer 128. An encapsulation film or an inorganic encapsulation layer of an encapsulation stack made of a combination of inorganic and organic encapsulation layers is disposed.

In addition, the signal link 176 may be formed together with the source and drain electrodes 106, 156, 108, and 158 through the same mask process as the source and drain electrodes 106, 156, 108, and 158, as shown in FIGS. 9A and 9B. In this case, the signal link 176 is formed of the same material as the source and drain electrodes 106, 156, 108, and 158 on the same plane, that is, on the upper interlayer insulating film 124, and is formed on the substrate 101 so as to contact the substrate 101. . At this time, the signal link 176 is formed on the side surface of the upper interlayer insulating film 124 exposed by the first opening 192 and the top surface of the upper buffer layer 122 and exposed by the second opening 194. Since it is formed on the side surfaces of the multi-buffer layer 140, the lower buffer layer 112, the lower gate insulating film 114, the first and second lower interlayer insulating films 116 and 118, and the upper buffer layer 122, it is formed in a stepped shape. At least one of the first and second planarization layers 126 and 128 is disposed on the signal link 176 to cover the signal link 176 formed in a stepped shape, or a sealing film without the first and second planarization layers 126 and 128. Alternatively, an inorganic encapsulation layer of an encapsulation stack composed of a combination of inorganic and organic encapsulation layers is disposed.

In addition, the signal link 176 may be disposed on the multi-buffer layer 140 as shown in FIGS. 9A and 9B. At this time, the multi-buffer layer 140 disposed between the signal links 176 is removed to facilitate bending without cracking, so that a trench 196 exposing the substrate 101 is formed between the signal links 176. do.

The trench 196 shown in FIG. 9A is formed to pass through a portion of the substrate 101 and the multi-buffer layer 140 between the signal links 176 . A second planarization layer 128 is disposed over these signal links 176 . The trench 196 shown in FIG. 9B is formed to pass through the passivation layer 166 between the signal links 176 , the multi-buffer layer 140 and a portion of the substrate 101 . A passivation layer 166 and first and second planarization layers 126 and 128 are disposed on the signal links 176 . Meanwhile, at least one moisture blocking hole (not shown) passing through the first and second planarization layers 126 and 128 may be disposed in the bending area BA. The moisture blocking hole is formed between the signal links 176 and at least one of the upper portions of the signal links 176 . The moisture blocking hole prevents moisture from outside from penetrating into the active area AA through at least one of the first and second planarization layers 126 and 128 disposed on the signal link 176 . In addition, an inspection line (not shown) used in the inspection process is formed in the bending area BA in the same structure as any one of the signal links 176 shown in FIGS. 7, 9A, and 9B.

As described above, the multi-buffer layer 140, the lower buffer layer 112, the lower gate insulating film 114, and the first and second lower interlayer insulating films 116 and 118 are formed in the bending area BA by the first and second openings 192 and 194. , the upper buffer layer 122 and the upper interlayer insulating film 124 are removed. That is, since the plurality of inorganic insulating layers 140 , 112 , 114 , 116 , 118 , 122 , and 124 that cause cracks are removed from the bending area BA, the substrate 101 can be easily bent without cracks occurring in the bending area BA.

10A to 10N are cross-sectional views illustrating a method of manufacturing the organic light emitting diode display shown in FIG. 7 .

Referring to FIG. 10A , a multi-buffer layer 140 , a lower buffer layer 112 , and a polycrystalline semiconductor layer 154 are sequentially formed on a substrate 101 .

Specifically, the multi-buffer layer 140 is formed by alternately stacking SiOx and SiNx on the substrate 101 at least once. Then, the lower buffer layer 112 is formed by depositing SiOx or SiNx on the multi-buffer layer 140 . Then, an amorphous silicon thin film is formed on the substrate 101 on which the lower buffer layer 112 is formed through a method such as low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD). Then, it is formed into a polycrystalline silicon thin film by crystallizing the amorphous silicon thin film. Then, the polycrystalline semiconductor layer 154 is formed by patterning the polycrystalline silicon thin film through a photolithography process and an etching process using a first mask.

Referring to FIG. 10B , a gate insulating film 114 is formed on the substrate 101 on which the polycrystalline semiconductor layer 154 is formed, and the first gate electrode 152 and the storage lower electrode 182 are formed on the gate insulating film 114. ) is formed.

Specifically, the gate insulating film 114 is formed by depositing an inorganic insulating material such as SiNx or SiOx on the entire surface of the substrate 101 on which the polycrystalline semiconductor layer 154 is formed. Then, after the first conductive layer is deposited on the entire surface of the gate insulating film 114, the first conductive layer is patterned through a photolithography process using a second mask and an etching process, thereby forming the first gate electrode 152 and the storage lower electrode. (182) is formed. Then, impurities are doped into the polycrystalline semiconductor layer 154 through a doping process using the first gate electrode 152 as a mask, thereby providing source and drain regions that do not overlap with the first gate electrode 152, and the first gate electrode. A channel region overlapping with (152) is formed.

Referring to FIG. 10C , at least one layer of a first lower interlayer insulating film 116 is formed on the substrate 101 on which the first gate electrode 152 and the storage lower electrode 182 are formed, and the first lower interlayer insulating film is formed. On 116, the storage upper electrode 184, the light blocking layer 178, and the first low potential supply line 162a are formed.

Specifically, an inorganic insulating material such as SiNx or SiOx is deposited on the entire surface of the substrate 101 on which the first gate electrode 152 and the storage lower electrode 182 are formed, thereby forming the first lower interlayer insulating layer 116 . Then, after the second conductive layer is deposited on the entire surface of the first lower interlayer insulating film 116, the second conductive layer is patterned through a photolithography process using a third mask and an etching process, thereby blocking the storage upper electrode 184 and light. A layer 178 and a first low potential supply line 162a are formed.

Referring to FIG. 10D , on the substrate 101 on which the storage upper electrode 184, the light blocking layer 178, and the first low potential supply line 162a are formed, at least one layer of the second lower interlayer insulating film 118 and the upper The buffer layer 122 is sequentially formed, and the oxide semiconductor layer 104 is formed on the upper buffer layer 122 .

Specifically, an inorganic insulating material such as SiNx or SiOx is entirely deposited on the substrate 101 on which the storage upper electrode 184, the light blocking layer 178, and the first low potential supply line 162a are formed, thereby forming a second lower interlayer insulating film. (118) is formed. Then, the upper buffer layer 122 is formed by depositing an inorganic insulating material such as SiNx or SiOx on the entire surface of the first lower interlayer insulating film 118 . Then, the oxide semiconductor layer 104 overlaps with the light blocking layer 178 by depositing the entire surface of the oxide semiconductor layer 104 on the upper buffer layer 122 and then patterning through a photolithography process and an etching process using a fourth mask. is formed

Referring to FIG. 10E , an upper gate insulating pattern 146 , a second gate electrode 102 , and a first high potential supply line 172a are formed on the substrate 101 on which the oxide semiconductor layer 104 is formed.

Specifically, an upper gate insulating film is formed on the substrate 101 on which the oxide semiconductor layer 104 is formed, and a third conductive layer is formed thereon by a deposition method such as sputtering. An inorganic insulating material such as SiOx or SiNx is used as the upper gate insulating layer. As the third conductive layer, a metal material such as Mo, Ti, Cu, AlNd, Al, Cr, or an alloy thereof is used as a single layer or as a multilayer structure using these materials. Then, each of the second gate electrode 102 and the first high-potential supply line 172a and each of them are respectively patterned by simultaneously patterning the third conductive layer and the upper gate insulating film through a photolithography process and an etching process using a fifth mask. An upper gate insulating pattern 146 is formed under the same pattern. At this time, when the upper gate insulating film is dry etched, the oxide semiconductor layer 104 that does not overlap with the second gate electrode 102 is exposed by plasma, and oxygen in the oxide semiconductor layer 104 exposed by the plasma is a plasma gas. reacts with and is eliminated. Accordingly, the oxide semiconductor layer 104 that does not overlap with the second gate electrode 102 is conductive and formed as source and drain regions.

Referring to FIG. 10F , a first opening 192 and first and second openings 192 are formed on the substrate 101 on which the upper gate insulating pattern 146, the second gate electrode 102, and the first high potential supply line 172a are formed. An upper interlayer insulating layer having 2 source contact holes 160S and 110S, first and second drain contact holes 160D and 110D, a first storage contact hole 188, and first and second line contact holes 164 and 174 ( 124) is formed.

Specifically, an inorganic insulating material such as SiNx or SiOx is deposited over the substrate 101 on which the upper gate insulating pattern 146, the second gate electrode 102, and the first high potential supply line 172 are formed, so that the upper interlayer interlayer An insulating film 124 is formed. Then, the upper interlayer insulating layer 124 is patterned through a photolithography process and an etching process using a sixth mask, thereby forming first and second source contact holes 160S and 110S, first and second drain contact holes 160D, 110D), the first storage contact hole 188, and the first and second line contact holes 164 and 174 are formed, and the upper interlayer insulating layer 124 of the bending area BA is removed, thereby forming the first opening 192. do. In this case, the first and second source contact holes 160S and 110S, the first and second drain contact holes 160D and 110D, the first storage contact hole 188, and the first and second line contact holes 164 and 174 ) and the first opening 192 are formed to pass through the upper interlayer insulating layer 124 .

Referring to FIG. 10G , a second opening 194 is formed in the bending area BA on the substrate 101 on which the upper interlayer insulating film 124 is formed, and the first source contact hole 160S and the first drain contact hole ( 160D), the first storage contact hole 188, the gate insulating layer 114 in the second line contact hole 174, the first and second lower interlayer insulating layers 116 and 118, and the upper buffer layer 122 are removed.

Specifically, on the substrate 101 on which the upper interlayer insulating film 124 is formed, the first source contact hole 160S and the first drain are formed through an etching process using a photoresist pattern formed by a photolithography process using a seventh mask as a mask. The gate insulating layer 114, the first and second lower interlayer insulating layers 116 and 118, and the upper buffer layer 122 in the contact hole 160D, the first storage contact hole 188, and the second line contact hole 174 are removed. . At the same time, the multi-buffer layer 140, the lower buffer layer 112, the gate insulating film 114, the first and second lower interlayer insulating films 116 and 118, and the upper buffer layer 122 of the bending area BA are removed, thereby opening the second opening ( 194) is formed. Meanwhile, when the second opening 194 is formed, a portion of the substrate 101 may also be removed.

Referring to FIG. 10H , first and second source electrodes 156 and 106 , first and second drain electrodes 158 and 108 , a storage supply line 186 and a second opening 194 are formed on the substrate 101 . 2 high potential supply lines 172b are formed.

Specifically, a fourth conductive layer such as Mo, Ti, Cu, AlNd, Al, Cr or an alloy thereof is deposited on the entire surface of the substrate 101 on which the second opening 194 is formed. Then, the fourth conductive layer is patterned through a photolithography process and an etching process using an eighth mask, thereby forming the first and second source electrodes 156 and 106 , the first and second drain electrodes 158 and 108 , and the storage supply line 186 . ) and the second high potential supply line 172b are formed.

Referring to FIG. 10I, the substrate 101 on which the first and second source electrodes 156 and 106, the first and second drain electrodes 158 and 108, the storage supply line 186, and the second high-potential supply line 172b are formed. A passivation layer 166 having a first pixel contact hole 120 is formed thereon.

Specifically, SiNx is formed on the substrate 101 on which the first and second source electrodes 156 and 106, the first and second drain electrodes 158 and 108, the storage supply line 186, and the second high-potential supply line 172b are formed. Alternatively, the protective layer 166 is formed by depositing an inorganic insulating material such as SiOx on the entire surface. Then, the passivation layer 166 is patterned through a photolithography process using a ninth mask, thereby forming a first pixel contact hole 120 penetrating the passivation layer 166 and also forming a first line contact hole 164 in a first line contact hole 164. It is formed to pass through the planarization layer 126 .

Referring to FIG. 10J , a first planarization layer 126 is formed on the substrate 101 on which the protective film 166 is formed.

Specifically, the first planarization layer 126 is formed by coating an organic insulating material such as an acrylic resin on the entire surface of the substrate 101 on which the protective film 166 is formed. Then, the first planarization layer 126 is patterned through a photolithography process using a tenth mask, so that the first pixel contact hole 120 and the first line contact hole 164 pass through the first planarization layer 126. is formed to

Referring to FIG. 10K , a signal link between a pixel connection electrode 142 and a second low potential supply line 162b is formed on a substrate 101 on which a first planarization layer 126 having a first pixel contact hole 120 is formed. (176) is formed.

Specifically, a fifth conductive layer such as Mo, Ti, Cu, AlNd, Al, Cr or an alloy thereof is formed on the substrate 101 on which the first planarization layer 126 having the first pixel contact hole 120 is formed. deposited on the front Then, the fifth conductive layer is patterned through a photolithography process and an etching process using an eleventh mask, thereby forming the pixel connection electrode 142, the second low potential supply line 162b, and the signal link 176.

Referring to FIG. 10L, a second planarization layer having a second pixel contact hole 144 on the substrate 101 on which the signal link 176, the pixel connection electrode 142, and the second low potential supply line 162b are formed. (128) is formed.

Specifically, an organic insulating material such as acrylic resin is deposited on the entire surface of the substrate 101 on which the signal link 176, the pixel connection electrode 142, and the second low potential supply line 162b are formed, thereby forming the second planarization layer 128. ) is formed. Then, the second planarization layer 128 is patterned through a photolithography process using a twelfth mask to form a second pixel contact hole 144 .

Referring to FIG. 10M , an anode electrode 132 is formed on the substrate 101 on which the second planarization layer 128 having the second pixel contact hole 144 is formed.

Specifically, a fifth conductive layer is entirely deposited on the substrate 101 on which the second planarization layer 128 having the second pixel contact hole 144 is formed. A transparent conductive film and an opaque conductive film are used as the fifth conductive layer. Then, the anode electrode 132 is formed by patterning the sixth conductive layer through a photolithography process and an etching process using a thirteenth mask.

Referring to FIG. 10N , a bank 138, an organic light emitting stack 134, and a cathode electrode 136 are sequentially formed on the substrate 101 on which the anode electrode 132 is formed.

Specifically, the bank 138 is formed by coating the entire surface of a photoresist film for banks on the substrate 101 on which the anode electrode 132 is formed, and then patterning the photoresist film for banks through a photolithography process using a 14th mask. Then, the light emitting stack 134 and the cathode electrode 136 are sequentially formed in the display area AA except for the non-display area NA through a deposition process using a shadow mask.

As described above, in the present invention, the first opening 192 of the bending region and the second source and drain contact holes 110S and 110D are formed through the same mask process, and the second opening 194 and , the first source and drain contact holes 160S and 160D are formed through the same single mask process, and the first source and first drain electrodes 156 and 158 and the second source and second drain electrodes 106 and 108 are the same. Since the storage contact hole 188 is formed through one mask process, and the storage contact hole 188 is formed through the same mask process as the first source and drain contact holes 160S and 160D, at least four mask processes can be reduced compared to the related art. Accordingly, the organic light emitting diode display according to the present invention can reduce the number of mask processes by at least four times compared to the prior art, thereby simplifying the structure and manufacturing process, thereby improving productivity.

The above description is merely illustrative of the present invention, and various modifications may be made by those skilled in the art without departing from the technical spirit of the present invention. Therefore, the embodiments disclosed in the specification of the present invention are not intended to limit the present invention. The scope of the present invention should be construed by the claims below, and all techniques within the scope equivalent thereto should be construed as being included in the scope of the present invention.

102, 152: gate electrode 104: oxide semiconductor layer
106,156: source electrode 108,110: drain electrode
130: light emitting element 154: polycrystalline semiconductor layer
162: low potential supply line 172: high potential supply line
176, LK: signal link 180: storage capacitor
192,194: opening

Claims (12)

a flexible substrate having a display area and a non-display area surrounding the display area; and
including a plurality of pixels arranged in the display area;
Each of the plurality of pixels includes a first transistor and a second transistor,
the non-display area includes a gate driver positioned on a first side of the display area and a bending portion positioned on a second side of the display area;
The first transistor includes a first semiconductor layer, a first gate electrode, a first source electrode, and a first drain electrode,
The second transistor includes a second semiconductor layer, a second gate electrode, a second source electrode, and a second drain electrode,
A first lower interlayer insulating film, a second lower interlayer insulating film, and an upper buffer layer are disposed between the first gate electrode and the second semiconductor layer,
The second gate electrode is disposed on the second semiconductor layer,
A first planarization layer is disposed on the first and second thin film transistors, and a second planarization layer is disposed on the first planarization layer.
The first planarization layer and the second planarization layer are disposed to extend into the bending portion,
In the bending portion, the lower surface of the first planarization layer and the upper surface of the flexible substrate are at least partially in contact with each other, and the upper surface of the first planarization layer and the lower surface of the second planarization layer are at least partially in contact with each other. According to claim 1,
The first semiconductor layer includes a polycrystalline semiconductor layer. According to claim 1,
The second semiconductor layer includes an oxide semiconductor layer. According to claim 1,
The first lower interlayer insulating layer, the second lower interlayer insulating layer, and the upper buffer layer include silicon nitride or silicon oxide. According to claim 1,
The display device further includes a light blocking layer disposed between the second semiconductor layer and the first lower interlayer insulating layer. According to claim 5,
The display device further comprising a first gate insulating layer disposed between the first semiconductor layer and the first gate electrode. According to claim 6,
The display device further includes a storage lower electrode disposed on the first gate insulating layer and a storage upper electrode disposed on the first lower interlayer insulating layer. According to claim 7,
The light blocking layer and the storage upper electrode are formed of the same material on the same plane. According to claim 1,
In the display area, a pixel connection electrode connected to the second source electrode through a hole in the first planarization layer and connected to an anode electrode of a light emitting device through a hole in the second planarization layer. According to claim 9,
The bending portion further includes a link wire,
The link wire connects a signal pad in the non-display area and a signal line in the display area. According to claim 10,
The link wire and the pixel connection electrode are formed of the same material on the same plane. According to claim 1,
The transistor included in the gate driver includes a polycrystalline semiconductor layer.

Images