KR20230017509A - Method of operating NAND flash memory device - Google Patents

Abstract

Provided in one aspect of the present invention is a method for operating a NAND flash memory device. The method for operating a NAND flash memory device, which includes: a plurality of NAND strings, each having a plurality of memory cells connected in series; a plurality of bit lines, each connected to the plurality of NAND strings; and a plurality of word lines connected to the gates of the memory cells in each row of the plurality of NAND strings, comprises at least a two-bit multi-bit program step of repeatedly carrying out a program operation and a verification operation while increasing a program voltage for selected memory cells connected to a selected word line among the plurality of word lines, wherein each verification operation is performed by applying different bit line voltages to at least a portion of the plurality of bit lines and applying a verification voltage to the selected word line. The method for operating a NAND flash memory device can significantly reduce the overall operation time by simplifying the verification operations.

Description

Method of operating NAND flash memory device {Method of operating NAND flash memory device}

The present invention relates to a semiconductor device, and more particularly, to a method of operating a NAND flash memory device.

A non-volatile memory device, for example, a flash memory, not only has excellent data retention, but also has advantages of low power consumption and resistance to external shocks compared to hard disks and the like. In particular, a flash memory device of a NOR structure is used for code storage in that high-speed random access is possible, and a flash memory device of a NAND structure is used for data storage in that a high degree of integration and a page operation are possible. generally used for

Recently, such a NAND flash memory device has been designed so that one memory cell is operated as a multi-bit of 2-bit or more. For example, FIG. 1 shows an erase state (E) and three program states (P1, P2, P3) when each memory cell operates with 2 bits. As shown in FIG. 2 , such a 2-bit program may be performed using an incremental step pulse program (ISPP) method. In this case, the program operation is performed while increasing the program voltage, and after each program operation, three verification voltages (V _vf1 , V _vf2 , and V _vf3 ) are used to verify the three program states. ) step.

Therefore, when using this programming method, three verification steps must be performed for each program operation during the ISPP program in order to store 2-bit data, which increases the program time. Furthermore, since seven verification steps must be performed to store 3-bit data, the number of verification steps increases significantly as the number of data bits increases.

An object of the present invention is to provide a method of operating a NAND flash memory device capable of reducing the overall program time by reducing the time for verifying data when programming 2-bit or more data. However, these tasks are illustrative, and the scope of the present invention is not limited thereby.

In order to solve the above problems, a method of operating a NAND flash memory device according to an aspect of the present invention includes a plurality of NAND strings each including a plurality of memory cells connected in series with each other, and a plurality of NAND strings respectively connected to the plurality of NAND strings. A method of operating a NAND flash memory device including bit lines of and a plurality of word lines connected to gates of memory cells of each row of the plurality of NAND strings, wherein a selected memory connected to a selected word line among the plurality of word lines and at least a 2-bit multi-bit program step of repeating a program operation and a verify operation while increasing a program voltage to cells, wherein each verify operation applies different bit line voltages to at least some of the plurality of bit lines. and applying a verification voltage to the selected word line.

According to the operating method of the NAND flash memory device, in the multi-bit programming step, 2-bit data is written to each memory cell, and in the multi-bit programming step, only one verification operation is performed for each program operation. can do.

According to the method of operating the NAND flash memory device, each verification operation may be performed by applying different bit line voltages to at least three bit lines among the plurality of bit lines.

According to the operating method of the NAND flash memory device, in each verification operation, the verification voltage may be lower than a threshold voltage of the lowest programmed state of the selected memory cells.

According to the method of operating the NAND flash memory device, the plurality of bit lines include a first bit line, a second bit line, and a third bit line,

the selected memory cells include a first memory cell connected to the first bit line, a second memory cell connected to the second bit line, and a third memory cell connected to the third bit line;

The target program states of the first memory cell, the second memory cell, and the third memory cell are a first program state, a second program state, and a third program state, respectively (provided that the first program state < the second program). state < third program state), in each verification operation, a first bit line voltage is applied to the first bit line, a second bit line voltage is applied to the second bit line, and a third bit line voltage is applied to the third bit line. It may be performed by applying a bit line voltage (where the first bit line voltage < the second bit line voltage < the third bit line voltage).

According to the method of operating the NAND flash memory device, in each verification operation, a read voltage capable of turning on memory cells connected to the non-selected word lines is applied to unselected word lines among the plurality of word lines. It can be.

A method of operating a NAND flash memory device according to another aspect of the present invention for solving the above problems is a plurality of NAND strings each including a plurality of memory cells connected in series with each other, a plurality of NAND strings each connected to the plurality of NAND strings A method of operating a NAND flash memory device including bit lines of and a plurality of word lines connected to gates of memory cells of each row of the plurality of NAND strings, wherein a selected memory connected to a selected word line among the plurality of word lines a first program operation step of applying a first program voltage to cells; applying different bit line voltages to at least some of the plurality of bit lines; and applying a first verify voltage to the selected word line. - A first verification operation step for multi-bit verification of a bit, and a second program applying a second program voltage higher than the first program voltage to selected memory cells connected to a selected word line among the plurality of word lines an operating step for multi-bit verification of at least 2 bits, wherein the different bit line voltages are applied to the at least some of the plurality of bit lines, and the first verification voltage is applied to the selected word line; 2 verification operation steps may be included.

According to the operating method of the NAND flash memory device according to an embodiment of the present invention made as described above, the entire operation time can be significantly reduced by simplifying the verification operation when programming multi-bit data of 2 bits or more.

Of course, these effects are exemplary, and the scope of the present invention is not limited by these effects.

1 and 2 are graphs showing a method of programming 2-bit data in a typical NAND flash memory device.
3 is a block diagram showing a NAND flash memory device according to an embodiment of the present invention.
FIG. 4 is a circuit diagram schematically showing a memory cell array in the NAND flash memory device of FIG. 3 .
5 and 6 are graphs showing a program operation of a NAND flash memory device according to an embodiment of the present invention.
7 is a graph showing a program operation in a program operation of a NAND flash memory device according to an embodiment of the present invention.
8 is a graph showing a verification operation in a program operation of a NAND flash memory device according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various different forms. It is provided to fully inform you. Also, for convenience of explanation, the size of at least some components may be exaggerated or reduced in the drawings. Like symbols in the drawings refer to like elements.

Unless defined otherwise, all terms used herein are used with the same meaning as commonly understood by one of ordinary skill in the art. In the drawings, the sizes of layers and regions are exaggerated for illustrative purposes and are therefore provided to illustrate the general structures of the present invention.

Like reference numerals denote like elements. It will be understood that when one element, such as a layer, region, or substrate, is referred to as being on another element, it may be directly on top of or intervening elements may also exist. On the other hand, when referring to a component being “directly on” another component, it is understood that there are no intervening components present.

3 is a block diagram showing a NAND flash memory device 100 according to an embodiment of the present invention, and FIG. 4 is a circuit diagram schematically showing a memory cell array in the NAND flash memory device of FIG. 3 .

Referring to FIGS. 3 and 4 together, the NAND flash memory device 100 includes a memory cell array 110, an X-buffer/row decoder 120, a Y-buffer/column decoder 130, and a control logic 140. can include

The memory cell array 110 may include an array arrangement of memory cells MC for data storage. For example, the memory cells MC may be arranged in a matrix or further divided into blocks.

The memory cell array 110 in the NAND flash memory device 100 may include a plurality of NAND strings NS. Each NAND string NS may include a plurality of memory cells MC connected in series with each other. Furthermore, each NAND string NS may include a string select transistor SST on one side of the plurality of memory cells MC and a ground select transistor GST on the other side.

The plurality of bit lines BL ₀ to BL _N may be connected to one end of the NAND strings NS, and the common source line CSL may be connected to the other end of the NAND strings NS. For example, the bit lines BL ₀ to BL _N may be connected to the drain terminal of the string select transistor SST, and the common source line CSL may be connected to the source terminal of the ground select transistor GST.

The string select line SSL may be connected to gates of the string select transistors SST to control operations of the string select transistors SST. The ground select line GSL may be connected to gates of the ground select transistors GST to control operations of the ground select transistors GST. The plurality of word lines WL ₀ to WL _m may be connected to gates of the memory cells MC arranged in each row of the NAND strings NS to control the operation of the memory cells MC.

The memory cell array 110 may be combined with the X-buffer/row decoder 120 and the Y-buffer/column decoder 130 . For example, word lines WL ₀ to WL _m of the memory cell array 110 may be connected to the X-buffer/row decoder 120 . Bit lines BL ₀ to BL _N of the memory cell array 110 may be connected to the Y-buffer/column decoder 130 . Control logic 140 may be coupled to X-buffer/row decoder 120 and Y-buffer/column decoder 130 to control them.

For example, looking at the transfer process of the address signal, the control logic 140 transfers the row address signal to the X-buffer/row decoder 120, and the X-buffer/row decoder 120 decodes these signals to obtain A row address signal may be transmitted to the memory cell array 110 . In addition, the control logic 140 transfers the column address signal to the Y-buffer/column decoder 130, and the Y-buffer/column decoder 130 decodes the signal to form bit lines BL ₀ to BL _N A column address signal may be transferred to the memory cell array 110 through

5 and 6 are graphs showing a program operation of the NAND flash memory device 100 according to an embodiment of the present invention.

Referring to FIGS. 1 to 6 , a method of operating a NAND flash memory device 100 according to an embodiment of the present invention includes selected memory cells (connected to selected word lines) among word lines (WL ₀ to WL _m ). MC) may include at least a 2-bit multi-bit program step of repeating a program operation and a verify operation while increasing the program voltage. Each verification operation may be performed by applying different bit line voltages to at least some of the bit lines BL ₀ to BL _N and applying the verification voltage to a selected word line.

In a typical program method, at least three or more verification operations are required to verify data of 2-bit or more after a program operation. However, according to this embodiment, the number of verification operations can be greatly reduced by applying different bit line voltages to at least some of the bit lines BL ₀ to BL _N .

For example, as shown in FIG. 5 , according to the incremental step pulse program (ISPP) method, the first program voltage V _pgm1 is applied to a selected word among word lines WL ₀ to WL _m . After a first program operation for applying a first program operation to a line, a first verification step in which different bit line voltages are applied to at least some of the bit lines BL ₀ to BL _N and a first verification voltage V _vf1 is applied to the selected word line. action can be performed. Subsequently, after a second program operation of applying the second program voltage V _pgm2 to the selected word line among the word lines WL ₀ to WL _m , different voltages are applied to at least some of the bit lines BL ₀ to BL _N . A second verification operation may be performed in which a bit line voltage is applied and a first verification voltage (V _vf1 ) is applied to the selected word line. In this way, the program operation and the verification operation may be repeated.

When different bit line voltages are applied, current flowing through the memory cells MC may vary. For example, as the bit line voltage increases, the current flowing through the memory cells MC may increase. Accordingly, as shown in FIG. 6 , when the target program states of the memory cells MC are different, the same verification voltage V _vf1 is applied to the selected word line among the word lines WL ₀ to WL _m . Also, if the bit line voltage applied to the bit lines BL ₀ to BL _N is changed, the magnitude of the current through the memory cells MC is changed, so the program state of the memory cells MC is verified with a small number of times. it becomes possible to do

In the case of writing 2-bit data for each memory cell MC, only one verification operation can be performed for each program operation. In some embodiments, each verification operation may be performed by applying different bit line voltages to at least three of the bit lines BL ₀ to BL _N . As the program operation is repeated, the states of the memory cells MC may be sequentially changed from the erased state E to the programmed states P1, P2, and P3.

For example, in the case of writing 2-bit data, each memory cell MC can have four states, that is, an erase state (E) and three program states (P1, P2, and P3). Depending on the data state, the threshold voltage of the memory cells MC may vary. For example, the threshold voltage of the memory cell MC in the first program state P1 is greater than the threshold voltage of the memory cell MC in the erase state E, and the threshold voltage in the second program state P2 is The threshold voltage of the memory cell MC in the first programmed state P1 may be greater than the threshold voltage of the memory cell MC in the third programmed state P3 and the threshold voltage of the memory cell MC in the second programmed state P2 may be greater.

In each verify operation, the verify voltage V _vf1 may be equal to or lower than the threshold voltage of the lowest program state of the selected memory cells MC, for example, the first program state P1. Until the memory cells MC are programmed to the first program state P1, a predetermined or more current flows through the memory cells MC in the verification operation. However, when the memory cells MC reach the first program state P1 by repeating the program operation, current does not flow through the memory cells MC in the verification operation thereafter. However, even when the memory cells MC reach the first program state P1, if the bit line voltage applied to the bit lines BL ₀ to BL _N is increased, the memory cells MC current will flow. Accordingly, when different bit line voltages are applied to the bit lines BL ₀ to BL _N , as shown in FIG. 6, it is possible to distinguish the first to third program states P1, P2, and P3. It happens.

Hereinafter, a 2-bit data program operation will be exemplarily described for three bit lines BL ₀ , BL ₁ , and BL ₂ .

7 is a graph showing a program operation in the program operation of the NAND flash memory device 100 according to an embodiment of the present invention.

Referring to FIG. 7 , during a program operation, a program voltage (V _pgm ) is applied to a selected word line (WL ₁ ), and a pass voltage (V _pass ) is applied to the remaining word lines (WL ₀ , WL ₂ to WL _m ). In addition, an operating voltage Vcc may be applied to the string select line SSL, and a turn-off voltage (eg, 0V) may be applied to the ground select line GSL. 0V may be applied to bit lines for programming among the bit lines BL ₀ , BL ₁ , and BL ₂ .

Meanwhile, when it is verified that a specific memory cell MC is in the target programmed state by repetitive programming operations, in a subsequent programming step, a program prevention voltage for preventing programming is applied to the bit line to which the memory cell MC belongs, e.g. A voltage (Vcc) may be applied.

8 is a graph showing a verification operation in a program operation of the NAND flash memory device 100 according to an embodiment of the present invention.

Referring to FIG. 8 , during a verification operation, a first bit line voltage (Vbl1 ) is applied to a first bit line (BL ₀ ), and a second bit line voltage (V _bl2 ) is applied to a second bit line (BL ₁ ) _. , and the third bit line voltage V _bl3 may be applied to the third bit line BL ₂ . The verification voltage (V _vf1 ) is applied to the selected word line (WL ₁ ), and the read voltage capable of turning on the memory cells (MC) is applied to the remaining non-selected word lines (WL ₀ , WL ₂ to WL _m ) (V _read ) can be applied.

For example, the target program state of the first memory cell MC1 connected to the first bit line BL ₀ is the first program state P1, and the second memory cell MC1 connected to the second bit line BL ₁ ( The target program state of MC2 is the second program state P2, and the target program state of the third memory cell MC3 connected to the third bit line BL ₂ is set to the third program state P3. (However, P3 > P2 > P1). In this case, the third bit line voltage V _bl3 may be greater than the second bit line voltage V _bl2 , and the second bit line voltage V _bl2 may be greater than the first bit line voltage V _bl2 .

Accordingly, during the verification operation, when the first memory cell MC1 reaches the first programmed state P1, current flow is not allowed, and the second memory cell MC2 enters the second programmed state P2. When it reaches the third program state P3, the flow of current is not allowed, and the third memory cell MC3 does not allow the flow of current when it reaches the third program state P3.

Therefore, according to the verification operation described above, the first programmed state P1 of the first memory cell MC1, the second programmed state P2 of the second memory cell MC2, and the third program state P1 of the third memory cell MC3 3 The program state (P3) can be verified with one verification operation. Accordingly, the operating time of the NAND flash memory device 100 can be significantly reduced by significantly reducing the number of verification operations in the ISPP programming method.

Meanwhile, in the case of verifying data of 3-bit or more, when different bit line voltages are applied to at least 7 bit lines among the bit lines BL ₀ to BL _N , 7 program states can also be checked with one verification operation. can be distinguished at the same time. However, since the current flowing through the memory cells MC may be saturated as the bit line voltage increases, in the case of verifying data of 3 or more bits, one or more verification operations may be performed according to the number of bit line voltages. there is.

As described above, according to the method of operating the NAND flash memory device 100 according to embodiments of the present invention, in the case of a multi-bit operation of 2 bits or more, the verification time can be significantly reduced, and the NAND flash memory device ( 100) can greatly improve the operation speed.

Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

50, 100: ferroelectric memory element
52, 102: substrate
104: interlayer insulating layer
106: sacrificial layer
56, 112: ferroelectric layer
58, 114: gate insulating layer
120: semiconductor channel layer
60, 130: gate electrode layer
135: vertical structure

Claims (7)

A plurality of NAND strings each including a plurality of memory cells connected in series with each other, a plurality of bit lines respectively connected to the plurality of NAND strings, and a plurality of NAND strings connected to gates of memory cells of each row of the plurality of NAND strings. As a method of operating a NAND flash memory device including word lines,
a multi-bit program step of at least 2 bits, repeating a program operation and a verify operation while increasing a program voltage on selected memory cells connected to a selected word line among the plurality of word lines;
Each verify operation is performed by applying different bit line voltages to at least some of the plurality of bit lines and applying a verify voltage to the selected word line.
Method of operating a NAND flash memory device. According to claim 1,
In the multi-bit programming step, 2-bit data is written to each memory cell;
In the multi-bit program step, performing only one verification operation for one program operation,
Method of operating a NAND flash memory device. According to claim 2,
Each verification operation is performed by applying different bit line voltages to at least three bit lines among the plurality of bit lines.
Method of operating a NAND flash memory device. According to claim 1,
In each verification operation, the verification voltage is equal to or lower than the threshold voltage of the lowest programmed state of the selected memory cells.
Method of operating a NAND flash memory device. According to claim 1,
the plurality of bit lines include a first bit line, a second bit line, and a third bit line;
the selected memory cells include a first memory cell connected to the first bit line, a second memory cell connected to the second bit line, and a third memory cell connected to the third bit line;
The target program states of the first memory cell, the second memory cell, and the third memory cell are a first program state, a second program state, and a third program state, respectively (provided that the first program state < the second program). state < 3rd program state),
In each verification operation, a first bit line voltage is applied to the first bit line, a second bit line voltage is applied to the second bit line, and a third bit line voltage is applied to the third bit line. (However, the first bit line voltage < the second bit line voltage < the third bit line voltage),
Method of operating a NAND flash memory device. According to any one of claims 1 to 5,
In each verification operation, a read voltage capable of turning on memory cells connected to the unselected word lines is applied to unselected word lines among the plurality of word lines.
Method of operating a NAND flash memory device. A plurality of NAND strings each including a plurality of memory cells connected in series with each other, a plurality of bit lines respectively connected to the plurality of NAND strings, and a plurality of NAND strings connected to gates of memory cells of each row of the plurality of NAND strings. As a method of operating a NAND flash memory device including word lines,
a first program operation step of applying a first program voltage to selected memory cells connected to a selected word line among the plurality of word lines;
a first verification operation step for multi-bit verification of at least 2 bits, applying different bit line voltages to at least some of the plurality of bit lines and applying a first verification voltage to the selected word line;
a second program operation step of applying a second program voltage higher than the first program voltage to selected memory cells connected to a selected word line among the plurality of word lines; and
a second verification operation step for multi-bit verification of at least 2 bits, applying the different bit line voltages to the at least some of the plurality of bit lines and applying the first verification voltage to the selected word line; including,
Method of operating a NAND flash memory device.

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