KR20230013414A - Semiconductor package - Google Patents

Abstract

The technical idea of the present invention provides a semiconductor package comprising: a first semiconductor chip including an upper surface, a bottom surface and a side surface, and including a chip pad arranged on the upper surface; a first conductive pillar on the chip pad of the first semiconductor chip; a first cover insulation layer covering the upper surface and the side surface of the first semiconductor chip and surrounding the side wall of the first conductive pillar; a first upper conductive layer extending along the upper surface of the first cover insulation layer and electrically connected to the chip pad of the first semiconductor chip through the first conductive pillar; a first side conductive layer extending along the side surface of the first cover insulation layer and connected to the first upper conductive layer; a second cover insulation layer covering the first upper conductive layer, the first side conductive layer and the first cover insulation layer; and a first lower conductive layer extending along the bottom surface of the first semiconductor chip and connected to the first side conductive layer, wherein the surface roughness of the upper surface of the first cover insulation layer is greater than the surface roughness of the surface of the first cover insulation layer being in contact with the upper surface of the first semiconductor chip. Therefore, the manufacturing process of a semiconductor package is simplified and manufacturing costs can be reduced.

Description

Semiconductor package {SEMICONDUCTOR PACKAGE}

The technical idea of the present invention relates to a semiconductor package, and more particularly to a wafer level package.

In general, semiconductor packages are manufactured by performing a semiconductor package process on semiconductor chips manufactured by performing various semiconductor processes on a wafer. Recently, in order to reduce the production cost of a semiconductor package, a wafer-level package technology has been proposed that performs a semiconductor packaging process at a wafer level and individualizes wafer-level semiconductor packages that have undergone the semiconductor packaging process into individual units.

A problem to be solved by the technical idea of the present invention is to provide a semiconductor package.

A first semiconductor chip including a top surface, a bottom surface, and a side surface, and including a chip pad provided on the top surface; a first conductive pillar on the chip pad of the first semiconductor chip; a first cover insulating layer covering the top surface and the side surface of the first semiconductor chip and surrounding sidewalls of the first conductive pillars; a first upper conductive layer extending along an upper surface of the first cover insulating layer and electrically connected to the chip pad of the first semiconductor chip through the first conductive pillar; a first side conductive layer extending along a side surface of the first cover insulating layer and connected to the first upper conductive layer; a second cover insulating layer covering the first upper conductive layer, the first side conductive layer, and the first cover insulating layer; and a first lower conductive layer extending along the bottom surface of the first semiconductor chip and connected to the first side conductive layer, wherein the upper surface of the first cover insulating layer has a surface roughness of the first side conductive layer. A semiconductor package having a greater surface roughness than a surface of the first cover insulating layer contacting the upper surface of the semiconductor chip.

In example embodiments, a vertical height of the first side conductive layer is greater than a vertical height of the first semiconductor chip, and a horizontal width of the first side conductive layer is a horizontal width of the first upper conductive layer and a vertical height of the first semiconductor chip. greater than the horizontal width of the lower conductive layer, and the first lower conductive layer contacts the bottom surface of the first semiconductor chip.

In example embodiments, the first side conductive layer may include a first side surface facing the side surface of the first semiconductor chip, a second side surface opposite to the first side surface, and top and bottom surfaces opposite to each other. wherein the first upper conductive layer is in contact with the first side surface of the first side conductive layer, and the first lower conductive layer is in contact with the bottom surface of the first side conductive layer.

In example embodiments, a first lower insulating layer covering the first lower conductive layer and the bottom surface of the first semiconductor chip; a first lower bump pad connected to the first lower conductive layer through an opening of the first lower insulating layer; and lower connection bumps on the first lower bump pads. an upper bump pad on an upper surface of the second cover insulating layer; a second conductive pillar extending between the upper bump pad and the first upper conductive layer; and upper connection bumps on the upper bump pads.

In example embodiments, an upper conductive structure provided on the top surface of the first semiconductor chip and having a single-layer structure or a multi-layer structure spaced apart from each other in a direction perpendicular to the top surface of the first semiconductor chip; a side conductive structure provided on the side surface of the first semiconductor chip, having a single layer structure or a multi-layer structure spaced apart from each other in a direction perpendicular to the side surface of the first semiconductor chip, and electrically connected to the upper conductive structure; a lower conductive structure provided on the bottom surface of the first semiconductor chip, having a single layer structure or a multi-layer structure spaced apart from each other in a direction perpendicular to the bottom surface of the first semiconductor chip, and electrically connected to the side conductive structure; a cover insulation structure covering the upper conductive structure and the side conductive structure; and a lower insulating structure covering the lower conductive structure.

In example embodiments, an upper bump pad on the first upper conductive layer; inter-package connection terminals on the upper bump pad; and a package structure on the inter-package connection terminal, wherein the package structure includes: a second semiconductor chip; a third cover insulating layer covering top and side surfaces of the second semiconductor chip; a second upper conductive layer extending along an upper surface of the third cover insulating layer and connected to a chip pad of the second semiconductor chip; a second side conductive layer extending along a side surface of the third cover insulating layer and connected to the second upper conductive layer; a fourth cover insulating layer covering the second upper conductive layer, the second side conductive layer, and the third cover insulating layer; a second lower conductive layer extending along a bottom surface of the second semiconductor chip and connected to the second side conductive layer; and a second lower bump pad connected to the second lower conductive layer and the inter-package connection terminal.

According to exemplary embodiments of the present invention, the first side conductive layer, which is an electrical connection structure between the first upper conductive layer and the first lower conductive layer, may be formed together through the same redistribution process as the first upper conductive layer. there is. Accordingly, the manufacturing process of the semiconductor package is simplified and manufacturing cost can be reduced.

According to exemplary embodiments of the present invention, the first side conductive layer for electrical connection between the first upper conductive layer and the first lower conductive layer is formed to a thin thickness of several micrometers, and the first side conductive layer Since the thickness of the covering first cover insulating layer and the second cover insulating layer are also formed to a thickness of several micrometers, the footprint of the semiconductor package can be reduced and a semiconductor package having a small form factor can be implemented.

1A is a cross-sectional view illustrating a semiconductor package according to exemplary embodiments of the present invention.
FIG. 1B is a layout diagram showing some configurations of the semiconductor package shown in FIG. 1A.
FIG. 1C is a perspective view illustrating a first conductive pillar, a first upper conductive layer, a first side conductive layer, a first lower conductive layer, and a first lower bump pad of the semiconductor package shown in FIG. 1A .
2 is a cross-sectional view illustrating a semiconductor package according to exemplary embodiments of the present invention.
3A to 3P are cross-sectional views illustrating a method of manufacturing the semiconductor package shown in FIG. 2 .
FIG. 4A is a top plan view of a portion of the structure shown in FIG. 3E.
FIG. 4B is a top plan view of a portion of the structure shown in FIG. 3F.
4C is a top plan view of a portion of the structure shown in FIG. 3H.
5 is a cross-sectional view illustrating a semiconductor package according to exemplary embodiments of the present invention.
6 is a cross-sectional view illustrating a semiconductor package according to exemplary embodiments of the inventive concept.
7 is a cross-sectional view illustrating a semiconductor package according to exemplary embodiments of the inventive concept.
8 is a cross-sectional view illustrating a semiconductor package according to exemplary embodiments of the present invention.
9 is a cross-sectional view illustrating a semiconductor package according to example embodiments of the inventive concepts.
10 is a cross-sectional view illustrating a semiconductor package according to example embodiments of the inventive concepts.
11 is a cross-sectional view illustrating a semiconductor package according to exemplary embodiments of the present invention.

Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. However, exemplary embodiments of the present disclosure may be modified in many different forms, and the scope of the present disclosure should not be construed as being limited due to the embodiments described below. Exemplary embodiments of the present disclosure are preferably interpreted as being provided to more completely explain the concept of the present disclosure to those with average knowledge in the art. The same sign means the same element throughout. Further, various elements and areas in the drawings are schematically drawn. Accordingly, the concepts of the present disclosure are not limited by the relative sizes or spacings drawn in the accompanying drawings.

Terms such as first and second may be used to describe various components, but the components are not limited by the terms. These terms are only used for the purpose of distinguishing one component from another. For example, a first element may be termed a second element, and conversely, a second element may be termed a first element, without departing from the scope of the present disclosure.

Terms used in the present disclosure are used only to describe specific embodiments, and are not intended to limit the concept of the present disclosure. Singular expressions include plural expressions unless the context clearly dictates otherwise. In this application, the expression "comprises" or "has" is intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, but one or more other features or It should be understood that the presence or addition of a number, operation, component, part, or combination thereof is not precluded.

Unless defined otherwise, all terms used herein, including technical terms and scientific terms, have the same meaning as commonly understood by those of ordinary skill in the art to which the concepts of the present disclosure belong. In addition, commonly used terms as defined in the dictionary should be interpreted as having a meaning consistent with what they mean in the context of the technology to which they relate, and in an overly formal sense unless explicitly defined herein. It will be understood that it should not be interpreted.

1A is a cross-sectional view illustrating a semiconductor package 10 according to exemplary embodiments of the present invention. FIG. 1B is a layout diagram showing some configurations of the semiconductor package 10 shown in FIG. 1A. FIG. 1C shows the first conductive pillar 131, the first upper conductive layer 141, the first side conductive layer 143, the first lower conductive layer 145, and It is a perspective view showing the first lower bump pad 151 .

1A to 1C , the semiconductor package 10 includes a first semiconductor chip 110, a first conductive pillar 131, a first cover insulating layer 121, a first upper conductive layer 141, 1 side conductive layer 143, second cover insulating layer 123, first lower conductive layer 145, first lower insulating layer 125, first lower bump pad 151, and lower connection bump 161 ) may be included.

The first semiconductor chip 110 may include a top surface 113 and a bottom surface 115 opposite to each other, and a side surface 114 extending between the top surface 113 and the bottom surface 115 . The upper surface 113 of the first semiconductor chip 110 may be a pad surface on which the chip pad 111 is provided. Hereinafter, a horizontal direction is defined as a direction parallel to the top surface 113 of the first semiconductor chip 110 (eg, an X direction and/or a Y direction), and a vertical direction is defined as a direction parallel to the top surface 113 of the first semiconductor chip 110 . It is defined as a direction perpendicular to the upper surface 113 (eg, Z direction). In addition, the horizontal width of an arbitrary member is defined as a length along the horizontal direction (eg, X direction and/or Y direction), and the vertical height of an arbitrary member is defined as the length in the vertical direction (eg, Z direction). defined as the length of

The first semiconductor chip 110 may include a semiconductor substrate including a semiconductor material such as silicon (Si) and a device layer formed on an active surface of the semiconductor substrate. A plurality of individual devices of various types may be formed in the device layer of the first semiconductor chip 110 . The chip pads 111 of the first semiconductor chip 110 may be electrically connected to individual devices formed on the device layer of the first semiconductor chip 110 . For example, the plurality of individual elements may be microelectronic devices, for example, a metal-oxide-semiconductor field effect transistor (MOSFET) such as a complementary metal-oxide-semiconductor transistor (CMOS transistor), a system large scale integration (LSI), ), an image sensor such as a CMOS imaging sensor (CIS), a micro-electro-mechanical system (MEMS), an active element, a passive element, and the like. In example embodiments, the first semiconductor chip 110 may be a memory chip. In example embodiments, the first semiconductor chip 110 may be a logic chip.

The first cover insulating layer 121 may cover the top surface 113 and the side surface 114 of the first semiconductor chip 110 . A portion of the first cover insulating layer 121 may extend along the top surface 113 of the first semiconductor chip 110 . In addition, another portion of the first cover insulating layer 121 may extend along the side surface 114 of the first semiconductor chip 110 to entirely cover the side surface 114 of the first semiconductor chip 110 . When viewed from a plan view, the first cover insulating layer 121 may entirely enclose the side surface 114 of the first semiconductor chip 110 . For example, when the first semiconductor chip 110 has a rectangular planar shape, the first cover insulating layer 121 may have a rectangular ring shape surrounding four side surfaces of the first semiconductor chip 110 . . In example embodiments, a footprint of the first cover insulating layer 121 may be the same as or similar to that of the first semiconductor chip 110 . That is, the planar area of the first cover insulating layer 121 may be the same as or similar to that of the first semiconductor chip 110 .

For example, the first cover insulating layer 121 may be formed of an insulating polymer, epoxy, or a combination thereof. In example embodiments, the first cover insulating layer 121 may be formed of photo imageable dielectric (PID) or polyimide.

The first conductive pillar 131 may be disposed on the chip pad 111 of the first semiconductor chip 110 . The first conductive pillars 131 extend through the first cover insulating layer 121 , and sidewalls of the first conductive pillars 131 may be surrounded by the first cover insulating layer 121 . The sidewall of the first conductive pillar 131 electrically connects the chip pad 111 of the first semiconductor chip 110 and the first upper conductive layer 141 provided on the upper surface of the first cover insulating layer 121. can The first conductive pillar 131 may have a pillar shape. The lower surface of the first conductive pillar 131 may contact the chip pad 111 of the first semiconductor chip 110, and the upper surface of the first conductive pillar 131 may contact the first upper conductive layer 141. .

In example embodiments, the first conductive pillar 131 may have the same material and/or the same material combination as the first upper conductive layer 141 . In other exemplary embodiments, the first conductive pillar 131 may have a material different from that of the first upper conductive layer 141 and/or a material combination different from that of the first upper conductive layer 141 .

In example embodiments, the top surface of the first conductive pillar 131 and the top surface of the first cover insulating layer 121 may be on the same plane. For example, the upper surface of the first conductive pillar 131 and the upper surface of the first cover insulating layer 121 may be polished together through a planarization process such as a chemical mechanical polishing process, and may be on the same plane.

In exemplary embodiments, the surface roughness of the upper surface of the first cover insulating layer 121 is the surface roughness of the side surface of the first cover insulating layer 121 and the second contacting the upper surface of the first cover insulating layer 121. It may be different from the surface roughness of the surface of the cover insulating layer 123 .

In example embodiments, the surface roughness of the upper surface of the first cover insulating layer 121 may be greater than the surface roughness of the side surface of the first cover insulating layer 121 . In example embodiments, the surface roughness of the upper surface of the first cover insulating layer 121 is greater than that of the surface of the first cover insulating layer 121 contacting the upper surface 113 of the first semiconductor chip 110 . can be big In example embodiments, the surface roughness of the upper surface of the first cover insulating layer 121 may be greater than that of the surface of the second cover insulating layer 123 contacting the upper surface of the first cover insulating layer 121 . there is.

The first upper conductive layer 141 may be provided on the upper surface of the first cover insulating layer 121 . The first upper conductive layer 141 may contact the upper surface of the first cover insulating layer 121 and extend along the upper surface of the first cover insulating layer 121 . The first upper conductive layer 141 may extend parallel to the top surface 113 of the semiconductor chip 110 . The first upper conductive layer 141 may be electrically connected to the chip pad 111 of the first semiconductor chip 110 through the first conductive pillar 131 . In example embodiments, the first upper conductive layer 141 may include a line pattern extending in a line shape on the upper surface of the first cover insulating layer 121 .

In example embodiments, the first upper conductive layer 141 may include tungsten (W), copper (Cu), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), or ruthenium (Ru). ), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), or a combination thereof. The material of each of the first side conductive layer 143, the first lower conductive layer 145, and the first lower bump pad 151 described later may be substantially the same as or similar to that of the first upper conductive layer 141. can

In example embodiments, the first upper conductive layer 141 may include a seed metal layer and a plating layer stacked on the seed metal layer. That is, the seed metal layer may be formed on the surface of the first cover insulating layer 121, and the plating layer may be formed on the seed metal layer. The plating layer may be formed through an electroplating process using a seed metal layer as a seed. For example, the seed metal layer may be made of titanium (Ti), copper (Cu), chromium (Cr), tungsten (W), nickel (Ni), aluminum (Al), palladium (Pd), gold (Au), or any of these Combinations may be included. For example, the plating layer may include copper (Cu) or an alloy of copper. The first side conductive layer 143, the first lower conductive layer 145, and the first lower bump pad 151, which will be described later, are also formed through an electroplating process similar to the formation method of the first upper conductive layer 141. and may have a multilayer structure in which a plating layer is stacked on a seed metal layer.

The first side conductive layer 143 may be provided on the side surface of the first cover insulating layer 121 . The first side conductive layer 143 is connected to the first upper conductive layer 141 and may extend along the side surface of the first cover insulating layer 121 . The first side conductive layer 143 may extend parallel to the side surface 114 of the first semiconductor chip 110 . The first side conductive layer 143 may extend downward from an upper end connected to the first upper conductive layer 141 . The first side conductive layer 143 may extend from an upper end to a lower end of a side surface of the first cover insulating layer 121 . In example embodiments, a lower end of the first side conductive layer 143 and a lower end of the first cover insulating layer 121 may be on the same plane as the bottom surface 115 of the first semiconductor chip 110 . . In example embodiments, a vertical height 143H of the first side conductive layer 143 may be greater than a vertical height 110H of the first semiconductor chip 110 .

The second cover insulating layer 123 may cover the first upper conductive layer 141 , the first side conductive layer 143 , and the first cover insulating layer 121 . A portion of the second cover insulating layer 123 extends along the upper surface of the first cover insulating layer 121 and may cover the first upper conductive layer 141 . Another part of the second cover insulating layer 123 may extend along the side surface of the first cover insulating layer 121 and cover the first side conductive layer 143 . The second cover insulating layer 123 has a top surface extending substantially parallel to the top surface 113 of the first semiconductor chip 110 and a side surface extending substantially parallel to the side surface 114 of the first semiconductor chip 110 . can include In example embodiments, top and side surfaces of the second cover insulating layer 123 may be exposed to the outside.

In example embodiments, the bottom of the second cover insulating layer 123 is the bottom of the first side conductive layer 143, the bottom of the first cover insulating layer 121, and the bottom of the first semiconductor chip 110. It may be coplanar with face 115 .

For example, the second cover insulating layer 123 may be formed of an insulating polymer, epoxy, or a combination thereof. In example embodiments, the second cover insulating layer 123 may be formed from PID or polyimide. In example embodiments, the second cover insulating layer 123 may be formed from a molding material such as an epoxy molding compound (EMC).

In example embodiments, the material and/or material composition of the second cover insulating layer 123 may be the same as the material and/or material composition of the first cover insulating layer 121 . For example, each of the first cover insulating layer 121 and the second cover insulating layer 123 may include polyimide.

In other exemplary embodiments, the material and/or material composition of the second cover insulating layer 123 may be different from the material and/or material composition of the first cover insulating layer 121 . For example, when the first cover insulating layer 121 includes polyimide, the second cover insulating layer 123 may include EMC.

The first lower conductive layer 145 may be provided on the bottom surface 115 of the first semiconductor chip 110 . The first lower conductive layer 145 may contact the bottom surface 115 of the first semiconductor chip 110 and may extend along the bottom surface 115 of the first semiconductor chip 110 . The first lower conductive layer 145 may extend parallel to the bottom surface 115 of the first semiconductor chip 110 . The first lower conductive layer 145 may further extend outward from an edge of the bottom surface 115 of the first semiconductor chip 110 and be connected to a lower end of the first side conductive layer 143 . In example embodiments, the first lower conductive layer 145 may include a line pattern extending in a line shape on the bottom surface 115 of the first semiconductor chip 110 .

The first lower insulating layer 125 may cover the bottom surface 115 of the first semiconductor chip 110 and the first lower conductive layer 145 . The first lower insulating layer 125 covers the bottom surface 115 of the first semiconductor chip 110 and is on the same plane as the bottom surface 115 of the first semiconductor chip 110. The first cover insulating layer ( 121) and the lower end of the second cover insulating layer 123 may be covered. In example embodiments, a footprint of the first lower insulating layer 125 may be the same as that of the second cover insulating layer 123 . That is, the planar area of the first lower insulating layer 125 may be the same as that of the second cover insulating layer 123 .

The first lower bump pad 151 may be connected to the first lower conductive layer 145 through the opening 1250 of the first lower insulating layer 125 . A portion of the first lower bump pad 151 may protrude from the first lower insulating layer 125 . For example, the first lower bump pads 151 may be an under bump metal layer (UBM).

The lower connection bump 161 may be provided on the first lower bump pad 151 . The lower connection bump 161 may include, for example, solder, tin (Sn), silver (Ag), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), zinc (Zn), or lead. (Pb) and/or alloys thereof. In example embodiments, the lower connection bumps 161 may have a generally ball shape attached to the first lower bump pads 151 . For example, the lower connection bump 161 may be formed by placing a solder ball on the first lower bump pad 151 and then performing a reflow process on the solder ball. In other exemplary embodiments, the lower connection bump 161 may have a plate shape and may be formed to have a substantially uniform thickness on the surface of the first lower bump pad 151 .

In example embodiments, the first side conductive layer 143 may have a plate shape extending substantially parallel to the side surface 114 of the first semiconductor chip 110 . For example, the first side conductive layer 143 may include a first side surface 1431 facing the side surface 114 of the first semiconductor chip 110 and a second side surface 1432 opposite the first side surface 1431 . ), a top surface 1433 and a bottom surface 1434 opposite to each other. The first side surface 1431 and the second side surface 1432 of the first side conductive layer 143 are parallel to the side surface 114 of the first semiconductor chip 110 facing the first side conductive layer 143 . can be extended appropriately.

It may have a first horizontal width 143W in a second horizontal direction (eg, Y direction) parallel to the side surface 114 of the first semiconductor chip 110 facing the first side conductive layer 143 . . In example embodiments, the first side conductive layer 143 may extend in a vertical direction (eg, a Z direction) with a substantially uniform first horizontal width 143W. That is, the horizontal width at the bottom of the first side conductive layer 143 and the horizontal width at the top of the first side conductive layer 143 may be the same.

In example embodiments, the first upper conductive layer 141 may be connected to the first side surface 1431 of the first side conductive layer 143, and the first side surface 1431 of the first side conductive layer 143 ) may have a line shape extending from. The first upper conductive layer 141 may have a line pattern extending from the first side surface 1431 of the first side conductive layer 143 to the second horizontal width 141W. In this case, the first horizontal width 143W of the first side conductive layer 143 may be greater than the second horizontal width 141W of the first upper conductive layer 141 . In example embodiments, when a contact area between the first upper conductive layer 141 and the first side conductive layer 143 is defined as the first contact area, the second horizontal direction of the first contact area (for example, For example, the horizontal width along the Y direction) may be smaller than the first horizontal width 143W of the first side conductive layer 143 . In example embodiments, the first horizontal width 143W of the first side conductive layer 143 is the horizontal width of the first contact region between the first upper conductive layer 141 and the first side conductive layer 143. It may be between 150% and 500%, between 200% and 400%, or between 250% and 300% of

In example embodiments, the first lower conductive layer 145 may be connected to the bottom surface 1434 of the first side conductive layer 143, and may be connected to the bottom surface 1434 of the first side conductive layer 143. It may have a line shape extending from the connected portion. The first lower conductive layer 145 may have a line pattern extending from the bottom surface 1434 of the first side conductive layer 143 to a third horizontal width 145W. In this case, the first horizontal width 143W of the first side conductive layer 143 may be greater than the third horizontal width 145W of the first lower conductive layer 145 . In example embodiments, when the contact area between the first lower conductive layer 145 and the first side conductive layer 143 is defined as the second contact area, the second horizontal direction of the second contact area (for example, For example, the horizontal width along the Y direction) may be smaller than the first horizontal width 143W of the first side conductive layer 143 . In example embodiments, the first horizontal width 143W of the first side conductive layer 143 is the horizontal width of the second contact area between the first lower conductive layer 145 and the first side conductive layer 143. It may be between 150% and 500%, between 200% and 400%, or between 250% and 300% of

The footprint (or planar area) of the semiconductor package 10 may be determined by the distance 501 between the side surface 114 of the first semiconductor chip 110 and the side surface of the semiconductor package 10 . The distance 501 between the side surface 114 of the first semiconductor chip 110 and the side surface of the semiconductor package 10 constitutes the side surface 114 of the first semiconductor chip 110 and the side surface of the semiconductor package 10. It may refer to a distance between the outer surface 1231 of the second cover insulating layer 123 along a direction perpendicular to the side surface 114 of the first semiconductor chip 110. In some exemplary embodiments, the distance 501 between the side surface 114 of the first semiconductor chip 110 and the side surface of the semiconductor package 10 may be between 10 μm and 80 μm.

In general, a connection between an upper wiring on the upper side and a lower wiring on the lower side of a semiconductor chip is implemented by a conductive post extending in a vertical direction. Such a conductive post is formed through a process separate from the forming process of the upper wiring and the forming process of the lower wiring. Also, a process of forming such a conductive post generally includes a process of forming a via hole in an insulating material layer and a plating process of filling the via hole with a conductive material. In the case of such a conductive post, in order to prevent a problem in that the via hole is incompletely filled with a conductive material during the plating process, the via hole and the conductive post are generally formed with a wide width of about tens to hundreds of micrometers, and the conductive post The size of the semiconductor package increases as much as the placement space.

According to exemplary embodiments of the present invention, the first side conductive layer 143, which is an electrical connection structure between the first upper conductive layer 141 and the first lower conductive layer 145, is the first upper conductive layer 141 ) and can be formed together through the same redistribution process. Accordingly, the manufacturing process of the semiconductor package 10 is simplified and manufacturing cost can be reduced. Furthermore, the first side conductive layer 143 for electrical connection between the first upper conductive layer 141 and the first lower conductive layer 145 is formed to a thickness of several micrometers, and the first side conductive layer ( 143), since the thickness of the first cover insulating layer 121 and the second cover insulating layer 123 are also formed to a thin thickness of several micrometers, the footprint of the semiconductor package 10 can be reduced, and small form The semiconductor package 10 having a factor may be implemented.

2 is a cross-sectional view illustrating a semiconductor package 10a according to example embodiments of the inventive concepts. Hereinafter, the semiconductor package 10a shown in FIG. 2 will be described, focusing on differences from the semiconductor package 10 described with reference to FIGS. 1A to 1C .

Referring to FIG. 2 , the semiconductor package 10a includes second conductive pillars 142 connected to the first upper conductive layer 141, upper bump pads 153 connected to the second conductive pillars 142, and upper bump pads. An upper connection bump 163 attached on 153 may be included.

The second conductive pillar 142 may be provided on the first upper conductive layer 141 . The second conductive pillar 142 extends through the second cover insulating layer 123 and may electrically connect the first upper conductive layer 141 and the upper bump pad 153 to each other. The second conductive pillar 142 may have a pillar shape. A lower surface of the second conductive pillar 142 may contact the first upper conductive layer 141 , and an upper surface of the second conductive pillar 142 may contact the upper bump pad 153 .

In example embodiments, the second conductive pillar 142 may have the same material and/or the same material combination as the first upper conductive layer 141 . In other exemplary embodiments, the second conductive pillar 142 may have a material different from that of the first upper conductive layer 141 and/or a different material combination.

In example embodiments, the top surface of the second conductive pillar 142 and the top surface of the second cover insulating layer 123 may be on the same plane. For example, the top surface of the second conductive pillar 142 and the top surface of the second cover insulating layer 123 may be polished together through a planarization process such as a chemical mechanical polishing process, and may be on the same plane.

In exemplary embodiments, the surface roughness of the upper surface of the second cover insulating layer 123 is in contact with the surface roughness of the side surface of the second cover insulating layer 123 and the upper surface and side surface of the first cover insulating layer 121. It may be different from the surface roughness of the surface of the second cover insulating layer 123 . In example embodiments, the surface roughness of the upper surface of the second cover insulating layer 123 may be greater than the surface roughness of the side surface of the second cover insulating layer 123 . In addition, the surface roughness of the upper surface of the second cover insulating layer 123 may be greater than that of the surface of the second cover insulating layer 123 contacting the upper and side surfaces of the first cover insulating layer 121 .

The upper bump pad 153 is provided on the upper surface of the second cover insulating layer 123 and may be electrically connected to the first upper conductive layer 141 through the second conductive pillar 142 . For example, the upper bump pad 153 may be an under bump metal layer.

The upper connection bump 163 may be provided on the upper bump pad 153 . The upper connection bump 163 may include, for example, solder, tin (Sn), silver (Ag), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), zinc (Zn), or lead. (Pb) and/or alloys thereof. In example embodiments, the upper connection bump 163 may have a shape of a ball attached to the upper bump pad 153 . For example, the upper connection bump 163 may be formed by placing a solder ball on the upper bump pad 153 and then performing a reflow process on the solder ball. In other exemplary embodiments, the upper connection bump 163 may have a plate shape and may be formed to have a substantially uniform thickness on the surface of the upper bump pad 153 .

The semiconductor package 10a may be connected to another semiconductor package or an electronic device disposed below the semiconductor package 10a through a lower connection bump 161, and may be connected to another semiconductor package 10a through an upper connection bump 163. It may be connected to other semiconductor packages or electronic devices disposed on the upper side.

3A to 3P are cross-sectional views illustrating a method of manufacturing the semiconductor package 10a shown in FIG. 2 . FIG. 4A is a plan view of a portion of the structure shown in FIG. 3E, FIG. 4B is a plan view of a portion of the structure shown in FIG. 3F, and FIG. 4C is a plan view showing a portion of the structure shown in FIG. 3H. Hereinafter, a method of manufacturing the semiconductor package 10a shown in FIG. 2 will be described with reference to FIGS. 3A to 3P and FIGS. 4A to 4C.

Referring to FIG. 3A , a wafer W on which a plurality of integrated circuits constituting the plurality of first semiconductor chips 110 are formed is prepared.

Referring to FIG. 3B , a portion of the wafer W is removed to form a trench TR between the plurality of first semiconductor chips 110 . The trench TR is a space recessed from the upper side of the wafer W, and may be formed by removing a portion of the wafer W. As the trenches TR between the plurality of first semiconductor chips 110 are formed, side surfaces of each of the plurality of first semiconductor chips 110 may be exposed. When viewed from a plan view, the plurality of first semiconductor chips 110 may be separated from each other by trenches TR.

Referring to FIG. 3C together with FIG. 3B , the first conductive pillar 131 is formed on the chip pad 111 of the first semiconductor chip 110 and the first insulating material layer 121m covering the wafer W is formed. form The first insulating material layer 121m may cover top surfaces of the first semiconductor chips 110 and the first conductive pillars 131 and fill trenches TR formed between the first semiconductor chips 110 .

Referring to FIG. 3D together with FIG. 3C , a first cover insulating layer 121 exposing the first conductive pillar 131 is formed by removing a portion of the first insulating material layer 121m. As a portion of the first insulating material layer 121m is removed, the upper surface of the first conductive pillar 131 may be exposed. In example embodiments, a polishing process such as an etch back process or chemical mechanical polishing may be performed to remove a portion of the first insulating material layer 121m.

In example embodiments, an upper surface of the first cover insulating layer 121 treated through an etch-back or polishing process on the first insulating material layer 121m may have a relatively large surface roughness. For example, the surface roughness of the upper surface of the first cover insulating layer 121 may be greater than that of the surface of the first cover insulating layer 121 in contact with the wafer (W). As the surface roughness of the upper surface of the first cover insulating layer 121 increases, the adhesive strength between the first upper conductive layer ( 141 in FIG. 1A ) and the first cover insulating layer 121 formed through a subsequent process can be strengthened. there is.

Referring to FIG. 3E together with FIG. 4A , a first hole 121V may be formed in the first insulating material layer 121m by removing a portion of the first insulating material layer 121m filled in the trench TR. . The first hole 121V may pass through the first insulating material layer 121m filled in the trench TR, and a portion of the wafer W may be exposed through the first hole 121V.

Referring to FIG. 3F together with FIG. 4B , the surface of the wafer W exposed through the first upper conductive layer 141, the first side conductive layer 143, and the first hole (121V in FIG. 3E) is covered. A conductive layer 503 may be formed. The first upper conductive layer 141, the first side conductive layer 143, and the conductive layer 503 may be formed together through the same metal wiring process.

Referring to FIG. 3G , second conductive pillars 142 are formed on the first upper conductive layer 141 .

Referring to FIG. 3H together with FIGS. 3G and 4C , a cutting process for forming the cutting region CR between the plurality of first semiconductor chips 110 is performed. The cutting region CR may be a region formed by removing portions of each of the material layers filled in the trench (TR of FIG. 3B ) of the wafer W. The cutting process may include cutting using a cutting blade, cutting using a laser, and the like. The cutting region CR may be formed by removing a portion of the first insulating material layer 121m between the plurality of first semiconductor chips 110 and the conductive layer 503 covering the surface of the wafer W. . A surface of the wafer W may be exposed through the cutting region CR. The cutting process may be performed such that the conductive layer 503 covering the surface of the wafer W is removed, but the first side conductive layer 143 on the sidewall of the first hole 121V is not removed. After the cutting process, a portion of the remaining first insulating material layer 121m may constitute the first cover insulating layer 121 .

Referring to FIG. 3I, a second preliminary cover insulating layer 123m covering the result of FIG. 3H is formed. The second preliminary cover insulating layer 123m may cover the first cover insulating layer 121, the first upper conductive layer 141, the second conductive pillar 142, and the first side conductive layer 143, and may be cut. It may fill the region CR and cover the surface of the wafer W exposed through the cutting region CR.

Referring to FIG. 3j together with FIG. 3i , a polishing process may be performed from the lower surface of the wafer W to remove a portion of the wafer W. The polishing process may be performed until the first side conductive layer 143 and the second preliminary cover insulating layer 123m are exposed. The polishing process may include a chemical mechanical polishing process, a grinding process, and the like. Through the polishing process, the bottom surface 115 of the first semiconductor chip 110 may be planarized. The surface of the second preliminary cover insulating layer 123m and the surface of the first cover insulating layer 121 exposed through the polishing process may be on the same plane as the bottom surface 115 of the first semiconductor chip 110 . .

Referring to FIG. 3K , a first lower conductive layer 145 is formed on the bottom surface of the product of FIG. 3J . The first lower conductive layer 145 may be connected to the first side conductive layer 143 and may extend along the bottom surface 115 of the first semiconductor chip 110 .

Referring to FIG. 3L, a first lower insulating layer 125 covering the bottom surface of the product of FIG. 3K is formed. In order to form the first lower insulating layer 125, an insulating material film covering the bottom surface of the resultant product of FIG. 3K is formed, and a portion of the insulating material film is removed to expose a portion of the first lower conductive layer 145. (125 O) can be formed.

Referring to FIG. 3M together with FIG. 3L , a first lower bump pad 151 connected to a portion of the first lower conductive layer 145 exposed through the opening 1250 of the first lower insulating layer 125 is formed. , lower connection bumps 161 are formed on the first lower bump pads 151 .

Referring to FIG. 3N together with FIG. 3M , a portion of the second preliminary cover insulating layer 123m is removed to form a second cover insulating layer 123 exposing the second conductive pillars 142 . As a portion of the second preliminary cover insulating layer 123m is removed, an upper surface of the second conductive pillar 142 may be exposed. In example embodiments, a polishing process such as an etch back process or chemical mechanical polishing may be performed to remove a portion of the second preliminary cover insulating layer 123m.

In example embodiments, an upper surface of the second cover insulating layer 123 treated through an etch-back or polishing process on a portion of the second preliminary cover insulating layer 123m may have a relatively large surface roughness. For example, the surface roughness of the upper surface of the second cover insulating layer 123 is the surface roughness of the surface of the second cover insulating layer 123 contacting the first cover insulating layer 121 and the second cover insulating layer 123 ) can be greater than the surface roughness of the side of the As the surface roughness of the upper surface of the second cover insulating layer 123 increases, the adhesive force between the upper bump pad 153 formed through a subsequent process and the second cover insulating layer 123 may be strengthened.

Referring to FIG. 3O , the upper bump pad 153 connected to the second conductive pillar 142, the upper connection bump 163 on the upper bump pad 153, and the lower connection bump on the first lower bump pad 151 ( 161) form.

Referring to Figure 3p, a ssoing process for the result of Figure 3o is performed. That is, the structure manufactured at the wafer level may be cut along the scribe lane SL to separate the structure manufactured at the wafer level into individual unit semiconductor packages 10 .

5 is a cross-sectional view illustrating a semiconductor package 10b according to example embodiments of the inventive concepts. Hereinafter, the semiconductor package 10b shown in FIG. 5 will be described, focusing on differences from the semiconductor package 10a described with reference to FIG. 2 .

Referring to FIG. 5 , the semiconductor package 10b may include an inductor pattern 147 disposed on the bottom surface 115 of the first semiconductor chip 110 . The inductor pattern 147 may contact the bottom surface 115 of the first semiconductor chip 110 and be covered by the first lower insulating layer 125 . The inductor pattern 147 may be formed together with the first lower conductive layer 145 during a metal wiring process for forming the first lower conductive layer 145 . The inductor pattern 147 may have the same material and/or the same material combination as the first lower conductive layer 145 .

6 is a cross-sectional view illustrating a semiconductor package 10c according to example embodiments of the inventive concepts. Hereinafter, the semiconductor package 10c shown in FIG. 6 will be described, focusing on differences from the semiconductor package 10 described with reference to FIGS. 1A to 1C .

Referring to FIG. 6 , the first lower conductive layer 145 of the semiconductor package 10c may include a lead pattern functioning as an external pad. The lead pattern may have, for example, a polygonal shape such as a circle or a quadrangle in a plan view. In example embodiments, the first lower insulating layer ( 125 in FIG. 1A ) may be omitted, and the first lower conductive layer 145 may be exposed to the outside. In example embodiments, a conductive adhesive layer 146 may be further disposed on the surface of the first lower conductive layer 145 . The conductive adhesive layer 146 may be formed to cover the bottom surface of the first lower conductive layer 145 . The conductive adhesive layer 146 may be formed by, for example, a plating method. The conductive adhesive layer 146 may include, for example, solder, tin (Sn), silver (Ag), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), zinc (Zn), or lead. (Pb) and/or alloys thereof.

7 is a cross-sectional view illustrating a semiconductor package 10d according to example embodiments of the inventive concepts. Hereinafter, the semiconductor package 10d shown in FIG. 7 will be described, focusing on differences from the semiconductor package 10c described with reference to FIG. 6 .

Referring to FIG. 7 , the semiconductor package 10d may include a first lower insulating layer 125 provided on the bottom surface 115 of the first semiconductor chip 110 . The first lower insulating layer 125 may cover the first lower conductive layer 145 including the lead pattern and may cover at least a portion of a side surface of the conductive adhesive layer 146 . The first lower insulating layer 125 does not cover the bottom surface of the conductive adhesive layer 146, and the bottom surface of the conductive adhesive layer 146 may be exposed to the outside.

8 is a cross-sectional view illustrating a semiconductor package 10e according to example embodiments of the inventive concepts. Hereinafter, the semiconductor package 10e shown in FIG. 8 will be described, focusing on differences from the semiconductor package 10 described with reference to FIGS. 1A to 1C .

Referring to FIG. 8 , the semiconductor package 10e includes a first semiconductor chip 110, a first cover insulating layer 121, a first upper conductive layer 141, a second conductive pillar 142, and a first side conductive layer. layer 143, second cover insulating layer 123, second upper conductive layer 181, third conductive pillar 182, second side conductive layer 183, third cover insulating layer 171, 3 upper conductive layer 185, fourth conductive pillar 186, third side conductive layer 187, fourth cover insulating layer 173, first lower conductive layer 145, first lower insulating layer 125 ), the second lower conductive layer 191, the second lower side conductive layer 193, the second lower insulating layer 175, the third lower conductive layer 195, the third lower side conductive layer 197, 3 may include a lower insulating layer 177 , a first lower bump pad 151 , and a lower connection bump 161 .

The second upper conductive layer 181 may be provided on the upper surface of the second cover insulating layer 123 . The second upper conductive layer 181 may contact the upper surface of the second cover insulating layer 123 and extend along the upper surface of the second cover insulating layer 123 . The second upper conductive layer 181 may be connected to the first upper conductive layer 141 through the opening of the second cover insulating layer 123 . In example embodiments, the second upper conductive layer 181 may include a line pattern extending in a line shape on the upper surface of the second cover insulating layer 123 .

The third conductive pillar 182 may be provided on the second upper conductive layer 181 . The third conductive pillar 182 extends through the third cover insulating layer 171 and may electrically connect the second upper conductive layer 181 and the third upper conductive layer 185 . The third conductive pillar 182 may have a pillar shape. The lower surface of the third conductive pillar 182 may contact the second upper conductive layer 181 , and the upper surface of the third conductive pillar 182 may contact the third upper conductive layer 185 .

The second side conductive layer 183 may be provided on the side of the second cover insulating layer 123 . The second side conductive layer 183 is connected to the second upper conductive layer 181 and may extend along the side surface of the second cover insulating layer 123 . The second side conductive layer 183 may extend downward from an upper end connected to the second upper conductive layer 181 . The second side conductive layer 183 may extend from an upper end to a lower end of a side surface of the second cover insulating layer 123 . In example embodiments, a lower end of the second side conductive layer 183 and a lower end of the second cover insulating layer 123 may be on the same plane as the bottom surface 115 of the first semiconductor chip 110 . . In example embodiments, the second side conductive layer 183 may have a plate shape extending parallel to the facing side surface 114 of the first semiconductor chip 110 .

The third cover insulating layer 171 may cover the second upper conductive layer 181 , the second side conductive layer 183 , and the second cover insulating layer 123 . A portion of the third cover insulating layer 171 extends along the upper surface of the second cover insulating layer 123 and may cover the second upper conductive layer 181 . Another part of the third cover insulating layer 171 may extend along the side surface of the second cover insulating layer 123 and cover the second side conductive layer 183 .

The third upper conductive layer 185 may be provided on the upper surface of the third cover insulating layer 171 . The third upper conductive layer 185 may contact the upper surface of the third cover insulating layer 171 and extend along the upper surface of the third cover insulating layer 171 . The third upper conductive layer 185 may be connected to the second upper conductive layer 181 through the opening of the third cover insulating layer 171 . In example embodiments, the third upper conductive layer 185 may include a line pattern extending in a line shape on the upper surface of the third cover insulating layer 171 .

The fourth conductive pillar 186 may be provided on the third upper conductive layer 185 . The fourth conductive pillar 186 extends through the fourth cover insulating layer 173 and may electrically connect the third upper conductive layer 185 and the upper bump pad 153 to each other. The fourth conductive pillar 186 may have a pillar shape. A lower surface of the fourth conductive pillar 186 may contact the third upper conductive layer 185 and an upper surface of the fourth conductive pillar 186 may contact the upper bump pad 153 .

The third side conductive layer 187 may be provided on the side surface of the third cover insulating layer 171 . The third side conductive layer 187 is connected to the third upper conductive layer 185 and may extend along the side surface of the third cover insulating layer 171 . The third side conductive layer 187 may extend downward from an upper end connected to the third upper conductive layer 185 . The third side conductive layer 187 may extend from an upper end to a lower end of a side surface of the third cover insulating layer 171 . In example embodiments, a lower end of the third side conductive layer 187 and a lower end of the third cover insulating layer 171 may be on the same plane as the bottom surface 115 of the first semiconductor chip 110 . . In example embodiments, the third side conductive layer 187 may have a plate shape extending parallel to the facing side surface 114 of the first semiconductor chip 110 .

The fourth cover insulating layer 173 may cover the third upper conductive layer 185 , the third side conductive layer 187 , and the third cover insulating layer 171 . A portion of the fourth cover insulating layer 173 may extend along the upper surface of the third cover insulating layer 171 and cover the third upper conductive layer 185 . Another part of the fourth cover insulating layer 173 may extend along the side surface of the third cover insulating layer 171 and cover the third side conductive layer 187 . In exemplary embodiments, the outermost fourth cover insulating layer 173 among the first to fourth cover insulating layers 121, 123, 171, and 173 includes a molding material such as EMC, and the remaining first The through third cover insulating layers 121, 123, and 171 may include polyimide.

The second lower conductive layer 191 may be provided on the bottom surface of the first lower insulating layer 125 . The second lower conductive layer 191 may contact the bottom surface of the first lower insulating layer 125 and may extend along the bottom surface of the first lower insulating layer 125 . The second lower conductive layer 191 may be connected to the first lower conductive layer 145 through an opening in the first lower insulating layer 125 . In example embodiments, the second lower conductive layer 191 may include a line pattern extending in a line shape on the bottom surface of the first lower insulating layer 125 .

The second lower side conductive layer 193 may be provided on the side surface of the first lower insulating layer 125 . The second lower side conductive layer 193 may electrically connect the second lower conductive layer 191 and the second side conductive layer 183 . The second lower side conductive layer 193 may extend along the side surface of the first lower insulating layer 125 . The second lower side conductive layer 193 may extend in a vertical direction (eg, Z direction) from an upper end connected to the second side conductive layer 183 to a lower end connected to the second lower conductive layer 191 . The second lower side conductive layer 193 may extend from an upper end to a lower end of a side surface of the first lower insulating layer 125 . In example embodiments, the second lower side conductive layer 193 may have a plate shape extending in a vertical direction (eg, Z direction) and have a horizontal width similar to that of the second side conductive layer 183 . may have a horizontal width of

The second lower insulating layer 175 may cover the second lower conductive layer 191 , the second lower side conductive layer 193 , and the first lower insulating layer 125 . A portion of the second lower insulating layer 175 may extend along the bottom surface of the first lower insulating layer 125 and cover the second lower conductive layer 191 . Another portion of the second lower insulating layer 175 may extend along the side surface of the first lower insulating layer 125 and cover the second lower side conductive layer 193 .

The third lower conductive layer 195 may be provided on the bottom surface of the second lower insulating layer 175 . The third lower conductive layer 195 may contact the bottom surface of the second lower insulating layer 175 and may extend along the bottom surface of the second lower insulating layer 175 . The third lower conductive layer 195 may be connected to the second lower conductive layer 191 through an opening of the second lower insulating layer 175 . In example embodiments, the third lower conductive layer 195 may include a line pattern extending in a line shape on the bottom surface of the second lower insulating layer 175 .

The third lower side conductive layer 197 may be provided on the side surface of the second lower insulating layer 175 . The third lower side conductive layer 197 may electrically connect the third lower conductive layer 195 and the third side conductive layer 187 to each other. The third lower side conductive layer 197 may extend along the side surface of the second lower insulating layer 175 . The third lower side conductive layer 197 may extend in a vertical direction (eg, Z direction) from an upper end connected to the third side conductive layer 187 to a lower end connected to the third lower conductive layer 195 . The third lower side conductive layer 197 may extend from an upper end to a lower end of a side surface of the second lower insulating layer 175 . In example embodiments, the third lower side conductive layer 197 may have a plate shape extending in a vertical direction (eg, Z direction) and have a horizontal width similar to that of the third side conductive layer 187 . may have a horizontal width of

The third lower insulating layer 177 may cover the third lower conductive layer 195 , the third lower side conductive layer 197 , and the second lower insulating layer 175 . A portion of the third lower insulating layer 177 may extend along the bottom surface of the second lower insulating layer 175 and cover the third lower conductive layer 195 . Another part of the third lower insulating layer 177 may extend along the side surface of the second lower insulating layer 175 and cover the third lower side conductive layer 197 . In example embodiments, among the first to third lower insulating layers 125 , 175 , and 177 , the outermost third lower insulating layer 177 includes a molding material such as EMC, and the remaining first and third lower insulating layers 177 contain a molding material such as EMC. The second lower insulating layers 125 and 175 may include polyimide.

In FIG. 8 , the semiconductor package 10e is illustrated as including first to third upper conductive layers 141 , 181 , and 185 forming three layers on the upper surface 113 of the semiconductor chip 110 , but the semiconductor package 10e includes the semiconductor package 10e. Two or more conductive layers may be provided on the upper surface 113 of the chip 110 . In other words, the semiconductor package 10e may further include an upper conductive structure having a single-layer or multi-layer structure in addition to the first upper conductive layer 141 . When the upper conductive structure has a multi-layer structure, a plurality of conductive layers spaced apart from each other in a direction perpendicular to the upper surface 113 of the semiconductor chip 110 and extending generally parallel to the upper surface 113 of the semiconductor chip 110 and , and may include conductive pillars electrically connecting the plurality of conductive layers. In the exemplary embodiment of FIG. 8 , the second and third upper conductive layers 181 and 185 and the third and fourth conductive pillars 182 and 186 may constitute an upper conductive structure.

In addition, the semiconductor package 10e is provided on the side surface 114 of the semiconductor chip 110 and may include two or more conductive layers. In other words, the semiconductor package 10e may further include a side conductive structure having a single-layer or multi-layer structure in addition to the first side conductive layer 143 . When the side conductive structure has a multi-layer structure, it includes a plurality of conductive layers spaced apart from each other in a direction perpendicular to the side surface 114 of the semiconductor chip 110 and extending substantially parallel to the side surface 114 of the semiconductor chip 110. can do. In the embodiment of FIG. 8 , the second and third side conductive layers 183 and 187 may constitute a side conductive structure.

In addition, the semiconductor package 10e may further include a cover insulation structure provided on the second cover insulation layer 123 and covering the upper conductive structure and the side conductive structure. The cover insulation structure may include single or multi-layer insulation layers provided on the second cover insulation layer 123 . When the cover insulation structure has a multi-layer structure, the insulation layers included in the cover insulation structure may extend along the upper surface 113 and the side surface 114 of the semiconductor chip 110 , respectively. In the embodiment of FIG. 8 , the third and fourth cover insulating layers 171 and 173 may constitute a cover insulating structure.

In addition, the semiconductor package 10e is provided on the bottom surface 115 of the semiconductor chip 110 and may include two or more conductive layers. In other words, the semiconductor package 10e may further include a lower conductive structure having a single-layer or multi-layer structure in addition to the first lower conductive layer 145 . When the lower conductive structure has a multi-layer structure, a plurality of conductive layers spaced apart from each other in a direction perpendicular to the bottom surface 115 of the semiconductor chip 110 and generally extending parallel to the bottom surface 115 of the semiconductor chip 110 . may include In the exemplary embodiment of FIG. 8 , the second and third lower conductive layers 191 and 195 may constitute a lower conductive structure. The lower conductive structure may be electrically connected to the side conductive structure through a lower side conductive structure extending in a vertical direction, such as the second and third lower side conductive layers 193 and 197 .

In addition, the semiconductor package 10e may further include a lower insulating structure provided on the first lower insulating layer 125 and covering the lower conductive structure. The lower insulating structure may include single or multi-layered insulating layers provided on the first lower insulating layer 125 . When the lower insulating structure has a multi-layer structure, the insulating layers included in the lower insulating structure may extend along the bottom and side surfaces of the first lower insulating layer 125 , respectively. In the embodiment of FIG. 8 , the second and third lower insulating layers 175 and 177 may constitute a lower insulating structure.

9 is a cross-sectional view illustrating a semiconductor package 20 according to exemplary embodiments of the present invention. In the following, descriptions overlapping those described above are omitted or simplified.

Referring to FIG. 9 , the semiconductor package 20 may be a semiconductor package having a package-on-package structure in which a first upper package 23 is attached to a lower package 21 .

The lower package 21 may be a semiconductor package having a fan-out structure. The lower package 21 may be substantially the same as or similar to the semiconductor package 10a described with reference to FIG. 2 .

The first upper package 23 may be stacked on the lower package 21 through the inter-package connection terminal 505 . In this disclosure, the first upper package 23 may be referred to as a package structure. The first upper package 23 may be a semiconductor package having a fan-out structure. The first upper package 23 may be similar to the semiconductor package 10 described with reference to FIGS. 1A to 1C . The first upper package 23 includes a second semiconductor chip 210 including a chip pad 211, a conductive pillar 231 connected to the chip pad 211 of the second semiconductor chip 210, and a second semiconductor chip ( 210) covering the top and side surfaces of the fifth cover insulating layer 221, the fourth upper conductive layer 241 extending along the top surface of the fifth cover insulating layer 221, and the side surface of the fifth cover insulating layer 221 The fourth side conductive layer 243 extending along the , the fourth upper conductive layer 241 and the sixth cover insulating layer 223 covering the fourth side conductive layer 243 , and the bottom of the second semiconductor chip 210 . The fourth lower conductive layer 245 extending along the surface, the fourth lower insulating layer 225 covering the fourth lower conductive layer 245, and the fourth lower conductive layer 225 through the opening of the fourth lower conductive layer 225 A second lower bump pad 251 connected to the layer 245 may be included. The second semiconductor chip 210 of the first upper package 23, the conductive pillar 231, the fifth cover insulating layer 221, the fourth upper conductive layer 241, the fourth side conductive layer 243, 6 The cover insulating layer 223, the fourth lower conductive layer 245, the fourth lower insulating layer 225, and the second lower bump pad 251 are respectively the semiconductor package described with reference to FIGS. 1A to 1C. (10) of the first semiconductor chip 110, the first conductive pillar 131, the first cover insulating layer 121, the first upper conductive layer 141, the first side conductive layer 143, the second cover It may correspond to the insulating layer 123 , the first lower conductive layer 145 , the first lower insulating layer 125 , and the first lower bump pad 151 . An inter-package connection terminal 505 may be disposed between the upper bump pad 153 of the lower package 21 and the second lower bump pad 251 of the first upper package 23 .

10 is a cross-sectional view illustrating a semiconductor package 20a according to example embodiments. Hereinafter, the semiconductor package 20a shown in FIG. 10 will be described, focusing on differences from the semiconductor package 20 described with reference to FIG. 9 .

Referring to FIG. 10 , the semiconductor package 20a may be a semiconductor package having a package-on-package structure in which a first upper package 23 and a second upper package 24 are attached to a lower package 21 . The first upper package 23 and the second upper package 24 may be disposed side by side on the lower package 21 .

The second upper package 24 may be a semiconductor package having a fan-out structure. In this disclosure, the second top package 24 may be referred to as a package structure. The second upper package 24 may be similar to the semiconductor package 10c described with reference to FIG. 6 . The second upper package 24 includes a third semiconductor chip 310 including a chip pad 311, a conductive pillar 331 connected to the chip pad 311 of the third semiconductor chip 310, and a third semiconductor chip ( 310) covering the top and side surfaces of the seventh cover insulating layer 321, the fifth upper conductive layer 341 extending along the top surface of the seventh cover insulating layer 321, and the side surface of the seventh cover insulating layer 321 The fifth side conductive layer 343 extending along, the fifth upper conductive layer 341 and the eighth cover insulating layer 323 covering the fifth side conductive layer 343, and the bottom of the third semiconductor chip 310. A fifth lower conductive layer 345 extending along the surface and a conductive adhesive layer 346 may be included. The third semiconductor chip 310 of the second upper package 24, the conductive pillar 331, the seventh cover insulating layer 321, the fifth upper conductive layer 341, the fifth side conductive layer 343, 8 The cover insulating layer 323, the fifth lower conductive layer 345, and the conductive adhesive layer 346 are respectively the first semiconductor chip 110 of the semiconductor package 10c described with reference to FIG. A pillar 131, a first cover insulating layer 121, a first upper conductive layer 141, a first side conductive layer 143, a second cover insulating layer 123, a first lower conductive layer 145, And it may correspond to the conductive adhesive layer 146 . The upper bump pads 153 of the lower package 21 and the fifth lower conductive layer 345 of the second upper package 24 may be coupled through the conductive adhesive layer 346 .

11 is a cross-sectional view illustrating a semiconductor package 20b according to example embodiments of the inventive concepts. Hereinafter, the semiconductor package 20b shown in FIG. 11 will be described, focusing on differences from the semiconductor package 20 described with reference to FIG. 9 .

Referring to FIG. 11 , the semiconductor package 20b may be a semiconductor package having a package-on-package structure in which a third upper package 25 is attached to a lower package 21 .

The third upper package 25 may be stacked on the lower package 21 through the inter-package connection terminal 505 . The third upper package 25 may be a semiconductor package having a fan-in structure. The third upper package 25 includes a fourth semiconductor chip 410 disposed such that the surface on which the chip pads 411 are provided faces the lower package 21, and the redistribution structure 420 on the fourth semiconductor chip 410. can include The redistribution structure 420 may include a conductive redistribution pattern 421 and a redistribution insulating layer 423 covering the redistribution pattern 421 . An inter-package connection terminal 505 may be disposed between a portion of the redistribution pattern 421 protruding from the redistribution insulating layer 423 and the upper bump pad 153 of the lower package 21 . The redistribution pattern 421 may electrically connect the chip pad 411 of the fourth semiconductor chip 410 and the inter-package connection terminal 505 .

As above, exemplary embodiments have been disclosed in the drawings and specifications. Embodiments have been described using specific terms in this specification, but they are only used for the purpose of explaining the technical spirit of the present disclosure, and are not used to limit the scope of the present disclosure described in the meaning or claims. Therefore, those of ordinary skill in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical scope of protection of the present disclosure should be determined by the technical spirit of the appended claims.

10: semiconductor package 110: semiconductor chip
121: first cover insulating layer 123: second cover insulating layer
125: first lower insulating layer 141: upper conductive layer
143: first side conductive layer 145: lower conductive layer
151: lower bump pad

Claims (6)

a first semiconductor chip including a top surface, a bottom surface, and a side surface, and including a chip pad provided on the top surface;
a first conductive pillar on the chip pad of the first semiconductor chip;
a first cover insulating layer covering the top surface and the side surface of the first semiconductor chip and surrounding sidewalls of the first conductive pillars;
a first upper conductive layer extending along an upper surface of the first cover insulating layer and electrically connected to the chip pad of the first semiconductor chip through the first conductive pillar;
a first side conductive layer extending along a side surface of the first cover insulating layer and connected to the first upper conductive layer;
a second cover insulating layer covering the first upper conductive layer, the first side conductive layer, and the first cover insulating layer; and
a first lower conductive layer extending along the bottom surface of the first semiconductor chip and connected to the first side conductive layer;
including,
The surface roughness of the upper surface of the first cover insulating layer is greater than the surface roughness of a surface of the first cover insulating layer contacting the upper surface of the first semiconductor chip. According to claim 1,
The vertical height of the first side conductive layer is greater than the vertical height of the first semiconductor chip;
The horizontal width of the first side conductive layer is greater than the horizontal width of the first upper conductive layer and the horizontal width of the first lower conductive layer;
The first lower conductive layer is in contact with the bottom surface of the first semiconductor chip. According to claim 1,
The first side conductive layer includes a first side surface facing the side surface of the first semiconductor chip, a second side surface opposite to the first side surface, and top and bottom surfaces opposite to each other;
The first upper conductive layer is in contact with the first side surface of the first side conductive layer,
The first lower conductive layer is in contact with the bottom surface of the first side conductive layer. According to claim 1,
a first lower insulating layer covering the first lower conductive layer and the bottom surface of the first semiconductor chip;
a first lower bump pad connected to the first lower conductive layer through an opening of the first lower insulating layer;
lower connection bumps on the first lower bump pads;
an upper bump pad on an upper surface of the second cover insulating layer;
a second conductive pillar extending between the upper bump pad and the first upper conductive layer; and
an upper connection bump on the upper bump pad;
A semiconductor package further comprising a. According to claim 1,
an upper conductive structure provided on the top surface of the first semiconductor chip and having a single-layer structure or a multi-layer structure spaced apart from each other in a direction perpendicular to the top surface of the first semiconductor chip;
a side conductive structure provided on the side surface of the first semiconductor chip, having a single layer structure or a multi-layer structure spaced apart from each other in a direction perpendicular to the side surface of the first semiconductor chip, and electrically connected to the upper conductive structure;
a lower conductive structure provided on the bottom surface of the first semiconductor chip, having a single layer structure or a multi-layer structure spaced apart from each other in a direction perpendicular to the bottom surface of the first semiconductor chip, and electrically connected to the side conductive structure;
a cover insulation structure covering the upper conductive structure and the side conductive structure; and
a lower insulating structure covering the lower conductive structure;
A semiconductor package further comprising a. According to claim 1,
an upper bump pad on the first upper conductive layer;
inter-package connection terminals on the upper bump pad; and
a package structure on the inter-package connection terminal;
Including more,
The package structure,
a second semiconductor chip;
a third cover insulating layer covering top and side surfaces of the second semiconductor chip;
a second upper conductive layer extending along an upper surface of the third cover insulating layer and connected to a chip pad of the second semiconductor chip;
a second side conductive layer extending along a side surface of the third cover insulating layer and connected to the second upper conductive layer;
a fourth cover insulating layer covering the second upper conductive layer, the second side conductive layer, and the third cover insulating layer;
a second lower conductive layer extending along a bottom surface of the second semiconductor chip and connected to the second side conductive layer; and
a second lower bump pad connected to the second lower conductive layer and the inter-package connection terminal;
A semiconductor package comprising a.

Images