KR20230008343A - Electrostatic Chuck Carrier - Google Patents

Abstract

The present invention relates to an electrostatic chuck carrier. In the electrostatic chuck carrier for supporting a disk-shaped ultra-thin semiconductor wafer having a first side as the front side and a second side as the back side located opposite to the first side, the electrostatic chuck carrier comprises: a) a carrier layer; b) a second electrically insulating layer surrounding the carrier layer; c) a conductive layer placed on the second electrically insulating layer and structured into at least two regions, wherein at least two regions are electrically insulated from each other, each region has an electrode on the front of the electrostatic chuck carrier and an electrical contact point on the back of the electrostatic chuck carrier, and the electrical contact point is electrically connected to the electrode; and d) a first electrically insulating layer placed on the conductive layer and surrounding at least the front of the electrostatic chuck carrier and an edge portion between the front and back of the electrostatic chuck carrier. At least one of the regions of the conductive layer has a conductor portion, and the conductor portion extends from the front of the electrostatic chuck carrier through the outer edge of the carrier layer to the back of the electrostatic chuck carrier, and at the same time electrically connects the electrical contact point and the electrode of the region. The electrostatic chuck carrier can handle a used wafer in a reliable manner without breaking or damaging an ultra-thin semiconductor wafer which is a used wafer.

Description

Electrostatic Chuck Carrier

The present invention relates to an electrostatic chuck carrier for handling thin semiconductor wafers, and particularly to an electrostatic chuck carrier capable of reinforcing and handling ultra-thin semiconductor wafers.

Thin-plate semiconductor components are widely used in fields requiring microelectronic technology. The best known example is an integrated circuit for a chip card, but the thickness of a silicon chip having such a circuit is currently 150um. In addition, in order to reduce material costs when manufacturing solar cells, the thickness of wafers for solar cells is gradually becoming thinner and ultra-thin. In addition, the power semiconductor market with a chip thickness of about 100um occupies an important portion. Thinner chip thicknesses, down to less than 50 µm, offer several significant advantages. First, the shape of the case can be made very flat. This is what a portable electronic device needs. Even in the case of a radio frequency identification (RFID) tag, thin-walled chips without a case are used. Second, the performance of the semiconductor component is improved by allowing current to flow in a vertical direction to the rear side of the chip. This is especially for applications in power semiconductors and solar cells. Third, a mechanically flexible silicon semiconductor chip can be manufactured by thinning a circuit wafer to a thickness of 30 μm or less. Such a flexible silicon semiconductor chip is very suitable for installation on a flexible flexible substrate. Vertically integrating chips or stacking each wafer requires a thin semiconductor wafer or thin chip with the thickness of the semiconductor wafer in the range of 10um to 30um in the case of making electrical connections in the vertical direction by direct penetrating contact through a thin silicon substrate. Do. This is not limited to silicon semiconductor wafers, but applies to Si-Ge, GaAs, III-V semiconductors, and the like, for example. Since extremely thin ultra-thin wafers made of these materials are expensive and more difficult to process than silicon semiconductor wafers, new handling devices and technologies for these materials are urgently required.

450mm 반도체 웨이퍼는 775um 두께를 갖는

300mm 반도체 웨이퍼와 같은 새깅 레벨(sagging level)를 유지하기 위해서 1800um 의 두께를 가질 필요가 있다.On the other hand, as the size of the semiconductor wafer increases, there is a problem in semiconductor wafer handling due to wafer warpage from the thin film growth process and sagging caused by the weight of the wafer. For example, wafer whitening occurs when growing various thin films on the surface of semiconductor wafers as part of the manufacturing process. For example,

A 450mm semiconductor wafer has a thickness of 775um

It needs to have a thickness of 1800um to maintain the same sagging level as a 300mm semiconductor wafer.

450mm 반도체 웨이퍼는 775um 두께를 갖는

300mm 반도체 웨이퍼와 거의 같은 레벨로 웨이퍼 휨을 제한하기 위해서 적어도 1180um 의 두께를 가질 필요가 있다.In another example, a 10 nm nitride film is grown or deposited

A 450mm semiconductor wafer has a thickness of 775um

It needs to have a thickness of at least 1180um to limit wafer warpage to about the same level as a 300mm semiconductor wafer.

가 증가되면서, 두께에 있어서 계속해서 감소됨에 따라, 프로세스 챔버에 배치된 울트라 박판 반도체 웨이퍼(ultra thin semiconductor wafer)들을 적절하게 지지할 수 있고, 프로세싱할 수 있는 반도체 프로세스 장비에 대한 필요성이 증가되고 있다. 전형적으로 반도체 웨이퍼는

300mm 로 핸들링될 수 있을 정도로, 그리고 프로세싱을 위해 프로세스 챔버에 배치되도록 로딩 및 트랜스퍼 시스템들에 지지될 수 있을 정도로 충분히 두꺼웠었다. 정전척은 전향적으로 프로세스 챔버내에 물리적으로 위치되고 고정되며, 일반적으로 반도체 웨이퍼 기판을 챔버내의 고정된 위치에서 지지하고 유지한다. 정전척에 의해 기판이 지지되는 동안에, 예컨대, 박막 재료를 증착하거나 또는 기판의 표면으로부터 재료를 제거하기 위해, 다양한 프로세스들이 기판에 적용된다. 그러나 큰 직경(

) 의 울트라 박판(ultra thin) 반도체 웨이퍼(예컨대, 약 10um 내지 200um 의 두께)는 표준 두께의 반도체 웨이퍼(예컨대, 775um 두께를 갖는

300mm 반도체 웨이퍼)와 동일한 방식으로 핸들링할 수 없게 된다. 게다가 현재의 프로세스 챔버들은 울트라 박판 (ultra thin) 반도체 웨이퍼들의 매엽식 프로세싱을 핸들링하도록 장비되지 않는다.Also, the critical dimensions for a semiconductor wafer are the diameter of the semiconductor wafer.

As λ increases and continues to decrease in thickness, the need for semiconductor process equipment capable of properly supporting and processing ultra thin semiconductor wafers placed in a process chamber is increasing. . Typically, semiconductor wafers

It was 300 mm thick enough to be handled, and thick enough to be supported on loading and transfer systems to be placed in a process chamber for processing. An electrostatic chuck is prospectively physically positioned and secured within a process chamber, and generally supports and holds a semiconductor wafer substrate in a fixed position within the chamber. While the substrate is supported by the electrostatic chuck, various processes are applied to the substrate, for example to deposit thin film material or to remove material from the surface of the substrate. However, large diameter (

) of an ultra thin semiconductor wafer (e.g., a thickness of about 10 um to 200 um) is a standard thickness semiconductor wafer (e.g., having a thickness of 775 um).

300mm semiconductor wafer) cannot be handled in the same way. Moreover, current process chambers are not equipped to handle single wafer processing of ultra thin semiconductor wafers.

1 shows an electrostatic chuck 60 (more specifically, electrodes 65 and 66) of an electrostatic chuck 60 that holds a semiconductor wafer 55 by static electricity in a conventional semiconductor wafer holding device. It is equipped with an adsorption power source 80 that adsorbs and holds the semiconductor wafer 55 by applying a voltage. The electrostatic chuck 60 of this example is called a dipole type ESC, and has two electrodes 65 and 66 ) is embedded close to the surface in the insulator 40. The electrodes 65 and 66 are filled in the insulator 40 so that they face each other and form a circle, for example, both of the electrodes 65 and 66 are semicircular. 80) is a bipolar output type consisting of two DC power supplies (70a) and (70b() in this example, and outputs reverse polarity DC voltages +V and -V with the same value, and applies them to each electrode of the electrostatic chuck 60 ( 66 and 65. When the substrate 55 is supplied on the electrostatic chuck 60 and the voltage is applied to the electrostatic chuck 60 from the suction power supply 80 at the same time, the substrate 55 Positive and negative charges are accumulated between the electrodes 66 and 65, and the substrate 55 is adsorbed and held by the electrostatic chuck 60 by the electrostatic force (or Johnson-Rabeck force) acting therebetween. In that state, the substrate ( 55) may be irradiated with an ion beam 22 to perform processing such as ion implantation into the substrate 55. In such a semiconductor wafer holding device 100, the adsorption state of the substrate 55 on the electrostatic chuck 60, etc. More specifically, the presence or absence of a substrate, the adsorption state of the substrate (how strongly the substrate is adsorbed when voltage is applied to the electrostatic chuck), the release state of the substrate (residual state after the voltage to the electrostatic chuck is turned off) It is important from the viewpoint of preventing overheating of the substrate during the transfer process of the substrate.

Conventionally, a vacuum chuck has been generally used as a holding device for supporting a semiconductor wafer, but when a thin semiconductor wafer is supported, there is a drawback that its periphery is bent. In contrast, with an electrostatic support device such as an electrostatic chuck, since the semiconductor wafer can be supported by the electrostatic force of the entire electrode surface, even when the thin plate is handled, the periphery may be bent. As such an electrostatic support device, for example, an electrostatic chuck shown in Figs. 2 and 3 is known. As shown in Fig. 2, this electrostatic chuck has a base plate 201 and a support portion 110 attached to the base plate. The support portion 110 is formed of an electrode composed of the electrode element group 202a and the electrode element group 202b, and an insulating layer 203 covering the electrode. A base plate 201 is fixed to the back surface 203b of the insulating layer 203 . Further, these electrode element groups 202a and 202b are electrically connected to the DC high-voltage power source 122 via switches 121a and 121b, respectively.

FIG. 2 is a configuration of a conventional electrostatic chuck. As shown in FIG. 3 , the support portion 110 includes a capacitor 112 and a resistor 111 that store charges. According to such an electrostatic chuck carrier, by turning on the switches 121a and 121b, a high voltage of +V volt is applied to the electrode element group 202a and -V volt is applied to the electrode element group 202b. do. Accordingly, when the switches 121a and 121b are turned on, the surface 203a of the insulating layer 203 serves as a support surface and induces an electrostatic attraction force between the handling objects 205, thereby inducing a semiconductor wafer ( 205) is attracted to and supported by the support surface 203a with an electrostatic attraction force. In the meantime, in the support part 110, the potential as the cause of the electrostatic attraction force is held in the capacitor 112, and the resistance 111 (the insulating layer 203 between the electrode element group 202a and the electrode element group 202b) ] has a normal leakage current. The volume resistivity of the resistor 111 (insulating layer 203) is generally 10 ¹⁴ Ωm or more, and when an electrode having a surface dimension of 200 mm×200 mm is used, this normal leakage current is very low, on the order of 1 nA or less. .

Next, when the switches 121a and 121b are turned off, the voltage of the DC high-voltage power source 122 is cut off. Leakage current between the electrode element group 202a and the electrode element group 202b continues to occur. Although this leakage current is an extremely low current of about 1 nA, the potential of the electrode element group 202a and the electrode element group 202b is gradually lowered, and the electrostatic attraction force is lowered. In the meantime, in the support part 110 of the electrical schematic, the potential of the capacitor 112 is lowered by the consumption of the electric charge which gradually leaks through the high resistance 111.

Accordingly, when the switches 121a and 121b are turned off, the electrostatic attraction force of the support portion 110 decreases, and the holding force of the semiconductor wafer 205 decreases, and eventually the handled semiconductor wafer 205 detaches. . According to this electrostatic chuck, a constant high voltage (e.g., +V volts for the electrode element group 202a, electrode element group 202b] outputs -V volts, and when off, these voltages are cut off. Accordingly, when the switches 121a and 121b are turned on, the surface 203a of the insulating layer 203 becomes a support surface, and an electrostatic attraction force is induced between the semiconductor wafers 205 to be handled. 205) is attracted to and supported by the support surface 203a with an electrostatic attraction force. When the switches 121a and 121b are turned off, these electrostatic suction forces are eliminated, and the handling object 205 can be released. Accordingly, an object to be handled, such as a conductor, semiconductor, or high-resistance material, is attracted and supported (loaded) by electrostatic attraction, and the object to be handled can be detached (unloaded) when released.

However, the voltage to be applied to the electrode element group (electrode) of such an electrostatic chuck requires a high-voltage DC voltage, for example, about ±1 KV or higher. For this reason, when using a low-voltage battery or a commercial AC power supply as a high-voltage DC power supply, a booster circuit and a voltage stabilization circuit had to be used together. However, since these booster circuits and voltage stabilization circuits generally consume large amounts of power, in the case of using a battery as a low-voltage power source, handling operation for a long time exceeding one hour, for example, becomes substantially difficult. For this reason, in order to secure a DC high voltage such as ±1 KV over a long period of time, a large-capacity power supply had to be always supplied from the outside.

In recent semiconductor chip manufacturing processes, thin bare wafers with a thickness of about 50 μm to 150 μm are introduced. Such thin semiconductor wafers (thin bare wafers) are difficult to handle because they are fragile. In addition, warpage tends to occur in thin semiconductor wafers (thin bare wafers), and the next manufacturing process must be carried out in a state where this warpage is corrected. Therefore, for example, it is proposed to transfer the thin semiconductor wafer (thin bare wafer) to the next manufacturing process in a state where the mechanical strength is reinforced by adhering the back side of the thin wafer to the support substrate via double-sided tape, and the warpage is suppressed or corrected. has been The wafer adhered to the support substrate in this way is separated from the support substrate through a UV (ultraviolet ray) irradiation process or the like.

Here, if an electrostatic chuck having a smooth surface as a support surface is introduced into the semiconductor chip manufacturing process, it is said that it is possible to easily support and remove the wafer by turning on/off the power, while suppressing or correcting warpage at the same time. have an advantage However, in the conventional electrostatic chuck, since a high-voltage direct current high-voltage power source must always be secured, a large obstacle is expected in the introduction of the electrostatic chuck into a semiconductor chip manufacturing process requiring simplified operation.

KR 10-0227821 B1 KR 10-1531647 B1 KR 10-0859061 B1 KR 10-1142000 B1

An object of the present invention is to provide an electrostatic chuck carrier having a carrier layer of a semiconductor wafer.

An object of the present invention is to provide an electrostatic chuck carrier capable of handling a used wafer in a reliable manner without damaging or damaging an ultra-thin semiconductor wafer, which is a used wafer.

An electrostatic chuck carrier for achieving the above object is

An electrostatic chuck carrier for supporting a disc-shaped ultra-thin semiconductor wafer, having a first surface as a front surface and a second surface as a rear surface positioned opposite to the first surface, comprising:

a) a carrier layer;

b) a second electrical insulating layer surrounding the carrier layer;

c) a conductive layer disposed on the second electrical insulating layer and structured into at least two regions, wherein the at least two regions are electrically insulated from each other, and each of the regions includes an electrode on the front surface of the electrostatic chuck carrier; the conductive layer having an electrical contact on the rear surface of the electrostatic chuck carrier and electrically conducting and connecting the electrical contact to the electrode;

d) a first electrical insulating layer disposed on the conductive layer, including at least the first electrical insulating layer surrounding the front surface of the electrostatic chuck carrier and an edge between the front surface and the rear surface of the electrostatic chuck carrier; do,

At least one of the regions of the conductive layer has a conductor portion, and the conductor portion extends from the front surface of the electrostatic chuck carrier to the rear surface of the electrostatic chuck carrier through the outer periphery of the carrier layer, and at the same time, the electrical contact of the region and the It is characterized in that the electrodes are electrically conducted and connected.

Preferably, the carrier layer has at least one through-contact portion, and the through-contact portion electrically conducts and connects each contact of the conductive layer region and the electrode.

Preferably, the carrier layer has at least one through-contact portion, and the through-contact portion electrically conducts and connects each contact of the conductive layer region and the electrode.

Preferably, the conductive layer is made of or includes at least one of a metal, an alloy, a metal silicide, or an appropriately doped material.

Preferably, the material of the carrier layer is characterized in that it includes at least one of silicon, III-V semiconductor, AlGaAsP, Ge, GaAs, SiC, InP, or InGaAs.

Preferably, at least one of the electrical insulating layers includes at least one of a silicon oxide film, silicon nitride, and titanium dioxide.

Preferably, the silicon oxide film is deposited by a thermal growth method or a CDV method.

Preferably, the electrical insulation layer has a thickness ranging from about 0.1 μm to about 5 μm.

Preferably, the electrical insulation layer is characterized in that it has a thickness ranging from about 0.1 μm to 1 μm.

According to the present invention, an electrostatic chuck carrier having a carrier layer made of semiconductor wafers and an ultra-thin wafer are integrated into a sandwiching structure, processed in equipment of a semiconductor fab line like a semiconductor wafer having a normal thickness, transported in a handler, and transferred to a wafer rack. it is possible to keep

1 is a configuration diagram showing an example of a conventional semiconductor wafer support device.
2 is a diagram explaining the configuration of a conventional electrostatic chuck.
FIG. 3 is an electrical schematic diagram illustrating electrical components of the support part of the electrostatic chuck of FIG. 2 .
4 is a cross-sectional view showing the construction of an electrostatic chuck carrier according to the present invention.
5 is a plan view showing the construction of an electrostatic chuck carrier according to the present invention.
6 is a plan view showing another configuration of an electrostatic chuck carrier according to the present invention.
7 is a rear view of an electrostatic chuck carrier having a contact surface according to the present invention.

Since the present invention can apply various transformations and have various embodiments, specific embodiments will be illustrated in the drawings and described in detail in the detailed description. However, this is not intended to limit the present invention to specific embodiments, and should be understood to include all conversions, equivalents, or substitutes included in the spirit and scope of the present invention. In describing the present invention, if it is determined that a detailed description of related known technologies may obscure the gist of the present invention, the detailed description will be omitted.

Hereinafter, some examples of electrostatic chuck carriers and configurations according to the present invention are as follows.

4 is a cross-sectional view showing the construction of an electrostatic chuck carrier according to the present invention.

This configuration includes an electrostatic carrier 1, and an ultra-thin semiconductor wafer 15 is supported as a usable wafer on the front surface of the electrostatic chuck carrier 1. The electrostatic chuck carrier 1 has a carrier layer 2 made of single crystal silicon. The carrier layer 2 can be used for the carrier layer 2 as well as monocrystalline silicon as well as III-V semiconductors, AlGaAsP, Ge, GaAs, SiC, InP, or InGaAs in a disk shape with a suitable thickness.

The periphery of the carrier layer 2 is surrounded by an electrical insulating layer 3 of silicon oxide (SiO2). The electrical insulating layer 3 is a dielectric layer and may be selected from silicon oxide (SiO2), silicon nitride, and titanium dioxide in consideration of processing for assembly of the electrostatic chuck carrier 1. A conductive layer 4 is disposed on the dielectric layer 3 and structured into two electrically spaced regions 4a and 4b. The conductive layer 4 can be made of metal, alloy, or metal silicide. In addition, if the material is properly doped and the material conductivity is excellent, it can be used as a conductive layer. Conductive regions 4a, 4b have front regions 5a, 5b, lateral regions 6a, 6b surrounding the edge of the carrier layer 2, and rear regions 7a, 7b. The regions including (4a), (5a), (6a) and (7a) in the conductive region are electrically connected to each other, while in the conductive region (4b), (5b), (6b) and (7b) ) are also electrically connected to each other. These two electrically conductive parts are electrically insulated from each other. For example, (4a) and (4b) are electrically insulated, and (5a) and (4b) are also electrically insulated. When an appropriate voltage is applied to the area 7a used as a contact on the rear side, the front area 5a, which is a conductive area on the front side, is treated with an anode, and on the other hand, when a voltage is applied to the area 7b used as a contact on the rear side, the front Region 5b is regarded as a cathode. The rear contact 7a and the front electrode 5a and the rear contact 7b and the front electrode 5b make contact via the periphery region 6a or region 6b, respectively. An electric field stably holding the used wafer 15 on the surface of the electrostatic chuck carrier 1 is formed between the front electrode 5a and the front electrode 5b. Since the electrostatic chuck carrier 1 is further surrounded by an electrical insulating layer 8 around it, the conductive coating regions 4a, 5a, 6a, and 4b, 5b, 6b are used. It is electrically isolated from the wafer (15). Since only the rear contact area 7a or the rear contact area 7b does not come into contact with the electrical insulation layer 8 containing a silicon oxide film, the rear contact is made through the openings 9a and 9b of the electrical insulation layer 8. A voltage can be applied to region 7a and back contact region 7b.

5 is a plan view showing the construction of an electrostatic chuck carrier according to the present invention.

A conductive coating is structured on the front surface of the electrostatic chuck carrier, the diameter of which is characterized by an edge 12 of the electrostatic chuck carrier and is slightly smaller than the overall diameter of the electrostatic chuck carrier. In the electrically separated areas (5a) and (5b), the coating is structured in a fan shape. Each fan shape is denoted as (10a) or (10b), and each adjacent fan shape is a part of another coated area 5a or coated area 5b. The fan shape 10a, which is a part of the coating area 5a, is electrically connected to each other through a common conductive area 11a, and a strip conductor 6a along the edge 12 of the electrostatic chuck carrier 1 ) through contact with the rear surface of the electrostatic chuck carrier 1. The fan shapes 10b associated with the conductive region 5b are conductively connected to each other through the strip conductor 11b and make penetrative contact with the back surface of the electrostatic chuck carrier 1 through the strip conductor 6b. The strip conductor is used in a comb-shaped and/or concentric ring shape or ring part shape as well as a fan shape in consideration of processing for the assembly of the electrostatic chuck carrier 1. The strip conductor 6b is disposed over the edge portion 12 of the electrostatic chuck carrier 1 . It is particularly advantageous because thin wafers can be supported on the structured electrostatic chuck carrier.

6 is a plan view showing another configuration of an electrostatic chuck carrier according to the present invention.

In Fig. 6, the conductive region 13a, the conductive region 14a or the conductive region 13b, and the conductive region 14b related to the conductive region 5a or the conductive region 5b have an annular structure. The conductive regions 13a or 13b are annular and are electrically connected to each other at certain locations along the circumference of the electrostatic chuck carrier 1 along the conductive regions 14a or 14b in the radial direction. do. The conductive regions 14a and 14b in the radial direction are disposed on the diagonal of the electrostatic chuck carrier 1 and extend in opposite directions to the edge 12 of the electrostatic chuck carrier 1 . Conductive region 14a and conductive region 14b at respective places are in penetrating contact on their backside by strip conductor 6a or strip conductor 6b of edge portion 12 of electrostatic chuck carrier 1 .

7 is a back view of an electrostatic chuck carrier with a contact surface.

Electrically conductive connection to strip conductors (6a) and (6b) over the edges of the front surface of the electrostatic chuck carrier (1) so that voltage can be applied to the annular regions (13a), (14a), (13b) and (14b). The contact to be made is marked as (7a) or (7b). Contact 7a forms the anode, while contact 7b forms the cathode.

Even using the electrostatic chuck carrier shown in FIGS. 5 and 6, a very thin wafer can be supported similarly. As a semiconductor component, individual chips can be fixed.

The diameter (vertical length a) of the electrostatic chuck carrier 1 is equal to the diameter of the wafer 15 used.

Therefore, the wafer 15 used is also composed of a very flat cylindrical body.

In addition, the electrostatic chuck wafer 1 meets the same precision requirements as the wafer 15 used. For so-called 6-inch wafers, i.e. 150 mm in diameter, the precision for this dimension is ±0.2 mm. However, to solve the problem of the sharp edge of the ultra-thin wafer 15, the diameter of the wafer 15 is slightly (several mm) smaller than the diameter of the electrostatic chuck carrier 1.

For example, to avoid undesirable etching of the electrostatic chuck carrier 1 in a plasma etcher or to avoid unwanted coating of the electrostatic chuck carrier 1 in a plasma deposition apparatus, the electrostatic chuck carrier 1 Alternatively, it is prudent to configure the diameter of the carrier layer 2 to be slightly (ie several mm) smaller than the diameter of the wafer 15 used. In this way, the electrostatic chuck carrier 1 is shielded and protected from plasma. The electrostatic chuck carrier 1 can also be slightly smaller in diameter than a conventional wafer standard with semiconductor technology. The sum of the thickness D of the carrier layer 2 and the conductive layer 4, the thickness i of the electrical insulation layer 3 and the electrical insulation layer 8, and the thickness d of the thin wafer 15 used (D + d + i) manufacture the electrostatic chuck carrier 1 so that it falls within the tolerance of the thickness for the diameter of the wafer. In other words, the total thickness of a wafer construction has a value corresponding to a layer normally handleable by standard handling equipment in the semiconductor industry. For a diameter of a = 150 mm, the total thickness of the wafer configuration is approximately in the range of 655 μm to 695 μm. Therefore, even if the electrostatic chuck carrier 1 and the used wafer 15 are combined, the thickness is similar to the standard thickness in the semiconductor wafer processing apparatus of the semiconductor manufacturing line. It is more convenient because it is only necessary to ensure that the tolerance of the thickness is satisfied by selecting the arrangement using a wafer of standard thickness as the electrostatic chuck carrier 1 . However, when the precision requirement is high, the carrier wafer 1 is manufactured to a required thickness by making the wafer as thin as the thickness of the used wafer 15 . Needless to say, the wafer may be configured to have other diameters and other total thicknesses.

Therefore, with the bipolar electrostatic chuck carrier manufactured according to the present invention, for example, extremely thin wafers can be supported and processed, transported, and stored with equipment used in the semiconductor industry. By applying a voltage to the conductive layer of the electrostatic chuck carrier, a bipolar electrostatic field is generated between electrodes having different poles on the front surface of the electrostatic chuck carrier, thereby stably maintaining the ultra-thin semiconductor wafer.

Such sandwiching structures, including electrostatic chuck carriers and ultra-thin used wafers processed in semiconductor lines, can be processed in equipment in semiconductor fab lines, transported in handlers, and stored in wafer racks, like semiconductor wafers having a normal thickness.

From the above description, those skilled in the art to which the present invention pertains will be able to understand that the present invention may be embodied in other specific forms without changing its technical spirit or essential features. In this regard, the embodiments described above should be understood as illustrative in all respects and not limiting. The scope of the present invention should be construed as including all changes or modifications derived from the meaning and scope of the claims to be described later and equivalent concepts rather than the detailed description above are included in the scope of the present invention.

1: electrostatic chuck carrier
2: carrier layer
3: electrical insulation layer, dielectric layer
4: conductive layer
4a, 4b: conductive area, conductive coating area, conductive coating portion
5a, 5b: front area, conductive area, conductive layer, front electrode, conductive coating area, conductive coating part
6a, 6b: lateral area, conductive area, conductive layer, conductive coating area, conductive coating part, strip conductor
7a, 7b: rear area, conductive area, conductive layer, contact, rear contact area
8: electrical insulation layer
9a, 9b: opening
10a, 10b: fan shape
11a: Areas of common challenge
11b: strip conductor
12: edge, edge
13a, 13b: conductive area
14a, 14b: conductive area

Claims (10)

An electrostatic chuck carrier for supporting a disc-shaped ultra-thin semiconductor wafer, having a first surface as a front surface and a second surface as a rear surface positioned opposite to the first surface, comprising:
a) a carrier layer;
b) a second electrical insulating layer surrounding the carrier layer;
c) a conductive layer disposed on the second electrical insulating layer and structured into at least two areas, wherein the at least two areas are electrically insulated from each other, and each of the areas is provided with an electrode on the front surface of the electrostatic chuck carrier; The conductive layer having an electrical contact on the rear surface of the chuck carrier and electrically conducting and connecting the electrical contact to the electrode;
d) a first electrical insulating layer disposed on the conductive layer, including at least the first electrical insulating layer surrounding the front surface of the electrostatic chuck carrier and an edge between the front surface and the rear surface of the electrostatic chuck carrier; do,
At least one of the regions of the conductive layer has a conductor portion, and the conductor portion extends from the front surface of the electrostatic chuck carrier to the rear surface of the electrostatic chuck carrier through the outer periphery of the carrier layer, and at the same time, the electrical contact of the region and the An electrostatic chuck carrier characterized by electrically conducting and connecting electrodes. According to claim 1,
The electrostatic chuck carrier according to claim 1 , wherein the carrier layer has at least one through-contact portion, and the through-contact portion electrically conducts and connects each contact of the conductive layer region to the electrode. According to claim 1,
The electrostatic chuck carrier of claim 1, wherein the conductive layer is made of or includes at least one of a metal, an alloy, a metal silicide, or an appropriately doped material. According to claim 1,
An electrostatic chuck carrier characterized in that the electric electrode is composed of a comb-shaped electrode, a fan-shaped and/or concentric ring or ring part. According to claim 1,
The electrostatic chuck carrier, wherein the material of the carrier layer includes at least one of silicon, III-V semiconductor, AlGaAsP, Ge, GaAs, SiC, InP, or InGaAs. According to claim 1,
At least one of the electrical insulating layers includes at least one of silicon oxide, silicon nitride, and titanium dioxide. According to claim 1,
The electrostatic chuck carrier, characterized in that the silicon oxide film is deposited by a thermal growth method or a CDV method. According to claim 1,
The electrostatic chuck carrier, characterized in that the electrical insulating layer has a thickness in the range of about 0.1μm to 5μm. According to claim 1,
The electrostatic chuck carrier, characterized in that the electrical insulating layer has a thickness in the range of about 0.1μm to 1μm. An electrostatic chuck carrier for supporting a disk-shaped ultra-thin wafer, having a first surface facing the front side and a second surface facing the rear side opposite to the first surface, comprising:
a) a carrier layer made of an electrical insulating material;
b) a conductive layer disposed on the carrier layer and structured into at least two regions, wherein the at least two regions are electrically insulated from each other, and each of the regions has an electrode on the front surface of the electrostatic chuck carrier. The conductive layer having an electrical contact on the rear surface and electrically conducting and connecting the electrical contact to the electrode;
c) a first electrical insulating layer disposed on the conductive layer, including at least the first electrical insulating layer surrounding the front surface of the electrostatic chuck carrier and an edge between the front surface and the rear surface of the electrostatic chuck carrier; do,
At least one of the regions of the conductive layer has a conductor portion, and the conductor portion extends from the front surface of the electrostatic chuck carrier to the rear surface of the electrostatic chuck carrier through the outer periphery of the carrier layer, and at the same time, the electrical contact of the region and the An electrostatic chuck carrier characterized by electrically conducting and connecting electrodes.

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